Manufacturing method of QFN (Quad Flat No-lead) chip comprising flank structure

Abstract

The invention provides a manufacturing method of a QFN (Quad Flat No-lead) chip comprising a flank structure, which belongs to the technical field of semiconductor packaging and comprises the following steps of: providing a carrier plate, and forming a temporary bonding layer on one side of the carrier plate; forming a flank structure removal layer corresponding to the flank structure on one side, deviating from the carrier plate, of the temporary bonding layer; forming a pin and a base island on one side, deviating from the temporary bonding layer, of the flank structure removal layer; mounting a chip on one side, deviating from the temporary bonding layer, of the base island; bonding wires between the chip and the pins to realize electrical connection; forming a plastic package body wrapping the temporary bonding layer, the flank structure removal layer, the pins, the base islands, the chip and the bonding wires; de-bonding to remove the carrier plate and the temporary bonding layer; removing the side wing structure removal layer; cutting the plastic package body to form single package bodies; according to the method, the manufacturing process of wet weldable products is optimized, the production efficiency is improved, and the problems caused by negative effects due to the fact that side wings are formed through cutting are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a method for manufacturing a QFN chip including a wing structure. Background Art

[0002] QFN (Quad Flat No-leads Package) is a surface mount package, which is characterized by electrode contacts on four sides, a large exposed pad in the center of the bottom for heat conduction, and conductive pads around the package periphery for electrical connection. This package does not have gull-wing leads like traditional SOIC and TSOP packages, and the conductive path between the internal pins and pads is short, the self-inductance coefficient and the wiring resistance in the package are very low, so it has excellent electrical performance and heat dissipation performance.

[0003] QFN chips with flank structures usually refer to QFN packages with wettable flanks. The sides of these chips usually have a step structure, which is usually formed by secondary cutting. In addition, the frames of these chips are also made by etching process.

[0004] However, there are some problems with the existing technology. First, due to the warping of the product, the step depth is uneven, which will affect the performance and reliability of the product. Secondly, since the frame used to make the product is made by etching, this limits the minimum size and spacing of the frame pins, which brings challenges to the application of high-density integrated circuits. Therefore, how to improve the manufacturing process of wet-weldable products and improve product quality and performance is a problem that needs to be solved urgently. Summary of the invention

[0005] Purpose of the invention: The purpose of the present invention is to address the deficiencies in the prior art and provide a method for manufacturing a QFN chip including a wing structure, by coating a temporary bonding layer on a temporary carrier, then drawing glue on the bonding layer according to the position and size of the QFN chip wing, then electroplating metal on the QFN chip pins and base island positions, mounting the chip on the base island, and connecting the base island and the pins with wires, finally plastic-sealing it, removing the bonding layer and glue, and cutting it into single QFN chips. This series of steps optimizes the manufacturing process of wet-weldable products, improves production efficiency, and solves the problems caused by the adverse consequences caused by cutting to form wing.

[0006] Technical solution: The present invention shows a method for manufacturing a QFN chip including a wing structure, providing a carrier board, forming a temporary bonding layer on one side of the carrier board; forming a wing structure removal layer corresponding to the wing structure on the side of the temporary bonding layer away from the carrier board; this removal layer will be removed in the subsequent steps to expose the wing structure. Pins and base islands are formed on the side of the wing structure removal layer away from the temporary bonding layer; pins and base islands are important components of the QFN chip, which provide electrical connection and physical support. The chip is mounted on the side of the base island away from the temporary bonding layer; this step is to accurately place the chip on the base island to prepare for subsequent electrical connection. Wires are welded between the chip and the pins to achieve electrical connection; this step is achieved through wire bonding technology, which connects the semiconductor chip to the lead frame, using very fine copper wires to create a strong electrical connection for the package. Subsequently, a plastic package is formed covering the temporary bonding layer, the wing structure removal layer, the pins, the base island, the chip and the bonding wires; the carrier board and the temporary bonding layer are removed by debonding; the wing structure removal layer is removed; and the plastic package is cut to form a single package.

[0007] Further, the side wing structure removal layer is drawn by glue line. The method of drawing the side wing structure removal layer by glue line involves a key step in the QFN packaging process, which is to add a tin plating layer on the side wing of the package to protect the copper material and improve the welding performance. This process allows visual inspection to ensure good lap welding and stable electrical connection.

[0008] Furthermore, the width of the glue line ranges from 0.3 to 0.6 mm, and the thickness ranges from 75 to 180 um.

[0009] Furthermore, the process used for the glue line includes but is not limited to the photolithography process or the glue drawing process. The photolithography process is used to form the desired pattern on the substrate, which includes coating a photoresist layer on the substrate and then forming a wing structure removal layer through a light exposure and development process; the glue drawing process, also known as the coating process, involves using a specific material (such as insulating glue) to form the desired wing structure removal layer on the substrate.

[0010] Furthermore, the processes used for the pins and the base islands include but are not limited to photolithography and electroplating metal. First, openings are formed on the temporary bonding layer by glue coating and photolithography. These openings are used for the subsequent production of pins and base islands. The pins and base islands are usually electroplated to ensure that they have good bonding strength. The commonly used material for electroplating metal is copper, which has good conductivity.

[0011] Furthermore, the bonding wire includes but is not limited to gold wire or copper wire. Gold wire has been widely used in integrated circuit packaging due to its excellent ductility, electrical conductivity and corrosion resistance, and gold wire has high reliability; copper wire has become a potential substitute for gold wire because of its lower cost and low resistivity. The application trend of copper wire in semiconductor bonding process is increasing, especially in packaging types such as QFN.

[0012] Furthermore, the process used for the plastic package includes but is not limited to injection molding or compression molding. Injection molding is a commonly used plastic molding method, which is formed by heating thermoplastic or thermosetting plastics to a molten state and then injecting them into a mold. For QFN packaging, the injection molding process is usually used to coat epoxy resin (EMC) around the soldered chips and gold wires to provide physical protection and prevent the influence of the external environment. During the injection molding process, the design of the mold and the control of the injection parameters are very critical to avoid the occurrence of bubbles and punching. Compression molding (or compression molding) is a process in which powdered, granular or fibrous plastics are placed in a mold, heated and pressurized. This method is suitable for thermosetting plastics and can solidify the material at a higher temperature. Compression molding can also be used to form a plastic package in QFN packaging, especially when larger parts or specific shapes are required.

[0013] Furthermore, the debonding process includes but is not limited to heating or ultraviolet irradiation. The viscosity of the bonding material is reduced by heating, making it separable. This method usually needs to be carried out at high temperature to soften and separate the bonding material. By using laser to pass through a transparent carrier, the photon energy is deposited on the photosensitive response material layer, thereby inducing rapid decomposition, vaporization or even plasma of the material and losing its viscosity. At the same time, the rapidly released decomposition gas will also increase the separation pressure at the interface of the response layer, thereby further promoting the automatic separation of the device wafer.

[0014] Furthermore, the wing structure removal layer is removed by chemical cleaning, which can be done by using a debonding solution.

[0015] Beneficial effects: Compared with the prior art, the advantages of the present invention are:

[0016] (1) The present invention ensures that the position of the glue line is not occupied by metal in the subsequent electroplating process by designing a wing structure removal layer corresponding to the wing mechanism, and finally removes the glue line to form a step structure of the wing, thereby improving production efficiency;

[0017] (2) The present invention avoids the problem of uneven step depth caused by secondary cutting of the flank structure in the traditional manufacturing process by designing a flank structure removal layer corresponding to the flank mechanism, thereby optimizing the manufacturing process;

[0018] (3) The lead frame of the present invention is made by electroplating metal instead of etching process. Therefore, the minimum size and spacing of the frame pins can be designed according to actual needs, breaking through the limitations of traditional etching process and having important significance for the application of high-density integrated circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a schematic diagram of step 2;

[0020] Figure 2 is a schematic diagram of step 3;

[0021] Figure 3 is a schematic diagram of step 4;

[0022] Figure 4 is a schematic diagram of step 5;

[0023] Figure 5 is a schematic diagram of step 6;

[0024] Figure 6 is a schematic diagram of step 7;

[0025] Figure 7 This is a schematic diagram of step 8;

[0026] Figure 8 Schematic diagram of the structure of the plastic package prepared in Example 1.

[0027] In the figure: 1. Glue wire, 2. Pin, 3. Base island, 4. Chip, 5. Solder wire, 6. Plastic package, 7. Temporary carrier board. DETAILED DESCRIPTION

[0028] The technical solution of the present invention is described in detail below with reference to the accompanying drawings, but the protection scope of the present invention is not limited to the embodiments.

[0029] Example 1

[0030] A method for manufacturing a QFN chip including a wing structure comprises the following steps:

[0031] Step 1: Select a flat temporary carrier, such as a silicon wafer or a glass plate, and coat a temporary bonding layer, such as a photosensitive adhesive layer, on its surface to provide stable support and a flat surface.

[0032] like Figure 2 As shown, step 2, a wing structure removal layer corresponding to the wing structure is formed on the side of the temporary bonding layer away from the carrier. The wing structure removal layer is formed by drawing corresponding glue lines on the temporary bonding layer according to the wing position and size of the product design, so that in the subsequent electroplating process, the position where the glue line is located is not occupied by metal. The wing structure removal layer is drawn by glue lines, the width of the glue lines ranges from 0.3 to 0.6 mm, and the thickness ranges from 75 to 180 um. The processes used for the glue lines include but are not limited to photolithography or glue drawing processes.

[0033] like Figure 3 As shown, step 3, according to the design drawing, electroplate metal at the corresponding position to form the pins and base island of the QFN chip.

[0034] like Figure 3As shown, step 4, mount the prepared chip on the base island.

[0035] like Figure 4 As shown, in step 5, the electrodes of the chip are connected to the base island and the pins through gold wires or copper wires to achieve electrical connection.

[0036] like Figure 5 As shown, in step 6, the entire QFN chip is encapsulated by injection molding or compression molding to protect the internal chip and circuit.

[0037] like Figure 6 As shown, in step 7, the temporary bonding layer is removed by heating or ultraviolet irradiation, so that the QFN chip can be separated from the temporary carrier.

[0038] like Figure 7 As shown, in step 8, the wing structure removal layer is removed by chemical cleaning.

[0039] Step 9: Finally, cut the QFN chip into individual packages.

[0040] As described above, although the present invention has been shown and described with reference to specific preferred embodiments, it should not be construed as limiting the present invention itself. Various changes in form and details may be made without departing from the spirit and scope of the present invention as defined in the appended claims.

Claims

1. A method for manufacturing a QFN chip including a wing structure, characterized in that: Providing a carrier, and forming a temporary bonding layer on one side of the carrier; forming a wing structure removal layer corresponding to the wing structure on a side of the temporary bonding layer away from the carrier; Forming a lead and a base island on a side of the wing structure removal layer away from the temporary bonding layer; Mounting a chip on a side of the base island away from the temporary bonding layer; Bonding wires between the chip and the pins to achieve electrical connection; Forming a plastic package covering a temporary bonding layer, a wing structure removal layer, pins, a base island, a chip and bonding wires; Debonding removes the carrier and temporary bonding layer; Removal of flanking structure removal layers; The plastic package is cut to form individual packages.

2. A method for manufacturing a QFN chip comprising a wing structure according to claim 1, characterized in that: The wing structure removal layer is drawn by glue lines.

3. A method for manufacturing a QFN chip comprising a wing structure according to claim 2, characterized in that: The width of the glue line ranges from 0.3 to 0.6 mm, and the thickness ranges from 75 to 180 um.

4. A method for manufacturing a QFN chip comprising a wing structure according to claim 2 or 3, characterized in that: The process used for the glue line includes but is not limited to a photolithography process or a glue drawing process.

5. The method for manufacturing a QFN chip including a wing structure according to claim 1, characterized in that: The processes used for the pins and the base islands include but are not limited to metal electroplating.

6. The method for manufacturing a QFN chip comprising a wing structure according to claim 1, characterized in that: The bonding wire includes but is not limited to gold wire or copper wire.

7. The method for manufacturing a QFN chip comprising a wing structure according to claim 1, characterized in that: The process used for the plastic package body includes but is not limited to injection molding or compression molding.

8. The method for manufacturing a QFN chip comprising a wing structure according to claim 1, characterized in that: Debonding processes include, but are not limited to, heating or ultraviolet radiation.

9. The method for manufacturing a QFN chip comprising a wing structure according to claim 1, characterized in that: The wing structure removal layer is removed by a chemical cleaning method.

Images