Semiconductor chip including chip protection structure and upper protection line

Abstract

The invention relates to a semiconductor chip including a chip protection structure and an upper protection line. A semiconductor chip according to a fundamentally disclosed embodiment includes: a chip region and a chip sealing region disposed in a substrate; a circuit pattern structure disposed in the chip area; a chip protection structure disposed in the chip sealing region and surrounding the chip region; a voltage supply line disposed over the circuit pattern structure in the chip region and providing a predetermined voltage to the circuit pattern structure; and an upper protection line disposed over the chip protection structure in the chip sealing region and electrically connected to the voltage supply line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0129837, filed on September 26, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure generally relate to a semiconductor chip including a protection pattern structure, and more particularly to a semiconductor chip including a chip protection structure and an upper protection line disposed spaced apart from each other. Background Art

[0004] A plurality of semiconductor chip regions separated from each other by scribe lane regions may be defined on a semiconductor wafer. After an integrated circuit is manufactured in the plurality of semiconductor chip regions through a semiconductor manufacturing process, the plurality of semiconductor chip regions may be divided into a plurality of semiconductor chips through a wafer cutting process.

[0005] Each of the plurality of semiconductor chip regions may be provided with a protection pattern structure, such as a protection ring, which is provided in an outer region of each of the plurality of semiconductor chip regions for protecting the integrated circuit. The protection pattern structure may block moisture and prevent moisture from penetrating from the outside of the plurality of semiconductor chip regions into the plurality of semiconductor chip regions, thereby preventing the integrated circuit from being damaged by moisture. Summary of the invention

[0006] According to an embodiment of the present disclosure, a semiconductor chip may include: a chip area and a chip sealing area arranged in a substrate; a circuit pattern structure arranged in the chip area; a chip protection structure arranged in the chip sealing area and surrounding the chip area; a voltage supply line arranged above the circuit pattern structure in the chip area to provide a predetermined voltage to the circuit pattern structure; and an upper protection line arranged above the chip protection structure in the chip sealing area and electrically connected to the voltage supply line.

[0007] A semiconductor chip according to another embodiment of the present disclosure may include: a substrate including a chip region and a chip sealing region outside the chip region; a chip protection structure disposed in the chip sealing region and surrounding the chip region; a voltage supply line disposed in the chip region; and an upper protection line disposed in the chip sealing region over the substrate and spaced apart from the chip protection structure. The upper protection line is electrically insulated from the chip protection structure and electrically connected to the voltage supply line. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a plan view schematically showing a semiconductor wafer according to an embodiment of the present disclosure.

[0009] Figure 2 is a plan view schematically showing a semiconductor chip according to an embodiment of the present disclosure.

[0010] Figure 3 yes Figure 2 The semiconductor chip shown is a cross-sectional view taken along line II'.

[0011] Figure 4 yes Figure 2 The semiconductor chip shown is a cross-sectional view taken along line II-II'.

[0012] Figure 5 is a plan view schematically showing a semiconductor chip according to a first comparative example of the present disclosure.

[0013] Figure 6 yes Figure 5 The semiconductor chip shown is a cross-sectional view taken along line III-III'.

[0014] Figure 7 is a cross-sectional view showing a semiconductor chip according to a second comparative example of the present disclosure.

[0015] Figure 8 is a plan view schematically showing a semiconductor chip according to another embodiment of the present disclosure.

[0016] Fig. 9 yes Figure 8 The semiconductor chip shown is a cross-sectional view taken along line IV-IV'.

[0017] Fig.10 yes Figure 8 The semiconductor chip shown is a cross-sectional view taken along line VV'.

[0018] Fig.11 is a plan view schematically showing a semiconductor chip according to another embodiment of the present disclosure.

[0019] Fig.12 yes Fig.11 The semiconductor chip shown is a cross-sectional view taken along line VI-VI'.

[0020] Fig.13 yes Fig.11 The semiconductor chip shown is a cross-sectional view taken along line VII-VII'. DETAILED DESCRIPTION

[0021] The terms used in the description of this specification are selected in consideration of the functions in the presented embodiments, and the meaning of the terms may vary according to the intention or habit of the user or operator in the technical field. If the terms used are specifically defined in this specification, their meanings follow the defined definitions, and if there are no specific definitions, the meanings may be interpreted according to the meanings commonly recognized by those skilled in the art. In the description of the disclosed embodiments, descriptions such as "first", "second", etc. are used to distinguish components and are not used to limit the components themselves or to indicate a specific order. In addition, unless otherwise clearly used in the context, the expression of the singular form of a word should be understood to include the plural form of the word.

[0022] Throughout the specification, the same reference numerals may refer to the same elements. Even if not mentioned or described in the corresponding drawings, the same or similar reference numerals may be described with reference to other drawings. In addition, even if the reference numerals are not shown, the description may be made with reference to other drawings.

[0023] Figure 1 Schematically shows a plan view of a semiconductor wafer 1 according to an embodiment of the present disclosure. The semiconductor wafer 1 may include multiple chip regions (e.g., chip regions 10A, 10B, 10C, and 10D), multiple chip sealing regions (e.g., chip sealing regions 20A, 20B, 20C, and 20D), and a scribe area 30L surrounding the multiple chip regions and the multiple chip sealing regions. Each chip sealing region may surround a corresponding chip region among the multiple chip regions 10A, 10B, 10C, and 10D. For example, the chip sealing region 20A may surround the chip region 10A, the chip sealing region 20B may surround the chip region 10B, the chip sealing region 20C may surround the chip region 10C, and the chip sealing region 20D may surround the chip region 10D. For ease of description, Figure 1 First to fourth chip regions 10A, 10B, 10C and 10D, first to fourth chip sealing regions 20A, 20B, 20C and 20D, and scribe lane region 30L are shown. However, the inventive concept of the present disclosure is not necessarily limited thereto, and other numbers of chip regions and other numbers of chip sealing regions are possible.

[0024] The integrated circuits may be arranged in the plurality of chip regions 10A, 10B, 10C, and 10D, respectively, to form semiconductor chips. The semiconductor chips formed in the plurality of chip regions 10A, 10B, 10C, and 10D may be substantially identical to each other. After the formation of the integrated circuits in the plurality of chip regions 10A, 10B, 10C, and 10D of the semiconductor wafer 1 is completed, the plurality of chip regions 10A, 10B, 10C, and 10D may be separated from each other, and a plurality of semiconductor chips A, B, C, and D may be provided.

[0025] Reference Figure 1 In the scribe line region 30L, the first to fourth chip regions 10A, 10B, 10C and 10D can be separated from each other along the first cutting line L1 along the y direction and the second cutting line L2 along the x direction to manufacture the first to fourth semiconductor chips A, B, C and D. A plurality of chip sealing regions 20A, 20B, 20C and 20D can be respectively located outside the plurality of chip regions 10A, 10B, 10C and 10D. Each of the plurality of chip sealing regions 20A, 20B, 20C and 20D can form a first boundary e1 with each of the plurality of chip regions 10A, 10C, 10C and 10D, and a second boundary e2 with the scribe line region 30L. Each of the plurality of chip sealing regions 20A, 20B, 20C and 20D can be disposed to surround a corresponding chip region of the plurality of chip regions 10A, 10B, 10C and 10D. As will be referred to later Figure 3 and Figure 4 As described, the chip protection structure 2100 and the upper protection line 130 may be provided in each of the plurality of chip sealing regions 20A, 20B, 20C, and 20D.

[0026] The scribe lane region 30L may be located outside the plurality of chip sealing regions 20A, 20B, 20C, and 20D. Figures 2 to 4 As described, various electrical test patterns or process monitoring patterns may be disposed in the scribe lane area 30L. However, the scribe lane area 30L may be divided along the first and second scribe lines L1 and L2 so that a plurality of semiconductor chips A, B, C, and D may be manufactured from the wafer 1.

[0027] Figure 2 is a plan view schematically showing a semiconductor chip E according to an embodiment of the present disclosure. Figure 3 yes Figure 2 The semiconductor chip E shown is a cross-sectional view taken along line II'. Figure 4 yes Figure 2 The semiconductor chip E shown is a cross-sectional view taken along line II-II'. The semiconductor chip E may correspond to Figure 1 One of the plurality of semiconductor chips A, B, C and D described.

[0028] Reference Figures 2 to 4 , the semiconductor chip E may include a chip region 10, a chip sealing region 20, and a scribe region 30 defined in the substrate 1001. The chip region 10 may correspond to the reference Figure 1The chip sealing region 20 may correspond to one of the chip regions 10A, 10B, 10C, and 10D described above. That is, the chip sealing region 20 may be provided outside the chip region 10 to surround the chip region 10. Figure 2 In the plan view, the chip sealing area 20 may be provided in a strip shape having a predetermined width W. The scribe area 30 may be provided in a strip shape having a predetermined width W. Figure 1 The scribe line region 30L is depicted along the first cutting line and the second cutting line ( Figure 1 The scribe lane region 30 may be provided outside the chip sealing region 20 .

[0029] Reference Figure 2 , the semiconductor chip E may include voltage supply lines Va and Vb disposed in the chip region 10. The voltage supply lines Va and Vb may be disposed on the surface of the interlayer insulating layer 4000 ( Figure 3 4000S) and can be Figure 3 and Figure 4 The circuit pattern structure 1100 of the chip region 10 shown provides a predetermined voltage. Figures 2 to 4 A pair of voltage supply lines Va and Vb is shown, but this is only an example and embodiments of the present disclosure are not limited thereto.

[0030] The voltage supply lines Va and Vb may include power pads 110 and 120, respectively. The power pad 110 may be a ground pad 110. The power pad 120 may be an operating voltage pad 120. The ground pad 110 and the operating voltage pad 120 may receive a predetermined voltage from an electronic device disposed outside the semiconductor chip E and redistribution layers 141 and 142 extending from the corresponding power pads 110 and 120, respectively. In the illustrated embodiment, the voltage supply lines Va and Vb include a ground voltage supply line Va and an operating voltage supply line Vb that are electrically separated from each other. The ground voltage supply line Va may include a ground pad 110 that receives a ground voltage from an electronic device and a first redistribution layer 141 extending from the ground pad 110 in a lateral direction (e.g., an x ​​direction). The operating voltage supply line Vb may include an operating voltage pad 120 that receives an operating voltage from an electronic device and a second redistribution layer 142 extending from the operating voltage pad 120 in a lateral direction (e.g., an x ​​direction).

[0031] Refer again Figure 2 , the semiconductor chip E may further include an upper protection line 130 disposed in the chip sealing region 20. The upper protection line 130 may surround the chip region 10. The upper protection line 130 may form or include a blocking structure that blocks moisture and prevents moisture from entering the chip region 10 from the outside.

[0032] In an embodiment, the upper protection line 130 may be disposed on substantially the same plane as the voltage supply lines Va and Vb. As an example, the upper protection line 130 may be disposed on the surface 4000S of the interlayer insulating layer 4000. In an embodiment, the upper protection line 130 and the voltage supply lines Va and Vb may include substantially the same conductive material. As an example, the upper protection line 130 and the voltage supply lines Va and Vb may include aluminum (Al).

[0033] In an embodiment, the upper protection line 130 may be electrically connected to the ground voltage supply line Va. Therefore, the upper protection line 130 may maintain an electrically grounded state within the semiconductor chip E. The upper protection line 130 may be connected to the ground voltage supply line Va through a conductive connection pattern 150. The conductive connection pattern 150 may be disposed on substantially the same plane as the upper protection line 130, the ground pad 110, and the first redistribution layer 141. As an example, the conductive connection pattern 150 may be disposed on a surface 4000S of the interlayer insulating layer 4000. The upper protection line 130, the ground pad 110, the first redistribution layer 141, and the conductive connection pattern 150 may include substantially the same material. As an example, the conductive connection pattern 150 may include aluminum (Al). In an embodiment, the upper protection line 130 may be electrically insulated from the operating voltage supply line Vb. The upper protection line 130 may be disposed on the surface ( 4000S) of the interlayer insulating layer 4000, spaced apart from the operating voltage pad 120 and the second redistribution layer 142. Figure 3 4000S).

[0034] Reference Figure 3 and Figure 4 , the circuit pattern structure 1100 may be disposed in the chip region 10 and include a plurality of circuit pattern layers m1, m2, m3, m4, and m5 spaced apart from each other. The plurality of circuit pattern layers m1, m2, m3, m4, and m5 may be arranged in a direction (e.g., z direction) perpendicular to or substantially perpendicular to the top surface 1001S of the substrate 1001. The plurality of interlayer vias v1, v2, v3, and v4 may electrically connect the plurality of circuit pattern layers m1, m2, m3, m4, and m5 to each other. Each of the plurality of circuit pattern layers m1, m2, m3, m4, and m5 and each of the plurality of interlayer vias v1, v2, v3, and v4 may include, for example, tungsten (W), tungsten nitride, titanium (Ti), titanium nitride, aluminum (Al), copper (Cu), or any combination of two or more thereof.

[0035] The circuit pattern structure 1100 may be an electrical wiring connected to an integrated circuit driving the semiconductor chip E. Figure 3 and Figure 4The first to fifth circuit pattern layers m1, m2, m3, m4 and m5 and the first to fourth interlayer vias v1, v2, v3 and v4 are shown as examples of multiple circuit pattern layers m1, m2, m3, m4 and m5 and multiple interlayer vias v1, v2, v3 and v4, but the embodiments of the present disclosure are not necessarily limited thereto, and various other numbers of circuit pattern layers and interlayer vias are possible.

[0036] The ground connection via 160 may be provided to connect the top layer (ie, the fifth circuit pattern layer m5) of the circuit pattern structure 1100 to the first redistribution layer 141. The ground connection via 160 may electrically connect the ground voltage supply line Va to the circuit pattern structure 1100. Therefore, the circuit pattern structure 1100 may maintain a ground state within the semiconductor chip E.

[0037] Reference Figure 3 and Figure 4 , the chip protection structure 2100 may be disposed in the chip sealing region 20. The chip protection structure 2100 may be disposed to surround the chip region 10 over the substrate 1001. That is, the chip protection structure 2100 may be disposed in a fence shape to surround the chip region 10. As an example, the chip protection structure 2100 may include a protection ring.

[0038] The chip protection structure 2100 may include a plurality of protection metal layers g1, g2, g3, g4, and g5 disposed on the substrate 1001 and spaced apart from each other in a direction perpendicular to or substantially perpendicular to the surface of the substrate 1001. The chip protection structure 2100 may also include a plurality of metal-to-metal contact layers gc1, gc2, gc3, and gc4 connecting the plurality of protection metal layers g1, g2, g3, g4, and g5 to each other, and a lower contact layer gc0 connecting the bottom protection metal layer g1 of the plurality of protection metal layers g1, g2, g3, g4, and g5 to the ground well 1001W of the substrate 1001. In some embodiments, the chip protection structure 2100 may include a gate structure GT. The gate structure GT may include a gate dielectric layer (not shown) and a gate electrode layer (not shown) sequentially disposed on the substrate 1001.

[0039] Each of the multiple protective metal layers gl, g2, g3, g4 and g5, each of the multiple metal inter-contact layers gcl, gc2, gc3 and gc4, and the lower contact layer gc0 may include, for example, tungsten (W), tungsten nitride, titanium (Ti), titanium nitride, aluminum (Al), copper (Cu), or any combination of two or more thereof.

[0040] Figure 3 and Figure 4The first to fifth protective metal layers gl, g2, g3, g4 and g5 and the first to fourth metal contact layers gc1, gc2, gc3 and gc4 are shown as multiple protective metal layers gl, g2, g3, g4 and g5 and multiple metal contact layers gc1, gc2, gc3 and gc4, respectively, but the embodiments of the present disclosure are not necessarily limited to this, and multiple numbers of protective metal layers and multiple numbers of metal contact layers are possible.

[0041] The ground well 1001W of the substrate 1001 may receive a ground voltage through a ground contact (not shown) connected to the ground well 1001W. The ground contact (not shown) may receive a ground voltage from an external device through various wirings inside the semiconductor chip E. The ground well 1001W may maintain a grounding state within the semiconductor chip E. In an embodiment, when the substrate 1001 is a p-type doped substrate, the ground well 1001W may be a p-type well having a higher doping concentration than the substrate 1001.

[0042] The chip protection structure 2100 may be used as a barrier structure to block and prevent external moisture from penetrating into the integrated circuit (e.g., the circuit pattern structure 1100) of the chip region 10. The chip protection structure 2100 may be electrically connected to the ground well 1001W of the substrate 1001. The chip protection structure 2100 may maintain an electrical grounding state within the semiconductor chip E.

[0043] Reference Figure 3 and Figure 4 , in the chip sealing region 20 having a predetermined width W, the upper protection line 130 may be disposed to be spaced apart from the chip protection structure 2100 in an upward direction of the chip protection structure 2100. The upper protection line 130 may be physically separated from the chip protection structure 2100. In addition, the upper protection line 130 may be disposed to overlap the chip protection structure 2100 in a direction perpendicular or substantially perpendicular to the surface 1001S of the substrate 1001 (i.e., the z direction).

[0044] In an embodiment, over the substrate 1001, a conductive connection component connecting the upper protection line 130 to the chip protection structure 2100 may not be disposed in the interlayer insulating layer 4000 between the upper protection line 130 and the chip protection structure 2100. The conductive connection component may include, for example, a contact pattern, a through hole, etc. In the present specification, the interlayer insulating layer 4000 may be a single layer or a structure in which a plurality of insulating layers are sequentially stacked.

[0045] Reference Figure 3, the conductive connection pattern 150 may be provided to cross the chip region 10 and the chip sealing region 20. The conductive connection pattern 150 may connect the first redistribution layer 141 to the upper protection line 130 on the surface 4000S of the interlayer insulating layer 4000. Therefore, the upper protection line 130 may receive the ground voltage provided from the ground pad 110. That is, the upper protection line 130 may maintain the ground state within the semiconductor chip E. Referring to Figure 4 , the upper protection line 130 may be disposed on the surface 4000S of the interlayer insulating layer 4000 to be spaced apart from the operation voltage pad 120 of the chip region 10 and the second redistribution layer 142 .

[0046] Reference Figures 2 to 4 , the scribe area 30 may be disposed outside the chip sealing area 20. In an embodiment, as Figure 3 and Figure 4 As shown, the test pattern structure 3100 may be disposed in the scribe lane region 30. The test pattern structure 3100 may include, for example, a plurality of conductive patterns z1, z2, z3, z4, and z5. The plurality of conductive patterns z1, z2, z3, z4, and z5 may constitute a variety of electrical test circuits or process monitoring patterns.

[0047] As described above, according to an embodiment of the present disclosure, the semiconductor chip E may include a chip protection structure 2100 and an upper protection line 130 disposed in the chip sealing region 20 and protecting the chip region 10 from external moisture. The upper protection line 130 may be disposed above the chip protection structure 2100. The upper protection line 130 may be disposed spaced apart from the chip protection structure 2100 in a direction perpendicular to or substantially perpendicular to the top surface 1001S of the substrate 1001. The chip protection structure 2100 may be connected to a ground well 1001W of the substrate 1001 to maintain a grounded state, and the upper protection line 130 may be connected to a ground voltage supply line Va disposed in the chip region 10 to maintain a grounded state. The conductive connection component that connects the chip protection structure 2100 to the upper protection line 130 may not be disposed in the interlayer insulating layer 4000 between the chip protection structure 2100 and the upper protection line 130.

[0048] Figure 5 is a plan view schematically showing a semiconductor chip F according to a first comparative example of the present disclosure. Figure 6 yes Figure 5 The semiconductor chip F shown is a cross-sectional view taken along line III-III'. Figure 7 is a cross-sectional view showing a semiconductor chip F′ according to a second comparative example of the present disclosure. Figure 7 The semiconductor chip F' is Figure 5 and Figure 6 A modified example of the semiconductor chip F is shown.

[0049] Reference Figure 5 and Figure 6 , the semiconductor chip F includes a chip protection structure 2100 and an upper protection line 130 that protect the chip region 10 from external moisture. The upper protection line 130 of the semiconductor chip F is not electrically connected to the ground voltage supply line Va or the operating voltage supply line Vb. In addition, the upper protection line 130 is not electrically connected to the chip protection structure 2100 that maintains an electrically grounded state. Therefore, the upper protection line 130 of the semiconductor chip F can maintain an electrically floating state within the semiconductor chip F. However, when the upper protection line 130, which serves as a blocking structure surrounding the chip region 10, maintains an electrically floating state, the upper protection line 130 may be electrically unstable. When an overvoltage or an overcurrent is supplied to the upper protection line 130, the upper protection line 130 may be susceptible to electrical damage caused by the overvoltage or the overcurrent. That is, unlike the chip protection structure 2100 that maintains a grounded state, the upper protection line 130 that maintains an electrically floating state may be susceptible to electrical damage phenomena. Therefore, unlike the chip protection structure 2100 that maintains a grounded state, the upper protection line 130 that maintains an electrically floating state may be susceptible to electrical damage phenomena. Figures 2 to 4 The semiconductor chip F may have reduced electrical stability compared to the semiconductor chip E.

[0050] and Figure 5 and Figure 6 Compared with the semiconductor chip F, Figure 7 In the semiconductor chip F' of the embodiment of the present invention, the upper protection line 130 is electrically connected to the chip protection structure 2100 through the chip protection connection contact 170. Therefore, the upper protection line 130 is electrically connected to the ground well 1001W to maintain an electrically grounded state. However, compared with the semiconductor chip E as an embodiment of the present disclosure, the upper protection line 130 of the semiconductor chip F' may be connected to the ground voltage supply line (e.g., Figure 5 Va) in is electrically open.

[0051] The chip protection connection contact 170 is disposed between the chip protection structure 2100 and the upper protection line 130 in the chip sealing region 20, and is disposed in a fence shape surrounding the chip region 10. However, since the chip protection connection contact 170 is disposed directly above the chip protection structure 2100, the chip protection connection contact 170 may apply stress to the chip protection structure 2100. Due to the applied stress, delamination and cracking phenomena may occur in the interlayer insulating layer 4000 adjacent to the chip protection structure 2100. In addition, when a subsequent heat treatment is performed, a defect may occur in which a metal pattern layer located near a region where the delamination phenomenon and the cracking phenomenon occur is partially melted.

[0052] As mentioned above, Figure 6 Compared with the semiconductor chip F, Figure 7 The semiconductor chip F' can prevent the upper protection line 130 from floating and becoming electrically unstable, but due to the stress applied downward by the chip protection connection contact 170, Figure 7Structural defects may occur in the chip sealing region 20 of the semiconductor chip F′.

[0053] On the other hand, according to an embodiment of the present disclosure, the upper protection line 130 of the semiconductor chip E may be electrically connected to the ground voltage supply line Va of the chip region 10 and spaced apart from the chip protection structure 2100. Figure 6 Compared with the semiconductor chip F of FIG. 1 , the electrical stability of the upper protection line 130 in the chip sealing area 20 can be improved, and Figure 7 Compared with the semiconductor chip F′, the structural stability of the chip protection structure 2100 in the chip sealing area 20 can be improved.

[0054] Figure 8 is a plan view schematically showing a semiconductor chip G according to another embodiment of the present disclosure. Fig. 9 yes Figure 8 The semiconductor chip G shown is a cross-sectional view taken along line IV-IV'. Fig.10 yes Figure 8 The semiconductor chip G shown is a cross-sectional view taken along the line V-V'. The semiconductor chip G may correspond to the semiconductor chip G shown in FIG. Figure 1 One of the plurality of semiconductor chips A, B, C and D described.

[0055] Reference Figures 8 to 10 , the semiconductor chip G can be connected with Figures 2 to 4 The difference between the semiconductor chip E of FIG. 1 and FIG. 2 is that the semiconductor chip G has an upper protection line 130 electrically connected to the operating voltage supply line Vb. The operating voltage provided by the operating voltage supply line Vb is applied to drive or operate the semiconductor chip G and may include a voltage greater than 0 V. For example, the upper protection line 130 may be electrically insulated from the ground voltage supply line Va.

[0056] Now refer to Figures 8 to 10 , the upper protection line 130 may be connected to the second redistribution layer 142 through the conductive connection pattern 180. When the second redistribution layer 142 is connected to the operating voltage pad 120, the upper protection line 130 may maintain the operating voltage provided by the operating voltage supply line Vb. The conductive connection pattern 180 may be disposed on the interlayer insulating layer 4000 across the chip region 10 and the chip sealing region 20.

[0057] As described above, the upper protection line 130 may be disposed to be spaced apart from the chip protection structure 2100 disposed below the upper protection line 130, and a conductive connection component connecting the upper protection line 130 to the chip protection structure 2100 may not be disposed. The upper protection line 130 may escape from an electrically floating state by maintaining an operating voltage provided by the operating voltage supply line Vb. As a result, in the semiconductor chip G, the electrical stability of the upper protection line 130 and the structural stability of the chip protection structure 2100 may be improved together.

[0058] Fig.11 is a plan view schematically showing a semiconductor chip H according to another embodiment of the present disclosure. Fig.12 yes Fig.11 The semiconductor chip H shown is a cross-sectional view taken along line VI-VI'. Fig.13 yes Fig.11 The semiconductor chip H shown is a cross-sectional view taken along line VII-VII'. The semiconductor chip H may correspond to the semiconductor chip H shown in FIG. Figure 1 One of the plurality of semiconductor chips A, B, C and D described.

[0059] Reference Figures 11 to 13 , the semiconductor chip H can be connected with Figures 2 to 4 The semiconductor chip H is different from the semiconductor chip E in that the semiconductor chip H has upper protection lines 130 electrically connected to the voltage supply lines Va and Vb, respectively.

[0060] Reference Fig.11 , the upper protection line 130 may include a first upper protection layer 130a and a second upper protection layer 130b separated from each other. That is, in the upper protection line 130 disposed along the periphery of the chip region 10, a disconnection portion CP where the first upper protection layer 130a and the second upper protection layer 130b are disconnected from each other may occur. The interlayer insulating layer 4000 may be disposed in the disconnection portion CP. Therefore, the first upper protection layer 130a and the second upper protection layer 130b may be electrically insulated from each other.

[0061] Reference Figures 11 to 13 , the first upper protective layer 130a may be electrically connected to the ground voltage supply line Va through the first conductive connection pattern 150 formed on the surface 4000S of the interlayer insulating layer 4000. The first conductive connection pattern 150 may connect the first upper protective layer 130a to the first redistribution layer 141. When the first redistribution layer 141 is connected to the ground pad 110, the first upper protective layer 130a may receive the ground voltage. In addition, the second upper protective layer 130b may be electrically connected to the operating voltage supply line Vb through the second conductive connection pattern 180 on the surface 4000S of the interlayer insulating layer 4000. The second conductive connection pattern 180 may connect the second upper protective layer 130b to the second redistribution layer 142. When the second redistribution layer 142 is connected to the operating voltage pad 120, the second upper protective layer 130b may receive the operating voltage.

[0062] Reference Fig.12 and Fig.13, the first upper protective layer 130a and the second upper protective layer 130b may be spaced apart from the chip protection structure 2100 disposed below the first upper protective layer 130a and the second upper protective layer 130b. In addition, a conductive connection component connecting the first upper protective layer 130a and the second upper protective layer 130b to the chip protection structure 2100 may not be formed. In addition, the first upper protective layer 130a may maintain a ground voltage through the ground voltage supply line Va, and the second upper protective layer 130b may maintain an operating voltage through the operating voltage supply line Vb. As a result, in the semiconductor chip H, the electrical stability of the first upper protective layer 130a and the second upper protective layer 130b and the structural stability of the chip protection structure 2100 may be improved.

[0063] As described above, the technical concept of the present invention has been disclosed in conjunction with some embodiments. It will be appreciated by those skilled in the art that multiple modifications, additions and substitutions are possible without departing from the scope of the present disclosure. Therefore, the embodiments disclosed in this specification should not be considered restrictive, but exemplary. The scope of the concept is not limited to the above description, but is defined by the appended claims, and all distinctive features within the equivalent scope should be interpreted as being included in the concept. In addition, these embodiments can be combined to form additional embodiments.

Claims

1. A semiconductor chip, comprising: A chip region and a chip sealing region disposed in the substrate; a circuit pattern structure, which is arranged in the chip area; a chip protection structure, which is disposed in the chip sealing area and surrounds the chip area; a voltage supply line which is provided above the circuit pattern structure in the chip region and supplies a predetermined voltage to the circuit pattern structure; as well as An upper protection line is disposed above the chip protection structure in the chip sealing region and is electrically connected to the voltage supply line.

2. The semiconductor chip according to claim 1, wherein: The upper protection line is arranged to surround the chip region. 3 . The semiconductor chip according to claim 1 , further comprising a conductive connection pattern connecting the voltage supply line to the upper protection line.

4. The semiconductor chip according to claim 1, wherein: The voltage supply line and the upper protection line are located on substantially the same plane over the substrate.

5. The semiconductor chip according to claim 1, wherein: The voltage supply line and the upper protection line include substantially the same material.

6. The semiconductor chip according to claim 1, in, The chip protection structure is arranged to surround the chip area, and The upper protection line is arranged to overlap with the chip protection structure in a direction perpendicular or substantially perpendicular to the surface of the substrate.

7. The semiconductor chip according to claim 1, wherein: The upper protection line is physically separated from the chip protection structure.

8. The semiconductor chip according to claim 1, wherein: The voltage supply line comprises: a power pad that receives the predetermined voltage from an external device; and A redistribution layer extends from the power pad.

9. The semiconductor chip according to claim 8, wherein: The power pad includes a ground pad or an operating voltage pad.

10. The semiconductor chip according to claim 1, wherein The voltage supply line comprises: a ground pad that receives a ground voltage from an external device; an operating voltage pad receiving an operating voltage from the external device; a first redistribution layer extending from the ground pad; and A second redistribution layer extends from the operating voltage pad.

11. The semiconductor chip according to claim 10, in, The upper protection line includes a first upper protection layer and a second upper protection layer separated from each other, wherein the first upper protection layer is electrically connected to the first redistribution layer, and Wherein, the second upper protection layer is electrically connected to the second redistribution layer.

12. The semiconductor chip according to claim 11, further comprising: a first conductive connection pattern connecting the first upper protection layer and the first redistribution layer to each other; as well as A second conductive connection pattern connects the second upper protection layer and the second redistribution layer to each other.

13. The semiconductor chip according to claim 1, wherein: The chip protection structure comprises: at least two protective metal layers disposed on the surface of the substrate and spaced apart from each other in a direction perpendicular or substantially perpendicular to the surface of the substrate; an intermetallic contact layer connecting the at least two protective metal layers to each other; and A lower contact layer connects the lowest protection metal layer of the at least two protection metal layers and a ground well of the substrate to each other.

14. A semiconductor chip, comprising: A substrate comprising a chip region and a chip sealing region located outside the chip region; a chip protection structure, which is arranged in the chip sealing area to surround the chip area; a voltage supply line disposed in the chip region; as well as An upper protection line is disposed in the chip sealing region over the substrate, is spaced apart from the chip protection structure, is electrically insulated from the chip protection structure, and is electrically connected to the voltage supply line.

15. The semiconductor chip according to claim 14, wherein: The voltage supply line and the upper protection line are located on substantially the same plane over the substrate. 16 . The semiconductor chip according to claim 15 , further comprising a conductive connection pattern connecting the voltage supply line to the upper protection line. 17 . The semiconductor chip according to claim 14 , further comprising a circuit pattern structure provided in the chip region to receive a predetermined voltage from the voltage supply line.

18. The semiconductor chip according to claim 14, wherein: The upper protection line is disposed to overlap the chip protection structure in a direction perpendicular or substantially perpendicular to a surface of the substrate.

19. The semiconductor chip according to claim 14, wherein: The voltage supply line comprises: a power pad that receives a predetermined voltage from an external device; and A redistribution layer extends from the power pad.

20. The semiconductor chip according to claim 19, wherein The power pad includes a ground pad or an operating voltage pad.

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