Electronic device and method of manufacturing same

Abstract

An electronic device and a method of manufacturing the electronic device. In one example, an electronic device includes a substrate including: a substrate interior side; the substrate outer side is opposite to the substrate inner side; a substrate lateral side connecting the substrate inner side to the substrate outer side; a dielectric structure; a conductive structure; and a substrate interior reinforcement at the inner side of the substrate. An electronic component is coupled to the conductive structure and includes a lower side proximate an inner side of the substrate, an upper side opposite the lower side, and a lateral side connecting the lower side to the upper side. An underfill is between the underside of the electronic component and the substrate interior side and covers the substrate interior reinforcement. An encapsulant covers a portion of the inner side of the substrate, a portion of the underfill, and a portion of the first electronic component. Other examples and related methods are also disclosed herein.

Description

Technical Field

[0001] The present disclosure relates generally to electronic devices, and more particularly, to semiconductor devices and methods for fabricating semiconductor devices. Background Art

[0002] Previous semiconductor packages and methods for forming semiconductor packages are inadequate, for example, resulting in excessive cost, reduced reliability, relatively low performance, or excessive package size. Other limitations and disadvantages of conventional and traditional methods will become apparent to those skilled in the art by comparing such methods with the present disclosure and referring to the drawings. Summary of the invention

[0003] This specification includes structures and associated methods and other features related to electronic devices with 3D wafer-level packaging. More specifically, structures and methods are described that improve the reliability of wafer-level substrates, such as redistribution layer (RDL) substrates used in fine-pitch fan-out configurations. In some instances, one or more substrate stiffeners are used to reduce distortion, module bending, and stress-related defects such as cracks. In some instances, the substrate external stiffeners can provide a stopper function that reduces unwanted bending when the electronic device is attached to the next level assembly. In practice, it has been found that the structure and method increase the mechanical strength by 1.5 to 2 times compared to previous electronic devices.

[0004] In an example, an electronic device includes a substrate, the substrate including: a substrate inner side; a substrate outer side, which is opposite to the substrate inner side; a substrate lateral side, which connects the substrate inner side to the substrate outer side; a dielectric structure; a conductive structure, the conductive structure including a substrate inward terminal adjacent to the substrate inner side and a substrate outward terminal adjacent to the substrate outer side; and a substrate inner reinforcement, which is at the substrate inner side. A first electronic component is coupled to the substrate inward terminal and includes a first lower side proximate to the substrate inner side, a first upper side opposite to the first lower side, and a first lateral side connecting the first lower side to the first upper side. An underfill is between the first lower side of the first electronic component and the substrate inner side and covers the substrate inner reinforcement. An encapsulant covers a portion of the substrate inner side, a portion of the underfill, and a portion of the first electronic component.

[0005] In an example, an electronic device includes a substrate, the substrate including: a substrate inner side; a substrate outer side, which is opposite to the substrate inner side; a substrate lateral side, which connects the substrate inner side to the substrate outer side; a dielectric structure; a conductive structure, the conductive structure including a substrate inner terminal adjacent to the substrate inner side and a substrate outer terminal adjacent to the substrate outer side; and a substrate internal reinforcement adjacent to the substrate inner side. A first electronic component is coupled to the substrate inner terminal and includes a first lower side proximate to the substrate inner side, a first upper side opposite to the first lower side, and a first lateral side connecting the first lower side to the first upper side. A second electronic component is coupled to the substrate inner terminal, is laterally spaced apart from the first electronic component, and includes a second lower side, a second upper side opposite to the second lower side, and a second lateral side connecting the second lower side to the second upper side. An encapsulant covers a portion of the substrate inner side, a portion of the first electronic component, and a portion of the second electronic component.

[0006] In an example, a method of manufacturing an electronic device includes providing a substrate, the substrate including: a substrate inner side; a substrate outer side, which is opposite to the substrate inner side; a substrate lateral side, which connects the substrate inner side to the substrate outer side; a dielectric structure; a conductive structure, the conductive structure including a substrate inner terminal adjacent to the substrate inner side and a substrate outer terminal adjacent to the substrate outer side; and a substrate inner stiffener coupled to the substrate inner side. The method includes coupling a first electronic component to the substrate inner terminal, the first electronic component including a first lower side proximate to the substrate inner side, a first upper side opposite to the first lower side, and a first lateral side connecting the first lower side to the first upper side. The method includes providing a first underfill between the first lower side of the first electronic component and the substrate inner side and covering the substrate inner stiffener. The method includes providing an encapsulant, the encapsulant covering at least a portion of the substrate inner side, at least a portion of the first underfill, and at least a portion of the first electronic component. The method includes providing an external stiffener structure coupled to the substrate outer side. The method includes providing an external interconnect coupled to the substrate outer side.

[0007] Other examples are included in the present disclosure. Such examples can be found in the drawings, in the claims, or in the description of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A A cross-sectional view of an example electronic device is shown.

[0009] Figure 1B A top view of an example electronic device is shown.

[0010] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F and Figure 2GA cross-sectional view illustrating an example method for manufacturing an example electronic device.

[0011] Figure 3A , Figure 3B and Figure 3C A cross-sectional view illustrating an example method for manufacturing an example electronic device.

[0012] Figure 4A A cross-sectional view of an example electronic device is shown.

[0013] Figure 4B A cross-sectional view of an example electronic device is shown.

[0014] Figure 4C A top view of an example electronic device is shown.

[0015] The following discussion provides various examples of semiconductor devices and methods of manufacturing semiconductor devices. Such examples are non-limiting, and the scope of the appended claims should not be limited to the specific examples disclosed. In the following discussion, the terms "example" and "for example" are non-limiting.

[0016] Each figure illustrates a general construction method, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessary confusion of the present disclosure. In addition, the elements in the figures are not necessarily drawn to scale. For example, the size of some elements in each figure may be enlarged relative to other elements to help improve the understanding of the examples discussed in the present disclosure. The same reference numerals in different figures represent the same elements.

[0017] The term "or" means any one or more of the items in the list connected by "or". As an example, "x or y" means any one of the three-element set {(x), (y), (x, y)}. As another example, "x, y or z" means any one of the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}.

[0018] The terms “comprises / comprising” and / or “includes / including” are “open” terms and specify the presence of stated features but do not preclude the presence or addition of one or more other features.

[0019] The terms "first", "second", etc. may be used herein to describe various elements, and these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, for example, a first element discussed in the present disclosure may be referred to as a second element without departing from the teachings of the present disclosure.

[0020] Unless otherwise specified, the term "coupled" may be used to describe two elements that are in direct contact with each other or to describe two elements that are indirectly connected through one or more other elements. For example, if element A is coupled to element B, element A may be in direct contact with element B or indirectly connected to element B by an intervening element C. Similarly, the terms "above" or "on" may be used to describe two elements that are in direct contact with each other or to describe two elements that are indirectly connected by one or more other elements. As used herein, the term "coupled" may refer to electrical coupling or mechanical coupling. DETAILED DESCRIPTION

[0021] Figure 1A A cross-sectional view of an example electronic device 100 is shown and Figure 1B 1 shows a top view of an example electronic device 100. Figure 1A and Figure 1B In the example shown in , the electronic device 100 may include a substrate 110 , an electronic component 120 , an electronic component 120 ′, an underfill 130 , an encapsulant 140 , and an external interconnect 150 .

[0022] In this example, the substrate 110 may include a substrate inner side 110a, a substrate outer side 110b opposite to the substrate inner side 110a, a dielectric structure 111, a conductive structure 112, a substrate inner reinforcement 113 adjacent to the substrate inner side 110a, and an outer reinforcement structure 114 adjacent to the substrate outer side 110b.

[0023] In some examples, conductive structure 112 may include substrate inward terminals 112a proximate substrate inner side 110a and substrate outward terminals 112b proximate substrate outer side 110b. Substrate inward terminals 112a may also be referred to as inner contact pads, and substrate outward terminals 112b may also be referred to as outer contact pads.

[0024] In some examples, the electronic component 120 includes an upper side 120a, a lower side 120b opposite to the upper side 120a, and a lateral side 120c connecting the upper side 120a and the lower side 120b. In this example, the lower side 120b of the electronic component 120 can be coupled to the conductive structure 112 through the component interconnect 121. In some examples, the electronic component 120' can be coupled to the conductive structure 112 through the component interconnect 121'. In some examples, the bottom filler 130 can be inserted between the lower side 120b of the electronic component 120 and the substrate 110, can surround the component interconnect 121, can cover all or part of the lateral side 120c of the electronic component 120, or can cover the exposed portion of the substrate internal reinforcement 113. In some examples, the bottom filler 130 can be inserted between the lower side of the electronic component 120 and the substrate 110, can surround the component interconnect 121', and can cover all or part of the lateral side of the electronic component 120'. In some examples, the encapsulant 140 is disposed at the periphery or edge portion of the substrate 110 to at least partially encapsulate or cover the electronic components 120 and the electronic components 120'. In some examples, portions of the electronic components 120 (e.g., the upper side 120a) and the electronic components 120' are exposed from the encapsulant 140 outside the electronic device 100. In other examples, the encapsulant 140 may overlap and cover the upper side 120a of the electronic components 120 and the upper side of the electronic components 120'. The external interconnect 150 may be coupled to the substrate-outward terminal 112b.

[0025] Substrate 110, substrate internal reinforcement 113, external reinforcement structure 114, bottom fill 130, encapsulant 140, and external interconnect 150 may be referred to as an electronic package or package. The electronic package may protect electronic components 120 and 120' from being exposed to external elements and / or the environment. The electronic package may also provide electrical coupling between electronic components 120 and 120' and between electronic components 120 and 120' and external components or other electronic packages.

[0026] Figure 2A to Figure 2G Shown are methods for making example electronic devices, such as Figure 1A and Figure 1B 00 is a cross-sectional view of an example method of an electronic device 100 as illustrated in FIG.

[0027] Figure 2A is a cross-sectional view of electronic device 100 at an early stage of manufacture. Figure 2A In the example shown in FIG. 1 , the substrate 110 and the substrate internal reinforcement 113 may be disposed on a carrier 160. In the present example, the substrate 110 is shown as a redistribution layer (RDL) substrate.

[0028] The RDL substrate may include one or more conductive redistribution layers (e.g., conductive structure 112) and one or more dielectric layers (e.g., dielectric structure 111), which may be (a) formed layer by layer over an electronic device to which the RDL substrate is electrically coupled, or (b) formed layer by layer over a carrier that may be completely or at least partially removed after the electronic device and the RDL substrate are coupled together as in this example. The RDL substrate may be manufactured layer by layer as a wafer-level substrate on a circular wafer with a wafer-level process, and / or manufactured layer by layer as a panel-level substrate on a rectangular or square panel carrier with a panel-level process.

[0029] The RDL substrate can be formed by an additive deposition process, which can include alternating one or more dielectric layers with one or more conductive layers defining corresponding conductive redistribution patterns or traces, which are configured to collectively (a) fan the electrical traces out of the footprint of the electronic device, and / or (b) fan the electrical traces into the footprint of the electronic device. The conductive pattern can be formed using a plating process such as an electroplating process or an electroless plating process. The conductive pattern can include a conductive material, such as copper or other plateable metal. The location of the conductive pattern can be manufactured using a photopatterning process, such as a photolithography process and a photoresist material used to form a photolithography mask.

[0030] The dielectric layer of the RDL substrate can be patterned using a photopatterning process that can include a photolithographic mask through which light is exposed to the desired features of the photopattern, such as through holes in the dielectric layer. The dielectric layer can be made of a photo-definable organic dielectric material such as polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO). Such dielectric materials can be spin-coated or otherwise applied in liquid form rather than attached as a preformed film. In order to allow the desired photo-defined features to be properly formed, such photo-definable dielectric materials can omit structural reinforcements, or can be filler-free and free of strands, woven fabrics, or other particles that may interfere with the light from the photopatterning process. In some instances, such filler-free properties of filler-free dielectric materials can reduce the thickness of the resulting dielectric layer.

[0031] Although the photo-definable dielectric material described above may be an organic material, in other examples, the dielectric material of the RDL substrate may include one or more inorganic dielectric layers. Some examples of inorganic dielectric layers may include silicon nitride (Si3N4), silicon oxide (SiO2) and / or SiON. The inorganic dielectric layer may be formed not by using a photo-defined organic dielectric material but by growing the inorganic dielectric layer using an oxidation or nitridation process. Such inorganic dielectric layers may be filler-free without strands, woven fabrics or other different inorganic particles. In some examples, the RDL substrate may omit a permanent core structure or carrier, such as a dielectric material including bismaleimide triazine (BT) or FR4, and these types of RDL substrates may be referred to as coreless substrates. The substrate 110 as disclosed herein may include and be referred to as an RDL substrate.

[0032] In an example manufacturing method, a carrier 160 may be provided. In some examples, the carrier 160 may be provided as a circular wafer in a wafer level process, or as a panel level substrate in a panel level process on a rectangular or square panel carrier. In some examples, the carrier 160 may include silicon, glass, ceramic, or other materials known to those of ordinary skill in the art. In some examples, the carrier 160 includes one or more materials selected to provide the external reinforcement structure 114. The carrier 160 may also be referred to as a support carrier or a support structure.

[0033] In an example manufacturing method, a substrate 110 may be provided on a carrier 160 in a build-up process (as previously described) to provide a dielectric structure 111 and a conductive structure 112 in a staggered configuration. In some examples, the substrate 110 may have an area of ​​about 8 millimeters (mm)×8 mm to about 150 mm×150 mm. In some examples, the substrate 110 may have a thickness of about 10 μm to about 1000 μm.

[0034] In some instances, the dielectric structure 111 may include or be referred to as one or more dielectrics, dielectric materials, dielectric layers, passivation layers, insulating layers, or protective layers. In some instances, the dielectric structure 111 may have a structure in which one or more dielectric layers are stacked. In some instances, the dielectric structure 111 may include a polymer, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), a molding material, a phenolic resin, an epoxy resin, a silicone resin, or an acrylate polymer. The dielectric structure 111 may be in contact with the conductive structure 112. The dielectric structure 111 may expose a portion of the conductive structure 112. In some instances, the dielectric structure 111 may maintain the outer shape of the substrate 110, and may structurally support the conductive structure 112 and the electronic components 120 and 120'.

[0035] In some examples, the dielectric structure 111 may be provided by spin coating, spray coating, printing, oxidation, PVD, CVD, MOCVD, ALD, LPCVD, PECVD, or other processes known to those of ordinary skill in the art. The upper side and the lower side of the dielectric structure 111 may be a portion of the substrate inner side 110a and the substrate outer side 110b of the substrate 110, respectively. In some examples, the thickness of each layer of the dielectric structure 111 may be in the range of about 1 μm to about 10 μm. The combined thickness of all layers of the dielectric structure 111 may define the thickness of the substrate 110. In some examples, the total thickness of the dielectric structure 111 may range from about 10 μm to about 1000 μm.

[0036] In some examples, conductive structure 112 may include or be referred to as one or more conductors, conductive materials, conductive paths, conductive layers, redistribution layers (RDLs), routing layers, traces, vias, pads, liners, or under bump metallization (UBMs). In some examples, substrate-inward terminal 112a may also be referred to as a pad, pad, UBM, or stud, and substrate-outward terminal 112b may be referred to as a two-step pad, pad, or pad.

[0037] In some examples, the conductive structure 112 may include copper, aluminum, palladium, titanium, tungsten, titanium / tungsten, nickel, gold, silver, or tin / silver. The conductive structure 112 may be formed by sputtering, electroless plating, electroplating, physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), or other processes known to those of ordinary skill in the art. In some examples, a portion of the conductive structure 112 may be exposed from the substrate inner side 110a of the substrate 110 and from the substrate outer side 110b. The substrate inner side 110a may also be referred to as the substrate top side 110a, and the substrate outer side 110b may also be referred to as the substrate bottom side 110b. In some examples, the thickness of each layer or portion of the conductive structure 112 may be in the range of 1 μm to about 10 μm.

[0038] In some instances, substrate inward terminals 112a are not coplanar with substrate inner side 110a, but may protrude outward from dielectric structure 111 at substrate inner side 110a. In some instances, the lateral sides or edges of substrate inward terminals 112a are free of dielectric material. In some instances, substrate inward terminals 112a may protrude outward and toward electronic component 120 or electronic component 120'. Substrate outward terminals 112b may be coupled to traces or vias inside dielectric structure 111. In some instances, traces or vias couple substrate outward terminals 112b to substrate inward terminals 112a. In some instances, substrate outward terminals 112b may be substantially coplanar with dielectric structure 111 at substrate outer side 110b. As described above, the substrate 110 including the dielectric structure 111 and the conductive structure 112 may support the electronic components 120 and 120 ′, and may couple the electronic components 120 and 120 ′ and an external device to each other (including electrical coupling or mechanical coupling).

[0039] In other examples, the substrate 110 may include a preformed substrate. The preformed substrate may be manufactured before being attached to the electronic device and may include a dielectric layer between the corresponding conductive layers. The conductive layer may include copper and may be formed using an electroplating process. The dielectric layer may be a relatively thick non-photodefinable layer and may be attached in a preformed film form rather than in a liquid form, and may include a resin having fillers such as strands, woven fabrics or other inorganic particles for rigidity or structural support. Since the dielectric layer is non-photodefinable, features such as through holes or openings may be formed by using drilling or lasers. In some examples, the dielectric layer may include a prepreg material or an Ajinomoto stacked film (ABF). The preformed substrate may include a permanent core structure or carrier, such as a dielectric material including bismaleimide triazine (BT) or FR4, and the dielectric layer and the conductive layer may be formed on the permanent core structure. In other examples, the preformed substrate may be a coreless substrate omitting the permanent core structure, and the dielectric layer and the conductive layer may be formed on a sacrificial carrier and removed after the dielectric layer and the conductive layer are formed and before being attached to the electronic device. The preformed substrate may be referred to as a printed circuit board (PCB) or a laminate substrate. Such a preformed substrate may be formed by a semi-additive process or a modified semi-additive process. In other examples, the substrate 110 may include a multi-layer substrate or a molded lead frame.

[0040] Figure 2A A substrate internal reinforcement 113 is shown disposed on or adjacent to the substrate inner side 110a of the substrate 110. In some examples, a substrate internal reinforcement 113 coupled to the dielectric structure 111 at the substrate inner side 110a may be provided. In some examples, a substrate internal reinforcement 113 coupled to the conductive structure 112 at the substrate inner side 110a may be provided. In some examples and with reference to Figure 1B , a substrate internal reinforcement 113 may be provided that extends between the lateral sides 110c of the substrate 110 toward a lateral side 110d of the substrate 110 that is opposite to the lateral side 110c. In this configuration, the substrate internal reinforcement 113 is substantially perpendicular to the lateral sides 110c and the lateral sides 110d, and substantially parallel to the opposite lateral sides 110e and 110f. In some examples, one or more ends of the substrate internal reinforcement 113 are embedded from the lateral sides 110c and 110d, so that the substrate internal reinforcement 113 does not extend all the way to the lateral side 110c or the lateral side 110d. In some examples, the substrate internal reinforcement 113 is offset from the center of the substrate 110 toward the lateral side 110f. In some examples, the lateral sides 110c and 110d or the lateral sides 110e and 110f may be referred to as an opposite lateral side pair.

[0041] In some instances, the substrate internal reinforcement 113 may be provided in a substantially lateral form along the length direction and / or width direction of the substrate 110. In some instances, the substrate internal reinforcement 113 may include a substantially straight shape, wherein the sides and ends are substantially linear and free of corrugations. In other instances, the substrate internal reinforcement 113 may include a nonlinear shape, including a shape preselected to reduce stress within the electronic device 100. In some instances, the substrate internal reinforcement 113 may be provided on a portion of the substrate 110 corresponding to a boundary region between the electronic component 120 and the electronic component 120'. In some instances, the substrate internal reinforcement 113 may be coupled to (including electrically coupled to) the conductive structure 112. In some instances, the substrate internal reinforcement 113 may be coupled to a trace, a through hole, or a substrate external terminal 112b. In some instances, the substrate internal reinforcement 113 may be coupled (including mechanically coupled) to the dielectric structure 111. In some instances, the substrate internal reinforcement 113 may include or be referred to as a reinforcement, a first reinforcement, a bracket, a support, a reinforcement, a rib or a protrusion. In some instances, the substrate internal reinforcement 113 may include a conductor. In other instances, the substrate internal reinforcement 113 may include a dielectric. In some instances, the substrate internal reinforcement 113 may be provided by plating or depositing copper, copper alloy, aluminum, aluminum alloy, gold, gold alloy, silver, silver alloy, nickel, nickel alloy, palladium, palladium alloy, tin silver or another conductor on the substrate 110. In some instances, the substrate internal reinforcement 113 may be provided by coating, depositing or laminating a dielectric material or an inorganic material, such as polyimide (PI), benzocyclobutene (BCB) or polybenzoxazole (PBO), a resin or an ajinomoto deposited film (ABF) on the substrate 110.

[0042] In some examples, substrate inward terminal 112a and substrate inner reinforcement 113 may be provided simultaneously using a bump process. In some examples, when substrate inward terminal 112a coupled to conductive structure 112 is provided, substrate inner reinforcement 113 may also be provided. In some examples, similar to substrate inward terminal 112a, substrate inner reinforcement 113 may also be coupled to conductive structure 112.

[0043] In some examples, when the substrate internal reinforcement 113 includes a different material than the substrate inward terminal 112a, a different manufacturing process may be used to provide the substrate internal reinforcement 113. For example, when the substrate internal reinforcement 113 includes a dielectric material or an inorganic material, the substrate internal reinforcement 113 may be provided using a different material.

[0044] The substrate internal reinforcement 113 can provide increased structural integrity to inhibit or reduce twisting or bending of the substrate 110 or the electronic device 100 due to, for example, CTE differences. In some instances, the substrate internal reinforcement 113 can have a thickness (or height) of about 1 μm to about 100 μm. In some instances, the substrate internal reinforcement 113 can have a lateral width of about 300 μm to about 2500 μm. In some instances, the thickness of the substrate internal reinforcement 113 can be different from the thickness of the substrate inward terminal 112a. For example, the thickness of the substrate internal reinforcement 113 can be greater than or less than the thickness of the substrate inward terminal 112a. In some instances, the thickness, width, and length of the substrate internal reinforcement 113 can be pre-selected based on the stress reduction requirements of the electronic device 100.

[0045] Typically, during a high temperature process such as a reflow process, stress may accumulate or concentrate in a boundary region between the electronic component 120 and the electronic component 120' (e.g., accumulated in an underfill region) due to a difference in coefficient of thermal expansion (CTE) between the electronic component 120 and the electronic component 120', respectively, and the CTE of other components of the electronic device 100. The substrate internal reinforcement 113 may prevent or reduce the occurrence of, for example, cracking of the underfill 130. The substrate internal reinforcement 113 is configured to release stress at a stress accumulation point that may be formed between the electronic component 120 and the electronic component 120'. In addition, the substrate internal reinforcement 113 may provide increased structural integrity to inhibit or reduce distortion or bending of the substrate 110 or the electronic device 100 due to a CTE difference.

[0046] Figure 2B A cross-sectional view of the electronic device 100 is shown in a later stage of manufacturing. Figure 2B In the example shown in FIG. 1 , electronic components 120 and 120 ′, an underfill 130 , and an encapsulant 140 may be provided.

[0047] In an example manufacturing method, electronic components 120 and 120' may be provided on substrate 110. In some examples, electronic component 120' is laterally spaced apart from electronic component 120. Electronic component 120 may include upper side 120a, lower side 120b, and lateral side 120c, and electronic component 120' may include upper side 120a', lower side 120b', and lateral side 120c'. In some examples, lower side 120b and lower side 120b' include active surfaces of electronic components 120 and 120', respectively, and may face substrate 110. In some examples, upper side 120a and upper side 120a' include inactive surfaces of electronic components 120 and 120', respectively, and may face away from substrate 110. Lower side 120b and 120b' are close to substrate inner side 110a, and upper side 120a and 120a' are far from substrate inner side 110a.

[0048] In some instances, electronic components 120 and 120' may be coupled to conductive structures 112 of substrate 110. In some instances, electronic components 120 or 120' may each include or be referred to as a semiconductor die, a semiconductor chip, or a semiconductor package. A die or chip may include an integrated circuit die separated from a semiconductor wafer. Electronic components 120 and 120' may include a digital signal processor (DSP), a network processor, a power management unit, an audio processor, an RF circuit, a wireless baseband system-on-chip (SoC) processor, a sensor, a memory, and an application-specific integrated circuit (ASIC). For example, electronic component 120 may include a processor or an ASIC, and electronic component 120' may include a memory device, such as a package with stacked memory chips. In some instances, one or more of electronic components 120 or 120' may be an encapsulated semiconductor package having an encapsulation that may be similar to encapsulation 140. Electronic components 120 or 120' may include active or passive components. The electronic components 120 and 120' may have a thickness of about 20 μm to about 1000 μm. The electronic components 120 and 120' may perform calculation and control processing, store data, or remove noise from an electrical signal.

[0049] In some examples, electronic components 120 and 120' may include component terminals or bonding pads adjacent to lower sides 120b and 120b', and the component terminals may be electrically connected to substrate-inward terminals 112a of substrate 110 through component interconnects 121 and 121'. Component interconnects 121 and 121' may include or be referred to as bumps, pillars, pads, or solder balls. Component interconnects 121 and 121' may be provided as electrical contacts between electronic components 120 and 120' and substrate 110. Component interconnects 121 and 121' may be coupled to conductive structure 112. For example, component interconnects 121 and 121' may be coupled to internal contact pads 112a of conductive structure 112 through a mass reflow process, a thermal compression process, or a laser bonding process. In some examples, component interconnects 121 and 121' may include copper (Cu), lead (Pb), tin (Sn), aluminum (Al), palladium (Pd), titanium (Ti), tungsten (W), titanium / tungsten (Ti / W), nickel (Ni), gold (Au), or silver (Ag). In other examples, component interconnects 121 and 121' may be provided on the lower side 120b of electronic component 120 or the lower side 120b' of electronic component 120' by electroplating, electroless plating, sputtering, PVD, CVD, MOCVD, ALD, LPCVD, or PECVD. For example, after providing a photoresist pattern to expose bonding pads of electronic component 120 or electronic component 120', component interconnects 121 and 121' may be provided so as to contact the exposed bonding pads on the lower side 120b of electronic component 120 or to contact the exposed bonding pads on the lower side 120b' of electronic component 120'. The component interconnects 121 and 121 ′ may have a thickness and a diameter of about 1 μm to about 100 μm. The component interconnects 121 and 121 ′ may couple (including electrically or mechanically) the electronic components 120 and 120 ′ to the substrate 110 .

[0050] In an example manufacturing method, an underfill 130 may be provided between the substrate 110 and the electronic components 120 and 120'. In some examples, the underfill 130 may also be provided laterally between the electronic components 120 and 120'. In some examples, the underfill 130 may contact or cover the substrate 110 (e.g., the dielectric structure 111 or the conductive structure 112), the substrate inward terminals 112a, the substrate internal reinforcement 113, the electronic components 120 and 120', and / or the component interconnects 121 and 121'.

[0051] In some examples, after the electronic components 120 and 120' are coupled to the substrate 110, the underfill 130 may be injected into the gap between the electronic components 120 and 120' and the substrate 110. In other examples, before the electronic components 120 and 120' are connected to the substrate 110, the underfill 130 may be pre-applied to the substrate 110. Thus, the electronic components 120 and 120' may be pressed onto the underfill 130, while the component interconnects 121 and 121' may penetrate the underfill 130 to be electrically connected to the substrate 110. In some examples, before the electronic components 120 and 120' are connected to the substrate 110, the underfill 130 may be pre-applied to the electronic components 120 and 120'. Thus, the electronic components 120 and 120' may be pressed onto the underfill 130, while the component interconnects 121 and 121' may be electrically connected to the substrate 110. In some examples, a curing process (eg, a thermal curing process or a photocuring process) of the underfill 130 may be performed.

[0052] In some instances, the bottom filler 130 may include or be referred to as a capillary bottom filler (CUF), a molded bottom filler (MUF), a non-conductive paste (NCP), a non-conductive film (NCF), or an anisotropic conductive film (ACF). In some instances, the bottom filler 130 may include an epoxy resin, a thermoplastic material, a thermosetting material, a polyimide, a polyurethane, a polymeric material, a filled epoxy resin, a filled thermoplastic material, a filled thermosetting material, a filled polyimide, a filled polyurethane, a filled polymeric material, or a flux bottom filler. In some instances, the bottom filler 130 is inserted between the lower side 120b of the electronic component 120 and the lower side 120b' of the electronic component 120' and the inner side 110a of the substrate. In some instances, the bottom filler 130 may cover or surround the component interconnects 121 and 121'. In some examples, the bottom filler 130 contacts the substrate inner side 110a of the substrate 110 and the lower sides 120b and 120b' of the electronic components 120 and 120'. In some examples, the bottom filler 130 may cover all or part of the lateral side 120c of the electronic component 120 and the lateral side 120c' of the electronic component 120'. In some examples, the bottom filler 130 may prevent or reduce the occurrence of separation of the electronic components 120 and 120' from the substrate 110. In some examples, the thickness of the bottom filler 130 may be in the range of about 80 μm to about 800 μm.

[0053] In an example manufacturing method, an encapsulant 140 may be provided. In some examples, the encapsulant 140 may cover the substrate 110, the electronic components 120 and 120', and the bottom filler 130. In some examples, the encapsulant 140 may contact the substrate 110, the bottom filler 130, and the electronic components 120 and 120'. In some examples, the encapsulant 140 may include an epoxy or phenolic resin, carbon black, a silica filler, or other materials known to those of ordinary skill in the art. In some examples, the encapsulant 140 may include or be referred to as a body, a molding, a molding compound, a resin, a sealant, a filler-reinforced polymer, or an organic body.

[0054] In some examples, the encapsulant 140 may be on the lateral sides 120c and 120c' and the upper sides 120a and 120a' of the electronic components 120 and 120', respectively. In some examples, the upper sides 120a and 120a' of the electronic components 120 and 120' and the top side 140a of the encapsulant 140 may be coplanar. In some examples, the upper sides 120a and 120a' of the electronic components 120 and 120' may be exposed to the outside of the electronic device 100 from the top side 140a of the encapsulant 140. In some examples, the portion 140b of the encapsulant is between the lateral side 120c of the electronic component 120 and the lateral side 120c' of the electronic component 120'. The portion 140b is inserted between the lateral sides of the electronic components 120 and 120' that face each other laterally. In some examples, the portion 140b overlies the substrate internal reinforcement 113. In some examples, a thermally conductive lid, heat sink, or heat sink may be attached to the exposed electronic components 120 and 120'. In some examples, a thermal interface material (TIM) and / or backside metallization (BSM) may be interposed between the electronic components 120 and 120' and the lid.

[0055] In some examples, the encapsulant 140 may be provided by compression molding, transfer molding, liquid phase molding, vacuum lamination, solder paste printing, or film assisted molding. Compression molding may be a process in which a flowable resin is supplied to a mold in advance and then an electronic component is placed in the mold to solidify the flowable resin, and transfer molding may be a process in which a flowable resin is supplied from a door (supply port) of the mold to the periphery of the electronic component and then solidified. The encapsulant 140 may have a thickness of about 100 μm to about 1000 μm. The encapsulant 140 may protect the electronic components 120 and 120' from being exposed to external elements or the environment, and may quickly dissipate heat from the electronic components 120 and 120'. In some examples, the bottom filler 130 may be omitted, and the encapsulant 140 may be filled between the electronic components 120 and 120' and the substrate 110. In some examples, when the size of the silicon dioxide filler is smaller than the gap between the electronic components 120 and 120 ′ and the substrate 110 , the encapsulant 140 may replace the function of the underfill 130 .

[0056] Figure 2C A cross-sectional view of the electronic device 100 is shown in a later stage of manufacturing. Figure 2C In the example shown in , a partial area or portion of carrier 160 can be removed to reduce the thickness of carrier 160. That is, a removal process can be used to reduce the initial or first carrier thickness to a second carrier thickness that is less than the first carrier thickness. In some examples, a wafer support system can be attached to encapsulation 140 or electronic components 120 and 120', and a partial area of ​​carrier 160 can be removed. In some examples, a partial area of ​​carrier 160 can be removed by mechanical grinding or chemical etching. In some examples, the wafer support system can be fixed and the grinder rotates, thereby removing a partial area of ​​carrier 160. In some examples, the removal process can be performed until the residual or remaining thickness of carrier 160 reaches about 1 μm to about 200 μm. In some examples, the remaining area or portion of carrier 160 can be used to provide an external reinforcement structure 114.

[0057] Figure 2D A cross-sectional view of the electronic device 100 is shown in a later stage of manufacturing. Figure 2D In the example shown in , a selective removal process can be used to remove portions of the carrier 160. In some examples, a mask 170, such as a patterned photoresist mask 170 or a photoresist pattern 170, can be provided adjacent to the underside of the carrier 160. In some examples, a photoresist can be applied to the lower surface of the carrier 160, and a photomask exposure process and a photoresist development process can be used to provide the photoresist pattern 170 on the carrier 160. The width of the photoresist pattern 170 can be pre-selected according to the desired size of the external reinforcement structure 114.

[0058] Figure 2E A cross-sectional view of the electronic device 100 is shown in a later stage of manufacturing. Figure 2E In the example shown in , a removal process, such as an etching process, may be performed to remove unmasked or exposed portions of the carrier 160 .

[0059] In some examples, the unmasked portion of the carrier 160 can be etched and removed by using the photoresist pattern 170 as a mask. In some examples, one or more first portions of the carrier 160 can be removed by dry etching or wet etching. In some examples, in the case of dry etching, a partial region or first portion of the carrier 160 can be removed by providing an etching gas (e.g., Cl2, HCl, HF, HBr, SF, etc.) in a plasma state to a partial region of the carrier 160, while leaving a second portion of the carrier 160 coupled to the substrate outer side 110b. In some examples, after dry etching, the dielectric structure 111 and the conductive structure 112 of the substrate 110 can be exposed. In some examples, the substrate-to-outer terminal 112b of the substrate 110 can be exposed.

[0060] Figure 2F A cross-sectional view of the electronic device 100 is shown in a later stage of manufacturing. Figure 2F In the example shown in , mask 170 may be removed using, for example, a photoresist stripping process.

[0061] In some examples, the photoresist pattern 170 can be removed by a liquid resist stripper. In some examples, the liquid resist stripper can include monoethanolamine and 2-butoxyethanol. In some examples, the photoresist pattern 170 can be removed by an oxygen-containing plasma. In some examples, the photoresist pattern 170 can also be removed by a 1-methyl-2-pyrrolidone (NMP) solvent. In some examples, once the photoresist pattern 170 is dissolved, the solvent can be heated to about 80 degrees Celsius to reduce the presence of any residue on the remaining portion of the carrier 160 used to provide the external reinforcement structure 114.

[0062] In this way, an external reinforcement structure 114 is provided that is attached to the substrate outer side 110b of the substrate 110. In some examples and with reference to Figure 1B, the external reinforcement structure 114 can be provided in a substantially rectangular linear shape along the lateral sides 110c, 110d, 110e, and 110f of the substrate 110. In some examples, the external reinforcement structure 114 can be provided as a series of straight lines or linear shapes that traverse along the length or width direction of the substrate 110 without necessarily intersecting each other. In other examples, the external reinforcement structure 114 can include other shapes, including non-linear shapes or shapes preselected to reduce stress within the electronic device 100 and provide other features including stop features.

[0063] The external reinforcement structure 114 may include a substrate external reinforcement 114a or a substrate peripheral reinforcement 114b. In some examples, the substrate internal reinforcement 113 and the substrate external reinforcement 114a do not overlap each other on the substrate 110. In other examples, the substrate external reinforcement 114a and the substrate internal reinforcement 113 may overlap each other or may be substantially collinear with each other. In some examples, the substrate outer side 110b includes a peripheral region, and the substrate peripheral reinforcement 114b extends around the peripheral region, such as, for example, in Figure 1B As described in .

[0064] In the present example, the external reinforcement structure 114 comprises the same material as the carrier 160. For example, when the carrier 160 comprises silicon, glass, or ceramic, the external reinforcement structure 114 also comprises silicon, glass, or ceramic. In some examples, the external reinforcement structure 114 may have a thickness of about 1 μm to about 200 μm. In some examples, the external reinforcement structure 114 may have a width of about 50 μm to about 600 μm. The external reinforcement structure 114 may suppress or reduce bending and twisting of the electronic device 100. In some examples, the external reinforcement structure 114 may also act as a stopper. For example, when the electronic device 100 is attached to a pick-and-place tool and then pressed by an external device, as the outer periphery of the substrate 110 first contacts the external device, the external interconnect 150 or the substrate-to-outward terminal 112 b may be damaged. However, when an external reinforcement structure 114 is provided around the peripheral area of ​​the substrate outer side 110b of the substrate 110, the external reinforcement structure 114 (for example, the substrate peripheral reinforcement 114b) first contacts the external device, and thus the outer periphery of the substrate 110 does not first contact the external device, thereby suppressing damage to the external interconnect 150 or the substrate external terminal 112b.

[0065] Figure 2G A cross-sectional view of the electronic device 100 is shown in a later stage of manufacturing. Figure 2GIn the example shown in , an external interconnect 150 coupled to the substrate-outward terminal 112 b may be provided. In some examples, the external interconnect 150 may be provided on the substrate-outward terminal 112 b using an electroplating process or a deposition process. The external interconnect 150 may include or be referred to as a conductive pillar, a conductive ball, a conductive bump, or a solder ball. In some examples, an electroplating or deposition process using copper, copper alloy, aluminum, aluminum alloy, gold, gold alloy, silver, silver alloy, nickel, nickel alloy, palladium, palladium alloy, or tin-silver may be used to provide the external interconnect 150 as a conductive pillar on the substrate-outward terminal 112 b. In some examples, flux may be provided on the substrate-outward terminal 112 b, conductive balls may be dripped on the flux, and then conductive balls may be provided on the substrate-outward terminal 112 b by a reflow process or a laser-assisted bonding process to provide the external interconnect 150. In some examples, the external interconnect 150 may include tin, silver, lead, copper, Sn-Pb ... 37 -Pb, Sn 95 -Pb, Sn-Pb-Ag, Sn-Cu, Sn-Ag, Sn-Au, Sn-Bi or Sn-Ag-Cu. In the present example, the thickness of the external interconnect 150 is greater than the thickness of the external reinforcement structure 114, so that the external interconnect 150 can be attached to the next level assembly. In some examples, the width of the external interconnect 150 can be greater than the width of the external reinforcement structure 114. In some examples, the external interconnect 150 can have a thickness or width of about 0.01 mm to about 10 mm. The external interconnect 150 can be used to couple (including mechanical coupling and electrical coupling) the electronic device 100 to an external device. In some examples, the substrate external reinforcement 114a of the external reinforcement structure 114 can be disposed between a first row or first column of external interconnects and a second row or second column of external interconnects. In some examples, the substrate external reinforcement 114a can be inserted between the first external interconnect 150a and the second external interconnect 150b in a cross-sectional view and at a location where the substrate external reinforcement 114a overlaps the substrate internal reinforcement 113. In some examples, the external reinforcement structure 114 has only the substrate external reinforcement 114a below the substrate internal reinforcement 113. In some examples, the substrate external reinforcement 114a and the substrate internal reinforcement 113 of the external reinforcement structure 114 are superimposed or co-linear with respect to each other.

[0066] In some instances, an optional singulation process may be used in an example manufacturing method. In some instances, a singulation process may be performed using a cutting wheel, a laser beam, or a plasma singulation. In some instances, when a plurality of electronic devices 100 are manufactured in a form having rows or columns, the electronic devices 100 may be separated into individual electronic devices 100 by a singulation process. In some instances, individual electronic devices 100 may be provided by singulation of the encapsulant 140, the substrate 110, and the external reinforcement structure 114. Therefore, the lateral sides of the encapsulant 140, the substrate 110, or the external reinforcement structure 114 may be coplanar. In some instances, the lateral sides of the encapsulant 140, the lateral sides 110c, 110d, 110e, and 110f of the substrate 110, and the outward facing sides of the external reinforcement structure 114 may be referred to as singulation surfaces or sides.

[0067] The electronic device 100 may include a component gap 160 c between respective electronic components 120 and 120 ′, an interconnect gap 160 i between adjacent respective component interconnects 121 and 121 ′, and an inner stiffener width 113 w of the substrate inner stiffener 113 .

[0068] In the electronic device 100, the relationship of the internal stiffener width 113w to the component gap 160c or the interconnect gap 160i can be configured to enable the substrate internal stiffener 113 to provide increased structural integrity to the electronic device 100 or the substrate 110. Through research and experimentation, the applicant has discovered that there is a tendency for stress concentrations to occur in the component gap 160c, such as along the interface of the lateral side 120c' of the component 120' with the encapsulant 140 and the bottom fill 130, extending to damage the substrate 110 around such stress concentration lines. As discovered by the applicant, such stress concentrations may be more pronounced in the case where the sidewalls of the component 120' itself include encapsulants that interface with the encapsulant 140 or the bottom fill 130.

[0069] To address such stress issues, the applicant added substrate internal reinforcements 113 along such stress concentrations, designed the dimensions between different elements to minimize the distance between the electronic components 120 and 120', while allowing sufficient separation and avoiding short circuits between the substrate inward terminals 112a and the substrate internal reinforcements 113 and between the component interconnects 121, 121' and the substrate internal reinforcements 113 during processing.

[0070] In some examples, for example, when considering the above, the component gap 160c may be about 50 μm to about 100 μm, or about 70 μm, the interconnect gap 160i may be about 500 μm to about 3000 μm, and the inner stiffener width 113w of the substrate inner stiffener 113 may be about 300 μm to about 2500 μm. In some examples, the ratio between the inner stiffener width 113w and the interconnect gap 160i may be about 3 / 5 to about 5 / 6. In some examples, the substrate inner stiffener 113 may overlap the lateral side 120c or 120c' of the electronic component 120 or 120' by about 50 μm to about 200 μm (i.e., the length of the overlap may be about 50 μm to about 200 μm). In some examples, this overlap may extend under the electronic component 120', but need not extend under the electronic component 120. In some examples, the length of the overlap may be about 100 μm. In some examples, the center of the inner reinforcement width 113w may be offset from the center of the assembly gap 160c.

[0071] In some examples, the substrate external reinforcement 114a may overlap with the substrate internal reinforcement 113 or may be substantially co-linear with the substrate internal reinforcement 113 across the substrate 110. In some examples, the substrate external reinforcement 114a may be configured or positioned similarly to the substrate internal reinforcement 113 to address similar stress considerations described above. For example, the substrate external reinforcement 114a may overlap with the lateral side 120c or 120c' of the electronic component 120 or 120', for example, by about 100 μm to about 200 μm. In some examples, this overlap may extend under the electronic component 120', but need not extend under the electronic component 120. There may be embodiments in which the center of the width of the substrate external reinforcement 114a may be offset from the center of the component gap 160c.

[0072] The dimensions of the external reinforcement structure 114 can be configured to provide structural integrity to address, for example, distortion of the substrate 110, or stress conditions around the component gap 160c described above. For example, the width of the substrate external reinforcement 114a can be about 300 μm to about 2500 μm, or can correspond to the internal reinforcement width 113w to address stress concentration. As another example, the width of the substrate peripheral reinforcement 114b can be about 50 μm to about 600 μm to address distortion of the substrate 110.

[0073] Figures 3A to 3C A cross-sectional view of an example method for manufacturing an electronic device (eg, electronic device 100) is shown. Figures 3A to 3C The electronic device 100 provided by the method may be similar or the same as previously described. Figures 3A to 3C The method can be used with Figure 2A to Figure 2GIn this regard, the following will discuss Figure 2A to Figure 2G The difference between the processes. Figure 3A A cross-sectional view of electronic device 100 is shown at an early stage of manufacture. Figure 3A In the example shown in , the carrier 160 can be removed. In some examples, the carrier 160 is completely removed, thereby exposing the substrate outer side 110b.

[0074] In some examples, the carrier 160 can be separated from the substrate 110. For example, the wafer support system can be first attached to the encapsulation 140 or the electronic components 120 and 120', and then the carrier 160 can be removed from the substrate 110. In some examples, when the temporary adhesive film is inserted between the substrate 110 and the carrier 160, the temporary adhesive film can be exposed to heat or light (e.g., a laser beam) to reduce the adhesive force of the temporary adhesive film, thereby facilitating the removal of the carrier 160 from the substrate 110. In some examples, the mechanical force of the carrier 160 can be used to separate the carrier 160 and the substrate 110. In some examples, the carrier 160 can be removed by mechanical grinding or chemical etching. By removing or separating the carrier 160, the substrate outer side 110b of the substrate 110 can be exposed. In some examples, some areas of the dielectric structure 111 and some areas of the conductive structure 112 can be exposed. In some examples, the substrate-to-outward terminal 112b of the substrate 110 can be exposed.

[0075] Figure 3B A cross-sectional view of the electronic device 100 is shown in a later stage of manufacturing. Figure 3B In the example shown in , a coating 180 may be provided, such as an organic material coating 180. In some examples, a polymer coating 180 may be provided.

[0076] In some examples, a coating 180 may be provided over the substrate outer side 110b of the substrate 110. In some examples, a polymer such as PI, BCB, PBO, resin, or ABF may be coated, laminated, or deposited on the entire substrate outer side 110b of the substrate 110. For example, the coating 180 may be provided using spin coating, spray coating, dip coating, or rod coating, and then cured. In some examples, the coating 180 may be provided by CVD, PVD, ALD, LPCVD, or PECVD. In some examples, the coating 180 may have a thickness of about 1 μm to about 200 μm.

[0077] Figure 3C A cross-sectional view of the electronic device 100 is shown in a later stage of manufacturing. Figure 3C In the example shown in , the outer reinforcement structure 114 may be provided by a patterned coating 180 .

[0078] In some examples, in order to provide the external reinforcement structure 114, a selective removal process, such as a photoresist process, can be used. For example, a photoresist can be applied to the polymer coating 180. By placing a photomask on the photoresist, performing an exposure process, and then performing a development process, the photoresist pattern can remain on the coating 180. The exposed area of ​​the coating 180 can be removed by etching the photoresist pattern and using the photoresist pattern as a mask. In some examples, a partial area of ​​the coating 180 can be etched by dry etching or wet etching. In some examples, in the case of dry etching, a partial area of ​​the coating 180 can be removed by providing an etching gas in a plasma state (e.g., a mixed gas of a fluorocarbon and oxygen, etc.) to a partial area of ​​the coating 180. In some examples, after etching, the dielectric structure 111 and the conductive structure 112 of the substrate 110 can be exposed. In some examples, the substrate-to-outward terminal 112b of the substrate 110 can be exposed. In some instances, after etching, the photoresist pattern may be stripped using a process similar to the process previously described. In this way, an external reinforcement structure 114 coupled to (including attached to) the substrate outer side 110b of the substrate 110 may be provided. In some instances, the external reinforcement structure 114 including a polymer may be provided in a substantially rectangular linear shape along the lateral sides 110c, 110d, 110e, and 110f of the substrate 110, or may be provided in a straight line that traverses along the length direction or width direction of the substrate 110. In some instances, the external reinforcement structure 114 including a polymer may have a thickness of about 1 μm to about 200 μm. The external reinforcement structure 114 including a polymer may suppress or reduce bending and twisting of the electronic device 100, or may also act as a stopper.

[0079] Figure 4A 1 shows a cross-sectional view of an example electronic device 100. Figure 4A In the example shown in , a second underfill 230 may be provided between the electronic device 100 and the external device 190 (e.g., a printed circuit board). For example, a capillary underfill may be provided to a gap 240 between the electronic device 100 and the external device 190. Since the gap 240 between the external reinforcement structure 114 and the external device 190 is smaller than the gap 241 between the substrate 110 and the external device 190, it is difficult to fill the capillary underfill. These may result in defects, such as voids.

[0080] Figure 4B A cross-sectional view of an example electronic device 100 is shown and Figure 4C 1 shows a top view of an example electronic device 100. Figure 4B and Figure 4CIn the example shown in , at least one area of ​​the external reinforcement structure 114 can be removed. In some examples, a perforation 1141 can be provided in the area of ​​the external reinforcement structure 114. For example, a perforation 1141 extending through a side portion of the external reinforcement structure 114 can be provided. In some examples, the substrate outer side 110b of the substrate 110 (e.g., the dielectric structure 111 or the conductive structure 112) can be exposed through the perforation 1141. In some examples, the bottom filler 230 can be smoothly filled into the gap 241 between the substrate 110 and the external device 190 through the perforation 1141. In this way, the gap between the substrate 110 and the external device 190 can be suppressed or reduced. In some examples, the perforation 1141 can have a width of about 30 μm to about 1000 μm, and in this range, the bottom filler can be easily injected, and the function of the external reinforcement structure 114 may not be adversely affected. Underfill 230 may be a similar material to underfill 130 , and may be provided using a similar process as described with respect to underfill 130 .

[0081] In summary, structures and associated methods have been described that relate to electronic devices with 3D wafer-level packaging. More specifically, structures and methods have been described that improve the reliability of wafer-level substrates, such as redistribution layer (RDL) substrates used in fine-pitch fan-out configurations. In some instances, substrate stiffeners can be used to reduce distortion, module bending, and stress-related defects such as cracks. In some instances, external substrate stiffeners can provide a stopper function that reduces unwanted bending when the electronic device is attached to a next-level assembly. In practice, it has been found that the structures and methods increase mechanical strength by 1.5 to 2 times compared to previous electronic devices.

[0082] The present disclosure includes references to certain examples; however, those skilled in the art will appreciate that various changes may be made and equivalents may be substituted without departing from the scope of the present disclosure. Additionally, modifications may be made to the disclosed examples without departing from the scope of the present disclosure. Therefore, it is intended that the present disclosure is not limited to the disclosed examples, but that the present disclosure will include all examples that fall within the scope of the appended claims.

Claims

1. An electronic device, comprising: A substrate, comprising: Inside of substrate; an outer side of the substrate, which is opposite to the inner side of the substrate; a substrate lateral side connecting the substrate inner side to the substrate outer side; Dielectric structure; A conductive structure comprising: a substrate inward terminal adjacent to the inner side of the substrate; and a substrate outward terminal adjacent to the outer side of the substrate; as well as a substrate internal reinforcement member at the inner side of the substrate; A first electronic component coupled to the substrate inward terminal and comprising: a first lower side, which is close to the inner side of the substrate; a first upper side opposite to the first lower side; and a first lateral side connecting the first lower side to the first upper side; an underfill between the first underside of the first electronic component and the inner side of the substrate and covering the substrate inner reinforcement; and An encapsulant covers a portion of the inner side of the substrate, a portion of the underfill, and a portion of the first electronic component.

2. The electronic device according to claim 1, further comprising: a second electronic component coupled to the substrate inward terminals and comprising: Second lower side; a second upper side opposite to the second lower side; and a second lateral side connecting the second lower side to the second upper side; in: the second electronic component being laterally spaced apart from the first electronic component; The substrate internal reinforcement is between the first electronic component and the second electronic component; and The underfill is between the second underside of the second electronic component and an inner side of the substrate.

3. The electronic device according to claim 2, wherein: The enclosure includes an enclosure top side; The first upper side of the first electronic component and the second upper side of the second electronic component are exposed from a top side of the encapsulation; The underfill is laterally between the first electronic component and the second electronic component; A portion of the top side of the encapsulant is between the first electronic component and the second electronic component; and The portion of the encapsulant top side contacts the underfill.

4. The electronic device according to claim 1, wherein: The substrate internal reinforcement has a first thickness; The substrate inward terminal comprises a second thickness; and The first thickness is different from the second thickness.

5. The electronic device according to claim 1, wherein: The substrate includes a redistribution layer (RDL) substrate; The substrate includes a pair of opposing lateral sides; The substrate interior reinforcement extends vertically between the pair of opposing lateral sides; and Ends of the substrate inner reinforcement are embedded from the pair of opposite lateral sides of the substrate.

6. The electronic device according to claim 1, further comprising: An external reinforcement structure is coupled to an outer side of the substrate.

7. The electronic device according to claim 6, wherein: The outer side of the substrate includes a peripheral area; and The outer reinforcement structure extends along the peripheral region.

8. The electronic device according to claim 6, wherein: The outer reinforcement structure includes a side portion and a perforation extending through the side portion.

9. The electronic device according to claim 6, further comprising: an external interconnect coupled to the conductive structure, proximate to an outside of the substrate, and comprising a first external interconnect and a second external interconnect laterally separated from the first external interconnect; in: The external reinforcement structure includes a substrate external reinforcement interposed between the first external interconnect and the second external interconnect; and The substrate inner reinforcement and the substrate outer reinforcement overlap in a cross-sectional view.

10. The electronic device according to claim 1, wherein: The substrate internal stiffener includes a conductor and is coupled to the conductive structure of the substrate.

11. An electronic device comprising: A substrate, the substrate comprising: Inside of substrate; an outer side of the substrate, which is opposite to the inner side of the substrate; a substrate lateral side connecting the substrate inner side to the substrate outer side; Dielectric structure; a conductive structure comprising a substrate-inward terminal adjacent to the inner side of the substrate and a substrate-outward terminal adjacent to the outer side of the substrate; and a substrate internal reinforcement member adjacent to the inner side of the substrate; A first electronic component coupled to the substrate inward terminal and comprising: a first lower side, which is close to the inner side of the substrate; a first upper side opposite to the first lower side; and a first lateral side connecting the first lower side to the first upper side; a second electronic component coupled to the substrate-inward terminals, laterally spaced apart from the first electronic component, and comprising: Second lower side; a second upper side opposite to the second lower side; and a second lateral side connecting the second lower side to the second upper side; as well as An encapsulant covers a portion of the inner side of the substrate, a portion of the first electronic component, and a portion of the second electronic component.

12. The electronic device according to claim 11, wherein: The substrate internal reinforcement is between the first electronic component and the second electronic component.

13. The electronic device according to claim 11, further comprising: a component interconnect coupling the first underside of the first electronic component and the second underside of the second electronic component to the conductive structure; as well as An underfill surrounds the component interconnects.

14. The electronic device according to claim 11, further comprising: an underfill between the first underside of the first electronic component and the inner side of the substrate, between the second underside of the second electronic component and the inner side of the substrate, and covering the substrate inner reinforcement; and a substrate external reinforcement member adjacent to the outer side of the substrate; in: The encapsulant covers a portion of the underfill; and The substrate outer reinforcement and the substrate inner reinforcement overlap in a cross-sectional view.

15. A method of manufacturing an electronic device, comprising: A substrate is provided, the substrate comprising: Inside of substrate; an outer side of the substrate, which is opposite to the inner side of the substrate; a substrate lateral side connecting the substrate inner side to the substrate outer side; Dielectric structure; A conductive structure comprising: a substrate inward terminal adjacent to the inner side of the substrate; and a substrate outward terminal adjacent to the outer side of the substrate; as well as a substrate internal reinforcement coupled to the inner side of the substrate; A first electronic component is coupled to the substrate inward terminal, the first electronic component comprising: a first lower side, which is close to the inner side of the substrate; a first upper side opposite to the first lower side; and a first lateral side connecting the first lower side to the first upper side; providing a first underfill between the first underside of the first electronic component and the inner side of the substrate and covering the substrate inner reinforcement; providing an encapsulant covering at least a portion of the inner side of the substrate, at least a portion of the first underfill, and at least a portion of the first electronic component; providing an external reinforcement structure coupled to an outer side of the substrate; and An external interconnect is provided that is coupled to the substrate outward terminal.

16. The method according to claim 15, further comprising: coupling a second electronic component to the substrate inward terminals, the second electronic component comprising: Second lower side; a second upper side opposite to the second lower side; and a second lateral side connecting the second lower side to the second upper side; in: the second electronic component being laterally spaced apart from the first electronic component; The substrate internal reinforcement is between the first electronic component and the second electronic component; and Providing the first underfill includes providing the first underfill between the second underside of the second electronic component and an inner side of the substrate.

17. The method according to claim 15, further comprising: Provide external devices; coupling the external interconnect to the external device; as well as providing a second underfill between the outside of the substrate and the external device; in: Providing the external reinforcement structure includes providing perforations in side portions of the external reinforcement structure; and Providing the second underfill includes providing the second underfill through the through-hole.

18. The method of claim 15, wherein: Providing the substrate includes providing a redistribution layer (RDL) substrate.

19. The method of claim 15, wherein: Providing the substrate comprises: providing a carrier, the carrier comprising a carrier top side, a carrier bottom side opposite the carrier top side, and a carrier thickness; providing the substrate on the carrier top side; reducing the thickness of the carrier; and selectively removing a first portion of the carrier while leaving a second portion of the carrier coupled to an outer side of the substrate; Wherein the second portion defines the outer reinforcement structure.

20. The method of claim 15, wherein: Providing the substrate comprises: providing a carrier, the carrier comprising a carrier top side and a carrier bottom side opposite the carrier top side; providing the substrate on the carrier top side; removing the carrier to expose the outside of the substrate; providing a coating over an outer side of the substrate; and Portions of the coating are selectively removed to define the outer reinforcement structure.

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