Semiconductor package with insulating layer

Abstract

The invention relates to a semiconductor package with an insulating layer. A semiconductor package includes a semiconductor wafer (104) having a first connection pad (116) and a second connection pad (118) spaced apart by a semiconductor region (106) of the semiconductor wafer (104). A portion of the semiconductor wafer (104) is covered by a protective overcoat (108). The semiconductor package also includes a cover wafer (112) mounted to the semiconductor wafer (104) and across the semiconductor region (106) of the semiconductor wafer (104). The cover wafer (112) extends between the first connection pad (116) and the second connection pad (118) of the semiconductor wafer (104). The semiconductor package further includes an insulating material (122) overlying the lid wafer (112). The insulating material (122) includes a via (114) leading to the first connection pad (116) and the second connection pad (118), the via being filled with a conductive material (120).

Description

Technical Field

[0001] The present specification relates to a semiconductor package having an insulating layer. Background Art

[0002] In some semiconductor packages, through-holes are used to allow current to pass from one semiconductor component within an integrated electronic device to another semiconductor component through the through-holes. During the formation of the through-holes, various conductive layers or films are typically deposited on the semiconductor wafer by processes such as electroplating. For example, copper is typically used to form through-holes due to its relatively high electrical conductivity. However, metals with high electrical conductivity resist adhesion to other layers formed on the semiconductor wafer. When ions that make up the lattice of the conductive material move across a weak interface along an electric field, poor adhesion of the layers within the through-holes results in delamination at the interface due to thermal stress and electromigration of the conductive material. Summary of the invention

[0003] A first example relates to a semiconductor package. The semiconductor package includes a semiconductor wafer having a first connection pad and a second connection pad separated by a semiconductor region of the semiconductor wafer. A portion of the semiconductor wafer is covered by a protective overcoat. The semiconductor package also includes a cover wafer mounted to the semiconductor wafer and over the semiconductor region of the semiconductor wafer. The cover wafer extends between the first connection pad and the second connection pad of the semiconductor wafer. The semiconductor package further includes an insulating material overlying the cover wafer. The insulating material includes a through hole leading to the first connection pad and the second connection pad, the through hole being filled with a conductive material.

[0004] A second example relates to a method for forming a semiconductor package. The method includes mounting a cover wafer on a semiconductor wafer to form a stacked wafer. The semiconductor wafer includes an array of dies. The dies include first and second connection pads separated by semiconductor regions of corresponding dies of the dies. The method also includes etching the cover wafer to expose the first and second connection pads of the dies such that a portion of the cover wafer passes over the semiconductor region of the dies. The method further includes coating the cover wafer with an insulating material. The method further includes processing the insulating material to form through holes in the insulating material leading to the first and second connection pads of the dies. The method further includes depositing a conductive material in the through holes and singulating the stacked wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 An example of a stacked wafer semiconductor ready for packaging is shown.

[0006] Figure 2 An example of wafer chip scale packaging is shown.

[0007] Figure 3 An example of a flat no-lead configuration of a semiconductor package is shown.

[0008] Figure 4 An example of a first stage of a first method for forming a stacked wafer semiconductor is shown.

[0009] Figure 5 An example of a second stage of a first method for forming a stacked wafer semiconductor is shown.

[0010] Figure 6 An example of a third stage of the first method for forming a stacked wafer semiconductor is shown.

[0011] Figure 7 An example of a fourth stage of the first method for forming a stacked wafer semiconductor is shown.

[0012] Figure 8 An example of a fifth stage of the first method for forming a stacked wafer semiconductor is shown.

[0013] Fig. 9 An example of a sixth stage of the first method for forming a stacked wafer semiconductor is shown.

[0014] Fig.10 An example of the seventh stage of the first method for forming a stacked wafer semiconductor is shown.

[0015] Fig.11 An example of a first stage of a second method for forming a semiconductor package is shown.

[0016] Fig.12 An example of a second stage of a second method for forming a semiconductor package is shown.

[0017] Fig.13 An example of a first stage of a third method for forming a semiconductor package is shown.

[0018] Fig.14 An example of a second stage of the third method for forming a semiconductor package is shown.

[0019] Fig.15 An example of a third stage of a third method for forming a semiconductor package is shown.

[0020] Fig.16 A flow chart illustrating an example method for fabricating a stacked wafer semiconductor having an insulating layer. DETAILED DESCRIPTION

[0021] A semiconductor package includes a plurality of semiconductor components. The semiconductor components are electrically connected through vias so that current is passed from one semiconductor component to another semiconductor component. As an example, vias (e.g., trenches) are etched into a silicon wafer layer or other dielectric separating semiconductor components. The vias contain a conductive material to allow current to pass from one semiconductor component to another semiconductor component in the semiconductor package. The conductive layer is formed of a conductive material such as copper, palladium, gold, silver, or other suitable conductive metals or metal alloys having similar properties.

[0022] The conductive layer is deposited on the semiconductor wafer by an electroplating process. In some examples, the conductive layer is separated from the semiconductor component by depositing various intermediate layers on the semiconductor wafer. In one example, the insulating layer is first deposited on the semiconductor wafer by plasma-enhanced chemical vapor deposition (PE-CVD). The insulating layer material includes silicon dioxide, which electrically isolates the silicon cap wafer from the subsequently deposited layers on the semiconductor wafer.

[0023] After depositing the insulating layer, the bottom of the insulating layer is etched to open the connection pad area, and then a seed layer is deposited on the semiconductor wafer. The seed layer is formed of a conductive material (e.g., titanium, copper). Since a wafer bonding material (e.g., SU-8) is used between the silicon cap wafer and the device wafer, in conventional methods, the seed layer covers the sidewalls of the silicon cap and the wafer bonding material. However, during wafer-to-wafer bonding, the bonding material is deformed by pressure, and the resulting deformed shape results in poor coverage of the seed layer.

[0024] In the semiconductor package and method described herein, an insulating layer overlies a cover wafer and forms sidewalls of a through hole filled with a conductive material. Instead of the insulating material used in conventional methods, an insulating layer is deposited and the through hole is etched into a connection pad in a semiconductor wafer. The insulating layer acts as a buffer layer and reduces the risk of cracking due to stress and reduces the number of photolithography steps during manufacturing. In some instances, the through hole in the insulating layer is tapered, with a wider opening at the end of the through hole away from the corresponding connection pad. The tapered sidewall increases the coverage of the seed layer and / or the conductive material during deposition. In various instances, the insulating layer includes a photosensitive material and / or a non-photosensitive material. In one instance, the photosensitive material is patterned by a photolithography process. The non-photosensitive material is patterned by laser ablation.

[0025] Figure 1An example of a stacked wafer semiconductor 100 ready for packaging is shown. The stacked wafer semiconductor 100 includes a semiconductor circuit module 102. In some examples, the semiconductor circuit module 102 is integrated with a semiconductor wafer 104 and includes a semiconductor region 106. The semiconductor wafer 104 is a substrate, such as silicon, silicon carbide, or other suitable material, in a substantially pure form or in combination with additional materials. As another example, the semiconductor wafer 104 is a single crystal material, such as a single crystal silicon substrate.

[0026] The formation of semiconductor wafer 104 depends on the application of semiconductor circuit module 102. As an example, semiconductor wafer 104 is a complementary metal oxide semiconductor (CMOS) substrate and includes a circuit system formed thereon. The circuit system in semiconductor wafer 104 is coupled to semiconductor circuit module 102 and performs appropriate functions for the application (e.g., controlling the operation of a mechanical resonator, detecting vibration of a mechanical resonator, etc.). In one example, semiconductor circuit module 102 of semiconductor wafer 104 includes a resonator, such as an LC resonator, a microelectromechanical system (MEMS) resonator, a surface acoustic wave (SAW) resonator, a bulk acoustic wave (BAW) resonator, or other external resonator. In some such examples, stacked wafer semiconductor 100 is a stress sensor, and semiconductor circuit module 102 is a field effect transistor having a structure for detecting stress generated therein. In yet another example, no circuit system is formed on semiconductor wafer 104.

[0027] A protective overcoat layer 108 overlies (e.g., covers) the semiconductor wafer 104. A wafer bonding layer 110 overlies the protective overcoat layer 108. The wafer bonding layer 110 is formed of a non-conductive material such as epoxy or other suitable non-conductive material (e.g., SU-8). The stacked wafer semiconductor 100 also includes a cap wafer 112. In one example, the semiconductor region 106 forms a cavity, and the cap wafer 112 facilitates forming a hermetic seal (e.g., a vacuum seal) of the cavity. In another example, the cap wafer 112 is a CMOS cap on which an integrated circuit system is formed.

[0028] The through-hole 114 provides electrical connection to the semiconductor circuit module 102 through the connection pads (e.g., the first connection pad 116 and the second connection pad 118). The first connection pad 116 and the second connection pad 118 are separated in the longitudinal direction by the semiconductor region 106. The cover wafer 112 is mounted to the semiconductor wafer 104 and passes over the semiconductor region 106 of the semiconductor wafer 104.

[0029] The through-hole 114 includes a conductive material 120. The conductive material 120 is copper or other conductive materials. The electrical signal communicates with the semiconductor circuit module 102 through the through-hole 114, thereby achieving electrical communication. In the example stacked wafer semiconductor 100, the through-hole 114 is separated by the semiconductor circuit module 102. Although two through-holes 114 are shown in other examples, there are fewer or greater numbers of through-holes 114.

[0030] The insulating material 122 overlies the cap wafer 112 and forms the sidewalls of the through hole 114. The sidewalls of the corresponding through hole include a first sidewall 124 opposite to a second sidewall 126 in the longitudinal direction. The first sidewall 124 is separated from the second sidewall 126 by the conductive material 120. In some examples, a seed layer separates the conductive material 120 from the insulating material 122. A main body portion 128 of the insulating material 122 is substantially parallel to the semiconductor wafer 104. The main body portion 128 has a first side 130 and a second side 132 extending in the longitudinal direction. The first side 130 forms the top surface of the stacked wafer semiconductor 100. The second side 132 of the main body portion 128 is adjacent to the cap wafer 112.

[0031] The insulating material 122 is patterned. In one example, the solubility of the insulating material 122 changes in response to irradiation, so that the insulating material 122 can be patterned with light. In another example, the insulating material is patterned with an ablative laser. The insulating material 122 is polyimide (PI), polybenzoxazole (PBO), SU-8, Ajinomoto stacked film (ABF) or other suitable materials with similar properties. The insulating material 122 forms a non-conductive insulating layer. The insulating material 122 acts as a buffer layer and reduces the risk of cracking due to stress, and reduces the number of photolithography steps during manufacturing. More specifically, the conductive material 120, the protective outer coating 108, the wafer bonding layer 110 and the cover wafer 112 have different Young's moduli. In addition, the insulating material 122 has a Young's modulus lower than the conductive material 120 and the protective outer coating 108. Thus, the insulating material 122 acts as a buffer layer (alternatively referred to as a shock absorber) to accommodate differential expansion or contraction between the conductive material 120 and the protective overcoat 108, the wafer bonding layer 110, and the cap wafer 112. In some examples, the through-holes 114 in the insulating material 122 are tapered, with wider openings at the ends of the through-holes 114 away from the corresponding connection pads 116, 118.

[0032] The sidewalls 124, 126 extend from the main body 128 and separate the conductive material 120 from the protective overcoat 108, the wafer bonding layer 110, and the cap wafer 112. Due to patterning with light or ablative laser, the sidewalls 124, 126 of the insulating material 122 have a regular and uniform surface. After etching, the sidewalls 124, 126 have a smoother surface than the wafer bonding layer 110.

[0033] The depth of the through hole 114 is defined in a lateral direction orthogonal to the longitudinal direction. The conductive material 120 extends from the first surface 134 of the first connection pad 116 and the second connection pad 118. The conductive material 120 extends from the first surface 134 to the first side 130 of the body portion 128. In some examples, the depth of the through hole 114 extends beyond the first side 130 of the body portion 128 in the lateral direction.

[0034] The sidewalls 124, 126 of the insulating material 122 are tapered so that the through hole 114 has a wider opening at the end away from the corresponding connecting pads 116, 118. The width of the through hole 114 defined in the longitudinal direction is based on the spacing between the opposite sidewalls 124, 126 of the through hole 114. In some examples, the width of the through hole 114 includes a first width continuous with the first surface 134 at a first depth and a second width continuous with the surface of the first side 130 of the main body portion 128. Therefore, the first width is located near the connecting pads 116, 118, and the second width is located far from the connecting pads 116, 118. The second width is greater than the first width. In one example, the first width is at least five microns, and the second width depends on the depth of the through hole 114 in the lateral direction. As an example, the through hole 114 has a truncated cone shape.

[0035] The taper of the sidewalls 124, 126 forms an angle 136 relative to the first surface 134 of the connection pads 116, 118. The angle 136 is less than 90 degrees. In some examples, the angle 136 is between 30 degrees and 89 degrees. The regular uniform surface of the sidewalls 124, 126 conforms to the angle. The taper improves the coverage of the material (e.g., seed layer or conductive material 120) deposited in the through hole 114.

[0036] Figure 2 Shows that it contains Figure 1 1. The stacked wafer semiconductor 100 of FIG. 1 is an example of a wafer chip scale package (WCSP) configuration 200 of a semiconductor package. The WCSP configuration 200 includes a semiconductor circuit module 202. In some examples, the semiconductor circuit module 202 is integrated with a semiconductor wafer 204 and includes a semiconductor region 206. A protective overcoat layer 208 overlies (e.g., covers) the semiconductor wafer 204. A wafer bonding layer 210 overlies the protective overcoat layer 208. A cover wafer 212 overlies the wafer bonding layer 210.

[0037] Through hole 214 (eg, Figure 1 The through hole 114 of the semiconductor circuit module 202 is provided with an electrical connection through the connection pads (e.g., the first connection pad 216 and the second connection pad 218). The through hole 214 is filled with a conductive material 220 such as copper. The insulating material 222 (e.g., Figure 1The insulating material 222 of the through hole 214 is overlying the cap wafer 212. The insulating material 222 forms sidewalls, which include a first sidewall 224 and a second sidewall 226 of the through hole 214. The sidewalls 224, 226 extend from the main body portion 228 and separate the conductive material 220 from the protective overcoat 208, the wafer bonding layer 210, and the cap wafer 212. The main body portion 228 has a first side 230 extending in a longitudinal direction and a second side 232 opposite the first side 230. The depth of the conductive material 220 of the through hole 214 extends beyond the first side 230 of the main body portion 228 in a lateral direction away from the semiconductor wafer 204. For example, the depth of the conductive material 220 extends from the first surface 234 of the connection pads 216, 218 to the conductive surface 236.

[0038] The width of the through hole 214 defined in the longitudinal direction is based on the spacing between the opposite sidewalls of the through hole 214. In some examples, the width of the through hole 214 includes a first width defined by the first surface 234 at the first depth and a second width defined by the surface of the first side 230. Therefore, the first width is located proximal to the connecting pads 216, 218, and the second width is located distal to the connecting pads 216, 218. The second width is greater than the first width.

[0039] The ends of the through-hole 214 are defined by the conductive surface 236 of the conductive material 220 of the through-hole 214. The through-hole 214 is coated with a solderable metal layer 238. The solderable metal layer 238 provides a protective coating that prevents oxidation at the conductive surface 236 of the conductive material 220. The solderable metal layer 238 is formed of a solderable metal material. Examples of solderable metal materials include various forms of nickel, palladium, silver, tin, gold, etc. In one example, the conductive material 220 is copper (Cu), and the solderable metal layer 238 is a tin / silver alloy. Therefore, the solderable metal layer 238 provides electroplating on the ends of the copper in the through-hole 214.

[0040] The solderable metal layer 238 is formed by applying a solderable metal material to the conductive surface 236 of the conductive material 220 in a deposition process such as electroplating. The solderable metal layer 238 has a first plated surface 240 extending in the longitudinal direction and a second plated surface 242 opposite the first plated surface 240. The first plated surface 240 is adjacent to the conductive surface 236 of the conductive material 220. The solderable metal layer 238 has a width defined by the width of the conductive material 220 in the longitudinal direction. The second plated surface 242 forms the top surface of the flip chip configuration 200 of the semiconductor package.

[0041] Figure 3 A circuit diagram showing a circuit having wire bonds 302 is shown. Figure 1The stacked wafer semiconductor 100 is an example of a flat no-lead configuration 300 of a semiconductor package, such as a quad flat no-leads (QFN) configuration or a dual flat no-leads (DFN) configuration. The wire bonds 302 are formed in through holes 304 (e.g., Figure 1 The through hole 114, Figure 2 The semiconductor wafer 310 is provided with a semiconductor circuit module 308. ...

[0042] A protective overcoat 318 overlies the semiconductor wafer 310. A wafer bonding layer 320 overlies the protective overcoat 318. A cap wafer 322 overlies the wafer bonding layer 320. An insulating material 324 (e.g., Figure 1 Insulation material 122, Figure 2 The insulating material 222 of the through hole 304 is overlying the cap wafer 322 and forming the sidewalls of the through hole 304. The sidewalls include a first sidewall 326 and a second sidewall 328 extending from the main body portion 330 and separated by the conductive material 316 of the corresponding through hole 304. The sidewalls 326, 328 are tapered with a wider opening at the end away from the corresponding connection pad.

[0043] Figures 4 to 10 A method for forming a stacked semiconductor wafer having an insulating layer (eg Figure 1 For the purpose of simplicity, Figures 4 to 10 Like reference numerals are used to refer to like structures.

[0044] Figure 4 An example of a first stage 400 of a first method of forming a stacked wafer semiconductor 100 is shown. A semiconductor wafer 502 is provided, and a protective overcoat 504 is deposited over the semiconductor wafer 502. Circuitry is integrated over the semiconductor wafer 502 within the protective overcoat 504. For example, a conductive element including a semiconductor circuit module 506, a first connection pad 508, and a second connection pad 510 is integrated within the protective overcoat 504. The conductive element is formed of a conductive material.

[0045] The protective overcoat layer 504 is removed from over portions of the first connection pad 508 and the second connection pad 510, thereby forming an etched region 512 that exposes the connection pads 508, 510. The protective overcoat layer 504 is further deposited and / or etched to form trenches 514 separated by the semiconductor circuit modules 506. Thus, the protective overcoat layer 504 is discontinuous in the longitudinal direction and has a variable height in the lateral direction depending on the location of the etched region 512.

[0046] Figure 5 An example of a second stage 410 of the first method for forming a stacked wafer semiconductor is shown. In the second stage 410, a wafer bonding layer 516 is applied on a cap wafer 518. The wafer bonding layer 516 is discontinuous in the longitudinal direction and is formed of a plurality of sections including a first section 520, a second section 522, a third section 524, and a fourth section 526.

[0047] Figure 6 An example of a third stage 420 of a first method for forming a stacked wafer semiconductor is shown. In the third stage 420, a cover wafer 518 is bonded to a protective overcoat layer 504 by means of a wafer bonding layer 516. In response to bonding, a first section 520 and a second section 522 of the wafer bonding layer 516 are separated in a longitudinal direction by a first connection pad 508, such that the first section 520 is located on a far side of the semiconductor circuit module 506, and the second section 522 is located on a near side of the semiconductor circuit module 506. Likewise, in response to bonding, a third section 524 and a fourth section 526 of the wafer bonding layer 516 are separated in a longitudinal direction by a second connection pad 510, such that the third section 524 is located on a near side of the semiconductor circuit module 506, and the fourth section 526 is located on a far side of the semiconductor circuit module 506.

[0048] When bonded, the semiconductor region 528 is defined by the second section 522 and the third section 524 of the wafer bonding layer 516. In one example, the semiconductor region 528 is a cavity having a width from an edge of the second section 522 extending in the lateral direction and located proximal to the semiconductor circuit module 506 to an edge of the third section 524 extending in the lateral direction and located proximal to the semiconductor circuit module 506. The cavity has a top surface defined by the cap wafer 518 and a bottom surface opposite the top surface defined by the protective overcoat 504 on the semiconductor wafer 502. The bottom surface is also defined by the bottom of the trench 514. In some examples, the cavity of the semiconductor region 528 is sealed to create an inert or non-inert environment, such as a vacuum environment for a mechanical resonator and for the semiconductor circuit module 506 (e.g., an electrode).

[0049] Figure 7An example of a fourth stage 430 of the first method for forming a stacked wafer semiconductor is shown. In the fourth stage 430, the cap wafer 518 is etched over the first connection pad 508 and the second connection pad 510 so that the cap wafer 518 is discontinuous in the longitudinal direction. By means of etching, a first opening 530 is formed over the first connection pad 508 and a second opening 532 is formed over the second connection pad 510. The openings 530, 532 have sidewalls formed by sections of the cap wafer 518 and the wafer bonding layer 516 extending in the lateral direction and substantially orthogonal to the surfaces of the connection pads 508, 510 extending in the longitudinal direction.

[0050] As an example, the cap wafer 518 is etched to form sidewalls that are continuous with the orthogonal sidewalls of the segments of the wafer bonding layer 516. In such examples, the first segment 520 of the wafer bonding layer 516 has a first wafer bonding sidewall 534 that extends in a lateral direction from a surface of the protective overcoat 504 to the cap wafer 518. The second segment 522 of the wafer bonding layer 516 has a second wafer bonding sidewall 536 that is opposite to the first wafer bonding sidewall 534. The second wafer bonding sidewall 536 extends in a lateral direction from the surface of the protective overcoat 504 to the cap wafer 518. The first wafer bonding sidewall 534 and the second wafer bonding sidewall 536 are orthogonal to the surface of the protective overcoat 504 that extends in a longitudinal direction.

[0051] In the fourth stage, the cap wafer 518 is etched so that the sidewall of the first opening 530 has a first opening sidewall 538 and a second opening sidewall 540 opposite to the first opening sidewall 538. The first opening sidewall 538 includes the first wafer bonding sidewall 534 and continues the plane of the first wafer bonding sidewall 534 through the cap wafer 518. The second opening sidewall 540 includes the second wafer bonding sidewall 536 and continues the plane of the second wafer bonding sidewall 536 through the cap wafer 518.

[0052] As another example, both the wafer bonding layer 516 and the cap wafer 518 are etched to define the first opening sidewall 538 and the second opening sidewall 540 as flat surfaces. The flat surfaces of the first opening sidewall 538 and the second opening sidewall 540 define the edges of the wafer bonding layer 516 and the cap wafer 518. The second opening 532 is formed over the second connection pad 510 in a manner similar to that described with respect to the first opening 530. For example, the opening sidewalls of the second opening 532 are etched to define a flat surface through the wafer bonding layer 516 and the cap wafer 518, the flat surface being orthogonal to the plane defined by the semiconductor wafer 502.

[0053] Figure 8 An example of a fifth stage 440 of a first method for forming a stacked wafer semiconductor is shown. In the fifth stage 440, an insulating material 542 (e.g., Figure 1 Insulation material 122, Figure 2 Insulation material 222, Figure 3 The insulating material 324 of the cover wafer 518 is deposited over the cover wafer 518 and into the first opening 530 and the second opening 532 to form a substantially planar surface 544 of the insulating material 542. The insulating material 542 is deposited using a spin coating operation or a spray coating operation or a lamination operation to achieve the planar surface 544 of the insulating material 542. In one example, by Figure 7 The structure shown in FIG. 1 is immersed in the insulating material 542 or a solution thereof as a pre-dip operation to deposit the insulating material 542. In the case where the first opening 530 and the second opening 532 have a high aspect ratio, the pre-dip operation allows the insulating material 542 or a solution thereof to fill the first opening 530 and the second opening 532. The pre-dip operation is followed by a spin coating operation to remove excess insulating material from the insulating material 542 or a solution thereof.

[0054] Fig. 9 An example of a sixth stage 450 of the first method for forming a stacked wafer semiconductor is shown. In the sixth stage 450, the insulating material 542 is patterned to form a first cavity 546 leading to the first connection pad 508 and a second cavity 548 leading to the second connection pad 510. The first cavity 546 and the second cavity 548 extend from the planar surface 544 of the insulating material 542 in orthogonal directions to the first connection pad 508 and the second connection pad 510, respectively.

[0055] The first cavity 546 and the second cavity 548 are defined in the longitudinal direction by the through-hole sidewalls of the insulating material 542. For example, the first cavity 546 is defined by the first through-hole sidewall 550 and the second through-hole sidewall 552. The distance between the opposite sidewalls of the cavity characterizes the width of the resulting through-hole. For example, the width of the first cavity 546 is defined by the first through-hole sidewall 550 and the second through-hole sidewall 552. In some examples, the sidewalls of the first cavity 546 and the second cavity 548 are tapered so that the widths of the first cavity 546 and the second cavity 548 are different. For example, the first cavity 546 has a first width 554 at the end of the connection pad surface 556 defined by the flat surface 544 away from the first connection pad 508 and the second connection pad 510. The first width 554 is greater than the second width 558 near the connection pad surface 556. Thus, the opposing sidewalls of the cavity and the resulting via are separated by a shorter distance at the connection pad surface 556 than at the planar surface 544 .

[0056] The opposing sidewalls of the first cavity 546 and the second cavity 548 are tapered. For example, the first through-hole sidewall 550 forms a first angle 560 with the connection pad surface 556, and the second through-hole sidewall 552 forms a second angle 562 with the connection pad surface 556. The first angle 560 and the second angle 562 can be the same or different. The first angle 560 and / or the second angle 562 are angles between 30 degrees and 89 degrees.

[0057] Fig.10 4. An example of a seventh stage 460 of the first method for forming a stacked wafer semiconductor is shown. In the seventh stage 460, the first cavity 546 and the second cavity 548 are filled with a conductive material 564 to form a first through hole 566 (e.g., Figure 1 The through hole 114, Figure 2 The through hole 214, Figure 3 through hole 304) and a second through hole 568 (eg, Figure 1 The through hole 114, Figure 2 The through hole 214, Figure 3 The conductive material 564 is copper. The conductive material 564 is deposited and etched to extend beyond the planar surface 544 of the insulating material 542 at a conductive height 570 to form a conductive surface 572.

[0058] Fig.11 A method for forming a semiconductor device including stacked wafers (e.g., Figure 1 The first method of semiconductor manufacturing is an example of a first stage 602 of a second method of semiconductor packaging of a stacked wafer semiconductor 100). Stages 400 to 460 of the first method of semiconductor manufacturing are performed before the first stage 602 of the second method. Figures 4 to 10 The first method described is performed while the second method is performed to manufacture a semiconductor package in a flip-chip configuration.

[0059] In the first stage 602, the conductive surface 572 is coated with a solderable metal layer 700 extending in a lateral direction from the conductive height 570 to form a solderable metal sidewall 702 having a solderable metal height 704. The solderable metal layer 700 has a solderable metal surface 706 opposite to the planar surface 544 of the insulating material 542 and spaced apart from the planar surface 544 by the solderable metal height 704.

[0060] The solderable metal layer 700 provides a protective coating that prevents oxidation at the conductive material 564 at the conductive surface 572. The solderable metal layer 700 is formed by a solderable metal material. Examples of solderable metal materials include various forms of nickel, palladium, tin, silver, gold, etc. In the example shown, the conductive material 564, here copper (Cu), and the solderable metal layer 700 are formed by a solderable material, such as matte tin (Sn), tin silver or other suitable solderable materials with similar properties. The solderable metal layer 700 is formed by applying the solderable metal material to the conductive surface 572 in a deposition process such as electroplating. The solderable metal layer 700 is delimited by the insulating material 542 in the longitudinal direction.

[0061] Fig.12 An example of a second stage 604 of a second method for forming a semiconductor package is shown. The stacked wafer semiconductor shown in the first stage 602 is encapsulated in a molding 708 to protect the semiconductor package in a flip chip configuration. For example, the molding 708 encapsulates the semiconductor wafer 502, the cap wafer 518, and the insulating material 542. In some examples, such as a wafer chip level packaging configuration, the molding 708 is omitted.

[0062] Fig.13 A method for forming a semiconductor device including stacked wafers (e.g., Figure 1 In response to the execution of the first stage 802 of the third method, stages 400 to 460 of the first method of semiconductor manufacturing are performed. Figures 4 to 10 The described first method is followed by a third method for manufacturing a semiconductor package in a flat no-lead configuration.

[0063] In the first stage 802, Fig.10 The stacked die semiconductor shown in FIG. 1 is mounted on an interconnect 900 (alternatively referred to as a lead frame). Specifically, the interconnect 900 includes a die pad 902, a first lead 904, and a second lead 906. Fig.10 The stacked wafer semiconductor shown in FIG. 1 is mounted to a wafer pad 902 with a die attach material 907. First leads 904 and second leads 906 are exposed to the external environment to enable one or more devices of the stacked wafer semiconductor to be electrically coupled to one or more other electrical components external to the stacked wafer semiconductor.

[0064] The stacked wafer semiconductor includes a through hole 908 (eg, Figure 1 The through hole 114, Figure 2 The through hole 214, Figure 3 The through hole 304, Fig.10The through hole 908 includes a conductive material 910, such as copper. The through hole 908 provides a conductive path through the stacked wafer semiconductor to a corresponding connection pad 912.

[0065] Fig.14 An example of a second stage 804 of a third method for forming a semiconductor package is shown. The second stage 804 includes applying wire bonds 914 between the ends of the copper deposited in the through-hole 908 and the leads 904, 906 of the interconnect 900. The wire bonds 914 are formed from the conductive material 910 or other conductive material of the through-hole 908. Thus, the wire bonds 914 form a conductive path from the connection pads 912 to the interconnect 900.

[0066] Fig.15 An example of a third stage 806 of a third method for forming a semiconductor package is shown. In the third stage 806, the stacked wafer semiconductor shown in the second stage 804 is encapsulated in a molding 916 to protect the semiconductor package in a flat no-lead configuration.

[0067] Fig.16 A method for manufacturing a stacked wafer semiconductor having an insulating layer (eg Figure 1 Example process flow 1000 of stacked wafer semiconductor 100). At 1010, a semiconductor wafer (e.g., Figure 1 The semiconductor wafer 104, Figure 2 The semiconductor wafer 204, Figure 3 A semiconductor wafer 310, Figure 4 In some examples, the semiconductor wafer is mounted on the interconnect. The semiconductor wafer includes a die array. The die includes corresponding first connection pads (e.g., Figure 1 116) and a corresponding second connection pad (eg, Figure 1 The second connection pads 118 are separated by semiconductor regions in the semiconductor region and corresponding ones of the dies.

[0068] At 1020, a cover wafer (eg, Figure 1 The cover wafer 112, Figure 2 The cover wafer 212, Figure 3 The cover wafer 322, Figure 5 The cover wafer 518 of the tube die is mounted on the semiconductor wafer to form a stacked wafer. At 1030, the cover wafer is etched to expose the first connection pad and the second connection pad of the tube die so that a portion of the cover wafer passes over the semiconductor region of the tube die.

[0069] At 1040, an insulating material (e.g., Figure 1 Insulation material 122, Figure 2 Insulation material 222, Figure 3 Insulation material 324, Figure 8 The insulating material 542 is coated on the cover wafer. The insulating material is polyimide or PBO. In one example, coating includes spraying the insulating material on the cover wafer. In another example, coating includes spin coating the insulating material on the cover wafer. In another example, coating includes laminating the insulating material on the cover wafer. In some examples, coating includes spin coating the insulating material on the cover wafer material.

[0070] At 1050, the insulating material is patterned to form through holes in the insulating material leading to the first and second connection pads of the die. In one example, the insulating material on the cover wafer material is tapered with a wider opening at the end away from the corresponding connection pad. The taper of the through hole has an angle between 30 degrees and 89 degrees.

[0071] At 1060, a conductive material is deposited in the through hole. In one example, the conductive material is copper. The conductive material is deposited using electroplating or metal printing with a seed layer. At 1070, the semiconductor package is encapsulated in a molding. At 1080, the stacked wafer is singulated. Singulation separates the semiconductor packages in the array. In one example, singulation cuts the molding and interconnects associated with the leads, thereby producing singulated semiconductor packages. In one example, the semiconductor region of the corresponding semiconductor package includes a resonator.

[0072] In this specification, unless otherwise stated, "about", "approximately" or "substantially" preceding a parameter means within + / -10% of the parameter. Modifications to the described embodiments are possible, and other embodiments are possible, within the scope of the claims.

Claims

1. A semiconductor package, comprising: a semiconductor wafer having a first connection pad and a second connection pad separated by a semiconductor region of the semiconductor wafer, wherein a portion of the semiconductor wafer is covered by a protective overcoat; a cap wafer mounted to the semiconductor wafer and extending over the semiconductor region of the semiconductor wafer, wherein the cap wafer extends between the first connection pad and the second connection pad of the semiconductor wafer; and An insulating material covers the cap wafer, wherein the insulating material includes through holes leading to the first connection pad and the second connection pad, and the through holes are filled with a conductive material. 2 . The semiconductor package of claim 1 , wherein the through hole of the insulating material is tapered with a wider opening at an end away from the first and second connection pads. 3 . The semiconductor package according to claim 2 , further comprising a molding encapsulating the semiconductor wafer, the cap wafer and the insulating material. The semiconductor package according to claim 3 , wherein the conductive material filling the through hole is copper. 5 . The semiconductor package of claim 4 , further comprising matte tin or tin-silver plated on ends of the copper in the through-holes. 6 . The semiconductor package of claim 4 , further comprising a wire bond between an end of the copper in the through-hole and a lead of an interconnect. 7 . The semiconductor package according to claim 3 , wherein the semiconductor region of the semiconductor wafer includes a resonator. The semiconductor package according to claim 7 , wherein the semiconductor package is a stress sensor. 9 . The semiconductor package of claim 2 , wherein the taper of the through hole has an angle between 30 degrees and 89 degrees. 10 . The semiconductor package according to claim 1 , wherein the insulating material is polyimide, PBO or SU-8.

11. A method for forming a semiconductor package, the method comprising: mounting a cap wafer on a semiconductor wafer to form a stacked wafer, wherein the semiconductor wafer comprises an array of dies, the dies comprising first and second connection pads separated by semiconductor regions of respective ones of the dies; etching the cap wafer to expose the first and second connection pads of the die such that a portion of the cap wafer passes over the semiconductor region of the die; coating the cap wafer with an insulating material; processing the insulating material to form through holes in the insulating material leading to the first and second connecting pads of the die; depositing a conductive material in the through hole; and The stacked wafers are singulated. 12 . The method of claim 11 , wherein the through-hole of the insulating material is tapered with a wider opening at ends away from the first and second connection pads. The method of claim 12 , wherein the conductive material deposited in the via is copper.

14. The method according to claim 13, further comprising: Plating matte tin or tin-silver plating on ends of the copper deposited in the through-holes; and The stacked wafers are encapsulated in a molding.

15. The method according to claim 13, further comprising: mounting the stacked wafer on an interconnect; applying a wire bond between an end of the copper deposited in the through hole and a pin of the interconnect; and The stacked wafers are encapsulated in a molding.

16. The method of claim 13, wherein the taper of the through hole has an angle between 30 degrees and 89 degrees.

17. The method of claim 11, wherein the semiconductor region of the semiconductor wafer comprises a resonator.

18. The method of claim 11, wherein the coating comprises spraying the insulating material onto the cap wafer.

19. The method of claim 11, wherein the coating comprises spin coating the insulating material onto the cap wafer.

20. The method of claim 11, wherein the coating comprises laminating the insulating material on the cap wafer.

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