Embedded substrate structure and manufacturing method thereof

Abstract

The invention relates to an embedded substrate structure and a manufacturing method thereof, the substrate structure comprises an embedded layer, a dielectric layer, a dielectric layer blind hole, a circuit layer, a solder mask layer and a window, and the embedded layer comprises a TMV adapter plate, a connecting copper column, a chip, a metal bump, a heat-conducting adhesive, a cooling fin and a molding compound. The manufacturing method comprises the following steps: providing a temporary bonding carrier, bonding a TMV adapter plate and a chip on a temporary bonding film, filling with a molding compound, removing the temporary bonding film and the carrier, grinding the front surface of an embedded layer, laminating a dielectric layer on the front surface and the back surface of the embedded layer, and manufacturing a dielectric layer blind hole, the method comprises the following steps of: laminating a dielectric layer on a substrate, filling a dielectric layer blind hole on the dielectric layer and manufacturing a circuit layer, laminating the dielectric layer on the circuit layer and manufacturing a dielectric layer blind hole, filling a dielectric layer blind hole on the dielectric layer and manufacturing a circuit layer, and coating a solder mask layer on the outermost circuit layer and manufacturing a window. According to the invention, the wiring density and the signal transmission efficiency are improved, the heat dissipation performance is improved, and the stable operation of an electronic product is ensured.

Description

Technical Field

[0001] The invention relates to the field of electronic technology, and specifically discloses an embedded substrate structure and a manufacturing method thereof. Background Art

[0002] In the field of electronic technology, substrates are the basic support for electronic devices and the key part of circuit connection. Their structure and performance have a vital impact on the overall performance of electronic products. The traditional substrate structure is relatively simple and can still meet the needs of early electronic products. However, with the rapid development of science and technology, especially the continuous advancement of high-end chips and high-density packaging technology, the traditional substrate structure has gradually exposed shortcomings such as low wiring density, large packaging thickness, and limited circuit performance.

[0003] In order to meet these challenges, the industry has begun to explore new substrate structures. Among them, embedded substrates have attracted much attention because they can significantly increase wiring density, reduce package thickness, and optimize circuit performance. The common processing method in the industry is to make grooves on the substrate and place the chip in the grooves. However, the existing embedded substrate structure and its manufacturing method still have the following technical difficulties: 1. Under traditional processes, the embedding accuracy and density of chips are limited, resulting in a limited number of chips on the substrate, making it difficult to achieve high integration.

[0004] 2. The wiring design of traditional embedded substrates is often limited by space, resulting in low wiring density and long signal transmission paths, which affects the signal transmission efficiency and the overall performance of the system.

[0005] 3. As the integration of electronic components increases, the heat generated also increases accordingly. The existing embedded substrate structure is insufficient in heat dissipation, which can easily lead to excessive temperature of electronic components, affecting performance and life. Summary of the invention

[0006] One of the purposes of the present invention is to overcome the deficiencies in the prior art and provide an embedded substrate structure with higher wiring density, lower packaging thickness and better circuit performance.

[0007] Another object of the present invention is to provide a method for manufacturing an embedded substrate structure.

[0008] According to the technical solution provided by the present invention, the embedded substrate structure includes an embedding layer, a dielectric layer, a dielectric layer blind hole, a circuit layer, a solder resist layer and an opening; The embedded layer includes a TMV adapter board, connecting copper pillars, a chip, metal bumps, thermal conductive adhesive, a heat sink and a plastic packaging material; the TMV adapter board and the chip are arranged at intervals, the gap between the TMV adapter board and the chip is filled with the plastic packaging material, the TMV adapter board is provided with a plurality of connecting copper pillars running through the front and back sides thereof, the front side of the chip is provided with metal bumps, and the back side of the chip is attached with the heat sink through thermal conductive adhesive; A circuit stack is arranged on the front and back of the embedded layer, the circuit stack includes dielectric layers and circuit layers which are stacked and staggered, a circuit layer is arranged between adjacent dielectric layers, a dielectric layer is arranged between adjacent circuit layers, the innermost layer of the circuit stack is a dielectric layer, the outermost layer is a circuit layer, each dielectric layer is provided with a dielectric layer blind hole, adjacent circuit layers are connected and conducted through the dielectric layer blind holes between them, and the dielectric layer blind holes on the dielectric layer of the innermost layer of the circuit stack are connected and conducted with the connecting copper pillars of the TMV adapter board, the metal bumps on the front of the chip, and the heat sink; A solder resist layer is arranged on the outermost circuit layer, and a window is arranged on the solder resist layer, so that a part of the front side or the back side of the outermost circuit layer is exposed through the window.

[0009] Preferably, the embedding layer has a thickness of 400-1000 μm.

[0010] Preferably, the distance between the edge of the TMV adapter plate and the edge of the chip is greater than 500 μm.

[0011] Preferably, the chip includes any one or more of a radio frequency chip, a digital-analog chip, a storage chip, a DSP chip, a passive device chip, and a bridge connection chip.

[0012] Preferably, the heat sink is made of copper, aluminum, molybdenum copper, ceramic or carbon fiber.

[0013] Preferably, the material of the first dielectric layer and the second dielectric layer is ABF, polyimide or epoxy resin.

[0014] The manufacturing method of the embedded substrate structure comprises the following steps: S1. Providing a temporary bonding carrier, wherein a temporary bonding film is attached to the front side of the temporary bonding carrier; S2, bonding the TMV adapter plate to the temporary bonding film at a preset position, wherein the TMV adapter plate is provided with a plurality of connecting copper pillars penetrating the front and back sides thereof, attaching a heat sink to the back side of the chip through a thermal conductive adhesive, and bonding the chip with the heat sink attached to the back side to the temporary bonding film at a preset position, with the metal bumps of the chip facing upwards; S3, filling the gap between the TMV adapter board and the chip with a plastic packaging material; S4, removing the temporary bonding film and the temporary bonding carrier to obtain an embedded layer, grinding the front side of the reconstructed embedded layer to thin it to a preset thickness and expose the front side connecting the copper pillar and the metal bump; S5, laminating a dielectric layer on the front and back sides of the embedded layer, and making dielectric layer blind holes on the dielectric layer by laser drilling process; S6, filling the blind holes of the dielectric layer on the dielectric layer through an electroplating process to produce a circuit layer; S7, laminating a dielectric layer on the circuit layer, and making dielectric layer blind holes on the dielectric layer by laser drilling process; S8, filling the dielectric layer blind holes on the dielectric layer through an electroplating process to produce a circuit layer; S9, determine the number of times to repeat steps S7 and S8 as required; S10, coating a solder resist layer on the outermost circuit layer, and making a window, the window being opened to partially expose the outermost circuit layer, and finally forming the embedded substrate structure.

[0015] The above technical solution of the present invention has the following advantages compared with the prior art: 1. The present invention enables the chip to be embedded in the embedding layer with higher precision and density, thereby achieving a high degree of integration, reducing the volume of the embedded substrate structure of the present invention, and improving the overall performance of the product.

[0016] 2. The present invention realizes vertical interconnection among the chip, the first circuit layer and the second circuit layer, further improving the wiring density and signal transmission efficiency.

[0017] 3. The present invention realizes rapid conduction and dissipation of heat, improves heat dissipation performance, and ensures stable operation of electronic products. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram of a temporary bonding carrier with a temporary bonding film in step S1 of Example 1.

[0019] Figure 2 It is a schematic diagram of bonding the TMV adapter plate and the chip to the temporary bonding film in step S2 of Example 1.

[0020] Figure 3 It is a schematic diagram of reconstructing the TMV adapter board and the chip by encapsulating them using a plastic encapsulation process in step S3 of Example 1.

[0021] Figure 4 It is a schematic diagram of thinning the embedded layer to expose the metal bumps and connecting copper pillars in step S4 of embodiment 1.

[0022] Figure 5 It is a schematic diagram of making a blind hole on the first dielectric layer by using a laser drilling process in step S5 of embodiment 1.

[0023] Figure 6 It is a schematic diagram of filling the blind hole and manufacturing the first circuit layer through the electroplating process in step S6 of embodiment 1.

[0024] Figure 7 It is a schematic diagram of making a blind hole on the second dielectric layer by using a laser drilling process in step S7 of embodiment 1.

[0025] Figure 8 It is a schematic diagram of filling the blind hole and manufacturing the second circuit layer through the electroplating process in step S9 of embodiment 1.

[0026] Fig. 9 It is a schematic diagram of coating a solder resist layer and making a window in step S9 of Example 1.

[0027] Description of the Figures in the Specification: 101. Temporary bonding carrier; 102. Temporary bonding film; 103. TMV adapter board; 104. Connecting copper pillars; 105. Chip; 106. Metal bumps; 107. Thermal conductive adhesive; 108. Heat sink; 109. Plastic packaging material.

[0028] 201, embedded layer; 202, dielectric layer; 203, blind hole; 204, circuit layer.

[0029] 301, solder mask layer; 302, window. DETAILED DESCRIPTION

[0030] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it, but the embodiments are not intended to limit the present invention.

[0031] In the present invention, if directions (up, down, left, right, front and back) are described, it is only for the convenience of describing the technical solution of the present invention, and does not indicate or imply that the technical features referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it cannot be understood as a limitation of the present invention.

[0032] In the present invention, "several" means one or more, "multiple" means more than two, "greater than", "less than", "exceed" and the like are understood to exclude the number itself; "above", "below", "within" and the like are understood to include the number itself. In the description of the present invention, if there is a description of "first" or "second", it is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0033] In the present invention, unless otherwise clearly defined, the words "set", "install", "connect" and the like should be understood in a broad sense, for example, they can be directly connected or indirectly connected through an intermediate medium; they can be fixedly connected, detachably connected, or integrally formed; they can be mechanically connected, electrically connected, or able to communicate with each other; they can be the internal connection of two elements or the interaction relationship between two elements. Those skilled in the art can reasonably determine the specific meanings of the above words in the present invention in combination with the specific content of the technical solution.

[0034] Example 1 An embedded substrate structure, such as Fig. 9 As shown, it includes an embedded layer 201, a dielectric layer 202, a dielectric layer blind hole 203, a circuit layer 204, a solder resist layer 301 and an opening 302; The embedded layer 201 includes a TMV adapter board 103, a connecting copper column 104, a chip 105, a metal bump 106, a thermal conductive adhesive 107, a heat sink 108 and a plastic packaging material 109; the TMV adapter board 103 and the chip 105 are arranged at intervals, and the gap between the TMV adapter board 103 and the chip 105 is filled with the plastic packaging material 109, and the TMV adapter board 103 is provided with a plurality of connecting copper columns 104 running through the front and back sides thereof, the front side of the chip 105 is provided with a metal bump 106, and the back side of the chip 105 is mounted with the heat sink 108 via the thermal conductive adhesive 107; A circuit stack is provided on the front and back of the embedded layer 201. The circuit stack includes two dielectric layers 202 and two circuit layers 204 which are stacked and staggered. A circuit layer 204 is provided between adjacent dielectric layers 202. A dielectric layer 202 is provided between adjacent circuit layers 204. The innermost layer of the circuit stack is the dielectric layer 202, and the outermost layer is the circuit layer 204. A dielectric layer blind hole 203 is provided on each dielectric layer 202. Adjacent circuit layers 204 are connected and conducted through the dielectric layer blind hole 203 between them. The dielectric layer blind hole 203 on the innermost dielectric layer 202 of the circuit stack is connected and conducted with the connecting copper pillar 104 of the TMV adapter board 103, the metal bump 106 on the front of the chip 105, and the heat sink 108; A solder resist layer 301 is disposed on the outermost circuit layer 204 , and a window 302 is disposed on the solder resist layer 301 . The window 302 exposes a portion of the front or back side of the outermost circuit layer 204 .

[0035] The thickness of the embedding layer 201 is 400-1000 μm.

[0036] The distance between the edge of the TMV adapter plate 103 and the edge of the chip 105 is greater than 500 μm.

[0037] The chip 105 includes any one or more of a radio frequency chip, a digital-analog chip, a storage chip, a DSP chip, a passive device chip, and a bridge connection chip.

[0038] The heat sink 108 is made of copper, aluminum, molybdenum copper, ceramic or carbon fiber.

[0039] The material of the dielectric layer 202 is ABF, polyimide or epoxy resin.

[0040] The manufacturing method of the above-mentioned embedded substrate structure comprises the following steps: S1. Provide a temporary bonding carrier 101, wherein a temporary bonding film 102 is attached to the front of the temporary bonding carrier 101. Figure 1 As shown; S2, bonding the TMV adapter plate 103 to the temporary bonding film 102 at a preset position, the TMV adapter plate 103 is provided with a plurality of connecting copper pillars 104 running through the front and back sides thereof, attaching a heat sink 108 to the back side of the chip 105 through a thermal conductive adhesive 107, bonding the chip 105 with the heat sink 108 attached to the back side to the temporary bonding film 102 at a preset position, with the metal bumps 106 of the chip 105 facing upwards, as shown in FIG. Figure 2 As shown; S3, using the plastic packaging material 109 to fill the gap between the TMV adapter board 103 and the chip 105, such as Figure 3 As shown; S4, removing the temporary bonding film 102 and the temporary bonding carrier 101 to obtain the embedded layer 201, grinding the front side of the reconstructed embedded layer 201 to thin it to a preset thickness and exposing the front side connecting the copper pillar 104 and the metal bump 106, as shown in FIG. Figure 4 As shown; S5, laminating the dielectric layer 202 on the front and back sides of the embedded layer 201, and making dielectric layer blind holes 203 on the dielectric layer 202 by laser drilling process, such as Figure 5 As shown; S6, filling the dielectric layer blind hole 203 on the dielectric layer 202 by electroplating process and manufacturing the circuit layer 204, such as Figure 6 As shown; S7, laminating the dielectric layer 202 on the circuit layer 204, and making dielectric layer blind holes 203 on the dielectric layer 202 by laser drilling process, such as Figure 7 As shown; S8, filling the dielectric layer blind hole 203 on the dielectric layer 202 by electroplating process and manufacturing the circuit layer 204, such as Figure 8 As shown; S9, coating the solder resist layer 301 on the outermost circuit layer 204, and making a window 302, the window 302 makes the outermost circuit layer 204 partially exposed, and finally forming the embedded substrate structure, such as Fig. 9 shown.

[0041] Example 2 An embedded substrate structure includes an embedded layer 201, a dielectric layer 202, a dielectric layer blind hole 203, a circuit layer 204, a solder resist layer 301 and a window 302; The embedded layer 201 includes a TMV adapter board 103, a connecting copper column 104, a chip 105, a metal bump 106, a thermal conductive adhesive 107, a heat sink 108 and a plastic packaging material 109; the TMV adapter board 103 and the chip 105 are arranged at intervals, and the gap between the TMV adapter board 103 and the chip 105 is filled with the plastic packaging material 109, and the TMV adapter board 103 is provided with a plurality of connecting copper columns 104 running through the front and back sides thereof, the front side of the chip 105 is provided with a metal bump 106, and the back side of the chip 105 is mounted with the heat sink 108 via the thermal conductive adhesive 107; A circuit stack is arranged on the front and back of the embedded layer 201, and the circuit stack includes 6 dielectric layers 202 and 6 circuit layers 204 arranged in a stacked and staggered manner. A circuit layer 204 is arranged between adjacent dielectric layers 202, and a dielectric layer 202 is arranged between adjacent circuit layers 204. The innermost layer of the circuit stack is the dielectric layer 202, and the outermost layer is the circuit layer 204. A dielectric layer blind hole 203 is arranged on each dielectric layer 202, and adjacent circuit layers 204 are connected and conducted through the dielectric layer blind hole 203 between them. The dielectric layer blind hole 203 located on the innermost dielectric layer 202 of the circuit stack is connected and conducted with the connecting copper pillar 104 of the TMV adapter board 103, the metal bump 106 on the front of the chip 105, and the heat sink 108; A solder resist layer 301 is disposed on the outermost circuit layer 204 , and a window 302 is disposed on the solder resist layer 301 . The window 302 exposes a portion of the front or back side of the outermost circuit layer 204 .

[0042] The thickness of the embedding layer 201 is 400-1000 μm.

[0043] The distance between the edge of the TMV adapter plate 103 and the edge of the chip 105 is greater than 500 μm.

[0044] The chip 105 includes any one or more of a radio frequency chip, a digital-analog chip, a storage chip, a DSP chip, a passive device chip, and a bridge connection chip.

[0045] The heat sink 108 is made of copper, aluminum, molybdenum copper, ceramic or carbon fiber.

[0046] The material of the dielectric layer 202 is ABF, polyimide or epoxy resin.

[0047] The manufacturing method of the above-mentioned embedded substrate structure comprises the following steps: S1, providing a temporary bonding carrier 101, wherein a temporary bonding film 102 is attached to the front side of the temporary bonding carrier 101; S2, bonding the TMV adapter plate 103 to the temporary bonding film 102 at a preset position, wherein the TMV adapter plate 103 is provided with a plurality of connecting copper pillars 104 penetrating the front and back sides thereof, attaching a heat sink 108 to the back side of the chip 105 through a thermal conductive adhesive 107, and bonding the chip 105 with the heat sink 108 attached to the back side to the temporary bonding film 102 at a preset position, with the metal bumps 106 of the chip 105 facing upwards; S3, using a plastic packaging material 109 to fill the gap between the TMV adapter board 103 and the chip 105; S4, removing the temporary bonding film 102 and the temporary bonding carrier 101 to obtain the embedded layer 201, grinding the front side of the reconstructed embedded layer 201 to thin it to a preset thickness and exposing the front side connecting the copper pillar 104 and the metal bump 106; S5, laminating the dielectric layer 202 on the front and back sides of the embedded layer 201, and making dielectric layer blind holes 203 on the dielectric layer 202 by laser drilling process; S6, filling the dielectric layer blind holes 203 on the dielectric layer 202 by electroplating process and manufacturing the circuit layer 204; S7, laminating the dielectric layer 202 on the circuit layer 204, and making dielectric layer blind holes 203 on the dielectric layer 202 by laser drilling process; S8, filling the dielectric layer blind holes 203 on the dielectric layer 202 by electroplating process and manufacturing the circuit layer 204; S9, repeating steps S7 and S8 for 5 times as required; S10, coating a solder resist layer 301 on the outermost circuit layer 204, and making a window 302, wherein the window 302 partially exposes the outermost circuit layer 204, thereby finally forming the embedded substrate structure.

[0048] The principles and advantages of the present invention are as follows: 1. An embedded substrate structure and a manufacturing method thereof described in the present invention firstly bond a TMV adapter plate and a chip 105 with a heat sink 108 on the back to a temporary bonding film 102 according to a preset position, and then use a plastic packaging material 109 to fill the gap between the TMV adapter plate 103 and the chip 105, and then remove the temporary bonding film 102 and the temporary bonding carrier 101, so that the chip 105 is embedded in the embedding layer 201 with higher precision and density, thereby achieving a high degree of integration of the chip 105, reducing the volume of the embedded substrate structure of the present invention, and improving the overall performance of the product.

[0049] 2. The present invention adopts a TMV adapter board 103, and the metal bumps 106 of the chip 105 are connected and conducted with the circuit layer 204 through the dielectric layer blind holes 203 in the dielectric layer 202 located above it, and adjacent circuit layers 204 are connected and conducted through the dielectric layer blind holes 203. The upper and lower circuit layers 204 covering the front and back sides of the embedded layer 201 are connected and conducted through the dielectric layer blind holes 203 and the connecting copper pillars 104 in the TMV adapter board 103. The adjacent circuit layers 204 located below the chip 105 are connected and conducted through the dielectric layer blind holes 203, thereby realizing vertical interconnection between the chip 105 and the circuit layer 204, further improving the wiring density and signal transmission efficiency.

[0050] 3. The present invention mounts a heat sink 108 on the back of the chip 105. The heat sink 108 is connected to the circuit layer 204 through the dielectric layer blind holes 203 in the dielectric layer 202 located therebelow, and adjacent circuit layers 204 are connected through the dielectric layer blind holes 203, thereby achieving rapid conduction and dissipation of heat, improving heat dissipation performance, and ensuring stable operation of electronic products.

[0051] Finally, it should be noted that the above specific implementation methods are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to examples, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present invention, which should be included in the scope of the claims of the present invention.

Claims

1. An embedded substrate structure, characterized in that: It includes an embedded layer (201), a dielectric layer (202), a dielectric layer blind hole (203), a circuit layer (204), a solder resist layer (301) and an opening (302); The embedded layer (201) comprises a TMV adapter plate (103), connecting copper pillars (104), a chip (105), metal bumps (106), thermal conductive adhesive (107), a heat sink (108) and a plastic encapsulation material (109); the TMV adapter plate (103) and the chip (105) are arranged at intervals, the gap between the TMV adapter plate (103) and the chip (105) is filled with the plastic encapsulation material (109), a plurality of connecting copper pillars (104) penetrating the front and back sides of the TMV adapter plate (103) are arranged inside the TMV adapter plate (103), the front side of the chip (105) is provided with metal bumps (106), and the back side of the chip (105) is mounted with the heat sink (108) via the thermal conductive adhesive (107); A circuit stack is arranged on the front and back sides of the embedded layer (201), the circuit stack comprises dielectric layers (202) and circuit layers (204) arranged in a stacked and staggered manner, a circuit layer (204) is arranged between adjacent dielectric layers (202), a dielectric layer (202) is arranged between adjacent circuit layers (204), the innermost layer of the circuit stack is the dielectric layer (202), and the outermost layer is the circuit layer (204), a dielectric layer blind hole (203) is arranged on each dielectric layer (202), adjacent circuit layers (204) are connected and conducted through the dielectric layer blind hole (203) between them, and the dielectric layer blind hole (203) located on the innermost dielectric layer (202) of the circuit stack is connected and conducted to the connecting copper pillars (104) of the TMV adapter board (103), the metal bumps (106) on the front side of the chip (105), and the heat sink (108); A solder resist layer (301) is provided on the outermost circuit layer (204), and a window (302) is provided on the solder resist layer (301). The window (302) exposes part of the front or back side of the outermost circuit layer (204).

2. The embedded substrate structure according to claim 1, wherein: The thickness of the embedded layer (201) is 400-1000 μm.

3. The embedded substrate structure according to claim 1, wherein: The distance between the edge of the TMV adapter plate (103) and the edge of the chip (105) is greater than 500 μm.

4. The embedded substrate structure according to claim 1, wherein: The chip (105) includes any one or more of a radio frequency chip, a digital-analog chip, a storage chip, a DSP chip, a passive device chip, and a bridge connection chip.

5. The embedded substrate structure according to claim 1, wherein: The material of the heat sink (108) is copper, aluminum, molybdenum copper, ceramic or carbon fiber.

6. The embedded substrate structure according to claim 1, wherein: The material of the dielectric layer (202) is ABF, polyimide or epoxy resin.

7. The method for manufacturing an embedded substrate structure according to any one of claims 1 to 6, characterized in that The preparation method comprises the following steps: S1, providing a temporary bonding carrier (101), wherein a temporary bonding film (102) is attached to the front side of the temporary bonding carrier (101); S2, bonding the TMV adapter plate (103) to the temporary bonding film (102) at a preset position, wherein the interior of the TMV adapter plate (103) is provided with a plurality of connecting copper pillars (104) penetrating the front and back sides thereof, attaching a heat sink (108) to the back side of the chip (105) via a thermal conductive adhesive (107), and bonding the chip (105) with the heat sink (108) attached to the back side to the temporary bonding film (102) at a preset position, with the metal bumps (106) of the chip (105) facing upwards; S3, using a plastic packaging material (109) to fill the gap between the TMV adapter plate (103) and the chip (105); S4, removing the temporary bonding film (102) and the temporary bonding carrier (101) to obtain an embedded layer (201), grinding the front side of the reconstructed embedded layer (201) to thin it to a preset thickness and expose the front side connecting the copper pillar (104) and the metal bump (106); S5, laminating a dielectric layer (202) on the front and back sides of the embedded layer (201), and producing dielectric layer blind holes (203) on the dielectric layer (202) by laser drilling technology; S6, filling the dielectric layer blind holes (203) on the dielectric layer (202) through an electroplating process to produce a circuit layer (204); S7, laminating the dielectric layer (202) on the circuit layer (204), and producing dielectric layer blind holes (203) on the dielectric layer (202) by laser drilling technology; S8, filling the dielectric layer blind holes (203) on the dielectric layer (202) through an electroplating process to produce a circuit layer (204); S9, determine the number of times to repeat steps S7 and S8 as required; S10, coating a solder resist layer (301) on the outermost circuit layer (204), and making a window (302), wherein the window (302) partially exposes the outermost circuit layer (204), thereby finally forming the embedded substrate structure.

Images