Semiconductor device, preparation method and electronic equipment

Abstract

The invention relates to a semiconductor device, a preparation method and electronic equipment. The semiconductor device includes a substrate, source pads including a first layer of source pads covering a gate structure and an active region and a second layer of source pads covering a portion of a top surface of the first layer of source pads, and a gate pad. The gate bonding pad comprises a first layer of gate bonding pad and a second layer of gate bonding pad, the first layer of gate bonding pad covers part of the top surface of the substrate, the second layer of gate bonding pad covers part of the top surfaces of the first layer of gate bonding pad and the first layer of source bonding pad, and the source bonding pad is insulated from the gate bonding pad. The coverage area of the first layer of gate bonding pad is smaller than that of the second layer of gate bonding pad, so that the space can be saved, the area of the active region is further increased, the specific on-resistance value of the device can be reduced, and the reliability and the electrical property of the semiconductor device are improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device, a preparation method and an electronic device. Background Art

[0002] Under the same high voltage environment, compared with traditional silicon insulated gate bipolar field effect transistors, silicon carbide metal oxide field effect transistors have higher operating temperature, lower switching loss and higher switching frequency.

[0003] However, in conventional technology, the gate pad and the source pad occupy a large area of ​​the chip, resulting in a reduction in the area of ​​the active region, which increases the value of the on-resistance and reduces the reliability and electrical properties of the device. Summary of the invention

[0004] The purpose of this application is to provide a semiconductor device, a preparation method and an electronic device, which can increase the area of ​​the active region, reduce the specific on-resistance of the device, and improve the reliability and electrical properties of the device. To achieve the purpose of this application, this application provides the following technical solutions:

[0005] In a first aspect, the present application provides a semiconductor device, comprising:

[0006] A substrate, the substrate comprising a plurality of active regions and a plurality of gate structures, the plurality of active regions being spaced apart in the substrate along a first direction, the plurality of gate structures being spaced apart on a top surface of the substrate along the first direction, the gate structures covering a portion of the active regions, and the gate structures and the active regions being staggered;

[0007] A source pad, comprising a first layer of source pads and a second layer of source pads, wherein the first layer of source pads covers the gate structure and the active area, and the second layer of source pads covers a portion of the top surface of the first layer of source pads;

[0008] The gate pad comprises a first layer of gate pads and a second layer of gate pads, wherein the first layer of gate pads covers a portion of the top surface of the substrate, and the second layer of gate pads covers a portion of the top surface of the first layer of gate pads and the first layer of source pads, wherein the source pad and the gate pad are insulated.

[0009] The semiconductor device of the present application includes a substrate, a source pad and a gate pad. The substrate includes multiple active areas and multiple gate structures. The multiple active areas are spaced in the substrate along a first direction. The multiple gate structures are spaced on the top surface of the substrate along the first direction. The gate structure covers part of the active area, and the gate structure and the active area are staggered. The gate pad includes a first layer of gate pads and a second layer of gate pads. The first layer of gate pads covers part of the top surface of the substrate and can provide an electrical connection point for the electrical lead-out of the gate. The second layer of gate pads covers part of the top surface of the first layer of gate pads and the first layer of source pads. The first layer of gate pads can be connected to the circuit, thereby realizing the electrical connection of the gate in the circuit. The coverage area of ​​the first layer of gate pads is smaller than that of the second layer of gate pads, so that space can be saved at the bottom of the second layer of gate pads, and then a cell is formed at the bottom of the second layer of gate pads, increasing the area of ​​the active area, reducing the specific on-resistance value of the device, and improving the reliability and electrical properties of the semiconductor device. The coverage area of ​​the first-layer source pad is larger than the coverage area of ​​the second-layer source pad. It is possible to provide an electrical connection point of the source for the increased active area through the first-layer source pad without changing the coverage area of ​​the gate pad and the source pad, and connect to the circuit through the second-layer source pad, thereby realizing the electrical connection of the source.

[0010] In one embodiment,

[0011] The size of the first layer of gate pads in the first direction is smaller than the size of the first layer of source pads in the first direction;

[0012] A size of the first-layer source pad in the first direction is smaller than a size of the second-layer source pad in the first direction.

[0013] In one embodiment, the semiconductor device further includes:

[0014] A first dielectric layer, the first dielectric layer covers the first layer source pad and the first layer gate pad, and the first dielectric layer is located between the first layer gate pad and the second layer gate pad, and between the first layer source pad and the second layer gate pad;

[0015] The first dielectric layer includes a first notch and a second notch, the first layer gate pad is connected to the second layer gate pad via the first notch, and the first layer source pad is connected to the second layer source pad via the second notch.

[0016] In one embodiment, the semiconductor device further includes:

[0017] A second dielectric layer covers the gate structure.

[0018] In a second aspect, the present application further provides an electronic device, including:

[0019] A semiconductor device as described in any of the above.

[0020] The electronic device of the present application includes any of the semiconductor devices described above, including a substrate, a source pad and a gate pad, the substrate includes multiple active areas and multiple gate structures, the multiple active areas are spaced in the substrate along a first direction, the multiple gate structures are spaced on the top surface of the substrate along the first direction, the gate structure covers part of the active area, and the gate structure and the active area are staggered. The gate pad includes a first layer of gate pads and a second layer of gate pads, the first layer of gate pads covers part of the top surface of the substrate, and can provide an electrical connection point for the electrical lead-out of the gate, the second layer of gate pads covers part of the top surface of the first layer of gate pads and the first layer of source pads, and can connect the first layer of gate pads to the circuit, thereby realizing the electrical connection of the gate in the circuit. The coverage area of ​​the first layer of gate pads is smaller than that of the second layer of gate pads, so that space can be saved at the bottom of the second layer of gate pads, and then a cell is formed at the bottom of the second layer of gate pads, the area of ​​the active area is increased, the specific on-resistance value of the device can be reduced, and the reliability and electrical properties of the semiconductor device can be improved. The coverage area of ​​the first-layer source pad is larger than the coverage area of ​​the second-layer source pad. It is possible to provide an electrical connection point of the source for the increased active area through the first-layer source pad without changing the coverage area of ​​the gate pad and the source pad, and connect to the circuit through the second-layer source pad, thereby realizing the electrical connection of the source.

[0021] In a third aspect, the present application further provides a method for preparing a semiconductor device, comprising:

[0022] Providing a substrate, the substrate comprising a gate structure and an active area;

[0023] Providing a substrate, the substrate comprising a plurality of active regions and a plurality of gate structures, the plurality of active regions being spaced apart in the substrate along a first direction, the plurality of gate structures being spaced apart and distributed on a top surface of the substrate along the first direction, the gate structures covering a portion of the active regions, and the gate structures and the active regions being staggered;

[0024] A source pad and a gate pad are formed on the top surface of the substrate, wherein the source pad includes a first layer of source pads and a second layer of source pads, the first layer of source pads covers the gate structure and the active area, the second layer of source pads covers a portion of the top surface of the first layer of source pads, and the gate pad includes a first layer of gate pads and a second layer of gate pads, the first layer of gate pads covers a portion of the top surface of the substrate, and the second layer of gate pads covers a portion of the top surface of the first layer of gate pads and the first layer of source pads, wherein the source pad and the gate pad are insulated.

[0025] The method for preparing a semiconductor device of the present application includes providing a substrate, the substrate including multiple active areas and multiple gate structures, the multiple active areas are spaced in the substrate along a first direction, the multiple gate structures are spaced on the top surface of the substrate along the first direction, the gate structure covers part of the active area, and the gate structure and the active area are staggered. Then, a source pad and a gate pad are formed on the top surface of the substrate, wherein the source pad includes a first layer of source pad and a second layer of source pad, the first layer of source pad covers the gate structure and the active area, the second layer of source pad covers part of the top surface of the first layer of source pad, the gate pad includes a first layer of gate pad and a second layer of gate pad, the first layer of gate pad covers part of the top surface of the substrate, the second layer of gate pad covers part of the top surface of the first layer of gate pad and the first layer of source pad, wherein the source pad and the gate pad are insulated. The first layer of gate pad provides an electrical connection point for the electrical lead-out of the gate, and the second layer of gate pad connects the first layer of gate pad to the circuit to realize the electrical connection of the gate in the circuit. The coverage area of ​​the first layer gate pad is smaller than that of the second layer gate pad, which can save space at the bottom of the second layer gate pad, and then form a cell at the bottom of the second layer gate pad, increase the area of ​​the active area, reduce the device's specific on-resistance value, and improve the reliability and electrical properties of the semiconductor device. The coverage area of ​​the first layer source pad is larger than that of the second layer source pad, which can provide an electrical connection point of the source for the increased active area through the first layer source pad without changing the coverage area of ​​the gate pad and the source pad, and connect to the circuit through the second layer source pad, thereby realizing the electrical connection of the source.

[0026] In one embodiment, forming a source pad and a gate pad on the top surface of the substrate includes:

[0027] forming a first metal layer on the top surface of the substrate;

[0028] Etching the first metal layer to form the first layer gate pad and the first layer source pad;

[0029] forming a second metal layer on top surfaces of the first layer of gate pads and the first layer of source pads;

[0030] The second metal layer is etched to form the second gate pad and the second source pad.

[0031] In one embodiment, after etching the first metal layer and before forming the second metal layer on the top surface of the first gate pad and the second gate pad, the method further includes:

[0032] forming a first dielectric material layer on top surfaces of the first layer of gate pads and the first layer of source pads;

[0033] The first dielectric material layer is etched to form a first dielectric layer, wherein the first dielectric layer includes a first notch and a second notch, the first layer gate pad is connected to the second layer gate pad through the first notch, and the first layer source pad is connected to the second layer source pad through the second notch.

[0034] In one embodiment,

[0035] The size of the first layer of gate pads in the first direction is smaller than the size of the first layer of source pads in the first direction;

[0036] A size of the first-layer source pad in the first direction is smaller than a size of the second-layer source pad in the first direction.

[0037] In one embodiment, after providing the substrate and before forming a source pad and a gate pad on the top surface of the substrate, the method further includes:

[0038] A second dielectric layer is formed, wherein the second dielectric layer covers the gate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0040] Figure 1 is a schematic cross-sectional structure diagram of a semiconductor device provided in an embodiment;

[0041] Figure 2 is a flow chart of a method for preparing a semiconductor device provided in another embodiment;

[0042] Figure 3 is a schematic cross-sectional view of a structure obtained in step S11 of a method for preparing a semiconductor device provided in another embodiment;

[0043] Figure 4 is a flow chart of steps S151 to S156 in a method for preparing a semiconductor device provided in another embodiment;

[0044] Figure 5 is a schematic cross-sectional view of a structure obtained in step S151 in a method for preparing a semiconductor device provided in another embodiment;

[0045] Figure 6is a flow chart of steps S153 and S154 in a method for preparing a semiconductor device provided in another embodiment;

[0046] Figure 7 It is a schematic cross-sectional view of a structure obtained in step S154 in a method for preparing a semiconductor device provided in another embodiment.

[0047] Description of Reference Numerals

[0048] 10. Substrate; 101. Active area; 102. Gate structure; 20. Source pad; 201. First-layer source pad; 202. Second-layer source pad; 30. Gate pad; 301. First-layer gate pad; 302. Second-layer gate pad; 40. First dielectric layer; 50. Second dielectric layer; 60. First metal layer. DETAILED DESCRIPTION

[0049] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0051] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0052] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0053] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0054] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0055] In the performance evaluation of power devices such as silicon carbide metal oxide field effect transistors, the specific on-resistance value is an important indicator for evaluating the performance of unipolar power devices. The smaller the value of the specific on-resistance, the better the performance of the device. Among them, the value of the specific on-resistance is negatively correlated with the area of ​​the active region.

[0056] However, in conventional technology, the gate pad and the source pad occupy a large area of ​​the chip, resulting in a smaller area of ​​the active region, which in turn increases the value of the on-resistance and reduces the reliability and electrical properties of the device.

[0057] The present application embodiment provides a semiconductor device. Figure 1 The semiconductor device may include: a substrate 10, a source pad 20 and a gate pad 30. The substrate 10 includes a plurality of active regions 101 and a plurality of gate structures 102. The plurality of active regions 101 are spaced apart in the substrate 10 along a first direction. The plurality of gate structures 102 are spaced apart on the top surface of the substrate 10 along the first direction. The gate structures 102 cover a portion of the active regions 101, and the gate structures 102 and the active regions 101 are staggered. The source pad 20 includes a first layer of source pads 201 and a second layer of source pads 202. The first layer of source pads 201 covers the gate structures 102 and the active regions 101, and the second layer of source pads 202 covers a portion of the top surface of the first layer of source pads 201. The gate pad 30 includes a first-layer gate pad 301 and a second-layer gate pad 302, wherein the first-layer gate pad 301 covers a portion of the top surface of the substrate 10, and the second-layer gate pad 302 covers a portion of the top surface of the first-layer gate pad 301 and the first-layer source pad 201, wherein the source pad 20 and the gate pad 30 are insulated.

[0058] By way of example, the substrate 10 may include, but is not limited to, a silicon carbide (SiC) substrate.

[0059] Exemplarily, the gate structure 102 may include a gate conductive layer, a gate oxide layer and a gate electrode. The gate conductive layer, the material of the gate conductive layer may include but is not limited to a conductive layer, for example, a doped polysilicon gate conductive layer. The size of the gate conductive layer in the second direction may be 30nm~50nm, for example, the size of the gate conductive layer in the second direction may be 30nm, 40nm or 50nm. The gate oxide layer may include but is not limited to an oxide layer, for example, a silicon dioxide layer. The gate electrode may include but is not limited to a metal gate electrode. The size of the gate oxide layer in the second direction may be 300nm~500nm, for example, the size of the gate oxide layer in the second direction may be 300nm, 400nm or 500nm, etc.

[0060] Exemplarily, the first direction is as follows Figure 1 The second direction is as shown in Figure 1 OY direction shown in .

[0061] Exemplarily, the active region 101 includes a source region and a drain region and a well region located at the bottom of the source region and the drain region. It should be noted that the semiconductor device may also include a source electrode and a drain electrode, the source electrode covers the top surface of the source region, and the drain electrode is located at the top surface of the drain region.

[0062] For example, the material of the source pad 20 may include, but is not limited to, copper or other conductive materials. The material of the gate pad 30 may include, but is not limited to, copper or other conductive materials.

[0063] The semiconductor device of the present application includes a substrate 10, a source pad 20 and a gate pad 30. The substrate 10 includes a plurality of active regions 101 and a plurality of gate structures 102. The plurality of active regions 101 are spaced apart in the substrate 10 along a first direction. The plurality of gate structures 102 are spaced apart on the top surface of the substrate 10 along the first direction. The gate structures 102 cover a portion of the active regions 101, and the gate structures 102 and the active regions 101 are staggered. The gate pad 30 includes a first layer of gate pads 301 and a second layer of gate pads 302. The first layer of gate pads 301 covers a portion of the top surface of the substrate 10 and can provide an electrical connection point for the electrical lead-out of the gate. The second layer of gate pads 302 covers a portion of the top surface of the first layer of gate pads 301 and the first layer of source pads 201, and can connect the first layer of gate pads 301 to a circuit, thereby realizing the electrical connection of the gate in the circuit. The coverage area of ​​the first layer gate pad 301 is smaller than that of the second layer gate pad 302, which can save space at the bottom of the second layer gate pad 302, and then form a cell at the bottom of the second layer gate pad 302, increase the area of ​​the active area 101, reduce the device's specific on-resistance value, and improve the reliability and electrical properties of the semiconductor device. The coverage area of ​​the first layer source pad 201 is larger than that of the second layer source pad 202, which can provide an electrical connection point of the source for the increased active area 101 through the first layer source pad 201 without changing the coverage area of ​​the gate pad 30 and the source pad 20, and connect to the circuit through the second layer source pad 202, thereby realizing the electrical connection of the source.

[0064] In some embodiments, please refer to Figure 1 The size of the first layer gate pad 301 in the first direction is smaller than the size of the first layer source pad 201 in the first direction. The size of the first layer source pad 201 in the first direction is smaller than the size of the second layer source pad 202 in the first direction.

[0065] In the semiconductor device provided in the embodiment of the present application, by setting the size of the first layer gate pad 301 in the first direction to be smaller than the size of the first layer source pad 201 in the first direction, the first layer gate pad 301 can save space to increase the coverage area of ​​the first layer source pad 201, and then more cells can be arranged below the first layer source pad 201, thereby increasing the area of ​​the active area 101, reducing the specific on-resistance value of the device, and improving the electrical properties of the semiconductor device. By setting the size of the first layer source pad 201 in the first direction to be smaller than the size of the second layer source pad 202 in the first direction, the first layer source pad 201 can be electrically led out by using the second layer source pad 202 when the first layer source pad 201 completely covers the active area 101, and then the source can be connected to the circuit to achieve the electrical connection of the source.

[0066] In some embodiments, please refer to Figure 1 The semiconductor device further includes: a first dielectric layer 40, the first dielectric layer 40 covers the first source pad 201 and the first gate pad 301, and the first dielectric layer 40 is located between the first gate pad 301 and the second gate pad 302, and between the first source pad 201 and the second gate pad 302; wherein the first dielectric layer 40 includes a first notch and a second notch, the first gate pad 301 and the second gate pad 302 are connected through the first notch, and the first source pad 201 and the second source pad 202 are connected through the second notch.

[0067] As an example, the material of the first dielectric layer 40 may include but is not limited to silicon oxide (SiO 2 ), silicon nitride (SiN x ), aluminum oxide (Al 2 O 3 ), low dielectric constant (Low-k) materials, high dielectric constant (High-k) materials, etc.

[0068] As an example, the sizes of the first notch and the second notch in the first direction can be set according to the actual use requirements of the semiconductor device to ensure electrical connection between the first layer gate pad 301 and the second layer gate pad 302, and between the first layer source pad 201 and the second layer source pad 202.

[0069] The semiconductor device provided in the embodiment of the present application can separate the source pad 20 and the gate pad 30 by providing the first dielectric layer 40, so as to achieve electrical isolation of the semiconductor device, and to achieve efficient transmission of signals in the multi-layer interconnection structure. The first notch and the second notch are provided in the first dielectric layer 40, so as to achieve electrical connection between the first layer gate pad 301 and the second layer gate pad 302, and between the first layer source pad 201 and the second layer source pad 202, so as to achieve efficient transmission of signals.

[0070] In some embodiments, please refer to Figure 1 The semiconductor device further includes: a second dielectric layer 50 , and the second dielectric layer 50 covers the gate structure 102 .

[0071] As an example, the material of the second dielectric layer 50 may include but is not limited to silicon oxide (SiO 2 ), silicon nitride (SiN x ), aluminum oxide (Al 2 O 3), low dielectric constant (Low-k) material, high dielectric constant (High-k) material, etc. The thickness of the second dielectric layer 50 can be 800nm~1100nm, for example, the thickness of the second dielectric layer 50 can be 800nm, 900nm, 1000nm or 1100nm, etc.

[0072] The semiconductor device provided in the embodiment of the present application can electrically isolate the gate structure 102 from other film layers by providing the second dielectric layer 50 to achieve signal transmission.

[0073] It should be noted that the semiconductor device in the embodiment of the present application may further include a metal silicide layer, and the metal silicide layer is located between the active area 101 and the first source pad 201, which can reduce the contact resistance of the device.

[0074] It should be noted that the semiconductor device in the embodiment of the present application may further include a passivation layer, which covers the gate pad 30, the source pad 20 and the first dielectric layer 40. The passivation layer can protect the device during the packaging process.

[0075] An embodiment of the present application provides an electronic device, comprising the semiconductor device in any one of the above embodiments.

[0076] The electronic device of the present application includes a substrate, a source pad and a gate pad. The substrate includes multiple active areas and multiple gate structures. The multiple active areas are spaced in the substrate along a first direction. The multiple gate structures are spaced on the top surface of the substrate along the first direction. The gate structure covers part of the active area, and the gate structure and the active area are staggered. The gate pad includes a first layer of gate pads and a second layer of gate pads. The first layer of gate pads covers part of the top surface of the substrate and can provide an electrical connection point for the electrical lead-out of the gate. The second layer of gate pads covers part of the top surface of the first layer of gate pads and the first layer of source pads, and can connect the first layer of gate pads to the circuit, thereby realizing the electrical connection of the gate in the circuit. The coverage area of ​​the first layer of gate pads is smaller than that of the second layer of gate pads, which can save space, thereby increasing the area of ​​the active area, reducing the specific on-resistance value of the device, and improving the reliability and electrical properties of the semiconductor device. The coverage area of ​​the first-layer source pad is larger than the coverage area of ​​the second-layer source pad. It is possible to provide an electrical connection point of the source for the increased active area through the first-layer source pad without changing the coverage area of ​​the gate pad and the source pad, and connect to the circuit through the second-layer source pad, thereby realizing the electrical connection of the source.

[0077] The present invention provides a method for preparing a semiconductor device. Figure 2 , the method for preparing the semiconductor device may include:

[0078] S11: providing a substrate, the substrate comprising a plurality of active regions and a plurality of gate structures, wherein the plurality of active regions are spaced apart in the substrate along a first direction, the plurality of gate structures are spaced apart on a top surface of the substrate along the first direction, the gate structures cover a portion of the active regions, and the gate structures and the active regions are staggered.

[0079] As an example, see Figure 3 The substrate 10 may include but is not limited to a silicon carbide (SiC) substrate.

[0080] As an example, see Figure 3 The gate structure 102 may include a gate conductive layer, a gate oxide layer and a gate electrode. The gate conductive layer, the material of the gate conductive layer may include but is not limited to a conductive layer, for example, a doped polysilicon gate conductive layer or a metal gate conductive layer, etc. Specifically, in this embodiment, the gate conductive layer is a doped polysilicon gate conductive layer. The size of the gate conductive layer in the second direction may be 30nm~50nm, for example, the size of the gate conductive layer in the second direction may be 30nm, 40nm or 50nm. The gate oxide layer may include but is not limited to an oxide layer, for example, a silicon dioxide layer. The gate electrode may include but is not limited to a metal gate electrode. The size of the gate oxide layer in the second direction may be 300nm~500nm, for example, the size of the gate oxide layer in the second direction may be 300nm, 400nm or 500nm, etc.

[0081] As an example, see Figure 3 The active region 101 includes a source region and a drain region, and a well region located at the bottom of the source region and the drain region. The active region can be formed by, but not limited to, ion implantation. It should be noted that the semiconductor device also includes a source electrode and a drain electrode, the source electrode covers the top surface of the source region, and the drain electrode is located on the top surface of the drain region.

[0082] As an example, the first direction is as follows Figure 3 The second direction is as shown in Figure 3 OY direction shown in .

[0083] S15: forming a source pad and a gate pad on the top surface of the substrate, wherein the source pad comprises a first layer of source pads and a second layer of source pads, the first layer of source pads covers the gate structure and the active area, the second layer of source pads covers a portion of the top surface of the first layer of source pads, and the gate pad comprises a first layer of gate pads and a second layer of gate pads, the first layer of gate pads covers a portion of the top surface of the substrate, the second layer of gate pads covers a portion of the top surface of the first layer of gate pads and the first layer of source pads, wherein the source pad and the gate pad are insulated from each other.

[0084] As an example, see Figure 1The material of the source pad 20 may include but is not limited to copper or other conductive materials. The material of the gate pad 30 may include but is not limited to copper or other conductive materials.

[0085] The method for preparing a semiconductor device of the present application includes providing a substrate, the substrate including multiple active areas and multiple gate structures, the multiple active areas are spaced in the substrate along a first direction, the multiple gate structures are spaced on the top surface of the substrate along the first direction, the gate structure covers part of the active area, and the gate structure and the active area are staggered. Then, a source pad and a gate pad are formed on the top surface of the substrate, wherein the source pad includes a first layer of source pad and a second layer of source pad, the first layer of source pad covers the gate structure and the active area, the second layer of source pad covers part of the top surface of the first layer of source pad, the gate pad includes a first layer of gate pad and a second layer of gate pad, the first layer of gate pad covers part of the top surface of the substrate, the second layer of gate pad covers part of the top surface of the first layer of gate pad and the first layer of source pad, wherein the source pad and the gate pad are insulated. The first layer of gate pad provides an electrical connection point for the electrical lead-out of the gate, and the second layer of gate pad connects the first layer of gate pad to the circuit to realize the electrical connection of the gate in the circuit. The coverage area of ​​the first layer gate pad is smaller than that of the second layer gate pad, which can save space, thereby increasing the area of ​​the active area, reducing the specific on-resistance of the device, and improving the reliability and electrical properties of the semiconductor device. The coverage area of ​​the first layer source pad is larger than that of the second layer source pad, which can provide an electrical connection point of the source for the increased active area through the first layer source pad without changing the coverage area of ​​the gate pad and the source pad, and connect to the circuit through the second layer source pad, thereby realizing the electrical connection of the source.

[0086] In some embodiments, see Figure 4 , forming a source pad and a gate pad on the top surface of the substrate includes:

[0087] S151: forming a first metal layer on the top surface of the substrate.

[0088] As an example, see Figure 5 The first metal layer 60 may be formed on the top surface of the substrate by, but not limited to, a molecular beam epitaxy process (MBE), a physical vapor deposition process (PVD), a chemical vapor deposition process (CVD), or an atomic layer deposition process (ALD). Specifically, in this embodiment, the first metal layer 60 is formed by a physical vapor deposition process. The material of the first metal layer may include, but not limited to, metal copper.

[0089] S152: Etching the first metal layer to form a first layer of gate pads and a first layer of source pads.

[0090] As an example, see Figure 1 The first metal layer 60 may be etched using, but not limited to, a photolithography process to form a first-layer gate pad 301 and a first-layer source pad 201 .

[0091] S155: forming a second metal layer on top surfaces of the first-layer gate pad and the first-layer source pad.

[0092] As an example, a second metal layer (not shown) may be formed on the top surface of the first layer gate pad and the first layer source pad by a molecular beam epitaxy process, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process, but not limited thereto. Specifically, in this embodiment, a physical vapor deposition process is used to form the second metal layer. The material of the second metal layer may include, but not limited to, copper.

[0093] S156: Etching the second metal layer to form a second gate pad and a second source pad.

[0094] As an example, see Figure 1 The second metal layer may be etched using, but not limited to, a photolithography process to form a second-layer gate pad 302 and a second-layer source pad 202 .

[0095] The method for preparing a semiconductor device in an embodiment of the present application forms a first metal layer on the top surface of a substrate, and then etches the first metal layer to form a first gate pad and a first source pad. The first source pad can be formed at the same time as the first gate pad is formed, thereby simplifying the process steps and processes. The first metal layer can be etched according to the actual use requirements of the semiconductor device to obtain first gate pads and first source pads of different sizes, thereby enhancing the applicability of the semiconductor device. Further, a second metal layer is formed on the top surface of the first gate pad and the first source pad, and then the second metal layer is etched to form a second gate pad and a second source pad. The second source pad can be formed at the same time as the second gate pad is formed, thereby simplifying the preparation process and preparation technology of the semiconductor device. The second metal layer can be etched according to the actual use requirements of the semiconductor device to obtain second gate pads and second source pads of different sizes, thereby further enhancing the applicability of the semiconductor device.

[0096] In some embodiments, see Figure 6 After etching the first metal layer and before forming the second metal layer on the top surfaces of the first gate pad and the second gate pad, the method for preparing the semiconductor device further includes:

[0097] S153: forming a first dielectric material layer on top surfaces of the first layer of gate pads and the first layer of source pads.

[0098] As an example, a molecular beam epitaxy process, a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process may be used but is not limited to form a first dielectric material layer (not shown) on the top surface of the first gate pad 301 and the first source pad 201. The material of the first dielectric material layer may include but is not limited to silicon oxide, silicon nitride, aluminum oxide, a low dielectric constant material, a high dielectric constant material, etc.

[0099] S154: etching the first dielectric material layer to form a first dielectric layer, wherein the first dielectric layer includes a first notch and a second notch, wherein the first layer gate pad is connected to the second layer gate pad via the first notch, and the first layer source pad is connected to the second layer source pad via the second notch.

[0100] As an example, see Figure 7 The first dielectric material layer may be etched using, but is not limited to, a photolithography process.

[0101] As an example, the sizes of the first notch and the second notch in the first direction can be set according to the actual use requirements of the semiconductor device to ensure electrical connection between the first layer gate pad 301 and the second layer gate pad 302, and between the first layer source pad 201 and the second layer source pad 202.

[0102] The method for preparing a semiconductor device provided in the embodiment of the present application forms a first dielectric material layer on the top surface of the first-layer gate pad and the first-layer source pad, and then etches the first dielectric material layer to form a first dielectric layer, so that the first-layer gate pad and the first-layer source pad can be electrically isolated. And by etching to obtain a first notch and a second notch, electrical connections can be achieved between the first-layer gate pad and the second-layer gate pad, and between the first-layer source pad and the second-layer source pad.

[0103] In some embodiments, see Figure 1 The size of the first layer gate pad 301 in the first direction is smaller than the size of the first layer source pad 201 in the first direction. The size of the first layer source pad 201 in the first direction is smaller than the size of the second layer source pad 202 in the first direction.

[0104] In the method for preparing a semiconductor device provided in an embodiment of the present application, by setting the size of the first layer gate pad in the first direction to be smaller than the size of the first layer source pad in the first direction, the first layer gate pad can save space to increase the coverage area of ​​the first layer source pad, and then more cells can be set under the first layer source pad, thereby increasing the area of ​​the active area, reducing the device's specific on-resistance value, and improving the electrical properties of the semiconductor device. By setting the size of the first layer source pad in the first direction to be smaller than the size of the second layer source pad in the first direction, the first layer source pad can be electrically led out by using the second layer source pad when the first layer source pad completely covers the active area, and then the source can be connected to the circuit to achieve electrical connection of the source.

[0105] In some embodiments, after providing the substrate and before forming a source pad and a gate pad on the top surface of the substrate, the method further includes:

[0106] S12: forming a second dielectric layer, wherein the second dielectric layer covers the gate structure.

[0107] As an example, see Figure 1 The second dielectric layer 50 may be formed by, but not limited to, a molecular beam epitaxy process, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process. The material of the second dielectric layer 50 may include, but not limited to, silicon oxide, silicon nitride, aluminum oxide, a low dielectric constant material, a high dielectric constant material, etc. The thickness of the second dielectric layer 50 may be 800nm ​​to 1100nm, for example, the thickness of the second dielectric layer 50 may be 800nm, 900nm, 1000nm, or 1100nm, etc.

[0108] The method for preparing a semiconductor device provided in an embodiment of the present application can achieve electrical isolation between the gate structure and other structures by forming a second dielectric layer, and the second dielectric layer covers the gate structure, thereby improving the electrical properties of the semiconductor device.

[0109] It should be noted that, the method for preparing the semiconductor device in the embodiment of the present application may further include, after forming the second dielectric layer:

[0110] S13: Etching the second dielectric layer to expose the active area.

[0111] As an example, see Figure 1 The second dielectric layer 50 may be etched using, but not limited to, a photolithography process.

[0112] S14: forming a metal silicide layer, wherein the metal silicide layer covers the exposed surface of the active region.

[0113] As an example, but not limited to, a metal silicide layer (not shown) is formed by a molecular beam epitaxy process, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process. The metal silicide layer can reduce the contact resistance of the device.

[0114] It should be noted that the method for preparing the semiconductor device in the embodiment of the present application may also include the step of forming a passivation layer, the passivation layer covers the gate pad, the source pad and the first dielectric layer, and the passivation layer can protect the device during the packaging process.

[0115] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0116] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A semiconductor device, characterized in that: include: A substrate, the substrate comprising a plurality of active regions and a plurality of gate structures, the plurality of active regions being spaced apart in the substrate along a first direction, the plurality of gate structures being spaced apart on a top surface of the substrate along the first direction, the gate structures covering a portion of the active regions, and the gate structures and the active regions being staggered; A source pad, comprising a first layer of source pads and a second layer of source pads, wherein the first layer of source pads covers the gate structure and the active area, and the second layer of source pads covers a portion of the top surface of the first layer of source pads; The gate pad comprises a first layer of gate pads and a second layer of gate pads, wherein the first layer of gate pads covers a portion of the top surface of the substrate, and the second layer of gate pads covers a portion of the top surface of the first layer of gate pads and the first layer of source pads, wherein the source pad and the gate pad are insulated.

2. The semiconductor device according to claim 1, wherein: The size of the first layer of gate pads in the first direction is smaller than the size of the first layer of source pads in the first direction; A size of the first-layer source pad in the first direction is smaller than a size of the second-layer source pad in the first direction.

3. The semiconductor device according to claim 2, characterized in that Also includes: A first dielectric layer, the first dielectric layer covers the first layer source pad and the first layer gate pad, and the first dielectric layer is located between the first layer gate pad and the second layer gate pad, and between the first layer source pad and the second layer gate pad; The first dielectric layer includes a first notch and a second notch, the first layer gate pad is connected to the second layer gate pad via the first notch, and the first layer source pad is connected to the second layer source pad via the second notch.

4. The semiconductor device according to claim 1, wherein: Also includes: A second dielectric layer covers the gate structure.

5. An electronic device, characterized in that: include: A semiconductor device as claimed in any one of claims 1 to 4.

6. A method for preparing a semiconductor device, characterized in that: include: Providing a substrate, the substrate comprising a plurality of active regions and a plurality of gate structures, the plurality of active regions being spaced apart in the substrate along a first direction, the plurality of gate structures being spaced apart and distributed on a top surface of the substrate along the first direction, the gate structures covering a portion of the active regions, and the gate structures and the active regions being staggered; A source pad and a gate pad are formed on the top surface of the substrate, wherein the source pad includes a first layer of source pads and a second layer of source pads, the first layer of source pads covers the gate structure and the active area, the second layer of source pads covers a portion of the top surface of the first layer of source pads, and the gate pad includes a first layer of gate pads and a second layer of gate pads, the first layer of gate pads covers a portion of the top surface of the substrate, and the second layer of gate pads covers a portion of the top surface of the first layer of gate pads and the first layer of source pads, wherein the source pad and the gate pad are insulated.

7. The method for preparing a semiconductor device according to claim 6, characterized in that: The forming of a source pad and a gate pad on the top surface of the substrate comprises: forming a first metal layer on the top surface of the substrate; Etching the first metal layer to form the first layer gate pad and the first layer source pad; forming a second metal layer on top surfaces of the first layer of gate pads and the first layer of source pads; The second metal layer is etched to form the second gate pad and the second source pad.

8. The method for preparing a semiconductor device according to claim 7, characterized in that: After etching the first metal layer and before forming the second metal layer on the top surfaces of the first gate pad and the second gate pad, the method further includes: forming a first dielectric material layer on top surfaces of the first layer of gate pads and the first layer of source pads; The first dielectric material layer is etched to form a first dielectric layer, wherein the first dielectric layer includes a first notch and a second notch, the first layer gate pad is connected to the second layer gate pad through the first notch, and the first layer source pad is connected to the second layer source pad through the second notch.

9. The method for preparing a semiconductor device according to claim 6, wherein: The size of the first layer of gate pads in the first direction is smaller than the size of the first layer of source pads in the first direction; A size of the first-layer source pad in the first direction is smaller than a size of the second-layer source pad in the first direction.

10. The method for preparing a semiconductor device according to claim 6, characterized in that: After providing the substrate and before forming a source pad and a gate pad on the top surface of the substrate, the method further includes: A second dielectric layer is formed, wherein the second dielectric layer covers the gate structure.

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