Semiconductor package with inclined lead frame

Abstract

The invention discloses a semiconductor package. The semiconductor package includes a lead frame, a chip, and a molded package. The lead frame includes a top plate, a plurality of drain pads, a plurality of inclined portions, a gate pad, and a plurality of source pads. The top plate of the lead frame includes a thicker region and a thinner region. Each of the plurality of sloped portions connects a respective drain pad of the plurality of drain pads to the top plate. A respective side surface of each of the plurality of drain pads is exposed from a side surface of the molded package. A respective bottom surface of each of the plurality of drain pads is exposed from a bottom surface of the molded package. A top surface of the thicker region is exposed from a top surface of the molded package.

Description

Technical Field

[0001] The present invention generally relates to a semiconductor package having a lead frame with an inclined portion. More particularly, the present invention relates to a semiconductor package having a lead frame with portions exposed from the top, side and bottom surfaces of a molded package. Background Art

[0002] The performance of dual flat no lead (DFN) packages depends on the heat dissipation capability. Optimized lead frame design can reduce the manufacturing cost of semiconductor packages. Summary of the invention

[0003] An object of the present invention is to provide a semiconductor package having an inclined lead frame, which has the advantage of reducing the manufacturing cost of the semiconductor package.

[0004] To achieve the above-mentioned object, the present invention proposes a semiconductor package, comprising: a lead frame, comprising a top plate, comprising: a thicker area; and a thinner area; a plurality of drain pads; a plurality of inclined portions, each of the plurality of inclined portions connecting a corresponding drain pad of the plurality of drain pads to the top plate; a gate pad; and a plurality of source pads; a chip attached to the lead frame, the chip comprising: a source electrode and a gate electrode on the top surface of the chip; and a drain electrode on the bottom surface of the chip; a molded package encapsulating the chip and most of the lead frame, the molded package comprising: a top surface; a first side surface; a second side surface opposite to the first side surface; and a bottom surface; the corresponding side surface of each of the plurality of drain pads is exposed from the first side surface of the molded package; the corresponding bottom surface of each of the plurality of drain pads is exposed from the bottom surface of the molded package; the top surface of the thicker area of ​​the top plate of the lead frame is exposed from the top surface of the molded package; the side surface of the gate pad is exposed from the second side surface of the molded package; the bottom surface of the gate pad is exposed from the bottom surface of the molded package; wherein the corresponding side surface of each of the plurality of source pads is exposed from the second side surface of the molded package; and wherein the corresponding bottom surface of each of the plurality of source pads is exposed from the bottom surface of the molded package.

[0005] Preferably, the drain electrode of the chip is attached to the bottom surface of the top plate of the lead frame.

[0006] Preferably, it also includes a gate connection bonding wire connecting the gate electrode of the chip to the gate connection plate of the lead frame; and a plurality of bonding wires connecting the source electrode of the chip to the source connection plate of the lead frame.

[0007] Preferably, a top surface of the thinner region of the top plate of the lead frame is not exposed from a top surface of the molded package.

[0008] Preferably, the lead frame further comprises: a source connection plate; and a plurality of source connection inclined portions; wherein each of the plurality of source connection inclined portions connects a corresponding source pad of the plurality of source pads to the source connection plate.

[0009] Preferably, a corresponding height between a corresponding bottom surface of each of the plurality of source pads and a bottom surface of the source connection plate is in a range of 0.3 mm to 1.0 mm.

[0010] Preferably, the lead frame further comprises: a gate connection plate; and a gate connection inclined portion; wherein the gate connection inclined portion connects the gate pad to the gate connection plate.

[0011] Preferably, a corresponding height between a corresponding bottom surface of each of the plurality of drain pads and a bottom surface of the top plate of the lead frame is in a range of 0.5 mm to 1.2 mm.

[0012] Preferably, the thickness of the top plate of the lead frame is in the range of 0.2 mm to 0.4 mm.

[0013] Preferably, the thickness of the thinner region of the top plate of the lead frame is 50% of the thickness of the thicker region of the top plate of the lead frame.

[0014] Preferably, the thinner area of ​​the top plate of the lead frame is arranged at a peripheral area of ​​the top plate of the lead frame.

[0015] Preferably, the entirety of the thicker region of the top plate of the lead frame is surrounded by the thinner region of the top plate of the lead frame.

[0016] Preferably, the top surface of the thinner area of ​​the top plate of the lead frame is in a hollow rectangular shape.

[0017] Preferably, the top surface of the thinner region of the top plate of the lead frame directly contacts the molded package.

[0018] Preferably, the entire thicker area of ​​the top plate of the lead frame is surrounded by the thinner area of ​​the bottom plate of the lead frame, except for a plurality of horizontal areas connected to the plurality of inclined portions of the lead frame.

[0019] In summary, compared with the prior art, the semiconductor package with an inclined lead frame provided by the present invention has the following beneficial effects: The advantages of the present disclosure include that the first portion of the lead frame is exposed from the top surface of the molded package, which helps to dissipate heat; the second portion of the lead frame is exposed from the side surface and the bottom surface of the molded package, which helps to increase wettability in the reflow process. The etched area of ​​the lead frame top plate improves the integration between the lead frame top plate and the molded package. Multiple bond wire connections improve the current carrying capacity. The lead frame strips squeeze the tie bars during the manufacturing process to provide sufficient high voltage creepage distance. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1A A top perspective view showing a semiconductor package in an example of the present disclosure, Figure 1B represents a bottom perspective view, and Figure 1C It shows a cross-sectional view taken from AA'.

[0021] Figure 2 A bottom perspective view of a chip and lead frame in an example of the present disclosure is shown.

[0022] Figure 3A A bottom view of a semiconductor package in an example of the present disclosure is shown. Figure 3B A bottom view of another semiconductor package in an example of the present disclosure is shown.

[0023] Figure 4 A bottom view of a lead frame strip in an example of the present disclosure is shown. DETAILED DESCRIPTION

[0024] The following will be combined with the accompanying drawings 1 to 2 in the embodiments of the present invention. Figure 4 , the technical solutions, structural features, objectives achieved and effects in the embodiments of the present invention are described in detail.

[0025] It should be noted that the drawings are in a very simplified form and use non-precise proportions. They are only used to conveniently and clearly assist in explaining the embodiments of the present invention, and are not used to limit the conditions for the implementation of the present invention. Therefore, they have no substantive technical significance. Any structural modification, change in proportional relationship or adjustment of size, without affecting the effects and purposes that can be achieved by the present invention, should still fall within the scope of the technical content disclosed by the present invention.

[0026] It should be noted that, in the present invention, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only the elements explicitly listed, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0027] Figure 1A 1 is a top perspective view showing a semiconductor package 100 in an example of the present disclosure, Figure 1B represents a bottom perspective view, and Figure 1C Indicates from Figure 1A AA' of the cross-sectional view. In one example, the semiconductor package 100 has a rectangular prism shape. In the example of the present disclosure, the width of the semiconductor package is in the range of 4mm to 10mm. The length of the semiconductor package is 4mm to 10mm. The semiconductor package 100 includes a lead frame 120, a chip 160, and a molded package 190. The lead frame 120 includes a top plate 122, a plurality of drain pads 132, a plurality of inclined portions 134, a gate pad 142, and a plurality of source pads 152. The top plate 122 of the lead frame 120 includes a thicker area 123 and a thinner area 125. In one example, the plurality of drain pads 132 include four drain regions, namely, a drain region 132A, a drain region 132B, a drain region 132C, and a drain region 132D. The number of drain pads may vary. In another example, the plurality of source pads 152 includes two source region pads, namely source pad 152A and source pad 152B. The number of source pads may vary.

[0028] Each of the plurality of inclined portions 134 connects a corresponding drain pad of the plurality of drain pads 132 to the top plate 122 .

[0029] The chip 160 is attached to the lead frame 120. In one example, the drain 162 of the chip 160 is attached to the bottom surface of the top plate 122 of the lead frame 120. The chip 160 includes a drain electrode 162 on the top surface of the chip 160. Figure 2 and a drain 162 on the bottom surface of the chip 160.

[0030] The molded package 190 includes the chip 160 and most of the lead frame 120. The term "most" literally means greater than 50%. The molded package 190 includes a top surface 191, a first side surface 193, a second side surface 195 opposite to the first side surface 193; and a bottom surface 197. The bottom surface 197 of the molded package 190 extends from the center of the molded package 190 to all sides.

[0031] A corresponding side surface (e.g., side surface 137) of each of the plurality of drain pads 132 is exposed from and coplanar with a first side 193 of the molded package 190. A corresponding bottom surface (e.g., bottom surface 139) of each of the plurality of drain pads 132 is exposed from and coplanar with a bottom surface 197 of the molded package 190 adjacent to the first side 193. A top surface 129 of a thicker region 123 of a top plate 122 of the lead frame 120 is exposed from a top surface 191 of the molded package 190. A side surface 147 of the gate pad 142 is exposed from and coplanar with a second side 195 of the molded package 190. A bottom surface 149 of the gate pad 142 is exposed from and coplanar with a bottom surface 197 of the molded package 190 adjacent to the second side 195. A corresponding side surface (e.g., side surface 157) of each of the plurality of source pads 152 is exposed from and coplanar with second side surface 195 of molded package 190. A corresponding bottom surface (e.g., bottom surface 159) of each of the plurality of source pads 152 is exposed from and coplanar with bottom surface 197 of molded package 190 adjacent to second side surface 195. Figure 1A and 1B As shown, the side surface of the molded package 190 perpendicular to the first side surface 193 of the molded package 190 is completely covered by the molded package 190 , and no chip bar is exposed.

[0032] In an example of the present disclosure, the top surface 125T of the thinner region 125 of the top plate 122 of the lead frame 120 is recessed from the top surface of the thicker region 123 of the top plate 122 and is not exposed from the top surface 191 of the molded package 190 .

[0033] The corresponding height 103 between the corresponding bottom surface of each source pad (eg, source pad 152B) of the plurality of source pads 152 and the bottom surface of the source connection plate 155 is in the range of 0.3 mm to 1.0 mm. The height 103 is a height that accommodates Figure 3A The plurality of bond wires 329 shown are required.

[0034] A corresponding height 105 between a corresponding bottom surface of each drain pad (e.g., drain pad 132B) in the plurality of drain pads 132 and a bottom surface of the top plate 122 of the lead frame 120 is in a range of 0.5 mm to 1.2 mm. In one example, the height 105 is greater than the height 103 by at least the thickness of the chip 160. In another example, the bottom surface of the top plate 122 is coplanar with the top surface of the source connection plate 155. In another example, the bottom surface of the source connection plate 155 is coplanar with the source and gate electrodes disposed on the top surface of the chip 160.

[0035] The thickness of the top plate 122 of the lead frame 120 is in the range of 0.2mm to 0.4mm. The thickness of the thinner region 125 of the top plate 122 of the lead frame 120 is 50% of the thickness of the thicker region 123 of the bottom plate 122 of the lead frame 120. In one example, the thicker region 123 of the top plate 122 of the lead frame 120 has a "full thickness". The thinner region 125 formed by the etching process of the top plate 122 of the lead frame 120 has a "half thickness". In an example, the half-etched thinner region 125 is formed at the edge of the top plate 122 near the source connection plate 155. In another example, the half-etched thinner region 125 is formed at all edges of the top plate 122.

[0036] Figure 2 2 shows a bottom perspective view of a chip 260 and a lead frame 220 in an example of the present disclosure. The lead frame 220 includes a plurality of source pads 252, a source connection plate 259, and a plurality of source connection inclined portions 254. Each of the plurality of source connection inclined portions 254 connects a corresponding source pad in the plurality of source region pads 252 to the source connection plate 259. In an example of the present disclosure, the plurality of source pads 252 includes two source welding pads, namely, a source pad 252A and a source pad 252B. The number of source pads may vary. In an example of the present disclosure, the plurality of source connection inclined portions 254 includes two source connector inclined portions, namely, a source connector inclined surface portion 254A and a source connector inclined surface portion 254B. The number of source connection inclined portions may vary.

[0037] The lead frame 220 further includes a gate pad 262, a gate connection plate 269, and a gate connection inclined portion 264. The gate connection inclined portion 264 connects the gate pad 262 to the gate connection plate 269.

[0038] Figure 3A 1 shows a bottom view of a semiconductor package 310 in an example of the present disclosure. Figure 3B 3 shows a bottom view of another semiconductor package 360 ​​in an example of the present disclosure. A gate connection bonding wire 349 connects a gate electrode 344 of a chip 341 to a gate connection plate 347 of a lead frame 320 .

[0039] A plurality of bonding wires 329 connects the source electrode 324 of the chip 341 to the source connection pad 327 of the lead frame 320 .

[0040] exist Figure 3A , the shaded area (thinner area 325) of the top plate 322 represents the thinner area 325 of the top plate 322. The thinner area 325 increases Figure 1A The contact area between the top plate 322 and the molded package 190 is shown, thereby improving Figure 1A The top plate 322 of the lead frame 320 is integrated with the molded package 190. The thinner area 325 of the top plate 322 of the lead frame 320 is located at its periphery. The entire thicker area 323 of the top plate 322 of the lead frame 320 is surrounded by the thinner area 325 of the top plate 322 of the lead frame 320. In one example, the top surface of the thinner area 325 of the top plate 322 of the lead frame 320 is a hollow rectangular shape. The top surface of the thinner area 325 of the top plate 322 of the lead frame 320 directly contacts the molded package 190.

[0041] exist Figure 3B , the shaded area (thinner area 375) of the top plate 372 represents the thinner area 375 of the top plate 372. Except for the multiple horizontal areas 399 connected to the multiple inclined portions 395 of the lead frame 370, the entire thicker area 373 of the top plate 372 of the lead frame 370 is surrounded by the thinner area 375 of the bottom plate 372 of the lead frame 370.

[0042] Figure 4 4. A bottom view of a lead frame strip 400 is shown in an example of the present disclosure. The lead frame strip 400 includes a plurality of lead frames 410 and a plurality of side rails 490. The lead frame strip 400 does not include a chip bar. In one example, the plurality of lead frames 410 includes four lead frames, namely, lead frame 422, lead frame 424, lead frame 426, and lead frame 428. The number of lead frames in the lead frame strip may vary. After the singulation process, lead frame 422, lead frame 424, lead frame 426, and lead frame 428 are separated from each other.

[0043] Those skilled in the art will recognize that modifications to the embodiments disclosed herein are possible. For example, the number of multiple bonding wires may vary. Other modifications may be made by those skilled in the art, and all such modifications are considered to fall within the scope of the invention as defined by the claims.

Claims

1. A semiconductor package, characterized in that: include: A lead frame including A top plate comprising: a thicker region; and a thinner region; multiple drain pads; a plurality of inclined portions, each of the plurality of inclined portions connecting a corresponding drain pad of the plurality of drain pads to the top plate; a gate pad; and a plurality of source pads; A chip attached to a lead frame, the chip comprising: a source electrode and a gate electrode on the top surface of the chip; and a drain electrode on the bottom surface of the chip; A molded package that encapsulates the chip and most of the lead frame. The molded package includes: a top surface; a first side surface; a second side surface opposite to the first side surface; and a bottom surface; A corresponding side surface of each of the plurality of drain pads is exposed from a first side of the molded package; A corresponding bottom surface of each of the plurality of drain pads is exposed from a bottom surface of the molded package; The top surface of the thicker area of ​​the top plate of the lead frame is exposed from the top surface of the molded package; A side surface of the gate pad is exposed from a second side surface of the molded package; A bottom surface of the gate pad is exposed from a bottom surface of the molded package; wherein a corresponding side surface of each of the plurality of source pads is exposed from a second side surface of the molded package; and A corresponding bottom surface of each of the plurality of source pads is exposed from a bottom surface of the molded package.

2. The semiconductor package according to claim 1, wherein: The drain electrode of the chip is attached to the bottom surface of the top plate of the lead frame.

3. The semiconductor package according to claim 2, wherein: Also included are a gate connection bonding wire that connects the gate electrode of the chip to the gate connection pad of the lead frame; and a plurality of bonding wires that connect the source electrode of the chip to the source connection pad of the lead frame.

4. The semiconductor package according to claim 1, wherein: The top surface of the thinner region of the top plate of the lead frame is not exposed from the top surface of the molded package.

5. The semiconductor package according to claim 1, wherein: The lead frame also includes: a source connection plate; and A plurality of source electrodes are connected to the inclined portion; Each of the plurality of source connection inclined portions connects a corresponding source pad of the plurality of source pads to the source connection plate.

6. The semiconductor package according to claim 5, wherein: A respective height between a respective bottom surface of each of the plurality of source pads and a bottom surface of the source connection plate is in a range of 0.3 mm to 1.0 mm.

7. The semiconductor package according to claim 6, wherein: The lead frame also includes: a grid connection plate; A gate is connected to the inclined portion; The gate connection inclined portion connects the gate pad to the gate connection plate.

8. The semiconductor package according to claim 1, wherein: A respective height between a respective bottom surface of each of the plurality of drain pads and a bottom surface of the top plate of the lead frame is in a range of 0.5 mm to 1.2 mm.

9. The semiconductor package according to claim 1, wherein: The thickness of the top plate of the lead frame is in the range of 0.2 mm to 0.4 mm.

10. The semiconductor package according to claim 1, wherein: The thickness of the thinner region of the top plate of the lead frame is 50% of the thickness of the thicker region of the top plate of the lead frame.

11. The semiconductor package according to claim 1, wherein: The thinner area of ​​the top plate of the lead frame is disposed at a peripheral area of ​​the top plate of the lead frame.

12. The semiconductor package according to claim 11, wherein: The entirety of the thicker area of ​​the top plate of the lead frame is surrounded by the thinner area of ​​the top plate of the lead frame.

13. The semiconductor package according to claim 12, wherein: The top surface of the thinner region of the top plate of the lead frame is in a hollow rectangular shape.

14. The semiconductor package according to claim 12, wherein: The top surface of the thinner area of ​​the top plate of the lead frame directly contacts the molded package.

15. The semiconductor package according to claim 11, wherein: The entire thicker area of ​​the top plate of the lead frame is surrounded by the thinner area of ​​the bottom plate of the lead frame, except for the plurality of horizontal areas connected to the plurality of inclined portions of the lead frame.

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