Chip packaging structure and packaging process thereof

Abstract

The invention relates to the technical field of chip packaging, solves the technical problem that single-base-island packaging limits the current bearing capacity of a chip and cannot meet the requirement for higher power, and particularly relates to a chip packaging structure and a packaging process thereof. The lead frame is provided with a source electrode base island and at least two chip placing areas located on the source electrode base island, a source electrode connecting part used for connecting source electrodes of at least two chips in series is arranged between every two adjacent chip placing areas, and the lead frame is provided with at least two drain electrode base islands and drain electrode connecting parts located on the drain electrode base islands. The lead frame is also provided with a grid electrode connecting part used for connecting a chip grid electrode. According to the invention, a plurality of chips can be placed by adopting multi-base-island packaging, and the overall current output can be effectively improved, so that the power density and the current bearing capacity of packaging are improved, a higher power level is achieved, and the requirement of a high-power application scene is met.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to a chip packaging structure and a packaging process thereof. Background Art

[0002] At present, LFPAK (Loss Free Package) packaging and TO series packaging generally adopt a single-chip, single-base island packaging structure, which is relatively simple in form and has the problem of insufficient power.

[0003] When applied to high-power control circuits (such as power management and motor control), since a single-island package can only accommodate one chip, this limits the current carrying capacity of the chip, resulting in a low current limit and unable to meet higher power requirements. Summary of the invention

[0004] In view of the shortcomings of the prior art, the present invention provides a chip packaging structure and packaging process thereof, which solves the technical problem that the single-island packaging limits the current carrying capacity of the chip and cannot meet the higher power requirements. The present invention uses two or more chips, and this architecture increases the current capacity exponentially compared to a single chip, thereby meeting the demand for higher power.

[0005] To solve the above technical problems, the present invention provides the following technical solutions: a chip packaging structure, comprising a lead frame as a packaging carrier, the lead frame is provided with a source base island and at least two chip placement areas thereon, and a source connection portion for connecting the sources of at least two chips in series is provided between two adjacent chip placement areas, the lead frame is provided with at least two drain base islands and a drain connection portion thereon, and the lead frame is also provided with a gate connection portion for connecting the chip gates.

[0006] Furthermore, the chips include GaN, IGBT, MOS, and SiC chips.

[0007] Furthermore, a source pin connected to the source connecting portion is disposed at one end of the source base island, a drain pin connected to the drain connecting portion is disposed at one end of the drain base island, and a gate pin is connected to one end of the gate connecting portion.

[0008] Furthermore, the source connection part, the drain connection part and the gate connection part are all provided with a silver-plated layer for wire welding.

[0009] Furthermore, a KS pin connected to the sources of at least two chips is provided at one end of the source base island.

[0010] Furthermore, the lead frame is provided with assembly holes for fixing the chip packaging structure on the heat dissipation plate.

[0011] The technical solution also provides a packaging process for the above chip packaging structure, including the following process:

[0012] Wafer processing before packaging: grinding the finished wafer into a wafer with a thickness of 200μm or 280μm;

[0013] Wafer cutting: completely cut and separate each die on the wafer;

[0014] Bonding: Place the cut die on the lead frame and use thermal conductive glue to adhere and fix it on the chip placement area;

[0015] Wire bonding: connect the S electrodes on die 1 and die 2 in series, and connect the D electrodes on die 1 and die 2 to the drain pins of the lead frame with copper wires;

[0016] Sealing glue: isolate the die from the outside world;

[0017] Glue and weft removal: Remove the excess glue between the pins on the lead frame after sealing, together with the weft rods between the pins, by punching;

[0018] Stamping: Print product information on the upper surface of the chip package structure;

[0019] Electroplating: A layer of tin-lead is plated on the pins connected to the IC body;

[0020] Cutting and forming: Cutting, bending and separating the external pins of the IC body sealed on the lead frame;

[0021] Inspection: Determine whether the die functions normally and meets the specifications after packaging.

[0022] By means of the above technical solution, the present invention provides a chip packaging structure and a packaging process thereof, which have at least the following beneficial effects:

[0023] 1. The packaging structure proposed in the present invention is suitable for the packaging of GaN, IGBT, MOS, SiC and other chips, and can be used in high-power control circuits, such as power management and motor control. At the same time, multiple base island packaging can be used to place multiple chips, and the current and withstand voltage of the chip can be increased exponentially, thereby meeting the needs of high-power application scenarios.

[0024] 2. The present invention can effectively improve the overall current output by integrating multiple chips into one package, thereby improving the power density and current carrying capacity of the package and achieving a higher power level. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0026] Figure 1 It is a schematic structural diagram of the chip packaging structure in the present invention;

[0027] Figure 2 This is a polar connection circuit diagram of the chip in the present invention;

[0028] Figure 3 It is a front view of the chip packaging structure in the present invention;

[0029] Figure 4 It is a rear view of the chip packaging structure in the present invention;

[0030] Figure 5 It is a schematic diagram of a plurality of chip packaging structures loaded on a frame support in the present invention;

[0031] Figure 6 This is a table of measured data after chip packaging in the present invention.

[0032] In the figure: 11, lead frame; 12, source base island; 13, chip placement area; 14, source connection part; 15, drain base island; 16, drain connection part; 17, gate connection part; 18, source pin; 19, drain pin; 110, gate pin; 111, KS pin; 112, assembly hole. DETAILED DESCRIPTION

[0033] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific implementation methods, so that the implementation process of how the present application uses technical means to solve technical problems and achieve technical effects can be fully understood and implemented accordingly.

[0034] Embodiment 1

[0035] LFPAK (Loss Free Package) packaging and TO (TO-247-5L series) series packaging generally adopt single-chip, single-base island packaging structure. Specific models include TO-247, TO-220, TO-252, TO-263, TO3P, TOLL, TOLT, LFPAK33, LFPAK56, LFPAK56E, LFPAK88, etc. Both TO series and LFPAK series face the problem of low upper limit of chip current carrying capacity and cannot meet higher power requirements. Please refer to Figure 1-Figure 6This embodiment proposes a chip packaging structure. The proposed packaging structure is suitable for the packaging of GaN, IGBT, MOS, SiC and other chips, and can be used in high-power control circuits, such as power management and motor control. At the same time, the multi-base island packaging can be used to place multiple chips, thereby meeting the needs of high-power application scenarios. The structure includes a lead frame 11 as a packaging carrier, and a source base island 12 and at least two chip placement areas 13 are arranged on the lead frame 11, and a source connection portion 14 for connecting the sources of at least two chips in series is arranged between two adjacent chip placement areas 13, wherein the source base island 12 is provided for chip patch and wire bonding connection, such as Figure 1 and Figure 2 As shown, the chip placement area 13 provided on the source base island 12 is used for the bonding of GaN, IGBT, MOS, SiC and other chips, and the source electrodes between the chips are connected in series with the source connection portion 14 using copper wires. The lead frame 11 is provided with at least two drain base islands 15 and drain connection portions 16 thereon, and the lead frame 11 is also provided with a gate connection portion 17 for chip gate connection. Figure 1 and Figure 2 As shown, there is a drain base island 15 for wire bonding on both sides of the lead frame 11, and the drains of the two chips are connected to the drain connection part 16 through copper wires.

[0036] One end of the source base island 12 is provided with a source pin 18 connected to the source connection portion 14. The source pin 18 is the source of charge and the starting point of the current. The source pin 18 is connected to the source connection portion 14 for power on. One end of the drain base island 15 is provided with a drain pin 19 connected to the drain connection portion 16. The drain pin 19 is the charge collection point and the end point of the current. One end of the gate connection portion 7 is connected to a gate pin 110. Specifically, the gate pin 110 is used to control the flow of current. By applying a voltage to the gate, the electric field between the gate and the source can be changed, thereby affecting the current path between the drain and the source. Changes in the gate control voltage will directly affect the on and off states of the device, thereby achieving control over the on and off of the current.

[0037] The source connection part 14, the drain connection part 16 and the gate connection part 17 are all provided with a silver-plated layer for wire welding. The silver-plated layer 14 is used for wire welding so that it can fit tightly with the copper frame. A KS pin 111 connected to the source of at least two chips is provided at one end of the source base island 12. The KS pin 111 serves as a protection circuit for overcurrent protection and overvoltage protection. The lead frame 11 is provided with an assembly hole 112 for fixing the chip packaging structure on the heat sink. The assembly hole 112 can be fixed to the heat sink by screws, which plays a role of fixing and heat dissipation.

[0038] like Figure 5 As shown, during packaging, multiple chip packaging structures can be uniformly arranged on a frame bracket to position the chip packaging structure and enable it to be transported within the track of the packaging equipment, wherein a pin plug-in matching the chip packaging structure is also positioned on the frame bracket for subsequent connection with the circuit board in a plug-in manner.

[0039] Embodiment 2

[0040] Based on the chip packaging structure proposed in the first embodiment, this embodiment proposes a packaging process of the chip packaging structure, which is used to package the IC body on the chip packaging structure. The specific process flow includes the following processes:

[0041] Wafer processing before packaging: The thickness of the wafer after production in the wafer factory is about 725μm. Considering the thickness of the packaged product, it must be ground into different thicknesses such as 280μm, 200μm, etc., or not ground.

[0042] Wafer dicing: Each die on the wafer is completely (100%) cut and separated.

[0043] Bonding: Place the die cut in the previous step on the lead frame and use thermally conductive adhesive to adhere and fix it to the lead frame.

[0044] Wire bonding: The S poles on grain 1 and grain 2 are connected in series, and the D poles on grain 1 and grain 2 are connected to the inner pins of the lead frame with copper wires.

[0045] Sealing: Isolate the die from the outside world to prevent moisture from entering, thereby avoiding corrosion and signal damage.

[0046] Glue and weft removal: Use Punch to remove the excess glue between the pins on the lead frame after sealing, together with the DamBar between the pins.

[0047] Stamping: Print IC type, serial number and other advertising information on the upper surface of the plastic package.

[0048] Electroplating: In order to make it easier to put the finished IC components on the board, a layer of tin-lead electroplating must be applied to the IC external pins.

[0049] Cutting and forming: The main purpose is to perform lead length trimming, bending and singulation on the IC body that has been sealed on the lead frame.

[0050] Testing: Determine whether the die after packaging is functioning normally and meets the specifications.

[0051] The present invention can effectively improve the overall current output by integrating multiple chips into one package, thereby improving the power density and current carrying capacity of the package and achieving a higher power level. This embodiment performs a performance test on the packaged chips. Taking two chip packages as an example, various performance parameters such as Figure 6 As shown. According to actual measurements, the chip's overcurrent can be doubled to 70A, and the withstand voltage can reach more than 650V. However, when more than two chips use this packaging structure, the overcurrent and withstand voltage can be doubled. This meets the needs of high-power application scenarios in high-power motor control and power management.

[0052] Each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the above embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0053] The above implementation methods have been described in detail. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A chip packaging structure, comprising a lead frame (11) as a packaging carrier, characterized in that: The lead frame (11) is provided with a source base island (12) and at least two chip placement areas (13) thereon, and a source connection portion (14) for connecting the sources of at least two chips in series is provided between two adjacent chip placement areas (13), the lead frame (11) is provided with at least two drain base islands (15) and a drain connection portion (16) thereon, and the lead frame (11) is also provided with a gate connection portion (17) for connecting the gates of the chips.

2. The chip packaging structure according to claim 1, characterized in that: The chips include GaN, IGBT, MOS and SiC chips.

3. The chip packaging structure according to claim 1, characterized in that: One end of the source base island (12) is provided with a source pin (18) connected to the source connection portion (14), one end of the drain base island (15) is provided with a drain pin (19) connected to the drain connection portion (16), and one end of the gate connection portion (7) is connected to a gate pin (110).

4. The chip packaging structure according to claim 1, characterized in that: The source connection part (14), the drain connection part (16) and the gate connection part (17) are all provided with a silver-plated layer for wire welding.

5. The chip packaging structure according to claim 1, characterized in that: One end of the source base island (12) is provided with a KS pin (111) connected to the sources of at least two chips.

6. The chip packaging structure according to claim 1, characterized in that: The lead frame (11) is provided with an assembly hole (112) for fixing the chip packaging structure on the heat dissipation plate.

7. The chip packaging structure according to claim 1, characterized in that: The chip packaging structure is applied to LFPAK packaging and TO series packaging, including TO-247, TO-220, TO-252, TO-263, TO3P, TOLL, TOLT, LFPAK33, LFPAK56, LFPAK56E, and LFPAK88.

8. A packaging process for the chip packaging structure according to any one of claims 1 to 7, characterized in that: The process includes: Wafer processing before packaging: grinding the finished wafer into a wafer with a thickness of 200μm or 280μm; Wafer cutting: completely cut and separate each die on the wafer; Bonding: Place the cut die on the lead frame and use thermal conductive glue to adhere and fix it on the chip placement area; Wire bonding: connect the S electrodes on die 1 and die 2 in series, and connect the D electrodes on die 1 and die 2 to the drain pins of the lead frame with copper wires; Sealing glue: isolate the die from the outside world; Glue and weft removal: Remove the excess glue between the pins on the lead frame after sealing, together with the weft rods between the pins, by punching; Stamping: Print product information on the upper surface of the chip package structure; Electroplating: A layer of tin-lead is plated on the pins connected to the IC body; Cutting and forming: Cutting, bending and separating the external pins of the IC body sealed on the lead frame; Inspection: Determine whether the die functions normally and meets the specifications after packaging.

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