Methods of forming electronic device structures having vertically directed electronic components and related structures

Abstract

Methods of forming electronic device structures having vertically directed electronic components and related structures. A method of forming an electronic device structure includes providing a first electronic component having a first major surface, an opposing second major surface, a first edge surface, and an opposing second edge surface. A substrate having a substrate first major surface and an opposing substrate second major surface is provided. The second major surface of the first electronic component is positioned proximate to the substrate first major surface and a conductive material is provided proximate to the first edge surface of the first electronic component. The conductive material is exposed to an elevated temperature to reflow the conductive material to raise the first electronic component into an upright position such that a spacing of the second edge surface from the first major surface of the substrate is farther than a spacing of the first edge surface from the first major surface of the substrate. The method is suitable for providing an electronic component, such as an antenna, a sensor or an optical device, in a vertical or upright manner.

Description

[0001] This application is a divisional application of a patent application with an application date of July 19, 2018, a priority date of February 27, 2018, an application number of 201810794981.X, and an invention name of “Method and related structure for forming an electronic device structure with vertically oriented electronic components”. Technical Field

[0002] The present invention relates generally to electronic devices and, more particularly, to electronic structures, their construction, and methods of forming electronic structures. Background Art

[0003] Wireless and portable handheld communication applications are examples of applications that continue to grow and evolve, with an emphasis on integrating more electronic functionality into smaller, lighter, thinner, and lower cost solutions. One of the ongoing challenges facing these applications is the improvement and integration of effective antennas into various product platforms. In the past, component structures for handheld communication applications used flexible cables or flexible circuit structures to orient various antenna devices in different directions relative to an integrated circuit packaged with the antenna device. In the component structure, the flexible cable is bent to orient the antenna device to a desired position to provide 3-axis coverage for a particular communication application. The flexible cable increases the complexity of the component process, increases the volume of the component structure, and may cause reliability issues due to aging of the flexible cable and exposure to harsh environmental conditions.

[0004] Furthermore, as cellular networks continue to evolve toward the next generation, such as 5G, there are many engineering challenges that need to be addressed. For example, beamforming technology, which helps focus the signal into a concentrated beam that points only in the direction of the user, requires antennas to provide 3-axis (i.e., x, y, and z-axis) directional capabilities at multiple locations on an assembly structure for communication applications. For example, it is expected that in 5G applications, multiple antenna devices may be placed in at least two separate locations to provide 3-axis signal coverage. This will be a challenge for manufacturers, especially with the need for smaller, lighter, thinner, and lower-cost solutions.

[0005] Therefore, it is desirable to have a method and structure for providing packaged electronic devices that overcomes the problems associated with flexible cable assemblies and supports next generation cellular network technologies. In addition, it would be beneficial to have a method and structure that utilizes existing manufacturing equipment and a method and structure for supporting a variety of electronic applications, such as antenna, optical and sensing device applications. Summary of the invention

[0006] Among other features, the present description includes methods of forming electronic device structures and related structures having electronic components provided in an on-edge or upright configuration. In some embodiments, an edge of an electronic component is placed adjacent to a conductive pattern on a substrate. A conductive material is placed adjacent to the edge and the conductive pattern. The conductive material is exposed to an elevated temperature to reflow the conductive material. During the reflow process, surface tension effects act to lift or rotate the electronic component upward into an upright or upright orientation. In some embodiments, the conductive material includes solder and a plurality of conductive bumps that may be substantially uniformly distributed along the edge of the electronic component. In some embodiments, the electronic component may be an antenna structure, such as a semiconductor antenna structure. In some embodiments, the electronic component may be a sensing device, such as an image sensing device. In some embodiments, the electronic component may be a bare semiconductor die or chip (i.e., unpackaged). In some embodiments, the electronic component includes a conductor that is electrically connected to one or more of the plurality of conductive bumps placed along the edge. In some embodiments, the conductive pattern may be on both sides of the electronic component. Multiple electronic components can be disposed on a substrate both in an upright configuration and in a conventionally attached configuration to provide an electronic device structure with 3-axis orientation capability. The methods and associated structures described herein provide electronic device structures with improved design flexibility and performance.

[0007] More particularly, in one embodiment, a method of forming an electronic device structure includes providing a first electronic component having a first major surface, an opposing second major surface, a first edge surface, and an opposing second edge surface. The method includes providing a substrate having a substrate first major surface and an opposing substrate second major surface. The method includes placing the second major surface of the first electronic component proximate to the substrate first major surface. The method includes providing a conductive material adjacent to the first edge surface of the first electronic component. The method includes exposing the conductive material to an elevated temperature to reflow the conductive material, causing the first electronic component to be raised to an upright position such that the second edge surface is spaced further from the substrate first major surface than the first edge surface is spaced from the substrate first major surface. The method includes: providing the substrate includes providing a first conductive pattern adjacent to the substrate first major surface; providing the conductive material includes placing the conductive material adjacent to the first conductive pattern; and providing the conductive material includes leaving the second edge surface of the first electronic component free of the conductive material. The method further includes: forming an underfill layer adjacent to the first edge surface; and forming a package body that encapsulates the first electronic component, wherein: providing the first electronic component includes providing one of an antenna device, a sensing device, and an optical device; and providing the conductive material includes providing a solder material and a plurality of conductive bumps. The method includes: providing the first electronic component includes providing a conductive pattern adjacent to one or more of the first major surface and the second major surface of the first electronic component. The method includes: providing the conductive pattern includes providing the conductive pattern adjacent to both the first major surface and the second major surface. The method further includes: using a through substrate via to electrically couple the conductive pattern to the conductive material.

[0008] In another embodiment, a method of forming an electronic device structure includes providing a first electronic component having a first major surface, an opposite second major surface, a first edge surface, and an opposite second edge surface. The method includes providing a substrate having a substrate first major surface, an opposite substrate second major surface, and a first conductive pattern adjacent to the substrate first major surface. The method includes placing the second major surface of the first electronic component proximate to the substrate first major surface. The method includes providing a conductive material adjacent to the first edge surface and the first conductive pattern of the first electronic component. The method includes exposing the conductive material to an elevated temperature to reflow the conductive material, lifting the first electronic component to an upright position so that the second edge surface is spaced further from the substrate first major surface than the first edge surface is spaced from the substrate first major surface. In certain embodiments, the method may include attaching a second electronic component to the substrate first major surface, attaching a third electronic component to the substrate second major surface, and providing a packaging body to encapsulate the first electronic component and the second electronic component. In other embodiments, providing the conductive material may include providing a solder material and a plurality of conductive bumps substantially uniformly distributed along the first edge surface of the first electronic component. In other embodiments, the method may include exposing the conductive material to the elevated temperature to lift the first electronic component such that the first major surface of the first electronic component is generally orthogonal to the first major surface of the substrate. In some embodiments, providing the first electronic component includes a semiconductor die configured as an antenna device, a sensing device (e.g., an image sensing device), or an optical device.

[0009] In another embodiment, an electronic device structure includes a substrate having a first major surface of the substrate, an opposite second major surface of the substrate, and a first conductive pattern adjacent to the first major surface of the substrate; and a first electronic component having a first major surface, an opposite second major surface, a first edge surface, an opposite second edge surface, and a first conductive pattern disposed at least adjacent to the first major surface. The first edge surface is attached to the first conductive pattern by a conductive material. The first major surface is generally disposed orthogonally to the first major surface of the substrate so that the second edge surface is away from the first major surface of the substrate. In some embodiments, the conductive material is electrically coupled to the first conductive pattern. In other embodiments, the electronic device structure further includes: a second electronic component attached to the first major surface of the substrate; a third electronic component attached to the second major surface of the substrate; a packaging body encapsulating the first electronic component and the second electronic component, wherein: the second electronic component includes a third major surface, an opposite fourth major surface, a third edge surface, and an opposite fourth edge surface; the conductive material includes a solder material and a plurality of conductive bumps; the first major surface of the first electronic component faces the first edge of the substrate; the third edge surface is attached to another portion of the first conductive pattern by additional solder material and additional plurality of conductive bumps; the third major surface is generally arranged to be orthogonal to the first major surface of the substrate so that the fourth edge surface is away from the first major surface of the substrate; the third major surface of the second electronic component faces the second edge of the substrate; and the structure further includes a bottom filling layer, which is arranged to be adjacent to one or more of the first edge surface of the first electronic component and the third edge surface of the second electronic component.

[0010] Other embodiments are also included in the disclosure scope of the present invention specification, and these embodiments can be found in the drawings, claims and / or the description of the present invention specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 For a packaged electronic device according to an embodiment of the present invention, Figure 2 A cross-sectional view obtained along reference line 1-1;

[0012] Figure 2 is a top plan view of a packaged electronic device according to an embodiment of the present invention;

[0013] Figure 3 is a partial cross-sectional view of an electronic device in a manufacturing step according to an embodiment of the present invention;

[0014] Figure 4is a top plan view of an electronic component according to an embodiment of the present invention;

[0015] Figure 5 For Figure 3 A partial cross-sectional view of an electronic device of FIG. 1 during an additional manufacturing step in a manufacturing apparatus;

[0016] Figure 6 is a manufacturing flow chart of a packaged electronic device according to an embodiment of the present invention;

[0017] Figure 7 is a partial cross-sectional view of an electronic device according to an embodiment of the present invention;

[0018] Figure 8 is a partial cross-sectional view of an electronic device according to an embodiment of the present invention;

[0019] Fig. 9 is a partial cross-sectional view of an electronic device according to an embodiment of the present invention;

[0020] Fig.10 is a partial cross-sectional view of an electronic device according to an embodiment of the present invention;

[0021] Fig.11 is a partial cross-sectional view of an electronic device according to an embodiment of the present invention;

[0022] Fig.12 is a partial cross-sectional view of an electronic device according to an embodiment of the present invention; and

[0023] Fig.13 is a partial cross-sectional view of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0024] For the sake of simplicity and clarity of illustration, the components in the drawings are not necessarily drawn to scale, and the same component symbols in different drawings represent the same components. In addition, in order to simplify the description, the description and details of the well-known steps and components are omitted. As used herein, the term "and / or" includes any and all combinations of one or more related listed items. In addition, the terms used in this article are only used for the purpose of describing specific embodiments, and are not intended to limit the content disclosed by the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. It will be further understood that when used in this specification, the terms "include", "include", "contain" and / or "have" specify the features, numbers, steps, operations, components and / or components currently described, but do not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components and / or their combinations. It will be understood that although the terms "first", "second" ... etc. are used to describe various components, components, regions, layers and / or sections in this article, these components, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish components, assemblies, regions, layers and / or sections from other components, assemblies, regions, layers and / or sections. Thus, for example, the first component, first component, first region, first layer and / or first section discussed below may be referred to as the second component, second component, second region, second layer and / or second section without departing from the teachings of the present disclosure. Reference to "one embodiment" or "embodiment" represents that the specific features, structures or characteristics described in conjunction with the embodiment are included in at least one embodiment of the present invention. Therefore, the words "in one embodiment" or "in an embodiment" appearing throughout the specification do not necessarily refer to the same embodiment, but may refer to a unified embodiment in some cases. Furthermore, in one or more embodiments, as is apparent to those with ordinary knowledge in the art, specific features, structures or characteristics may be combined in any suitable manner. In addition, the term "when..." means that an action occurs at least within a certain portion of the duration of the initiation of the action. The use of the words "about", "approximately" or "substantially" represents that the numerical value of the desired component is close to the state value or position. However, as is well known in the art, there are always slight differences that prevent accurate descriptions of values ​​or positions. Unless otherwise specified, as used herein, the terms "above" or "on" include directions, positions, or relationships in which designated components may be in direct or indirect physical contact. It should be further understood that the embodiments illustrated and described hereinafter may suitably have embodiments and / or may be implemented in the absence of any components not specifically described herein.

[0025] Figure 1is a cross-sectional view of a packaged electronic device according to a first embodiment having electronic components 12 , 14 , 16 , and 17 connected to a substrate 11 . Figure 1 It is along Figure 2 The reference line 1-1 intercepts the Figure 2 A top plan view of the packaged electronic device 10 is shown. Figure 2 As shown in FIG. 1 , the packaged electronic device 10 further includes electronic components 18 and 19 . Figure 1 and Figure 2 An example of an electronic device structure having 3-axis orientation capability is shown.

[0026] According to the present embodiment, the electronic components 12 and 18 are provided as upright components 12 and 18 or electronic components that are oriented non-parallel to the major surface 110 of the substrate 11. In some embodiments, the electronic components 12 and the electronic components 18 can be provided in a generally orthogonal orientation relative to the major surface 110 of the substrate 11. In some embodiments, the electronic components 12, 14, 16, 17, 18 and 19 can be constructed as antenna devices disposed on the substrate 11 to provide 3-axis coverage. In some embodiments, one or more of the electronic components 12, 14, 16, 17, 18 and 19 include packaged semiconductor dies or unpackaged semiconductor dies (bare semiconductor dies). In other examples, one or more of the electronic components 12, 14, 16, 17, 18 and 19 include passive components. As an example, the electronic components 12 and 17 are oriented along Figure 1 and Figure 2 The x-axis sends and receives signals 120; the electronic components 14 and 16 are directed along Figure 1 The z-axis sends and receives signals 121; and the electronic components 18 and 19 are directed to be along Figure 2 The y-axis sends and receives signal 122.

[0027] It will be understood that other electronic components may be placed on substrate 11, but are not shown here to avoid crowding out the figures. Other components may include integrated circuit devices, such as digital signal processing (DSP) devices, microprocessors, memory devices, microcontroller devices, power devices, passive devices, or other devices known to those of ordinary skill in the art. It will be further understood that one or more of electronic components 12, 14, 16, 17, 18, and 19 may be other types of electronic devices, such as sensor devices (e.g., CMOS or CCD image sensors), optical devices, or other devices known to those of ordinary skill in the art. It will be understood by those of ordinary skill in the art that the electronic components are shown in simplified form and may also include multiple diffusion regions, multiple conductive layers, and multiple dielectric layers.

[0028] The substrate 11 may be any type of electronic component substrate, such as a printed circuit board (PCB), a component substrate, a laminate substrate, a lead frame substrate, a ceramic substrate, a molded substrate, a molded lead frame, or other substrates known to those skilled in the art. In one embodiment, the substrate 11 is provided with a conductive pattern 21 adjacent to the major surface 110 and a conductive pattern 22 adjacent to a major surface 111 opposite to the major surface 110. The conductive patterns 21 and 22 may include conductive pads, conductive traces, or a combination thereof. In most embodiments, the conductive patterns 21 and 22 include one or more materials, such as copper, copper alloys, plated materials, gold, nickel, or other materials known to those skilled in the art.

[0029] The substrate 11 may further include buried traces and conductive interconnect vias (not shown) that electrically connect specific portions of the conductive pattern 21 to other portions of the conductive pattern 21, to the conductive pattern 22, or to conductive bumps 23 adjacent to the major surface 111 of the substrate 11. As examples, the conductive bumps 23 include temperature reflowable solder bumps, thermosonic or thermal compression bonding bumps (e.g., gold bumps), adhesive bonding bumps, or other bump materials known to those of ordinary skill in the art. The conductive bumps 23 are constructed for attaching or electrically connecting the packaged electronic device 10 to the next level of assembly.

[0030] In some embodiments, the electronic component 14 is attached to the conductive pattern 21 by means of conductive bumps 31 and the electronic component 16 is similarly attached to the conductive pattern 22 by means of conductive bumps 31. The conductive bumps 31 may include temperature reflowable solder bumps, thermosonic or thermocompression bonding bumps (e.g., gold bumps), adhesive bonding bumps, or other bump materials known to those of ordinary skill in the art.

[0031] According to the present embodiment, the edge 126 of the electronic component 12 is attached to the conductive pattern 21 using one or more conductive bumps 32 and solder 33. In some embodiments, the edge 126 only partially overlaps the conductive pattern 21, while the conductive bumps 32 and solder 33 overlap the conductive pattern 21. The opposite edge 127 is disposed away from the main surface 110 of the substrate 11. The edge 176 of the electronic component 17 is attached to the conductive pattern 21 using one or more conductive bumps 32 and solder 33. The opposite edge 177 is disposed away from the main surface 110 of the substrate 11. As an example, the conductive bumps 32 include a plurality of lead-free solder balls or bumps (e.g., tin (Sn), silver (Ag)). According to the present embodiment, reference will be made to Figure 3 and Figure 5Explaining in more detail, during the reflow process of attaching or bonding the electronic components 12, 14, 16, 17, 18, and 19 to the substrate 11, the tension effect from the melted or softened solder and the conductive bumps is used to lift or push the electronic components 12, 17, 18, and 19 to an upright or non-parallel orientation relative to the major surface 110 of the substrate 11. In other words, after the reflow process, the electronic components 12, 17, 18, and 19 are disposed on the substrate 11 in an upright configuration such that the major surfaces of these components are disposed in a configuration relationship other than parallel to the major surface 110 of the substrate 11. In one embodiment, the underfill layer 34 may be disposed adjacent to the edges of the electronic components 12, 17, 18, and 19 and close to the major surface 110 of the substrate 11 to provide additional support or protection for the electronic components 12, 17, 18, and 19 after the electronic components 12, 17, 18, and 19 are placed in the desired upright orientation. Although not shown in this example, multiple underfill layers may be used under the electronic components 14 and 16. The solder 33 may be a lead-free solder, such as tin (Sn), silver (Ag) solder, and may be provided as a solder paste. According to this embodiment, the electronic components 12, 17, 18, and 19 are attached to only one edge of the substrate 11. In some embodiments, one or more of the solder 33 and the conductive bumps may be referred to as a conductive material. Figure 1 As shown in FIG. 1 , electronic component 12 has a major surface 125 that faces edge 112 of substrate 11, and electronic component 17 has a major surface 175 that faces edge 113 of substrate. It will be understood that electronic components 18 and 19 also have major surfaces that face other edges 118 and 116 of substrate 11, such as Figure 2 as shown in .

[0032] In some embodiments, the package body 36 encapsulates or covers the electronic components 12, 14, 17, 18 and 19. In some embodiments, the package body 36 can be a polymer-based composite material, such as an epoxy resin with filler, an epoxy acrylate with filler, or a polymer with appropriate filler. The package body 36 includes a non-conductive and environmentally protective material that protects the electronic components 12, 14, 17, 18 and 19 from external components and contaminants. The formation of the package body 36 can utilize steel plate printing (paste printing), compression molding, transfer molding, over-molding, liquid encapsulation molding, vacuum lamination, other suitable applicators or other processes known to those with ordinary knowledge in the art. In some embodiments, the package body 36 is an epoxy mold compound (EMC) and can be formed using transfer or injection molding technology. In some embodiments, an additional package body (not shown) can be used to encapsulate the electronic component 16 disposed adjacent to the main surface 111 of the substrate 11. In other embodiments, the package body 36 may include a cap, a cover, or other covering structures known to those skilled in the art. In other embodiments, the package body 36 is not used.

[0033] Reference Figure 2 , examples of attachment methods will be described. In one embodiment, only one side or edge 126 of electronic component 12 is attached to individual conductive pads 21A to 21F using multiple conductive bumps 32A to 32F and solder layer 33 or multiple solder layers 33. In one embodiment, only one side or edge 176 of electronic component 17 is attached to individual conductive pads 21G to 21L using multiple conductive bumps 32G to 32L and solder layer 33 or multiple solder layers 33 (examples of multiple solder layers 33 are shown in FIG. Figure 1 In some embodiments, it is preferred that the conductive pads 21A to 21F are substantially uniformly distributed along the edge 126 of the electronic component 12 and the conductive pads 21G to 21L are substantially uniformly distributed along the edge 176 of the electronic component 17. Figure 2 As shown in FIG. 1 , the conductive pads 21A to 21F and the conductive bumps 32A to 32F are disposed at the outer edges 115 of the substrate 11 and the electronic component 12. That is, the active surface of the electronic component 12 is adjacent to or close to the conductive bumps 32A to 32F. Figure 2 As shown, the conductive pads 21G to 21L and the conductive bumps 32G to 32L are disposed at the outer edges 117 of the substrate 11 and the electronic component 17. That is, the active surface of the electronic component 17 is adjacent to or close to the conductive bumps 32G to 32L.

[0034] In one embodiment, only one side or edge 186 of the electronic component 18 is attached to the respective conductive pads 21M to 21P using a plurality of conductive bumps 32M to 32W and a solder layer 33 or a plurality of solder layers 33. In this embodiment, at least some of the conductive pads 21M to 21P accommodate more than one conductive bump 32M to 32W. In some embodiments, it is preferred that the conductive pads 21M to 21P are substantially evenly distributed along the lower edge 186 of the electronic component 18. Figure 2 As shown in FIG. 1 , the electronic component 18 is disposed at the outer edge 116 of the substrate 11 and between the conductive pads 21M to 21P and the conductive bumps 32M to 32W. That is, the active surface of the electronic component 18 is opposite to the conductive bumps 32M to 32W.

[0035] In one embodiment, only one side or edge 196 of the electronic component 19 is attached to the respective conductive pads 21Q to 21T using a plurality of conductive bumps 32X to 32AF and a solder layer 33 or a plurality of solder layers 33. In this embodiment, at least some of the conductive pads 21Q to 21T accommodate more than one conductive bump 32X to 32AF. In some embodiments, it is preferred that the conductive pads 21Q to 21T are substantially evenly distributed along the lower edge 196 of the electronic component 19. Figure 2 As shown in FIG. 1 , the electronic component 19 is disposed between the outer edge 118 of the substrate 11 and the conductive pads 21Q to 21T and the conductive bumps 32X to 32AF. That is, the active surface of the electronic component 19 is opposite to the conductive bumps 32X to 32AF.

[0036] It is understood that the number of conductive pads and solder bumps is determined by the electrical I / O requirements of the electronic component and the cumulative volume of material required to raise the electronic assembly to the desired upright position. It is further understood that some of the conductive pads and solder bumps may not provide electrical connections, but may be used to provide the surface tension effect of the present invention to attach the electronic component to the substrate.

[0037] Figure 31 is a partial cross-sectional view of an exemplary electronic device 30 in an early step of a manufacturing process according to an embodiment of the present invention. In the present embodiment, the electronic component 12 includes a conductive pattern 128 placed on a major surface 129 facing upward and is arranged in a manner that the edge 126 is adjacent to the conductive pattern 21 on the substrate 11. In the present embodiment, the major surface 131 of the electronic component 12 faces the major surface 110 of the substrate 11, but is separated from the major surface 110 to provide a gap 113. The conductive bump 32 is arranged adjacent to the major surface 129 of the electronic component 12, and the solder layer 33 is arranged on the conductive pattern 21 and contacts the edge 126 and the solder bump 32. In the present embodiment, the major surface 129 can be an active surface of the electronic component 12, which is on the same side as the conductive bump 32. According to the present embodiment, the edge 127 of the electronic component 12 relative to the edge 126 is provided to lack any conductive bump 32. In other words, the conductive bump 32 is arranged only along or adjacent to the edge 126 of the electronic component 12.

[0038] Figure 4 1 is a top plan view of an electronic component 12 according to a preferred embodiment of the present invention. More specifically, the electronic component 12 preferably has a ratio of width 1200 to height 1201 or an aspect ratio greater than 1, such as an aspect ratio of about 5 to 1, wherein the standard thickness is about 100 microns to about 200 microns. This aspect ratio is preferably used to facilitate raising the electronic component 12 to an elevated position (e.g., an upright position) in a subsequent process step (e.g., a solder reflow process). Furthermore, according to this embodiment, the aspect ratio of the electronic component 12 can be used to determine the number and size of the conductive bumps and the volume of the solder 33 to be used to raise the electronic component 12 to a desired position in the solder reflow process.

[0039] Figure 5 for Figure 35 is a partial cross-sectional view of an electronic device 30 in a back-end step in a manufacturing apparatus 50 according to an embodiment. As an example, the manufacturing apparatus 50 may be a reflow oven having a chamber 500, a support structure 501, and a heat source 502. According to the present embodiment, during the reflow process, surface tension acts to move the electronic component 12 to an elevated orientation, such as an upright orientation. More particularly, the adhesion between the solder 33, the conductive bump 31, and the electronic component 12 causes a moment 504 in which the surface tension rotates the edge 126 of the electronic component 12, thereby raising the electronic component 12 to an upright position. According to the present embodiment, the moment 504 is caused by the fact that the opposite edge 127 of the electronic component 12 is not attached to the substrate 11 during the reflow process. In an embodiment, the electronic component 12 generally has an orthogonal orientation to the major surface 110 of the substrate 11. As an example, when a lead-free solder material is used, the electronic device 30 may be exposed to a temperature in the range of about 220 degrees C to 250 degrees C for about 30 to 90 seconds.

[0040] Figure 6 6 is a flow chart of manufacturing a packaged electronic device according to an embodiment of the present invention. In step 601, an electronic component is provided, which is configured to be non-parallel oriented relative to a substrate. As an example, the electronic component can be an antenna device, a sensing device, or an optical device. In some embodiments, the electronic component can be Figure 1-3 The electronic component 12 or the electronic component 18 in the embodiment, or the electronic component 12 or the electronic component 18 in the embodiment Figure 7-13 In some preferred embodiments, the electronic component has an aspect ratio of about 5 to 1. In some embodiments, the electronic component is provided with conductive bumps, such as conductive bumps 32, which are disposed on the surface of the electronic component adjacent to the edge of the electronic component along the width dimension of the electronic component.

[0041] In step 602, a substrate for supporting the electronic components is provided. As an example, the substrate can be a PCB substrate, a component substrate, a laminated substrate, a lead frame substrate, a ceramic substrate, a molded substrate, a molded lead frame, or other substrates known to those of ordinary skill in the art. In some embodiments, the substrate can be a substrate 11, which is provided with conductive patterns 21 and 22 for receiving one or more electronic components.

[0042] In step 603, the electronic component is attached to the substrate using a solder material. As an example, a pick-and-place device may be used to place the electronic component at a desired location on the substrate. In some embodiments, solder material 33 is used to initially attach the electronic component 18 only along the edge with the conductive bump 32. That is, the edge opposite to the edge with the conductive bump 32 is not attached to the substrate. As an example, the solder material may be first dispensed in a desired amount to a desired location on the conductive pattern before the electronic component is placed on the substrate. A dispensing or screen printing process may be used to provide the solder material to the desired location on the substrate. In some embodiments, the solder material at least partially covers individual portions of the conductive pattern 21 in which the electronic component is attached to the substrate. As an example, the solder material may include SnAg or other lead-free solder, may include flux material, and may be provided as solder paste. In step 603, other electronic components may be attached to the substrate in a known configuration. For example, the other components may include integrated circuit devices, such as digital signal processing (DSP) devices, microprocessors, memory devices, microcontroller devices, power devices, passive devices, or other devices known to those skilled in the art.

[0043] In step 604, the substrate and electronic components are exposed to elevated temperatures to reflow the conductive bumps and solder material to permanently attach the electronic components to the substrate. According to this embodiment, at least one electronic component is raised to an elevated position during step 604 so that the at least one electronic component is ultimately attached to the substrate in an orientation that is not parallel to the substrate. As an example, it may be Figure 1 and Figure 5 The electronic component 12 shown in Fig.10 The electronic component 1012 shown in Fig.13 In other words, after step 604, as shown in FIG. Figure 5 As shown, the main surface 129 of the electronic component 12 is oriented non-parallel to the main surface 110 of the substrate 11 .

[0044] In optional step 605, a package body may be provided to cover or encapsulate at least a portion of the substrate and the electronic components. In some embodiments, a package body 36 may be used and may be a polymer-based composite material, such as an epoxy resin with a filler, an epoxy acrylate with a filler, or a polymer with a suitable filler. The package body may be formed by stencil printing, compression molding, transfer molding, over-molding, liquid encapsulation molding, vacuum lamination, other suitable applicators, or other processes known to those of ordinary skill in the art. In some embodiments, before the package body is provided, a bottom fill material (e.g. Figure 1 An underfill material 34 ) shown in FIG. 5 is placed between the electronic component and the substrate.

[0045] about Figure 7-13 , other embodiments will be described. Figure 7-9 , 11 and 12, the electronic component is shown before the reflow process. In other words, the electronic component has not yet been raised to an upright position. It should be understood that after the reflow process, Figure 7-9 The electronic components in , 11 and 12 are in an elevated configuration. Fig.10 and 13 , the electronic components are illustrated in a raised configuration.

[0046] Figure 77 is a partial cross-sectional view of an electronic device 70 according to a first embodiment, which has an electronic component 712 attached to a conductive pattern 21 on a substrate 11 at an edge 726. The electronic device 70 is similar to the electronic device 30, and the main differences will be described below. In this embodiment, the substrate 11 is further provided with a structure 72 (such as a stand-off 72, a pad 72, or a bump 72) that is constructed to provide temporary support for the electronic component 712 adjacent to the major surface 731 before the electronic component 712 is raised to an elevated position above the major surface 110 of the substrate 11. The structure 72 may include a material that does not adhere to the electronic component 712 during the reflow process. In some embodiments, the structure 72 includes a polymer material, a ceramic material, or other materials known to those of ordinary skill in the art. In addition, the electronic component 712 has a conductive layer 728 on the major surface 729, which is laterally separated from the conductive bump 32. More specifically, the electronic component 712 is not in electrical communication with at least one conductive bump 32. Similar to the electronic device 30, the edge 726 of the electronic component 712 overlaps only a portion of the conductive pattern 21. According to the present embodiment, an edge 727 of the electronic component 712 opposite to the edge 726 is provided to lack the conductive bump 32. In other words, the conductive bump 32 is provided only along or adjacent to the edge 726 of the electronic component 712.

[0047] Figure 8 8 is a partial cross-sectional view of an electronic device 80 according to another embodiment, which has an electronic component 812 attached to a conductive pattern 21 on a substrate 11 at an edge 826. The electronic device 80 is similar to the electronic devices 30 and 70, and only the main different parts are described below. In this embodiment, the electronic component 812 has a conductive layer 828 on a major surface 829 and a conductive layer 838 on a major surface 831. In other words, the electronic component 812 has an active device on two opposing major surfaces. In addition, conductive bumps 321 and 322 are provided on the opposing major surfaces 829 and 831 of the electronic component 812, respectively. More particularly, in this embodiment, the conductive bump 322 physically contacts the conductive pattern 21 at an edge 826 close to the electronic component 812. According to this embodiment, an edge 827 of the electronic component 812 relative to the edge 826 is provided to lack any conductive bumps 321 or 322. In other words, the conductive bumps 321 and 322 are disposed only along or adjacent to the edge 826 of the electronic component 812 .

[0048] Fig. 99 is a partial cross-sectional view of an electronic device 90 according to another embodiment, which has an electronic component 912 attached to a conductive pattern 21 on a substrate 11 at an edge 926. The electronic device 90 is similar to the electronic devices 30, 70 and 80, and only the main different parts are described below. In this embodiment, the electronic component 912 has a conductive layer 928 on a major surface 929, and the conductive layer 928 extends to cover the edge 926 and extends to be adjacent to at least a portion of the major surface 931. Conductive bumps 321 and 322 are provided on the opposite major surfaces 929 and 931 of the electronic component 912, respectively. More specifically, in this embodiment, the conductive bump 322 physically contacts the conductive pattern 21 near the edge 926 of the electronic component 912. According to this embodiment, an edge 927 of the electronic component 912 opposite to the edge 926 is provided to lack any conductive bumps 321 or 322. In other words, the conductive bumps 321 and 322 are disposed only along or adjacent to the edge 926 of the electronic component 912 .

[0049] Fig.10 1 is a partial cross-sectional view of an electronic device 100 according to another embodiment, which has an electronic component 1012 attached to a conductive pattern 21 on a substrate 11 at an edge 1026. The electronic device 100 is similar to the electronic devices 30, 70, 80 and 90, and only the main different parts are described below. In this embodiment, the electronic component 1012 is illustrated as being in an elevated or upright configuration. In this embodiment, the electronic component 1012 has a conductive through-substrate via (TSV) 1127 extending from a major surface 1029 of the electronic component 1012 to an opposite major surface 1031, and the conductive through-substrate via 1127 electrically connects a conductive bump 32 adjacent to the major surface 1029 to a conductive layer 1033 disposed adjacent to the major surface 1031. In the electronic component 1012, the main surface 1031 is an active surface that electrically communicates with the conductive pattern 21 through the TSV 1127, the conductive bumps 32, and the solder 33. According to the present embodiment, the edge 1027 of the electronic component 1012 opposite to the edge 1026 is provided to lack any conductive bumps 32. In other words, the conductive bumps 32 are provided only along or adjacent to the edge 1026 of the electronic component 1012.

[0050] Fig.1130 is a partial cross-sectional view of an electronic device 301 according to another embodiment of the present invention, which has an electronic component 12 attached to a conductive pattern 21 on a substrate 11 at an edge 126. The electronic device 301 is similar to the electronic device 30, and the main differences between the two devices will be described below. In this embodiment, the electronic component 12 overlaps with most of the conductive pattern 21. That is, in the cross-sectional view, the electronic component 12 overlaps with at least half of the conductive pattern 21. According to this embodiment, an edge 127 of the electronic component 12 opposite to the edge 126 is provided to lack any conductive bumps 32. In other words, the conductive bumps 32 are provided only along or adjacent to the edge 126 of the electronic component 12.

[0051] Fig.12 1 is a partial cross-sectional view of an electronic device 302 according to another embodiment of the present invention, which has an electronic component 12 attached to a conductive pattern 21 on a substrate 11 at an edge 126. The electronic device 302 is similar to the electronic devices 30 and 301, and the main differences between these devices will be described below. In this embodiment, the electronic component 12 does not overlap the conductive pattern 21 before the electronic component is raised to an upright position.

[0052] Fig.13 3 is a partial cross-sectional view of an electronic device 303 according to another embodiment of the present invention, which has an electronic component 12 attached to a conductive pattern 21 on a substrate 11 at an edge 126. In this embodiment, the electronic component is provided in an elevated position so that a major surface 129 of the electronic component 12 is not parallel to the major surface 110 of the substrate 11. In addition, in this embodiment, the active surface 129 of the electronic component 12 is not orthogonal to the major surface 110 of the substrate 11. In other words, the electronic component 12 is in an elevated position, which is greater than 0 degrees and less than 90 degrees relative to the major surface 110 of the substrate 11.

[0053] From all of the foregoing, according to one embodiment, a person of ordinary skill in the art can determine that a method can further include forming an underfill layer near the first edge surface. In another embodiment, providing the conductive material can include providing a plurality of conductive bumps substantially evenly distributed along the first edge surface of the first electronic component. In further embodiments, providing a conductive pattern adjacent to both the first major surface and the second major surface can include coupling the conductive pattern on the first major surface to the conductive pattern on the second major surface by extending the conductive pattern to overlap the first edge surface of the first electronic component. In yet another embodiment, providing a substrate can include providing a pillar adjacent to the first major surface of the substrate, and placing the second major surface of the first electronic component can include placing the second major surface adjacent to the pillar.

[0054] From all of the foregoing, according to another embodiment, one of ordinary skill in the art can determine that the first electronic component may include a semiconductor die having an aspect ratio of about 5 to about 1.

[0055] Based on all of the above, it is apparent that a novel method and related structure have been disclosed that provide an electronic component in an upright or upright configuration. In some embodiments, an edge of the electronic component is placed adjacent to a conductive pattern on a substrate. A conductive material is placed adjacent to the edge and the conductive pattern. The conductive material is exposed to an elevated temperature to reflow the conductive material. During the reflow process, surface tension effects act to lift or rotate the electronic component upward into an upright or upright orientation. In some examples, the conductive material includes solder and a plurality of conductive bumps that can be substantially uniformly distributed along the edge of the electronic component. In some embodiments, the electronic component can be an antenna structure, such as a semiconductor antenna structure. In some embodiments, the electronic component can be a sensing device, such as an image sensing device. In some embodiments, the electronic component can be a bare semiconductor die or chip (i.e., unpackaged). In some embodiments, the electronic component includes a conductor that is electrically connected to one or more of the plurality of conductive bumps placed along the edge. In some embodiments, the conductive pattern can be on both sides of the electronic component. Multiple electronic components can be arranged on a substrate in both an upright configuration and in a conventional attachment configuration to provide an electronic device structure with 3-axis orientation capability. The method and related structures described in the present invention provide an electronic device structure with improved design flexibility and performance. In addition, the method and related structures can support upcoming electronic component requirements, such as 5G applications.

[0056] Although the objects of the present invention are described by specific preferred embodiments and exemplary embodiments, the foregoing drawings and their descriptions depict only typical embodiments of the objects and are therefore not to be considered as limiting the scope thereof. Many alternatives and variations will be apparent to those of ordinary skill in the art. As an example, multiple electronic devices may be attached to a substrate in a side-by-side configuration, a stacked configuration, a combination thereof, or other configurations known to those of ordinary skill in the art.

[0057] As reflected in the claims of the present invention, aspects of the invention may lie in less than all the features of a single aforementioned disclosed embodiment. Therefore, the claims expressed hereinafter are hereby expressly incorporated into the detailed description of the drawings, with each claim itself as a separate embodiment of the present invention. In addition, although some embodiments described herein include some features included in other embodiments but not other features, as will be understood by those of ordinary skill in the art, the combination of features of different embodiments is also considered to be within the scope of the present invention and is intended to form different embodiments.

Claims

1. An electronic device structure, characterized in that: Include: A substrate comprising a first major surface of the substrate, an opposite second major surface of the substrate, and a first conductive pattern adjacent to the first major surface of the substrate; a first electronic component coupled to the substrate and comprising a first component first side and an opposing first device structure adjacent the first component first side; a second electronic component including a second component first side and an opposing second device structure adjacent to the second component first side; as well as a third electronic component coupled to the substrate; in: The first electronic component is orthogonal to the substrate, and the first device structure is oriented in a first direction; the second device structure being oriented in a second direction different from the first direction; The third electronic component includes a third component first side and a third device structure adjacent to the third component first side; the third device structure being oriented in a third direction different from the first direction and the second direction; The third electronic component includes a third component second side opposite the third component first side; and The third member second side is attached to the first conductive pattern through a conductive bump.

2. The electronic device structure as claimed in claim 1, wherein: The first electronic component includes an edge; and The edge of the first electronic component is attached to the first conductive pattern with a first conductive material such that the first electronic component is in an edge orientation.

3. The electronic device structure as claimed in claim 2, characterized in that: The first conductive material includes a conductive bump at the edge of the first electronic component, the conductive bump being proximate to the substrate first major surface.

4. The electronic device structure as claimed in claim 3, characterized in that: The first conductive material further comprises a solder material.

5. The electronic device structure as claimed in claim 1, wherein: The third direction is orthogonal to the first direction.

6. The electronic device structure as claimed in claim 1, characterized in that: Also includes: A through substrate via extends through the first electronic component and couples the first device structure to the first conductive pattern.

7. The electronic device structure as claimed in claim 1, wherein: The second direction is orthogonal to the first direction.

8. The electronic device structure as claimed in claim 1, characterized in that: Also includes: A packaging body is located above the third electronic component.

9. The electronic device structure as claimed in claim 1, characterized in that: Also includes: The packaging body encapsulates the first electronic component and the third electronic component but does not encapsulate the second electronic component.

10. The electronic device structure as claimed in claim 1, wherein: The first device structure and the second device structure include sensors.

11. The electronic device structure as claimed in claim 1, wherein: The first device structure and the second device structure include optical devices.

12. The electronic device structure as claimed in claim 1, wherein: The first device structure and the second device structure include antennas.

13. An electronic device structure, characterized in that: Include: A substrate comprising a first major surface of the substrate, a second major surface of the substrate opposite to the first major surface of the substrate, and a first conductive pattern adjacent to the first major surface of the substrate; a first electronic component oriented perpendicular to the first major surface of the substrate and comprising a first antenna structure oriented in a first direction; a second electronic component adjacent the substrate second major surface and including a second antenna structure oriented in a second direction different from the first direction; as well as a third electronic component disposed on the first major surface of the substrate and coupled to the first conductive pattern; in: The first electronic component includes a first edge surface; The first edge surface of the first electronic component is attached to the first conductive pattern by a first conductive material so that the first electronic component is in an edge direction; and The first conductive material includes a conductive bump located at the first edge surface of the first electronic component, proximate to the substrate first major surface, and laterally disposed along the first edge surface of the first electronic component.

14. The electronic device structure as claimed in claim 13, wherein: The conductive bumps include a first conductive bump and a second conductive bump; The first electronic component includes a first major surface, a second major surface opposite the first major surface, a second edge surface opposite the first edge surface, and a first conductive layer over a portion of the first major surface, over the first edge surface, and over a portion of the second major surface; the second edge surface being spaced apart from the first major surface of the substrate; the first conductive bump being coupled to the first conductive layer proximate the first major surface; the second conductive bump is coupled to the first conductive layer proximate the second major surface; and The first conductive bump is electrically coupled to the second conductive bump.

15. The electronic device structure as claimed in claim 13, wherein: The second direction is perpendicular to the first direction; and The third electronic component is perpendicular to the first electronic component.

16. The electronic device structure as claimed in claim 13, characterized in that: Also includes: A packaging body is located above the third electronic component.

17. The electronic device structure as claimed in claim 13, wherein: The first electronic component includes a first edge, a second edge opposite the first edge, and a third edge extending between the first edge and the second edge; The first edge is adjacent to the substrate; The second edge is away from the substrate; and The first electronic component has an aspect ratio greater than 1, wherein a width is defined by the first edge and a height is defined by the third edge.

18. An electronic device structure, characterized in that: Include: A substrate comprising a substrate first major surface, a substrate second major surface opposite to the substrate first major surface, and a substrate conductive pattern adjacent to the substrate first major surface; a first antenna structure, orthogonal to and coupled to the substrate, and oriented in a first direction; a second antenna structure disposed adjacent a second major surface of the substrate and oriented in a second direction different from the first direction; an electronic component coupled to the substrate at the substrate first major surface and comprising a component first major surface; as well as A packaging body is located on the electronic component and the first main surface of the substrate, in: The electronic component includes a component first side and a device structure adjacent to the component first side; the device structure being oriented in a third direction different from the first direction and the second direction; The electronic component includes a component second side opposite the component first side; and The second side of the member is attached to the substrate conductive pattern through conductive bumps.

19. The electronic device structure as claimed in claim 18, wherein: The first direction is perpendicular to the second direction.

20. The electronic device structure as claimed in claim 18, wherein: The device structure of the electronic component includes a third antenna structure.

21. An electronic device structure, characterized in that: Include: A substrate having a substrate first major surface, a substrate second major surface opposite to the substrate first major surface, and a substrate conductive pattern adjacent to the substrate first major surface; a first semiconductor grain having a first major surface, a second major surface opposite to the first major surface, a first edge, a second edge opposite to the first edge, and a first conductive pattern disposed adjacent to at least the first major surface; a conductive material coupling the first semiconductor die to the substrate conductive pattern so that the first edge is close to the substrate conductive pattern and the second edge is away from the substrate conductive pattern, the conductive material covering a portion of the first major surface of the first semiconductor die close to the substrate conductive pattern and covering a portion of the substrate conductive pattern; as well as an underfill between the first edge and the first major surface of the substrate, the underfill abutting a side surface of the substrate conductive pattern, wherein: The underfill contacts a portion of the second major surface of the first semiconductor die proximate to the first edge; as well as The conductive material is electrically coupled to the first conductive pattern.

22. The electronic device structure as claimed in claim 21, characterized in that: Also includes: A packaging body encapsulates the first semiconductor die, wherein: The conductive material includes conductive bumps; The substrate includes a first edge; The first major surface of the first semiconductor die faces the first edge of the substrate; and The aspect ratio of the first semiconductor grain is 5:

1.

23. The electronic device structure as claimed in claim 21, characterized in that: The conductive material includes conductive bumps; The first semiconductor crystal grain further comprises: a through substrate via extending from the first major surface to the second major surface; and The through substrate via electrically couples at least one conductive bump to the first conductive pattern.

24. An electronic device structure, characterized in that: Include: A substrate comprising a first major surface of the substrate, a second major surface of the substrate opposite to the first major surface of the substrate, and a first conductive pattern adjacent to the first major surface of the substrate; a first electronic component coupled to the substrate and comprising a first component first side and a first active surface adjacent to the first component first side; a second electronic component adjacent the substrate second major surface and including a second component first side and a second active surface adjacent the second component first side; as well as a third electronic component coupled to the substrate; in: The first electronic component is coupled to the substrate in an edge configuration such that the first active surface faces in a first direction; The second active surface is oriented in a second direction different from the first direction; The third electronic component includes a third component first side and a third active surface adjacent to the third component first side; The third active surface faces a third direction different from the first direction and the second direction; The third electronic component includes a third component second side opposite the third component first side; The second side of the third member is attached to the first conductive pattern through a conductive bump; and The first active surface and the second active surface include antennas.

25. The electronic device structure as claimed in claim 24, characterized in that: Also includes: A through substrate via extends through the first electronic component and couples the first active surface to the first conductive pattern.

26. The electronic device structure as claimed in claim 24, characterized in that: Also includes: a first conductive bump; and a second conductive bump; in: The first electronic component includes a first component second side opposite the first component first side, a first edge surface, a first conductive layer over the second edge surface and a portion of the first component first side, and over the first edge surface and a portion of the first component second side; the first electronic component being attached to the substrate first major surface at the first edge surface such that the first electronic component is upright to space the second edge surface from the substrate first major surface; the first conductive bump is coupled to the first conductive layer proximate the first side of the first member; the second conductive bump is coupled to the first conductive layer proximate a second side of the first member; and The first conductive bump is electrically coupled to the second conductive bump.

27. The electronic device structure as claimed in claim 24, characterized in that: The second direction is perpendicular to the first direction; and The third electronic component is perpendicular to the first electronic component.

28. The electronic device structure as claimed in claim 24, characterized in that: Also includes: A packaging body is located above the third electronic component.

29. The electronic device structure as claimed in claim 24, characterized in that: The first electronic component includes a first edge, a second edge opposite the first edge, and a third edge extending between the first edge and the second edge; The first edge is adjacent to the substrate; The second edge is away from the substrate; and The first electronic component has an aspect ratio greater than 1, wherein a width is defined by the first edge and a height is defined by the third edge.

30. An electronic device structure, characterized in that: Include: A substrate comprising a first major surface of the substrate, a second major surface of the substrate opposite to the first major surface of the substrate, and a first conductive pattern adjacent to the first major surface of the substrate; a first electronic component coupled to the substrate and comprising a first component first side and a first active surface adjacent to the first component first side; a second electronic component adjacent the substrate second major surface and including a second component first side and a second active surface adjacent the second component first side; a third electronic component coupled to the substrate; as well as A packaging body, above the third electronic component; in: The first electronic component is coupled to the substrate in an edge configuration such that the first active surface faces in a first direction; The second active surface is oriented in a second direction different from the first direction; The third electronic component includes a third component first side and a third active surface adjacent to the third component first side; The third active surface faces a third direction different from the first direction and the second direction; The third electronic component includes a third component second side opposite the third component first side; and The third member second side is attached to the first conductive pattern through a conductive bump.

31. The electronic device structure as claimed in claim 30, characterized in that: Also includes: A through substrate via extends through the first electronic component and couples the first active surface to the first conductive pattern.

32. The electronic device structure as claimed in claim 30, characterized in that: The second direction is orthogonal to the first direction.

33. The electronic device structure as claimed in claim 30, characterized in that: The packaging body encapsulates the first electronic component but does not encapsulate the second electronic component.

34. The electronic device structure as claimed in claim 30, characterized in that: The first active surface and the second active surface include sensors.

35. The electronic device structure as claimed in claim 30, characterized in that: The first active surface and the second active surface include optical devices.

36. The electronic device structure as claimed in claim 30, characterized in that: The first active surface and the second active surface include antennas.

37. An electronic device structure, characterized in that: include: A substrate comprising a first major surface of the substrate and a first conductive pattern adjacent to the first major surface of the substrate; An electronic component comprises a first major surface, an opposite second major surface, a first edge surface, and an opposite second edge surface; wherein, The first major surface of the electronic component is non-parallel to the first major surface of the substrate; The second major surface portion is provided with a first member conductive pattern; the first edge surface being attached to the first conductive pattern by a first conductive material; The first conductive material includes a solder material and a conductive bump; the solder material is disposed on the first conductive pattern and contacts the first edge surface and the conductive bump, the conductive bump is located on the second major surface and coupled to the first member conductive pattern.

38. The electronic device structure as claimed in claim 37, characterized in that: The electronic component further includes an underfill layer adjacent to and between the first edge surface of the electronic component and the first major surface of the substrate to provide additional support or protection.

39. An electronic device structure, characterized in that: include: A substrate comprising a first major surface of the substrate and a first conductive pattern adjacent to the first major surface of the substrate; A first electronic component, comprising a first major surface, an opposite second major surface, a first edge surface, and an opposite second edge surface; wherein the first major surface of the electronic component is non-parallel to the first major surface of the substrate; The first major surface is partially provided with a first member conductive pattern and partially provided with a conductive bump, the conductive bump being coupled to the first member conductive pattern; The first edge surface, a portion of the first major surface, and a portion of the first major surface are attached to the first conductive pattern by a solder material.

40. The electronic device structure as claimed in claim 39, characterized in that: The electronic device structure further comprises: a second electronic component attached to the first major surface of the substrate; a third electronic component attached to the second major surface of the substrate; The first electronic component, the second electronic component, and the third electronic component provide 3-axis orientation capability.

41. An electronic device structure, characterized in that: A substrate comprising a first major surface of the substrate and a first conductive pattern adjacent to the first major surface of the substrate; An electronic component comprising a first major surface, a second major surface opposite to the first major surface, a first edge surface, and a second edge surface opposite to the first edge surface; wherein the first major surface of the electronic component is non-parallel to the first major surface of the substrate; a conductive material for coupling a first edge surface of an electronic component to the first major surface of the substrate and causing the electronic component to be lifted into an upright position during a reflow process; A plurality of conductive bumps are distributed along the first edge surface of the electronic component, and the electronic component is attached to the first conductive pattern through the plurality of conductive bumps.

42. The electronic device structure as claimed in claim 41, characterized in that: The first major surface of the electronic component is not orthogonal to the first major surface of the substrate.

43. The electronic device structure as claimed in claim 41, characterized in that: The first major surface portion of the electronic component is provided with a first component conductive pattern coupled to the plurality of conductive bumps.

44. A method of forming an electronic device structure, characterized in that: The following steps are involved: providing a first electronic component having a first major surface, an opposing second major surface, a first edge surface, and an opposing second edge surface; Providing a substrate having a first major surface of the substrate, an opposite second major surface of the substrate, and a first conductive pattern adjacent to the first major surface of the substrate; wherein the first major surface of the substrate provides a supporting structure; Providing a conductive material and attaching the first electronic component to the substrate; wherein the second major surface of the first electronic component is placed close to the first major surface of the substrate, and the conductive material is adjacent to the first edge surface of the first electronic component and the first conductive pattern; and the supporting structure supports the second major surface of the first electronic component and is adjacent to the second edge surface; Exposing the conductive material to an elevated temperature to reflow the conductive material lifts the first electronic component to an upright position such that the second edge surface is spaced further from the first major surface of the substrate than the first edge surface is spaced from the first major surface of the substrate.

45. The method of forming an electronic device structure as claimed in claim 44, characterized in that: The supporting structure does not adhere to the first electronic component during the reflow process.

46. ​​The method of forming an electronic device structure as claimed in claim 44, wherein: The supporting structure comprises a polymer material or a ceramic material.

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