Mixed packaging structure of chips with different thicknesses and packaging method thereof

Abstract

The invention relates to the field of circuit board packaging, and discloses a mixed packaging structure of chips with different thicknesses and a packaging method thereof.The mixed packaging structure comprises a first substrate layer, a first chip and a second chip, the thickness of the first chip is larger than that of the second chip, the first substrate layer is provided with a chip semi-embedding groove, and the chip semi-embedding groove is provided with a chip semi-embedding groove; the first chip is arranged in the semi-embedded groove, and the second chip is arranged on the upper surface of the first substrate layer; the thickness of the first substrate layer is 90%-110% of the thickness difference between the first chip and the second chip; through the design of a semi-embedded chip groove matched with the height of a chip interconnection layer, the groove is designed into an inverted trapezoidal groove body; filling of plastic packaging materials and tight arrangement of the plastic packaging materials are considered in the slope angle of the groove body, plastic packaging holes are reduced, the area of a bonding pad and the height of a via hole are reduced, the technical difficulty of mixed packaging of chips with different thicknesses is solved, and unified processing parameters and control standards are simplified.

Description

Technical Field

[0001] The invention relates to the field of circuit board packaging, and in particular to a mixed packaging structure of chips with different thicknesses and a packaging method thereof. Background Art

[0002] After entering the information age, the development trend of electronic products is high-density integration and miniaturization. However, the technical route of semiconductor chips has encountered the failure of physical nodes and economic laws since the 21st century, as well as the difficulties in maintaining performance, power consumption, and area (PPA) indicators. Simply by compressing the process size and increasing the single chip area, it is difficult to improve the system function and performance of the chip to meet the greater needs of future development. In order to continue the post-Moore's Law, the role of advanced packaging and system-level packaging technology has been increasingly valued, and the advanced packaging technology of multi-chip heterogeneous integration has also received attention and application development.

[0003] In the existing technology, chips of different thicknesses are mounted on the same packaging substrate, and the front pads of different chips are at different heights. As a result, the depths of the interconnection via holes of different chips after plastic packaging vary greatly. The drilling process of various hole depths is complicated, and it is difficult to unify the processing parameters and quality control. Via holes with excessive hole depths are difficult to process, and large hole depths correspond to large-diameter via holes, which increases the package size. Therefore, how to unify the via hole depth and reduce the aperture to unify the laser parameters and reduce the processing difficulty has become a technical problem that needs to be solved urgently. Summary of the invention

[0004] The main purpose of the present invention is to provide a mixed packaging structure of chips of different thicknesses and a packaging method thereof, aiming to solve the technical problem that the hole depths of interconnection vias of different chips differ greatly, resulting in a complicated processing flow.

[0005] To achieve the above-mentioned purpose, in a first aspect, the present invention provides a hybrid packaging structure of chips of different thicknesses, comprising a first substrate layer, a first chip and a second chip, the thickness of the first chip being greater than the thickness of the second chip, the first substrate layer being provided with a first chip semi-buried groove, the first chip being arranged in the first chip semi-buried groove, and the second chip being arranged on the upper surface of the first substrate layer; the thickness of the first substrate layer is between 90% and 110% of the thickness difference between the first chip and the second chip.

[0006] Optionally, in one embodiment, it further includes a plastic encapsulation layer, the plastic encapsulation layer is provided with a first conductive hole, a second conductive hole and a third conductive hole, and the first substrate layer is provided with a fourth conductive hole and a fifth conductive hole;

[0007] The first conductive hole is used to connect the upper and lower layers of the plastic packaging layer;

[0008] The second conductive hole connects the upper pad of the second chip and the upper surface circuit of the plastic packaging layer;

[0009] The third conductive hole connects the upper pad of the first chip and the upper surface circuit of the plastic packaging layer;

[0010] The fourth conductive hole connects the lower pad of the second chip with the lower surface circuit of the first substrate layer;

[0011] The fifth conductive hole connects the lower surface circuit and the upper surface circuit of the first substrate layer.

[0012] Optionally, in one embodiment, the first chip semi-buried groove is arranged in an inverted trapezoidal shape, and the size of the upper opening of the first chip semi-buried groove is larger than the size of the groove bottom of the first chip semi-buried groove;

[0013] The size of the upper opening of the first chip semi-buried groove is the sum of the size of the first chip and the equipment accuracy;

[0014] The size of the bottom of the groove in which the first chip is half buried is the size of the first chip.

[0015] Optionally, in one embodiment, the angle between the vertical line of the bottom of the first chip semi-buried groove and the groove wall of the first chip semi-buried groove is α; 0°<α≤45°;

[0016] A plastic packaging material is arranged between the first chip semi-buried groove and the side wall of the first chip.

[0017] Optionally, in one embodiment, the depth of the first conductive hole is equal to the depth of the fourth conductive hole;

[0018] The depth of the second conductive hole is equal to the depth of the third conductive hole;

[0019] The depth of the fourth conductive hole is equal to the depth of the fifth conductive hole;

[0020] The depth of the first via hole is equal to the sum of the depth of the second via hole, the thickness of the second chip and the thickness of the upper pad of the second chip.

[0021] Optionally, in one embodiment, a plurality of air-conducting holes are provided on the lower surface circuit of the first chip semi-buried groove, and the air-conducting holes are evenly arranged on the outer periphery of the bottom of the first chip semi-buried groove, and one end of each air-conducting hole close to the center of the first chip semi-buried groove is located in the first chip semi-buried groove.

[0022] In a second aspect, the present invention provides a hybrid packaging structure of chips of different thicknesses, comprising the hybrid packaging structure of chips of different thicknesses disclosed in the first aspect above, and further comprising a third chip and a second substrate layer;

[0023] The thickness of the third chip is greater than the thickness of the first chip;

[0024] The second substrate layer is provided with a third chip semi-buried groove, and the third chip is arranged in the third chip semi-buried groove; the second substrate layer is arranged on the lower surface of the first substrate layer;

[0025] The thickness of the second substrate layer is between 90% and 110% of the difference between the thickness of the first chip and the thickness of the third chip.

[0026] Optionally, in one embodiment, the plastic encapsulation layer is further provided with a sixth conductive hole, and the second substrate layer is provided with a seventh conductive hole and an eighth conductive hole;

[0027] The sixth conductive hole connects the upper pad of the third chip with the upper surface circuit of the plastic packaging layer;

[0028] The seventh conductive hole connects the upper and lower layers of the second substrate layer;

[0029] The eighth conductive hole connects the lower pad of the first chip and the lower surface circuit of the second substrate layer.

[0030] The fifth conductive hole is used to connect the lower surface circuit and the upper surface circuit of the first substrate layer.

[0031] Optionally, in one embodiment, the depth of the fourth conductive hole is equal to the depth of the seventh conductive hole;

[0032] The depth of the sixth conductive hole is equal to the depth of the third conductive hole;

[0033] The depth of the eighth conductive hole is equal to the depth of the seventh conductive hole;

[0034] The depth of the first via hole is equal to the sum of the depth of the second via hole, the thickness of the second chip and the thickness of the upper pad of the second chip.

[0035] Optionally, in one embodiment, the third chip semi-buried groove is arranged in an inverted trapezoidal shape, and the size of the upper opening of the third chip semi-buried groove is larger than the size of the groove bottom of the third chip semi-buried groove;

[0036] The size of the upper opening of the semi-buried groove of the third chip is the sum of the size of the third chip and the equipment accuracy;

[0037] The size of the bottom of the groove in which the third chip is half buried is the size of the third chip.

[0038] Optionally, in one embodiment, the lower surface circuit of the third chip semi-buried groove is provided with a plurality of air-conducting through holes, and the air-conducting through holes are evenly arranged on the outer periphery of the bottom of the third chip semi-buried groove, and one end of each air-conducting through hole close to the center of the third chip semi-buried groove is located in the third chip semi-buried groove.

[0039] In a third aspect, the present invention provides a method for hybrid packaging of chips of different thicknesses, comprising the following steps:

[0040] S1: Select a first substrate layer, fabricate circuits on the upper and lower surfaces of the first substrate layer, and fabricate a fourth conductive hole and a fifth conductive hole between the first substrate layers;

[0041] The thickness of the first substrate layer is between 90% and 110% of the difference between the thickness of the first chip and the thickness of the second chip, and the thickness of the first chip is greater than the thickness of the second chip; the fourth conductive hole is used to connect the lower pad of the second chip to the lower surface circuit of the first substrate layer, and the fifth conductive hole is used to connect the upper and lower surface circuits of the first substrate layer;

[0042] S2: making a first chip semi-buried groove on the upper surface of the first substrate layer corresponding to the first chip mounting position;

[0043] The depth of the first chip semi-buried groove is the thickness of the first substrate layer; the angle between the vertical line of the bottom of the first chip semi-buried groove and the groove wall of the first chip semi-buried groove is α; 0°<α≤45°;

[0044] The first chip semi-buried groove is arranged in an inverted trapezoidal shape, and the size of the upper opening of the first chip semi-buried groove is larger than the size of the groove bottom of the first chip semi-buried groove;

[0045] The size of the upper opening of the first chip semi-buried groove is the sum of the size of the first chip and the equipment accuracy;

[0046] The size of the bottom of the groove in which the first chip is half buried is the size of the first chip;

[0047] S3: completing solder printing, chip mounting and reflow soldering for the first chip and the second chip through a chip mounting reflow process, embedding the first chip in the semi-embedded groove of the first chip, and mounting the second chip on the upper surface of the first substrate layer;

[0048] S4: Pressing plastic sealing materials on the upper surfaces of the first substrate layer, the first chip and the second chip respectively for plastic sealing, and baking the plastic sealing materials to solidify and form a plastic sealing layer;

[0049] Wherein, the gap between the first chip semi-buried groove and the first chip is filled with plastic packaging material;

[0050] S5: drilling holes in the plastic layer to form a first conductive hole, a second conductive hole and a third conductive hole, and performing metallization, electroplating, patterning and etching processes on the plastic layer so that the upper and lower layer lines of the plastic layer are electrically interconnected with the first chip and the second chip respectively;

[0051] Wherein, the first conductive hole is used to connect the upper and lower layers of the plastic packaging layer;

[0052] The second via hole is used to connect the upper pad of the second chip with the upper surface circuit of the plastic packaging layer;

[0053] The third conductive hole is used to connect the upper pad of the first chip with the upper surface circuit of the plastic packaging layer;

[0054] The upper surface circuit of the plastic encapsulation layer is exposed on the top of the plastic encapsulation layer, or the upper surface circuit of the plastic encapsulation layer is buried inside the plastic encapsulation layer.

[0055] Optionally, in one embodiment, S further includes:

[0056] S101: forming a plurality of air-conducting through holes on the lower surface of the semi-buried groove of the first chip by a pattern etching process;

[0057] The air-conducting through holes are evenly arranged on the outer periphery of the bottom of the first chip semi-buried groove, and one end of each air-conducting through hole close to the center of the first chip semi-buried groove is located in the first chip semi-buried groove;

[0058] S4 and later also include:

[0059] S401: Filling air-conducting through holes on the lower surface of the semi-buried groove of the first chip through metallization and electroplating processes.

[0060] Optionally, in one embodiment, the method further includes:

[0061] S102: Selecting a second substrate layer, manufacturing circuits on the upper and lower surfaces of the second substrate layer, and manufacturing a seventh conductive hole and an eighth conductive hole between the layers of the second substrate layer;

[0062] Wherein, the thickness of the second substrate layer is between 90% and 110% of the difference between the thickness of the first chip and the thickness of the third chip; the thickness of the third chip is greater than the thickness of the first chip;

[0063] The seventh conductive hole connects the upper and lower layers of the second substrate layer;

[0064] The eighth conductive hole connects the lower pad of the first chip and the lower surface circuit of the second substrate layer;

[0065] S201: making a third chip semi-buried groove on the upper surface of the second substrate layer and the first substrate corresponding to the third chip mounting position;

[0066] The depth of the third chip semi-buried groove is the sum of the thickness of the first substrate layer, the second substrate layer, and the thickness of the circuit between the first substrate layer and the second substrate layer; the angle between the vertical line of the bottom of the third chip semi-buried groove and the groove wall of the third chip semi-buried groove is β; 0°<β≤45°;

[0067] The third chip semi-buried groove is arranged in an inverted trapezoidal shape, and the size of the upper opening of the third chip semi-buried groove is larger than the size of the groove bottom of the third chip semi-buried groove;

[0068] The size of the upper opening of the semi-buried groove of the third chip is the sum of the size of the third chip and the equipment accuracy;

[0069] The size of the bottom of the groove in which the third chip is half-buried is the size of the third chip;

[0070] S301: completing solder printing, chip mounting and reflow soldering processing on the third chip through a patch reflow process, and embedding the third chip in the third chip semi-embedded groove;

[0071] S402: Pressing a plastic sealing material onto the upper surface of the third chip for plastic sealing, and baking the plastic sealing material to solidify and form a plastic sealing layer;

[0072] Wherein, the gap between the third chip semi-buried groove and the third chip is filled with plastic packaging material;

[0073] S501: drilling a sixth via hole in the plastic layer, and performing metallization, electroplating, patterning and etching processes on the plastic layer so that upper and lower layer lines of the plastic layer are respectively electrically interconnected with the third chip;

[0074] The sixth via hole is used to connect the upper pad of the third chip with the upper surface circuit of the plastic packaging layer.

[0075] Optionally, in one embodiment, the method further includes:

[0076] S102 and later also include:

[0077] S103: making a plurality of air-conducting through holes on the lower surface of the semi-buried groove of the third chip by a pattern etching process;

[0078] The air-conducting through holes are evenly arranged on the outer periphery of the bottom of the third chip semi-buried groove, and one end of each air-conducting through hole close to the center of the third chip semi-buried groove is located in the third chip semi-buried groove;

[0079] S4 and later also include:

[0080] S403: Filling the air-conducting through holes on the lower surface of the semi-buried groove of the third chip through metallization and electroplating processes.

[0081] In the technical solution provided by the present invention, through the semi-embedded design, chips of different thicknesses can be flexibly matched, so that the hole depth of the interconnection vias is consistent, which can simplify the processing technology and unify the parameters and quality control standards. The interconnection vias between the first chip of the semi-embedded mounting and the package carrier can also be divided into two layers of shallow holes by the middle layer, which reduces the difficulty of the process and improves the product and processing quality; at the same time, the first chip of the semi-embedded design is generally a high-power chip. For the heat dissipation problem of the high-power chip, the chip designed by the packaging structure directly contacts the external pad with a large area, which greatly improves the heat dissipation efficiency and can reduce the total thickness of the package body; the thickness difference between chips of different thicknesses can be flexibly matched. The present invention can match as long as the appropriate substrate thickness or the depth of the chip semi-embedded groove is selected. The design of the packaging structure has a wide range of applicability matching for the thickness of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0082] One or more embodiments are exemplarily described by corresponding drawings, which do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and the figures in the drawings do not constitute proportional limitations unless otherwise stated.

[0083] Figure 1 It is a schematic diagram of the structure of mixed packaging structure of different chips in the prior art;

[0084] Figure 2 It is a structural schematic diagram of the first several substrate layers of a hybrid packaging structure of chips with different thicknesses and a packaging method thereof of the present invention;

[0085] Figure 3 It is a schematic diagram of the structure of a mixed packaging structure of chips of different thicknesses and a packaging method thereof after the chip is half-buried in a groove;

[0086] Figure 4 It is a schematic diagram of placing a first chip and a second chip on a first substrate layer in a hybrid packaging structure of chips of different thicknesses and a packaging method thereof according to the present invention;

[0087] Figure 5 It is a schematic diagram of laminating a plastic sealing layer on a first substrate layer in a hybrid packaging structure of chips of different thicknesses and a packaging method thereof according to the present invention;

[0088] Figure 6 It is a schematic diagram of making a via hole on a plastic packaging layer in a hybrid packaging structure of chips of different thicknesses and a packaging method thereof according to the present invention;

[0089] Figure 7 It is a schematic diagram of making a pad or a circuit on a plastic packaging layer in a mixed packaging structure of chips of different thicknesses and a packaging method thereof of the present invention;

[0090] Figure 8 This is one of the structural schematic diagrams of a mixed packaging structure of chips of different thicknesses and a packaging method thereof of the present invention;

[0091] Fig. 9 This is the second structural schematic diagram of a mixed packaging structure of chips with different thicknesses and a packaging method thereof of the present invention;

[0092] Fig.10 It is a schematic diagram of the structure of a mixed packaging structure of chips of different thicknesses and a packaging method thereof when a thin metal sheet is attached to the bottom of the chip and after being bent;

[0093] Fig.11 It is a schematic cross-sectional structure diagram of a gas-conducting through hole in a hybrid packaging structure of chips of different thicknesses and a packaging method thereof according to the present invention;

[0094] Fig.12 It is a schematic diagram of a mixed packaging structure of chips of different thicknesses and a packaging method thereof in which the slope angle of the first chip semi-buried groove or the third chip semi-buried groove is arctan (1 / n) where n=3;

[0095] Fig.13 It is a schematic diagram of a hybrid packaging structure of chips of different thicknesses and a packaging method thereof in which the groove slope angle of the first chip semi-buried groove or the third chip semi-buried groove is arctan (1 / n) where n=4;

[0096] Fig.14 It is a schematic diagram of a hybrid packaging structure of chips of different thicknesses and a packaging method thereof in which the groove slope angle of the first chip semi-buried groove or the third chip semi-buried groove is arctan (1 / n) where n=5;

[0097] Fig.15 It is a structural schematic diagram of another embodiment of a hybrid packaging structure of chips of different thicknesses and a packaging method thereof of the present invention;

[0098] Fig.16 It is a structural schematic diagram of another embodiment of a hybrid packaging structure of chips of different thicknesses and a packaging method thereof of the present invention;

[0099] Fig.17 It is a structural schematic diagram of another embodiment of a mixed packaging structure of chips with different thicknesses and a packaging method thereof of the present invention.

[0100] In the figure: 01-first substrate layer; 011-first chip semi-buried in groove; 0111-air conduction hole; 012-fourth conduction hole; 013-fifth conduction hole; 02-plastic sealing layer; 021-first conduction hole; 022-second conduction hole; 023-third conduction hole; 024-sixth conduction hole; 03-second substrate layer; 031-third chip semi-buried in groove; 032-seventh conduction hole; 033-eighth conduction hole; 1-first chip; 2-second chip; 3-third chip; 4-thin metal sheet. DETAILED DESCRIPTION

[0101] In order to facilitate the understanding of the present invention, the present invention is described in more detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that when an element is described as "fixed to" another element, it can be directly on another element, or there can be one or more centered elements therebetween. When an element is described as "connected" to another element, it can be directly connected to another element, or there can be one or more centered elements therebetween. The terms "vertical", "horizontal", "left", "right", "inside", "outside" and similar expressions used in this specification are only for illustrative purposes. In the description of the present invention, the terms "first" and "second" are used only for descriptive purposes and cannot be understood as indicating relative importance or implicitly indicating the number of technical features indicated. Therefore, unless otherwise specified, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features; the meaning of "multiple" is two or more. The term "include" and any variation thereof means non-exclusive inclusion, and one or more other features, integers, steps, operations, units, components and / or combinations thereof may be present or added.

[0102] In addition, unless otherwise expressly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, an indirect connection through an intermediate medium, or a connection between two components. All technical and scientific terms used in this specification have the same meaning as those generally understood by technicians in the technical field of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used in this specification includes any and all combinations of one or more related listed items.

[0103] In addition, the technical features involved in different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0104] Embodiment 1

[0105] To achieve the above purpose, please refer to Figures 1 to 17 , attached Figure 1 Schematic diagram of a mixed packaging structure for chips of different thicknesses in the prior art. Figure 7 and Figure 8 This is a schematic diagram of a hybrid packaging structure of chips of different thicknesses in the present application. Specifically, a hybrid packaging structure of chips of different thicknesses includes:

[0106] It includes a first substrate layer 01, a first chip 1 and a second chip 2. The thickness of the first chip 1 is greater than that of the second chip 2. The first substrate layer 01 is provided with a first chip semi-buried groove 011. The first chip 1 is arranged in the first chip semi-buried groove 011, and the second chip 2 is arranged on the upper surface of the first substrate layer 01. The thickness of the first substrate layer 01 is between 90% and 110% of the difference in thickness between the first chip 1 and the second chip 2.

[0107] In some embodiments, the relationship between the thickness H2 of the second chip 2 and the thickness H1 of the first chip 1 is H2≤(H1-50 μm) / 2;

[0108] Specifically, the thickness H1 of the first chip 1 is 300 μm, and the thickness H2 of the second chip 2 is 120 μm. At this time, the hole depth and the thickness of the substrate can be optimized by adjusting the copper thickness of the pad on the upper surface of the first substrate layer 01. Here, the copper thickness of the pad is 20 μm, and the thickness of the first substrate is selected as 160 μm. If the copper thickness of the pad is 30 μm, the thickness of the first substrate is selected as 150 μm.

[0109] Or, the thickness H1 of the chip 1 is 350 μm, the thickness H2 of the second chip 2 is 150 μm, and if the copper thickness of the pad on the upper surface of the first substrate layer 01 is 20 μm, the thickness of the first substrate is selected to be 180 μm.

[0110] In some embodiments, please refer to the attached Figure 5 To Attachment Figure 8 Specifically, it also includes a plastic encapsulation layer 02, the plastic encapsulation layer 02 is provided with a first conductive hole 021, a second conductive hole 022 and a third conductive hole 023, and the first substrate layer 01 is provided with a fourth conductive hole 012 and a fifth conductive hole 013;

[0111] The first conductive hole 021 is used to connect the upper and lower layers of the plastic packaging layer 02;

[0112] The second conductive hole 022 connects the upper pad of the second chip 2 with the upper surface circuit of the plastic packaging layer 02;

[0113] The third conductive hole 023 connects the upper pad of the first chip 1 with the upper surface circuit of the plastic packaging layer 02;

[0114] The fourth conductive hole 012 connects the lower pad of the second chip 2 with the lower surface circuit of the first substrate layer 01;

[0115] The fifth conductive hole 013 connects the lower surface circuit and the upper surface circuit of the first substrate layer 01 .

[0116] Specifically, the first substrate layer 01 is subjected to conventional plastic encapsulation processing, and the resin material is molded or pressed to achieve chip plastic encapsulation, and the second chip 2 and the first chip 1 are completely wrapped by the plastic encapsulation material, and baked and cured. Among them, the material of the plastic encapsulation layer 02 is preferably silicon dioxide.

[0117] The material of the plastic encapsulation layer 02 is silicon dioxide, which can form a close arrangement with the inverted trapezoidal setting of the first chip semi-buried groove 011, ensuring that the plastic encapsulation material can tightly fill the gap between the groove wall of the first chip semi-buried groove 011 and the first chip 1, reducing plastic encapsulation voids, reducing the pad area and the height of the via hole, and effectively reducing the use of copper materials with a higher thermal expansion coefficient.

[0118] In some embodiments, the first chip semi-buried groove 011 is arranged in an inverted trapezoidal shape, and the size of the upper opening of the first chip semi-buried groove 011 is larger than the size of the groove bottom of the first chip semi-buried groove 011;

[0119] The size of the upper opening of the first chip semi-buried groove 011 is the sum of the size of the first chip 1 and the equipment accuracy;

[0120] The size of the bottom of the first chip half-buried in the groove 011 is the size of the first chip 1 .

[0121] In some embodiments, please refer to the attached Fig.12 To Attachment Fig.14 Specifically, the angle between the vertical line of the bottom of the first chip semi-buried groove 011 and the groove wall of the first chip semi-buried groove 011 is α; 0°<α≤45°;

[0122] A plastic packaging material is arranged between the first chip semi-buried groove 011 and the side wall of the first chip 1 .

[0123] Specifically, a double-sided two-layer first substrate layer 01 with a thickness of 160μm is selected. The functions of the general conventional process are the pad pattern and interlayer conduction. The copper thickness of the upper surface pad of the first substrate layer 01 is 20μm; a first chip 1 with a thickness of 300μm and a second chip 2 with a thickness of 120μm are selected, and a first chip semi-buried groove 011 with a depth of 110μm and a slope of about 11.31° (i.e. n=5) in the first substrate layer 01 corresponding to the first chip 1 corresponding to the patch position is designed, and the semi-buried chip groove 5 is processed and formed by controlled depth drilling or laser drilling. The following table is an example of the relationship between the slope angle, equipment accuracy and groove depth of the chip semi-buried groove:

[0124]

[0125]

[0126] In some embodiments, the depth of the first conductive via 021 is equal to the depth of the fourth conductive via 012 ;

[0127] The depth of the second conductive hole 022 is equal to the depth of the third conductive hole 023;

[0128] The depth of the fourth conductive hole 012 is equal to the depth of the fifth conductive hole 013;

[0129] The depth of the first conductive hole 021 is equal to the sum of the depth of the second conductive hole 022 , the thickness of the second chip 2 , and the thickness of the upper pad of the second chip 2 .

[0130] Specifically, controlled depth drilling or laser drilling is used to process and form via holes at the second chip 2, the first chip 1 and other interlayer conduction locations, wherein the processing technology and parameters of the second via hole 022 and the third via hole 023 of the chip pads on the upper surfaces of the second chip 2 and the first chip 1 are stable and uniform, and the depths of the second via hole 022 and the third via hole 023 can be 40μm, respectively; the processing technology and parameters of the first via hole 021 between other layers are also stable and uniform, and the large deep hole in the prior art of interlayer conduction of the first chip 1 is divided into two, and one large deep hole is divided into two first via holes 101, which is also conducive to filling and covering the holes with plastic packaging material.

[0131] In some embodiments, please refer to the attached Figure 2 To Attachment Fig.11 , attached Fig.11 This is a schematic diagram of the cross-sectional structure of the air-conducting holes of a hybrid packaging structure of chips of different thicknesses in the present application. Specifically, the lower surface circuit of the first chip semi-buried groove 011 is provided with a plurality of air-conducting holes 0111, and the air-conducting holes 0111 are evenly arranged on the outer periphery of the bottom of the first chip semi-buried groove 011, and one end of each air-conducting hole 0111 close to the center of the first chip semi-buried groove 011 is located in the first chip semi-buried groove 011.

[0132] Specifically, the air-conducting through hole 0111 is a strip-shaped slot-type through hole, and the air-conducting through hole 0111 is arranged at the periphery of the bottom of the first chip semi-buried groove 011 and is evenly arranged; one end of the air-conducting through hole 0111 faces the center of the bottom of the first chip semi-buried groove 011; the end of the air-conducting through hole 0111 close to the center of the first chip semi-buried groove 011 is located in the first chip semi-buried groove 011, considering that the size tolerance of the laser-burned groove of the first chip semi-buried groove 011 is ±50μm, the distance between the end of the air-conducting through hole 0111 close to the center of the first chip semi-buried groove 011 and the groove bottom edge of the first chip semi-buried groove 011 closest to it is H3, 0<H3≤50μm, preferably, H3 is 50μm;

[0133] When the first chip 1 falls into the first chip semi-buried groove 011, air will be brought into the place where the first chip 1 and the first chip semi-buried groove 011 are attached, so that bubbles may be generated during the hot pressing of the plastic sealing layer 02, resulting in the problem that the first chip 1 and the first chip semi-buried groove 011 are not pressed tightly, thereby affecting the working performance of the packaging structure, and etching the air guide hole 0111 on the copper layer on the lower surface of the first substrate layer 01 through a graphic process can make the air be discharged from the air guide hole 0111 during the step of hot pressing the plastic sealing layer 02, thereby reducing the internal gas content and reducing the probability of bubble generation; secondly, due to a certain error in the accuracy of the equipment during chip mounting, when the first chip 1 falls into the first chip semi-buried groove 011 There may be deviations in the falling position. In the loading process, the air conducting hole 0111 can be subjected to negative pressure adsorption, thereby achieving the function of adsorbing the first chip 1 through the air conducting hole 0111, so that the first chip 1 can be better positioned and the loading accuracy can be improved; thirdly, in the loading process, the optical detection of the air conducting hole 0111 can be used to detect the situation of the first chip 1 falling into the first chip semi-buried groove 011, and the shadow area, shadow position, number of blocking holes and other data of the air conducting hole 0111 before and after the first chip 1 falls into the first chip 1 are obtained through optical equipment, so as to obtain the falling situation of the first chip 1 and accurately obtain the falling position of the first chip 1, thereby performing the loading correction step of the first chip 1.

[0134] In this embodiment, the size of the first chip 1 is 1000μm*1000μm, the placement accuracy of the placement machine is ±25μm, and considering the laser burning groove size tolerance of ±50μm, the size of the first chip semi-buried groove 011 is 1100μm*1100μm, and the size of the air guide hole 0111 is 100μm*50μm.

[0135] In some embodiments, after the heat-pressing plastic sealing layer 03, conventional substrate or PCB metallization, electroplating and other processing techniques can be used to fill and restore the gas conducting through hole 0111.

[0136] Please refer to the attached Fig.10 , attached Fig.10 The present invention is a schematic diagram of the structure of a thin metal sheet of a mixed packaging structure of chips of different thicknesses when it is attached to the bottom of the chip and after being bent. Specifically, in some embodiments, after the hot pressing of the plastic sealing layer 03, the plastic sealing material may enter the air conducting hole 0111 through the semi-buried groove 011 of the first chip, thereby blocking the air conducting hole 0111, which may cause a certain risk of poor contact when the lower surface of the first substrate layer 01 is usually connected to the external circuit. A layer of thin metal sheet 4 can be pre-pasted on the bottom of the first chip 1, and the size of the thin metal sheet 4 is larger than the size of the first chip 1 and less than or equal to the size of the first chip 1. The size of the chip semi-buried groove 011, and the outer periphery of the thin metal sheet 4 is exposed from the bottom of the first chip 1, and then the first chip 1 and the thin metal sheet 4 are mounted in the first chip semi-buried groove 011. At this time, the thin metal sheet 4 is bent along the groove wall of the first chip semi-buried groove 011, so that the thin metal sheet 4 completely covers the groove bottom of the first chip semi-buried groove 011. When the subsequent hot pressing plastic sealing layer 03 is performed, the plastic sealing material is blocked by the thin metal sheet 4 and cannot enter the groove bottom of the chip semi-buried groove 011 and the air conducting hole 0111, thereby improving the conductive performance and working performance of the packaging structure.

[0137] In some embodiments, the thin metal sheet 4 is a metal with a melting point of 200-400°C, which can be melted in a hot pressing process (the conventional temperature is 300-400°C); it has a certain hardness and can be mounted in a sheet shape on the bottom of the chip, and has a certain toughness and can be bent in the first chip semi-embedded groove 011. In this embodiment, the thin metal sheet 4 is a copper-tin alloy, wherein the copper metal is arranged on the top of the thin metal sheet 4 and fits with the bottom of the chip, and at the same time plays a role in supporting the tin metal. The tin metal is arranged at the bottom of the thin metal sheet 4 and contacts with the first chip semi-embedded groove 011. When the hot pressing molding process is performed, the tin metal melts at the bottom of the first chip semi-embedded groove 011 and fills the air conducting hole 0111 at the same time, thereby maintaining the conductive performance and working performance of the packaging structure.

[0138] The present invention designs a semi-buried chip slot that flexibly matches the height of the chip interconnection layer, designs the rectangular semi-buried slot into an inverted trapezoidal slot body, and the inverted trapezoidal design takes into account the adaptive positioning of the chip semi-buried mounting point; at the same time, the slope angle of the slot body takes into account the inflow filling of the plastic packaging material and the close arrangement of the silica particles of the plastic packaging filler, and fully fills to reduce plastic packaging voids, reduces the pad area and the height of the via hole, effectively reduces the use of copper materials with a higher thermal expansion coefficient, and solves the technical difficulties of mixed packaging of chips of different thicknesses with a high cost performance, simplifies and unifies processing parameters and control standards, reduces process control difficulties and reduces product processing difficulty, improves product processing quality and product reliability.

[0139] The thickness difference between chips of different thicknesses can be flexibly matched. The present invention can match the thickness of the chip by selecting a suitable substrate thickness or the depth of the chip semi-buried groove. The design of the packaging structure has a wide range of applicability to the thickness of the chip.

[0140] The present invention not only unifies and stabilizes the processing parameters and quality control standards in the packaging process, but also reduces the use of copper materials with higher thermal expansion coefficients in the packaging structure and effectively improves the heat dissipation efficiency, which will greatly improve the product quality stability and reliability.

[0141] Embodiment 2

[0142] To achieve the above purpose, please refer to Figures 1 to 17 , attached Figure 1 Schematic diagram of a mixed packaging structure for chips of different thicknesses in the prior art. Fig. 9 Schematic diagram of a hybrid packaging structure of chips with different thicknesses in the present application. Specifically, the hybrid packaging structure of chips with different thicknesses includes the hybrid packaging structure of chips with different thicknesses disclosed in the first embodiment, and further includes a third chip 3 and a second substrate layer 03;

[0143] The thickness of the third chip 3 is greater than the thickness of the first chip 1;

[0144] The second substrate layer 03 is provided with a third chip semi-buried groove 031, and the third chip 3 is arranged in the third chip semi-buried groove 031; the second substrate layer 03 is arranged on the lower surface of the first substrate layer 01;

[0145] The thickness of the second substrate layer 03 is between 90% and 110% of the difference between the thickness of the first chip 1 and the thickness of the third chip 3 .

[0146] Optionally, in one embodiment, the plastic encapsulation layer 02 is further provided with a sixth conductive hole 024, and the second substrate layer 03 is provided with a seventh conductive hole 032 and an eighth conductive hole 033;

[0147] The sixth conductive hole 024 connects the upper pad of the third chip 3 with the upper surface circuit of the plastic packaging layer 02;

[0148] The seventh conductive hole 032 connects the upper and lower layers of the second substrate layer 03;

[0149] The eighth conductive hole 033 connects the lower pad of the first chip 1 with the lower surface circuit of the second substrate layer 03 .

[0150] The fifth conductive hole 013 is used to connect the lower surface circuit and the upper surface circuit of the first substrate layer 01 .

[0151] Optionally, in one embodiment, the depth of the fourth conductive hole 012 is equal to the depth of the seventh conductive hole 032;

[0152] The depth of the sixth conductive hole 024 is equal to the depth of the third conductive hole 023;

[0153] The depth of the eighth conductive hole 033 is equal to the depth of the seventh conductive hole 032;

[0154] The depth of the first conductive hole 021 is equal to the sum of the depth of the second conductive hole 022 , the thickness of the second chip 2 , and the thickness of the upper pad of the second chip 2 .

[0155] Optionally, in one embodiment, the third chip semi-buried groove 032 is arranged in an inverted trapezoidal shape, and the size of the upper opening of the third chip semi-buried groove 032 is larger than the size of the groove bottom of the third chip semi-buried groove 032;

[0156] The size of the upper opening of the third chip semi-buried groove 032 is the sum of the size of the third chip 3 and the equipment accuracy;

[0157] The size of the bottom of the groove where the third chip is half-buried in the groove 032 is the size of the third chip 1 .

[0158] Optionally, in one embodiment, a plurality of air-conducting holes 0111 are provided on the lower surface circuit of the third chip semi-buried groove 032, and the air-conducting holes 0111 are evenly arranged on the outer periphery of the bottom of the third chip semi-buried groove 032, and one end of each air-conducting hole 0111 close to the center of the third chip semi-buried groove 032 is located in the third chip semi-buried groove 032.

[0159] Specifically, the air-conducting through hole 0111 is a strip-shaped slot-type through hole, and the air-conducting through hole 0111 is arranged at the periphery of the bottom of the first chip semi-buried groove 011 and is evenly arranged; one end of the air-conducting through hole 0111 faces the center of the bottom of the first chip semi-buried groove 011; the end of the air-conducting through hole 0111 close to the center of the first chip semi-buried groove 011 is located in the first chip semi-buried groove 011, considering that the size tolerance of the laser-burned groove of the first chip semi-buried groove 011 is ±50μm, the distance between the end of the air-conducting through hole 0111 close to the center of the first chip semi-buried groove 011 and the groove bottom edge of the first chip semi-buried groove 011 closest to it is H3, 0<H3≤50μm, preferably, H3 is 50μm;

[0160] When the first chip 1 falls into the first chip semi-buried groove 011, air will be brought into the place where the first chip 1 and the first chip semi-buried groove 011 are attached, so that bubbles may be generated during the hot pressing of the plastic sealing layer 02, resulting in the problem that the first chip 1 and the first chip semi-buried groove 011 are not pressed tightly, thereby affecting the working performance of the packaging structure, and etching the air guide hole 0111 on the copper layer on the lower surface of the first substrate layer 01 through a graphic process can make the air be discharged from the air guide hole 0111 during the step of hot pressing the plastic sealing layer 02, thereby reducing the internal gas content and reducing the probability of bubble generation; secondly, due to a certain error in the accuracy of the equipment during chip mounting, when the first chip 1 falls into the first chip semi-buried groove 011 There may be deviations in the falling position. In the loading process, the air conducting hole 0111 can be subjected to negative pressure adsorption, thereby achieving the function of adsorbing the first chip 1 through the air conducting hole 0111, so that the first chip 1 can be better positioned and the loading accuracy can be improved; thirdly, in the loading process, the optical detection of the air conducting hole 0111 can be used to detect the situation of the first chip 1 falling into the first chip semi-buried groove 011, and the shadow area, shadow position, number of blocking holes and other data of the air conducting hole 0111 before and after the first chip 1 falls into the first chip 1 are obtained through optical equipment, so as to obtain the falling situation of the first chip 1 and accurately obtain the falling position of the first chip 1, thereby performing the loading correction step of the first chip 1.

[0161] In this embodiment, the size of the third chip 1 is 1500μm*1500μm, the placement accuracy of the placement machine is ±25μm, and considering the laser burning groove size tolerance of ±50μm, the size of the semi-buried groove 031 of the third chip is 1600μm*1600μm, and the size of the air guide hole 0111 is 100μm*50μm.

[0162] In some embodiments, after the heat-pressing plastic sealing layer 03, conventional substrate or PCB metallization, electroplating and other processing techniques can be used to fill and restore the gas conducting through hole 0111.

[0163] In some embodiments, after the hot-pressing plastic sealing layer 03, there is a possibility that the plastic sealing material enters the air conducting hole 0111 through the semi-buried groove 031 of the third chip, thereby blocking the air conducting hole 0111, which may cause a certain risk of poor contact when the lower surface of the first substrate layer 01 is usually connected to the external circuit. A layer of thin metal sheet 4 can be pre-pasted on the bottom of the third chip 3. The size of the thin metal sheet 4 is larger than the size of the third chip 3 and less than or equal to the size of the semi-buried groove 031 of the third chip, and the periphery of the thin metal sheet 4 is uniformly The bottom of the third chip 3 is exposed, and then the third chip 3 and the thin metal sheet 4 are mounted in the third chip semi-buried groove 031. At this time, the thin metal sheet 4 is bent along the groove wall of the third chip semi-buried groove 031, so that the thin metal sheet 4 completely covers the bottom of the third chip semi-buried groove 031. When the plastic sealing layer 03 is subsequently hot-pressed, the plastic sealing material is blocked by the thin metal sheet 4 and cannot enter the groove bottom of the chip semi-buried groove 011 and the air conducting hole 0111, thereby improving the conductive performance and working performance of the packaging structure.

[0164] In some embodiments, the thin metal sheet 4 is a metal with a melting point of 200-400°C, which can be melted in a hot pressing process (the conventional temperature is 300-400°C); it has a certain hardness and can be mounted in a sheet shape on the bottom of the chip, and has a certain toughness and can be bent in the third chip semi-embedded groove 031. In this embodiment, the thin metal sheet 4 is a copper-tin alloy, wherein the copper metal is arranged on the top of the thin metal sheet 4 and fits the bottom of the chip, and at the same time plays a role in supporting the tin metal. The tin metal is arranged at the bottom of the thin metal sheet 4 and contacts with the third chip semi-embedded groove 031. When the hot pressing molding process is performed, the tin metal melts at the bottom of the third chip semi-embedded groove 031 and fills the air conducting hole 0111 at the same time, thereby maintaining the conductive performance and working performance of the packaging structure.

[0165] Embodiment 3

[0166] Please refer to the attached Figure 1 To Attachment Fig.14 Specifically, the present invention provides a mixed packaging method for chips of different thicknesses, comprising the following steps:

[0167] Please refer to the attached Figure 2 , S1: Select the first substrate layer 01, make circuits on the upper and lower surfaces of the first substrate layer 01, and make a fourth conductive hole 012 and a fifth conductive hole 013 between the layers of the first substrate layer 01;

[0168] The thickness of the first substrate layer 01 is between 90% and 110% of the difference between the thickness of the first chip 1 and the second chip 2, and the thickness of the first chip 1 is greater than the thickness of the second chip 2; the fourth conductive hole 012 is used to connect the lower pad of the second chip 2 to the lower surface circuit of the first substrate layer 01, and the fifth conductive hole 013 is used to connect the upper and lower surface circuits of the first substrate layer 01;

[0169] Please refer to the attached Figure 3 , S2: making a first chip semi-buried groove 011 on the upper surface of the first substrate layer 01 corresponding to the first chip mounting position;

[0170] Among them, the depth of the first chip semi-buried groove 011 is the thickness of the first substrate layer 01; the angle between the vertical line of the bottom of the first chip semi-buried groove 011 and the groove wall of the first chip semi-buried groove 011 is α; 0°<α≤45°; specifically, α can be 0°, 15°, 20°, 30°, or 45°.

[0171] The first chip semi-buried groove 011 is arranged in an inverted trapezoidal shape, and the size of the upper opening of the first chip semi-buried groove 011 is larger than the size of the groove bottom of the first chip semi-buried groove 011;

[0172] The size of the upper opening of the first chip semi-buried groove 011 is the sum of the size of the first chip 1 and the equipment accuracy;

[0173] The size of the bottom of the first chip half-buried in the groove 011 is the size of the first chip 1;

[0174] Please refer to the attached Figure 4 S3: completing solder printing, chip mounting and reflow soldering for the first chip 1 and the second chip 2 through a chip reflow process, embedding the first chip 1 in the first chip semi-embedded groove 011, and attaching the second chip 2 on the upper surface of the first substrate layer 01;

[0175] Please refer to the attached Figure 5 S4: Pressing plastic sealing materials on the upper surfaces of the first substrate layer 01, the first chip 1 and the second chip 2 for plastic sealing, and baking the plastic sealing materials to solidify and form a plastic sealing layer 02;

[0176] The gap between the first chip semi-buried groove 011 and the first chip 1 is filled with a plastic packaging material; the plastic packaging material is preferably silicon dioxide.

[0177] Please refer to the attached Figure 6 and attached Figure 7 S5: drilling holes in the plastic layer 02 to form a first conductive hole 021, a second conductive hole 022 and a third conductive hole 023, and performing metallization, electroplating, patterning and etching processes on the plastic layer 02 so that the upper and lower layer lines of the plastic layer 02 are electrically interconnected with the first chip 1 and the second chip 2 respectively;

[0178] Among them, the first conductive hole 021 is used to connect the upper and lower layers of the plastic packaging layer 02;

[0179] The second via hole 022 is used to connect the upper pad of the second chip 2 with the upper surface circuit of the plastic packaging layer 02;

[0180] The third conductive hole 023 is used to connect the upper pad of the first chip 1 with the upper surface circuit of the plastic packaging layer 02;

[0181] Please refer to the attached Figure 7 , the upper surface circuit of the plastic layer 02 is exposed on the top of the plastic layer 02, or, please refer to the attached Figure 8 The circuit on the upper surface of the plastic encapsulation layer 02 is buried inside the plastic encapsulation layer 02 .

[0182] In some embodiments, S1 further includes:

[0183] Please refer to the attached Figure 2 and attached Fig.11 S101: a plurality of gas conducting holes 0111 are formed on the lower surface of the semi-buried groove 011 of the first chip by a graphic etching process;

[0184] Please refer to the attached Fig.11 Specifically, the air-conducting through holes 0111 are evenly arranged on the outer periphery of the bottom of the first chip semi-buried groove 011, and one end of each air-conducting through hole 0111 close to the center of the first chip semi-buried groove 011 is located in the first chip semi-buried groove 011;

[0185] S4 and later also include:

[0186] Please refer to the attached Figure 5 S401: Filling the gas conducting through hole 0111 on the lower surface of the semi-buried groove 011 of the first chip through metallization and electroplating processes.

[0187] In some embodiments, it also includes:

[0188] S102: Select a second substrate layer 03, fabricate circuits on the upper and lower surfaces of the second substrate layer 03, and fabricate a seventh conductive hole 032 and an eighth conductive hole 033 between the layers of the second substrate layer 03;

[0189] The thickness of the second substrate layer 03 is between 90% and 110% of the difference between the thickness of the first chip 1 and the thickness of the third chip 3; the thickness of the third chip 3 is greater than the thickness of the first chip 1;

[0190] The seventh conductive hole 032 connects the upper and lower layers of the second substrate layer 03;

[0191] The eighth conductive hole 033 connects the lower pad of the first chip 1 with the lower surface circuit of the second substrate layer 03;

[0192] S201: making a third chip semi-buried groove 031 on the upper surface of the second substrate layer 03 and the first substrate 01 corresponding to the mounting position of the third chip 3;

[0193] The depth of the third chip semi-buried groove 031 is the sum of the thickness of the first substrate layer 01, the second substrate layer 02, and the thickness of the line between the first substrate layer 01 and the second substrate layer 02; the angle between the vertical line of the bottom of the third chip semi-buried groove 031 and the groove wall of the third chip semi-buried groove 031 is β; 0°<β≤45°; please refer to the attached Fig.11 To Attachment Fig.13 Specifically, β can be 0°, 15°, 20°, 30°, or 45°.

[0194] The third chip semi-buried groove 031 is arranged in an inverted trapezoidal shape, and the size of the upper opening of the third chip semi-buried groove 031 is larger than the size of the groove bottom of the third chip semi-buried groove 031;

[0195] The size of the upper opening of the third chip semi-buried groove 031 is the sum of the size of the third chip 3 and the equipment accuracy;

[0196] The size of the bottom of the groove where the third chip is half-buried in the groove 031 is the size of the third chip 3;

[0197] S301: completing solder printing, chip mounting and reflow soldering for the third chip 3 through a chip reflow process, and embedding the third chip 3 in the third chip semi-embedded groove 031;

[0198] S402: Pressing a plastic sealing material onto the upper surface of the third chip 3 for plastic sealing, and baking the plastic sealing material to solidify and form a plastic sealing layer 02;

[0199] The gap between the third chip half-buried groove 031 and the third chip 3 is filled with plastic packaging material;

[0200] Please refer to the attached Fig. 9 S501: drilling a sixth conductive hole 024 in the plastic layer 02, and performing metallization, electroplating, patterning and etching processes on the plastic layer 02 so that the upper and lower layer lines of the plastic layer 02 are respectively electrically interconnected with the third chip 3;

[0201] The sixth conductive hole 024 is used to connect the upper pad of the third chip 3 with the upper surface circuit of the plastic packaging layer 02 .

[0202] In some embodiments, it also includes:

[0203] S102 and later also include:

[0204] S103: a plurality of gas-conducting through holes 0111 are formed on the lower surface of the semi-buried groove 031 of the third chip by a pattern etching process;

[0205] The air-conducting through holes 0111 are evenly arranged on the periphery of the bottom of the third chip semi-buried groove 031, and one end of each air-conducting through hole 0111 close to the center of the third chip semi-buried groove 031 is located in the third chip semi-buried groove 031;

[0206] S4 and later also include:

[0207] S403: Filling the gas conducting through hole 0111 on the lower surface of the semi-buried groove 031 of the third chip through metallization and electroplating processes.

[0208] In some embodiments, S1 further includes:

[0209] S103: pre-pasting a thin metal sheet 4 on the bottom of the first chip 1 and the third chip 3;

[0210] S3 also includes:

[0211] S302: mounting the first chip 1 and the thin metal sheet 4 in the first chip semi-buried groove 011; mounting the third chip 3 and the thin metal sheet 4 in the first chip semi-buried groove 011;

[0212] The size of the thin metal sheet 4 mounted on the first chip 1 is larger than the size of the first chip 1, and smaller than or equal to the size of the first chip semi-buried groove 011, and the outer periphery of the thin metal sheet 4 mounted on the first chip 1 is exposed from the bottom of the first chip 1, and then the first chip 1 and the thin metal sheet 4 are mounted in the first chip semi-buried groove 011;

[0213] The size of the thin metal sheet 4 mounted on the third chip 3 is larger than the size of the third chip 3, and smaller than or equal to the size of the third chip semi-buried groove 031, and the outer periphery of the thin metal sheet 4 mounted on the third chip 3 is exposed from the bottom of the third chip 3, and then the third chip 3 and the thin metal sheet 4 are mounted in the third chip semi-buried groove 031;

[0214] The thin metal sheet 4 is bent along the groove walls of the first chip semi-buried groove 011 and the third chip semi-buried groove 031, so that the thin metal sheet 4 completely covers the groove bottom of the third chip semi-buried groove 031. When the plastic sealing layer 03 is subsequently hot-pressed, the plastic sealing material is blocked by the thin metal sheet 4 and cannot enter the groove bottom of the third chip semi-buried groove 031 and the air conducting hole 0111, thereby improving the conductive performance and working performance of the packaging structure.

[0215] In some embodiments, the thin metal sheet 4 is a metal with a melting point of 200-400°C, which can be melted into a liquid in a hot pressing process (the conventional temperature is 300-400°C); it has a certain hardness and can be attached to the bottom of the chip in a sheet shape, and has a certain toughness and can be bent in the first chip semi-buried groove 011 and the third chip semi-buried groove 031. Please refer to the attached Fig.10In this embodiment, the thin metal sheet 4 is a copper-tin alloy, wherein the copper metal is arranged on the top of the thin metal sheet 4 and fits with the bottom of the chip, and at the same time plays a role in supporting the tin metal. The tin metal is arranged at the bottom of the thin metal sheet 4 and contacts with the first chip semi-buried groove 011. When the hot pressing molding process is performed, the tin metal melts at the bottom of the first chip semi-buried groove 011 and the third chip semi-buried groove 031, and at the same time fills the air conducting through hole 0111, thereby maintaining the conductive performance and working performance of the packaging structure.

[0216] The present invention designs a semi-buried chip slot that flexibly matches the height of the chip interconnection layer, designs the rectangular semi-buried slot into an inverted trapezoidal slot body, and the inverted trapezoidal design takes into account the adaptive positioning of the chip semi-buried placement point; at the same time, the slope angle (i.e., α and β) of the slot body takes into account the inflow filling of the plastic encapsulation material and the close arrangement of the silica particles of the plastic encapsulation filler, and fully fills to reduce the plastic encapsulation voids, reduces the pad area and the height of the via hole, effectively reduces the use of copper materials with a higher thermal expansion coefficient, and solves the technical difficulties of mixed packaging of chips of different thicknesses with a high cost performance, simplifies and unifies processing parameters and control standards, reduces process control difficulties and reduces product processing difficulty, improves product processing quality and product reliability.

[0217] The thickness difference between chips of different thicknesses can be flexibly matched. The present invention can match the thickness of the chip by selecting a suitable substrate thickness or the depth of the chip semi-buried groove. The design of the packaging structure has a wide range of applicability to the thickness of the chip.

[0218] Embodiment 4

[0219] To achieve the above purpose, please refer to Figures 1 to 17 , attached Fig.15 FIG. 1 is a schematic diagram of a mixed packaging structure for chips of different thicknesses in this embodiment. Fig.16 Another structural schematic diagram of a hybrid packaging structure for chips of different thicknesses in this embodiment; specifically, a hybrid packaging structure for chips of different thicknesses includes a first substrate layer 01, a plastic packaging layer 02, a first chip 1, a second chip 2 and a third chip 3, wherein the thickness of the first chip 1 is greater than that of the second chip 2, and the thickness of the third chip 3 is greater than that of the first chip 1;

[0220] The plastic sealing layer 02 is arranged on the upper part of the first substrate layer 01;

[0221] The first substrate layer 01 is provided with at least three chip semi-buried grooves, and the first chip 1, the second chip 2 and the third chip 3 are respectively arranged in the three chip semi-buried grooves;

[0222] The chip semi-buried groove for accommodating the first chip 1 and the chip semi-buried groove for accommodating the second chip 2 share a groove bottom, and the opening directions of the chip semi-buried groove for accommodating the first chip 1 and the chip semi-buried groove for accommodating the second chip 2 are in opposite directions.

[0223] The first chip 1 is disposed below the second chip 2 , and the upper portion of the first chip 1 and the bottom portion of the second chip 2 are disposed opposite to each other.

[0224] The bottom of the first chip 1 is provided with a conductive pad, the bottom of the third chip 3 is provided with a conductive pad, and the top of the second chip 2 is provided with a conductive hole, which is used to be electrically connected to the circuits in the plastic encapsulation layer 02 and the first substrate layer 01, and is also used to be electrically connected to the upper circuit of the third chip 3; the upper part of the third chip 3 is provided with a conductive hole, which is used to be electrically connected to the circuits in the plastic encapsulation layer 02 and the first substrate layer 01, and is also used to be electrically connected to the upper circuit of the second chip 2;

[0225] The thickness of the first substrate layer 01 is between 90% and 110% of the difference between the thicknesses of the first chip 1 and the second chip 2 , and the sum of the thicknesses of the first chip 1 and the second chip 2 is between 90% and 110% of the thickness of the third chip 3 .

[0226] The first substrate layer 01 can be a complete substrate or can be composed of two stacked substrates. When the first substrate layer 01 is a complete substrate, grooves can be made on both the upper and lower surfaces of the first substrate layer 01 to form chip semi-buried grooves for accommodating the first chip 1 and the second chip 2, and a chip semi-buried groove for accommodating the third chip 3 can be made on one side.

[0227] When the first substrate layer 01 is used as a substrate composed of two stacked substrates, grooves can be respectively made on the two substrates, and the two substrates are positioned and stacked before / after the grooves are made to form the first substrate layer 01 .

[0228] In some embodiments, the opening direction of the chip semi-buried groove accommodating the first chip 1 and the chip semi-buried groove accommodating the second chip 2 are in the same direction, and the opening direction of the chip semi-buried groove accommodating the first chip 1 faces the bottom direction of the chip semi-buried groove accommodating the second chip 2.

[0229] The first chip 1 is disposed below the second chip 2 , and the upper portion of the first chip 1 and the bottom portion of the second chip 2 are disposed opposite to each other.

[0230] The chip semi-buried groove accommodating the first chip 1 is located at the lower part of the chip semi-buried groove accommodating the second chip 2 .

[0231] The first chip 1 and the second chip 2 are electrically connected via a conductive pad located between the first chip 1 and the second chip 2. A large-area conductive pad is provided at the bottom of the first chip 1 and the third chip 3, so that the heat dissipation function of chips of different thicknesses in the packaging structure is enhanced. At the same time, the number of drilling holes is reduced, and the types of drilling holes are also reduced, thereby reducing the production of conductive holes between the first chip 1 and the second chip 2 and simplifying the production process.

[0232] Embodiment 5

[0233] To achieve the above purpose, please refer to Figures 1 to 17 , attached Fig.17 Schematic diagram of a hybrid packaging structure for chips of different thicknesses in this embodiment. Specifically, a hybrid packaging structure for chips of different thicknesses includes a first substrate layer 01, a plastic packaging layer 02, a first chip 1, a second chip 2, and a third chip 3. The thickness of the first chip 1 is greater than that of the second chip 2, and the thickness of the third chip 3 is greater than that of the first chip 1.

[0234] The plastic sealing layer 02 is arranged on the upper part of the first substrate layer 01;

[0235] The first substrate layer 01 is provided with at least two chip semi-buried grooves, and the first chip 1 and the third chip 3 are respectively arranged in the two chip semi-buried grooves;

[0236] The first chip 1 is disposed below the second chip 2 , and conductive pads are disposed on the top of the first chip 1 and the bottom of the second chip 2 , and the first chip 1 and the second chip 2 are electrically connected via the conductive pads.

[0237] The opening direction of the chip semi-buried groove accommodating the third chip 3 is opposite to the opening direction of the chip semi-buried groove accommodating the first chip 1 .

[0238] The bottom of the third chip 3 is provided with a conductive pad, and the top of the second chip 2 is provided with a conductive hole, which is used to be electrically connected to the circuits in the plastic encapsulation layer 02 and the first substrate layer 01, and is also used to be electrically connected to the upper circuit of the third chip 3; the upper part of the third chip 3 is provided with a conductive hole, which is used to be electrically connected to the circuits in the plastic encapsulation layer 02 and the first substrate layer 01, and is also used to be electrically connected to the upper circuit of the second chip 2;

[0239] The thickness of the first substrate layer 01 is between 90% and 110% of the thickness of the first chip 1 , and the sum of the thickness of the first chip 1 and the second chip 2 is between 90% and 110% of the thickness of the third chip 3 .

[0240] It includes a second substrate layer 03, which is arranged at the bottom of the first substrate layer 01, and the second substrate layer 03 is provided with conductive through holes for connecting with the first chip 1 and the third chip 3. The bottom of the second substrate layer 03 is provided with conductive pads, and the conductive through holes connected with the first chip 1 and the third chip 3 are electrically connected to the conductive pads.

[0241] In this embodiment, the packaging structure is used to place two chips of different thicknesses by setting two chip semi-embedded grooves with opening directions on the first substrate layer 01. At the same time, the second chip 2 is set on the thinner chip located in the chip semi-embedded groove. The first chip 1 and the second chip 2 are directly electrically connected through the conductive pad. The first chip 1 and the third chip 3 are electrically connected by pressing the second substrate layer 03 at the bottom of the first substrate layer 01 and drilling conductive holes in the second substrate layer 03. The number of holes drilled between the first chip 1 and the second chip 2 is reduced, and the types of holes drilled in the packaging structure are reduced, simplifying the manufacturing process.

[0242] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them. Under the concept of the present invention, the technical features in the above embodiments or different embodiments may also be combined, the steps may be implemented in any order, and there are many other changes in different aspects of the present invention as described above, which are not provided in detail for the sake of simplicity. Although the present invention has been described in detail with reference to the above embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the above embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A hybrid packaging structure of chips of different thicknesses, comprising a first substrate layer (01), a first chip (1) and a second chip (2), wherein the thickness of the first chip (1) is greater than the thickness of the second chip (2), and characterized in that: The first substrate layer (01) is provided with a first chip semi-buried groove (011), the first chip (1) is arranged in the first chip semi-buried groove (011), and the second chip (2) is arranged on the upper surface of the first substrate layer (01); the thickness of the first substrate layer (01) is between 90% and 110% of the difference in thickness between the first chip (1) and the second chip (2).

2. The mixed packaging structure of chips with different thicknesses as claimed in claim 1, characterized in that: It also includes a plastic encapsulation layer (02), wherein the plastic encapsulation layer (02) is provided with a first conductive hole (021), a second conductive hole (022) and a third conductive hole (023), and the first substrate layer (01) is provided with a fourth conductive hole (012) and a fifth conductive hole (013); The first conductive hole (021) is used to connect the upper and lower layers of the plastic packaging layer (02); The second conductive hole (022) connects the upper pad of the second chip (2) with the upper surface circuit of the plastic packaging layer (02); The third conductive hole (023) connects the upper pad of the first chip (1) with the upper surface circuit of the plastic packaging layer (02); The fourth conductive hole (012) connects the lower pad of the second chip (2) with the lower surface circuit of the first substrate layer (01); The fifth conductive hole (013) connects the lower surface circuit and the upper surface circuit of the first substrate layer (01).

3. The mixed packaging structure of chips with different thicknesses as claimed in claim 1, characterized in that: The first chip semi-buried groove (011) is arranged in an inverted trapezoidal shape, and the size of the upper opening of the first chip semi-buried groove (011) is larger than the size of the groove bottom of the first chip semi-buried groove (011); The size of the upper opening of the first chip semi-buried groove (011) is the sum of the size of the first chip (1) and the equipment accuracy; The size of the bottom of the groove (011) in which the first chip is half buried is the size of the first chip (1).

4. The mixed packaging structure of chips with different thicknesses as claimed in claim 1, characterized in that: The angle between the vertical line of the bottom of the first chip semi-buried groove (011) and the groove wall of the first chip semi-buried groove (011) is α; 0°<α≤45°; A plastic encapsulation material is provided between the first chip semi-buried groove (011) and the side wall of the first chip (1).

5. The mixed packaging structure of chips with different thicknesses as claimed in claim 2, characterized in that: The depth of the first conductive hole (021) is equal to the depth of the fourth conductive hole (012); The depth of the second conductive hole (022) is equal to the depth of the third conductive hole (023); The depth of the fourth conductive hole (012) is equal to the depth of the fifth conductive hole (013); The depth of the first conductive hole (021) is equal to the sum of the depth of the second conductive hole (022), the thickness of the second chip (2) and the thickness of the upper pad of the second chip (2).

6. The mixed packaging structure of chips with different thicknesses as claimed in claim 1, characterized in that: The lower surface circuit of the first chip semi-buried groove (011) is provided with a plurality of air-conducting through holes (0111), and the air-conducting through holes (0111) are evenly arranged on the outer periphery of the bottom of the first chip semi-buried groove (011), and one end of each air-conducting through hole (0111) close to the center of the first chip semi-buried groove (011) is located in the first chip semi-buried groove (011).

7. A mixed packaging structure of chips with different thicknesses, comprising any one of the mixed packaging structures of chips with different thicknesses as claimed in claims 1 to 4, characterized in that: It also includes a third chip (3) and a second substrate layer (03); The thickness of the third chip (3) is greater than the thickness of the first chip (1); The second substrate layer (03) is provided with a third chip semi-buried groove (031), the third chip (3) The second substrate layer (03) is arranged on the lower surface of the first substrate layer (01); The thickness of the second substrate layer (03) is between 90% and 110% of the difference in thickness between the first chip (1) and the third chip (3).

8. The mixed packaging structure of chips with different thicknesses as claimed in claim 7, characterized in that: The plastic encapsulation layer (02) is further provided with a sixth conductive hole (024), and the second substrate layer (03) is provided with a seventh conductive hole (032) and an eighth conductive hole (033); The sixth conductive hole (024) connects the upper pad of the third chip (3) with the upper surface circuit of the plastic packaging layer (02); The seventh conductive hole (032) is connected to the upper and lower layers of the second substrate layer (03); The eighth conductive hole (033) connects the lower pad of the first chip (1) with the lower surface circuit of the second substrate layer (03). The fifth conductive hole (013) is used to connect the lower surface circuit and the upper surface circuit of the first substrate layer (01).

9. The mixed packaging structure of chips with different thicknesses as claimed in claim 8, characterized in that: The depth of the fourth conductive hole (012) is equal to the depth of the seventh conductive hole (032); The depth of the sixth conductive hole (024) is equal to the depth of the third conductive hole (023); The depth of the eighth conductive hole (033) is equal to the depth of the seventh conductive hole (032); The depth of the first conductive hole (021) is equal to the sum of the depth of the second conductive hole (022), the thickness of the second chip (2) and the thickness of the upper pad of the second chip (2).

10. The mixed packaging structure of chips with different thicknesses as claimed in claim 7, characterized in that: The third chip semi-buried groove (031) is arranged in an inverted trapezoidal shape, and the size of the upper opening of the third chip semi-buried groove (031) is larger than the size of the groove bottom of the third chip semi-buried groove (031); The size of the upper opening of the third chip semi-buried groove (031) is the sum of the size of the third chip (3) and the equipment accuracy; The size of the bottom of the groove (031) in which the third chip is half buried is the size of the third chip (1).

11. The mixed packaging structure of chips with different thicknesses as claimed in claim 7, characterized in that: The lower surface circuit of the third chip semi-buried groove (031) is provided with a plurality of air-conducting through holes (0111), and the air-conducting through holes (0111) are evenly arranged on the outer periphery of the bottom of the third chip semi-buried groove (031), and one end of each air-conducting through hole (0111) close to the center of the third chip semi-buried groove (031) is located in the third chip semi-buried groove (031).

12. A mixed packaging method for chips of different thicknesses, characterized in that: The following steps are involved: S1: Selecting a first substrate layer (01), manufacturing circuits on the upper and lower surfaces of the first substrate layer (01), and manufacturing a fourth conductive hole (012) and a fifth conductive hole (013) between the layers of the first substrate layer (01); The thickness of the first substrate layer (01) is between 90% and 110% of the difference in thickness between the first chip (1) and the second chip (2), and the thickness of the first chip (1) is greater than the thickness of the second chip (2); the fourth conductive hole (012) is used to connect the lower pad of the second chip (2) to the lower surface circuit of the first substrate layer (01), and the fifth conductive hole (013) is used to connect the upper and lower surface circuits of the first substrate layer (01); S2: making a first chip semi-buried groove (011) on the upper surface of the first substrate layer (01) corresponding to the first chip mounting position; The depth of the first chip semi-buried groove (011) is the thickness of the first substrate layer (01); the angle between the vertical line of the groove bottom of the first chip semi-buried groove (011) and the groove wall of the first chip semi-buried groove (011) is α; 0°<α≤45°; The first chip semi-buried groove (011) is arranged in an inverted trapezoidal shape, and the size of the upper opening of the first chip semi-buried groove (011) is larger than the size of the groove bottom of the first chip semi-buried groove (011); The size of the upper opening of the first chip semi-buried groove (011) is the sum of the size of the first chip (1) and the equipment accuracy; The size of the bottom of the groove (011) in which the first chip is half buried is the size of the first chip (1); S3: completing solder printing, chip mounting and reflow soldering processing on the first chip (1) and the second chip (2) through a chip mounting reflow process, embedding the first chip (1) in the first chip semi-embedded groove (011), and mounting the second chip (2) on the upper surface of the first substrate layer (01); S4: Pressing plastic encapsulation materials onto the upper surfaces of the first substrate layer (01), the first chip (1) and the second chip (2) for plastic encapsulation, and baking the plastic encapsulation materials to solidify and form a plastic encapsulation layer (02); The gap between the first chip semi-buried groove (011) and the first chip (1) is filled with a plastic packaging material; S5: drilling holes in the plastic encapsulation layer (4) to form a first conductive hole (021), a second conductive hole (022) and a third conductive hole (023), and performing metallization, electroplating, patterning and etching processes on the plastic encapsulation layer (02) so that the upper and lower layer lines of the plastic encapsulation layer (02) are electrically interconnected with the first chip (1) and the second chip (2) respectively; Wherein, the first conducting hole (021) is used to connect the upper and lower circuits of the plastic encapsulation layer (02); The second conducting hole (022) is used to connect the upper pad of the second chip (2) with the upper surface circuit of the plastic packaging layer (02); The third conductive hole (023) is used to connect the upper pad of the first chip (1) with the upper surface circuit of the plastic packaging layer (02); The circuit on the upper surface of the plastic encapsulation layer (02) is exposed on the top of the plastic encapsulation layer (02), or the circuit on the upper surface of the plastic encapsulation layer (02) is buried inside the plastic encapsulation layer (02).

13. The mixed packaging method of chips with different thicknesses as claimed in claim 12, characterized in that: S1 and later also include: S101: a plurality of air-conducting through holes (0111) are formed on the lower surface of the semi-buried groove (011) of the first chip by a pattern etching process; The air-conducting through holes (0111) are evenly arranged on the periphery of the bottom of the first chip semi-buried groove (011), and one end of each air-conducting through hole (0111) close to the center of the first chip semi-buried groove (011) is located inside the first chip semi-buried groove (011); S4 and later also include: S401: Filling the gas conducting through-hole (0111) on the lower surface of the semi-buried groove (011) of the first chip through metallization and electroplating processes.

14. The mixed packaging method of chips with different thicknesses as claimed in claim 12, characterized in that: Also includes: S102: Selecting a second substrate layer (03), manufacturing circuits on the upper and lower surfaces of the second substrate layer (03), and manufacturing a seventh conductive hole (032) and an eighth conductive hole (033) between the layers of the second substrate layer (03); Wherein, the thickness of the second substrate layer (03) is between 90% and 110% of the difference between the thickness of the first chip (1) and the third chip (3); the thickness of the third chip (3) is greater than the thickness of the first chip (1); The seventh conductive hole (032) is connected to the upper and lower layers of the second substrate layer (03); The eighth conductive hole (033) connects the lower pad of the first chip (1) with the lower surface circuit of the second substrate layer (03); S201: making a third chip semi-buried groove (031) on the upper surface of the second substrate layer (03) and the first substrate (01) corresponding to the mounting position of the third chip (3); The depth of the third chip semi-buried groove (031) is the sum of the thickness of the first substrate layer (01), the second substrate layer (02), and the circuit between the first substrate layer (01) and the second substrate layer (02); the angle between the vertical line of the groove bottom of the third chip semi-buried groove (031) and the groove wall of the third chip semi-buried groove (031) is β; 0°<β≤45°; The third chip semi-buried groove (031) is arranged in an inverted trapezoidal shape, and the size of the upper opening of the third chip semi-buried groove (031) is larger than the size of the groove bottom of the third chip semi-buried groove (031); The size of the upper opening of the third chip semi-buried groove (031) is the sum of the size of the third chip (3) and the equipment accuracy; The size of the bottom of the groove (031) in which the third chip is half buried is the size of the third chip (3); S301: completing solder printing, chip mounting and reflow soldering processing on the third chip (3) through a chip reflow process, and embedding the third chip (3) in the third chip semi-embedded groove (031); S402: Pressing a plastic sealing material onto the upper surface of the third chip (3) for plastic sealing, and baking the plastic sealing material to solidify and form a plastic sealing layer (02); The gap between the third chip semi-buried groove (031) and the third chip (3) is filled with a plastic packaging material; S501: drilling a sixth conductive hole (024) in the plastic encapsulation layer (02), and performing metallization, electroplating, patterning and etching processes on the plastic encapsulation layer (02) so that upper and lower layer lines of the plastic encapsulation layer (02) are respectively electrically interconnected with the third chip (3); The sixth conductive hole (024) is used to connect the upper pad of the third chip (3) with the upper surface circuit of the plastic packaging layer (02).

15. The mixed packaging method of chips with different thicknesses as claimed in claim 14, characterized in that: Also includes: S102 and later also include: S103: a plurality of air-conducting through holes (0111) are produced on the lower surface of the semi-buried groove (031) of the third chip by means of a pattern etching process; The air-conducting through holes (0111) are evenly arranged on the outer periphery of the bottom of the third chip semi-buried groove (031), and one end of each air-conducting through hole (0111) close to the center of the third chip semi-buried groove (031) is located inside the third chip semi-buried groove (031); S4 and later also include: S403: Filling the gas conducting through-hole (0111) on the lower surface of the semi-buried groove (031) of the third chip through metallization and electroplating processes.

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