Packaging method, packaging structure and electronic equipment

Abstract

The embodiment of the invention provides a packaging method, a packaging structure and electronic equipment, and the packaging method comprises the steps: providing a plurality of to-be-stacked interposer structures, and carrying out the preprocessing of the mutually stacked interposer structures, so as to at least form matched bonding structures in the mutually stacked interposer structures; carrying out hybrid bonding processing on the mutually stacked interposer structures by using a bonding structure matched with the mutually stacked interposer structures to form a 3D interposer structure in which the plurality of interposer structures are stacked; wherein the total capacitance value of the deep trench capacitors of the 3D interposer structure is the sum of the capacitance values of the deep trench capacitors of the plurality of interposer structures; a chip module and a package substrate are connected by using the 3D interposer structure. According to the packaging method provided by the embodiment of the invention, the deep trench capacitance value of the 3D interposer structure can be improved, and the electrical performance is improved, so that the operation performance of the chip is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor packaging technology, and specifically to a packaging method, a packaging structure, and an electronic device. Background Art

[0002] Chip packaging is a key step in the semiconductor manufacturing process. It not only protects the chip from physical damage, but also provides electrical connections to ensure communication between the chip and external circuits.

[0003] However, the chip operating performance of the existing packaging structure still needs to be improved. How to provide a packaging structure to improve the chip operating performance has become an urgent problem to be solved by those skilled in the art. Summary of the invention

[0004] In view of this, the embodiments of the present application provide a packaging method, a packaging structure and an electronic device, which can improve the total capacitance of the deep trench capacitor of the intermediate layer structure, improve the electrical performance, and thus improve the operating performance of the chip.

[0005] To achieve the above objectives, the embodiments of the present application provide the following technical solutions.

[0006] In a first aspect, an embodiment of the present application provides a packaging method, comprising:

[0007] Providing a plurality of interposer structures to be stacked, and pre-processing the interposer structures stacked on each other respectively, so as to form matching bonding structures at least in the interposer structures stacked on each other;

[0008] Using a bonding structure that matches the stacked interposer structures, the stacked interposer structures are subjected to a mixed bonding process to form a 3D interposer structure in which the multiple interposer structures are stacked; wherein the total capacitance of the deep trench capacitor of the 3D interposer structure is the sum of the capacitances of the deep trench capacitors of the multiple interposer structures;

[0009] The 3D interposer structure is used to connect the chip module and the packaging substrate.

[0010] Optionally, the pre-processing the mutually stacked interposer structures respectively to form matching bonding structures at least in the mutually stacked interposer structures includes:

[0011] For the lower interposer structure in the interposer structures stacked on each other, through holes, through hole connection points and bonding pads are formed; for the upper interposer structure in the interposer structures stacked on each other, a bonding pad matching the bonding pad of the lower interposer structure is formed, and the bonding pad is the bonding structure.

[0012] Optionally, the method of performing hybrid bonding processing on the stacked interlayer structures by using a bonding structure matching the stacked interlayer structures to form a 3D interlayer structure in which the plurality of interlayer structures are stacked includes:

[0013] Bonding the stacked interposer structures to each other via matching bonding pads;

[0014] After the bonding, an annealing process is performed to diffuse the material of the bonding pad to form an electrical connection between the interposer structures stacked on each other; the material of the bonding pad is a conductive material.

[0015] Optionally, the step of connecting the chip module and the packaging substrate by using the 3D interposer structure includes:

[0016] Mounting the chip module on the top surface of the 3D interposer structure;

[0017] The 3D interposer structure with the chip module mounted thereon is mounted on the top surface of the package substrate.

[0018] Optionally, after forming the 3D interposer structure and before mounting the chip module on the top surface of the 3D interposer structure, the method further includes:

[0019] forming a first bump structure on a top surface of the 3D interposer structure, wherein the first bump structure is used to connect the chip module;

[0020] And, a second bump structure is formed on the bottom surface of the 3D interposer structure, and the second bump structure is used for connecting the packaging substrate.

[0021] Optionally, the plurality of intermediate layer structures include any one of the following:

[0022] multiple interposer wafers;

[0023] Part of the interposer wafer and part of the interposer chip, wherein the interposer structure stacked on each other includes: interposer wafers stacked on each other, and / or, interposer wafers and interposer chips stacked on each other, and / or, interposer chips stacked on each other;

[0024] Multiple interposer chips.

[0025] Optionally, the interposer structure includes an interposer wafer, the interposer structure is an interposer wafer, and the 3D interposer structure is a 3D interposer wafer in which a plurality of interposer wafers are stacked; the method further includes:

[0026] After the chip module and the packaging substrate are connected by using the 3D interposer wafer, the 3D interposer wafer connecting the chip module and the packaging substrate is cut into a plurality of packaging units.

[0027] In a second aspect, an embodiment of the present application provides a packaging structure, including:

[0028] Package substrate;

[0029] Chip module;

[0030] A 3D interposer structure connecting the packaging substrate and the chip module, the 3D interposer structure comprising a plurality of stacked interposer structures, wherein the stacked interposer structures are connected via matching bonding structures; wherein the total capacitance of the deep trench capacitors of the 3D interposer structure is the sum of the capacitances of the deep trench capacitors of the plurality of interposer structures.

[0031] In a third aspect, an embodiment of the present application provides an electronic device, wherein the electronic device includes the packaging structure described above.

[0032] The packaging method provided in the embodiment of the present application first pre-processes the stacked intermediary layer structures in the multiple intermediary layer structures to be stacked, so that a matching bonding structure can be formed in the stacked intermediary layer structures; then, the stacked intermediary layer structures are subjected to mixed bonding processing by using the matching bonding structure of the stacked intermediary layer structures to form a 3D intermediary layer structure in which multiple intermediary layer structures are stacked, and finally, the 3D intermediary layer structure is used to connect the chip module and the packaging substrate to form a packaging structure. In other words, the embodiment of the present application uses a 3D intermediary layer structure to connect the chip module and the packaging substrate, and the 3D intermediary layer structure is formed by bonding and connecting multiple stacked intermediary layer structures together using a mixed bonding process, so that the total capacitance of the deep trench capacitor of the 3D intermediary layer structure is the sum of the capacitance of the deep trench capacitors of the multiple intermediary layer structures, so the packaging structure formed by the packaging method of the embodiment of the present application can improve the deep trench capacitance value of the 3D intermediary layer structure, improve the electrical performance, and thus improve the operating performance of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0034] Figure 1 It is a schematic diagram of the process of the packaging method provided in the embodiment of the present application;

[0035] Figures 2 to 6 It is a structural schematic diagram corresponding to each step in the packaging method provided in the embodiment of the present application. DETAILED DESCRIPTION

[0036] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0037] In the field of modern electronic manufacturing, chip packaging is a crucial link. Chip packaging is to encapsulate semiconductor bare crystals (dies), that is, integrated circuits manufactured on silicon wafers, in a protective shell to facilitate circuit connection, heat dissipation, and physical installation in electronic devices. Chip packaging technology not only protects integrated circuits from physical damage and environmental influences, but also provides an interface for electrical connection to external circuits.

[0038] The packaging technology used by the chip can be 2D packaging technology, 2.5D packaging technology, and 3D packaging technology, etc. Among them, 2D packaging technology is a packaging technology that places multiple core particles on a single plane and connects multiple core particles through wires; 2.5D packaging technology is a packaging technology that places multiple core particles on a silicon interposer and connects multiple core particles through a silicon interposer; 3D packaging technology is a packaging technology that stacks multiple core particles in a vertical direction and connects multiple core particles through vertical interconnection technology.

[0039] In the 2.5D packaging structure, embedded deep trench capacitor (eDTC) is an important structure in the interposer. Specifically, a capacitor can be formed in the trench by etching a deep trench on the interposer and forming an oxide layer and a conductive layer on the sidewall of the trench. This capacitor structure can provide additional capacitance, improve the power integrity (PI) and signal integrity of the interposer, and improve the electrical performance of the interposer. Therefore, the interposer, as a connecting layer between the chip and the packaging substrate, can more effectively transmit the power of the electrical signal, thereby improving the performance and reliability of the entire chip packaging structure.

[0040] As the demand for chip computing power continues to grow, more and more products are using 2.5D packaging structures, and the requirements for the capacitance of the interposer in the packaging structure are also increasing. However, the current capacitance of the eDTC of the interposer may not be able to meet the computing power requirements of the chip, thus affecting the chip's operating performance.

[0041] In view of this, an embodiment of the present application provides a packaging method that can increase the total capacitance of the deep trench capacitor of the 3D interposer structure, improve the electrical performance, and thus improve the operating performance of the chip.

[0042] Figure 1 is a flow chart of the packaging method provided in the embodiment of the present application, Figures 2 to 6 is a schematic diagram of the packaging structure corresponding to each step in the packaging method provided in the embodiment of the present application, referring to Figure 1 , the packaging method may include:

[0043] Step S101: providing a plurality of interposer structures to be stacked, and pre-processing the interposer structures stacked on each other respectively, so as to at least form matching bonding structures in the interposer structures stacked on each other.

[0044] Since the deep trench capacitance value generated by a single interposer is limited, the embodiment of the present application introduces the concept of a 3D interposer structure, which is used to connect the chip module and the packaging substrate. The 3D interposer structure is formed by stacking and bonding multiple interposer structures, thereby improving the deep trench capacitance value of the formed 3D interposer structure.

[0045] Specifically, before stacking multiple interposer structures, the stacked interposer structures need to be preprocessed to at least form matching bonding structures in the stacked interposer structures for subsequent bonding connection between the multiple interposer structures.

[0046] In an optional implementation, the step of pre-processing the mutually stacked interposer structures respectively to form matching bonding structures at least in the mutually stacked interposer structures may include:

[0047] For the lower interposer structure in the interposer structures stacked on each other, through holes, through hole connection points and bonding pads are formed; for the upper interposer structure in the interposer structures stacked on each other, a bonding pad matching the bonding pad of the lower interposer structure is formed, and the bonding pad is the bonding structure.

[0048] In an alternative embodiment, referring to Figure 2 , taking the stacking of two interposer structures as an example, for the lower interposer structure 201 in the interposer structures stacked on each other, through holes, through hole connection points and bonding pads are formed; for the upper interposer structure 202 in the interposer structures stacked on each other, a bonding pad matching the bonding pad of the lower interposer structure 201 is formed, and the bonding pad is the bonding structure.

[0049] In the embodiment of the present application, the lower interposer structure needs to form a through-hole structure TSV (Through Silicon Via), which can transfer the signal and power of the lower interposer structure to the surface of the upper interposer structure for electrical connection and communication; correspondingly, the lower interposer structure also needs to form a through-hole connection point to receive the signal and power output by the through-hole structure;

[0050] Bond pads can be used to achieve bonding, electrical connection and signal transmission. Matching bonding pads are formed in the upper interposer structure and the lower interposer structure, which can provide a basis for the stacking bonding of the interposer structures stacked on each other, wherein the upper interposer structure and the lower interposer structure can be directly bonded through the bonding pads to form an electrical connection to achieve signal transmission.

[0051] It should be noted that the present application does not limit the number of the multiple interposer structures, and the embodiments of the present application are merely described by taking any two interposer structures among the multiple interposer structures that need to be stacked on each other as an example.

[0052] Further, in an optional implementation, the plurality of intermediate layer structures may include any of the following:

[0053] Multiple interposer wafers; wherein, the interposer wafer refers to a complete silicon-based, glass-based or organic-based wafer, which is used as an interposer between chips or between chips and substrates for electrical signal transmission and thermal management, that is, the interposer wafer is a whole wafer that has not yet been cut into separate interposers. At this time, multiple interposers in the form of wafers (i.e., multiple interposer wafers) can be stacked, that is, the interposer structures stacked on each other are interposer wafers stacked on each other;

[0054] Part of the interposer wafer and part of the interposer chip; wherein the interposer chip is an interposer unit cut from the interposer wafer, and is used to be integrated with the logic chip, memory chip, etc. in the package; in an embodiment of the present application, the embodiment of the present application supports that part of the interposer structures in the stacked multiple interposer structures are interposer wafers, and part of the interposer structures are interposer chips; at this time, the interposer structures stacked on each other may include: interposer wafers stacked on each other, and / or, interposer wafers and interposer chips stacked on each other, and / or, interposer chips stacked on each other;

[0055] Multiple interposer chips, at this time, multiple interposers in the form of unit chips (ie, multiple interposer chips) can be stacked, that is, the interposer structures stacked on each other are interposer chips stacked on each other.

[0056] In an optional implementation, when stacked interposer wafers are stacked, they can be mounted using a W2W (wafer to wafer) process; when stacked interposer wafers and interposer chips are stacked, they can be mounted using a C2W (Chip to wafer) process.

[0057] Step S102: performing a mixed bonding process on the stacked interposer structures using a bonding structure that matches the stacked interposer structures to form a 3D interposer structure in which the multiple interposer structures are stacked; wherein the total capacitance of the deep trench capacitors of the 3D interposer structure is the sum of the capacitances of the deep trench capacitors of the multiple interposer structures.

[0058] After completing the preprocessing of the stacked interposer structures, the stacked interposer structures may be subjected to hybrid bonding processing using a bonding structure matching the stacked interposer structures to form a 3D interposer structure in which the multiple interposer structures are stacked.

[0059] Hybrid bonding is a method that combines physical and chemical bonding to form bonds between different types of bonding materials. This bonding method can overcome the limitations of a single bonding method, while greatly reducing the bonding spacing and increasing the bonding density.

[0060] Therefore, in the embodiment of the present application, multiple interposer structures are bonded together through a hybrid bonding process, which can reduce the bonding spacing and increase the bonding density while forming a 3D interposer structure in which multiple interposer structures are stacked.

[0061] Reference Figure 3 The lower interposer structure 201 and the upper interposer structure 202 can be bonded together by a hybrid bonding process using matching bonding structures to form a 3D interposer structure 303 in which two interposer structures are stacked.

[0062] In an optional implementation, the step of performing a hybrid bonding process on the stacked intermediary layer structures by utilizing a bonding structure that matches the stacked intermediary layer structures to form a 3D intermediary layer structure in which the multiple intermediary layer structures are stacked may include: bonding the stacked intermediary layer structures via matching bonding pads; after the bonding, performing an annealing process to diffuse the material of the bonding pads to form an electrical connection between the stacked intermediary layer structures; the material of the bonding pads is a conductive material.

[0063] In an alternative embodiment, referring to Figure 4 , Figure 4It is a cross-sectional view of the 3D interposer structure; specifically, the interposer structures stacked on each other (e.g., the lower interposer structure 201 and the upper interposer structure 202) are bonded together through matching bonding structures (e.g., bonding pads); after the bonding, an annealing process is performed to diffuse the material of the bonding structure (e.g., bonding pad) 400 in the interposer structures stacked on each other to form an electrical connection between the interposer structures stacked on each other; the material of the bonding structure (e.g., bonding pad) can be a conductive material, including but not limited to copper.

[0064] In the embodiment of the present application, the total capacitance of the deep trench capacitor of the 3D interposer structure is: the sum of the capacitance of the deep trench capacitors of each of the multiple interposer structures. For example, in the embodiment of the present application, two interposer structures are stacked as an example, and the deep trench capacitance of the formed 3D interposer structure is: twice the deep trench capacitance of one interposer structure; therefore, the 3D interposer structure formed by the above steps can greatly improve the deep trench capacitance, thereby improving the electrical performance and the operating performance of the chip.

[0065] Step S103: using the 3D interposer structure to connect the chip module and the packaging substrate.

[0066] After the 3D interposer structure is formed, the 3D interposer structure may be used to connect a chip module and a packaging substrate to perform chip packaging.

[0067] In an optional implementation, the step of connecting the chip module and the packaging substrate using the 3D interposer structure may include: mounting the chip module to the top surface of the 3D interposer structure; and mounting the 3D interposer structure with the chip module mounted to the top surface of the packaging substrate.

[0068] Furthermore, after forming the 3D interposer structure, before mounting the chip module on the top surface of the 3D interposer structure, it is necessary to first form a bump structure for connecting the chip module and the packaging substrate on the top and bottom surfaces of the interposer.

[0069] Specifically, a first bump structure is formed on the top surface of the 3D interposer structure, and the first bump structure is used to connect the chip module; and a second bump structure is formed on the bottom surface of the 3D interposer structure, and the second bump structure is used to connect the packaging substrate.

[0070] Among them, the first bump structure can be a micro bump structure (ubump), which is a tiny metal bump used to achieve electrical interconnection between the chip and the 3D interposer structure; the second bump structure can be a controlled collapse chip connection bump (C4 bump), which is a large metal bump used for interconnection between the chip and the packaging substrate, and can provide good electrical and thermal performance.

[0071] In the embodiment of the present application, in the process of forming the micro-bump structure, BVR (Bump-to-Via Redistribution) technology can be used. BVR is a redistribution layer technology that allows the micro-bump structure to be redistributed on the top surface of the 3D interposer structure so as to be aligned with the I / O (input / output) pads of the subsequently connected chip. This can improve the density and flexibility of the interconnection with the chip.

[0072] Further, taking the interposer structure as an interposer wafer as an example, after forming the bump structure, the C2W process can be used to mount the chip module to the top surface of the 3D interposer structure, referring to Figure 5 , Figure 5 3D interposer structure 303 is a schematic diagram of the top surface and chip module structure of the 3D interposer structure. The top surface of the 3D interposer structure 303 is mounted with multiple chip modules 500. In an optional implementation, a chip module may include at least one SOC (System on Chip) chip and multiple HBM (High Bandwidth Memory) chips. Figure 5 As shown, a chip module 500 includes a SOC chip 501 and four HBM chips 502. The chip module composed of a SOC chip and an HBM chip can significantly improve memory bandwidth, reduce power consumption, and further improve the operating performance of the chip.

[0073] In other embodiments, the chip module connected by the 3D interposer structure may also be a single chip.

[0074] Further, Figure 6 is an overall schematic diagram of the packaging structure provided in the embodiment of the present application, referring to Figure 6 , wherein the 3D interposer structure 303 is connected to the chip module 500 through the first bump structure 601, and the chip module 500 includes at least one SOC chip 501 and multiple HBM chips 502; after completing the mounting of the 3D interposer structure and the chip module, a flip chip bonding (Flip chip attach, AB2) process can be used to mount the 3D interposer structure 303 with the chip module 500 mounted on the top surface of the packaging substrate 603 through the second bump structure 602 to form the packaging structure.

[0075] It should be noted that in an embodiment of the present application, if the interposer structure includes an interposer wafer, after using the 3D interposer wafer to connect the chip module and the packaging substrate, the 3D interposer wafer connecting the chip module and the packaging substrate needs to be cut into multiple packaging units to form a final chip packaging structure.

[0076] It can be seen that the packaging method provided in the embodiment of the present application first pre-processes the intermediary layer structures stacked on each other among the multiple intermediary layer structures to be stacked, so that a matching bonding structure can be formed in the intermediary layer structures stacked on each other; then, the intermediary layer structures stacked on each other are subjected to mixed bonding processing by using the matching bonding structure of the intermediary layer structures stacked on each other, so as to form a 3D intermediary layer structure in which multiple intermediary layer structures are stacked on each other, and finally, the chip module and the packaging substrate are connected by using the 3D intermediary layer structure to form a packaging structure. In other words, the embodiment of the present application adopts a 3D intermediary layer structure to connect the chip module and the packaging substrate, and the 3D intermediary layer structure is formed by bonding and connecting multiple intermediary layer structures stacked on each other by using a mixed bonding process, so that the total capacitance of the deep trench capacitor of the 3D intermediary layer structure is the sum of the capacitance of the deep trench capacitors of the multiple intermediary layer structures, so the packaging structure formed by the packaging method of the embodiment of the present application can improve the deep trench capacitance value of the 3D intermediary layer structure, improve the electrical performance, and thus improve the operating performance of the chip.

[0077] Accordingly, continue to refer to Figure 6 , an embodiment of the present application also provides a packaging structure formed by using the aforementioned packaging method.

[0078] The packaging structure includes: a packaging substrate 603; a chip module 500; a 3D interposer structure 303 connecting the packaging substrate 603 and the chip module, the 3D interposer structure including a plurality of stacked interposer structures, wherein the stacked interposer structures are connected via a matching bonding structure 400; wherein the total capacitance of the deep trench capacitor of the 3D interposer structure is the sum of the capacitances of the deep trench capacitors of the plurality of interposer structures.

[0079] In an optional implementation, the packaging structure also includes: a first bump structure 601 connecting the chip module 500 and the 3D interposer structure 303; a second bump structure 602 connecting the packaging substrate 603 and the 3D interposer structure 303 on which the chip module is mounted; and a solder ball 604 located on the bottom surface of the packaging substrate 603.

[0080] The packaging structure can be formed by the packaging method described in the aforementioned embodiment. For the specific description of the packaging structure described in the embodiment of the present application, reference can be made to the corresponding description in the aforementioned embodiment, which will not be repeated here.

[0081] It can be seen that the packaging structure provided in the embodiment of the present application may include: a 3D interposer structure connecting the packaging substrate and the chip module, wherein the 3D interposer structure is formed by connecting multiple interposer structures through matching bonding structures; that is, the embodiment of the present application adopts a 3D interposer structure to connect the chip and the packaging substrate, and the 3D interposer structure is formed by bonding multiple stacked interposer structures together using a hybrid bonding process, which makes the total capacitance of the deep trench capacitor of the 3D interposer structure the sum of the capacitances of the deep trench capacitors of the multiple interposer structures. Therefore, the packaging structure formed by the packaging method of the embodiment of the present application can improve the deep trench capacitance value of the 3D interposer structure, improve the electrical performance, and thus improve the operating performance of the chip.

[0082] An embodiment of the present application further provides an electronic device, such as a terminal device or a server device, wherein the electronic device includes the packaging structure described in the aforementioned embodiment.

[0083] The above describes multiple implementation schemes provided by the embodiments of the present application. The various optional methods introduced in each implementation scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible implementation schemes, which can all be considered as implementation schemes disclosed and open in the embodiments of the present application.

[0084] Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined by the claims.

Claims

1. A packaging method, characterized in that: include: Providing a plurality of interposer structures to be stacked, and pre-processing the interposer structures stacked on each other respectively, so as to form matching bonding structures at least in the interposer structures stacked on each other; Using a bonding structure that matches the stacked interposer structures, the stacked interposer structures are subjected to a mixed bonding process to form a 3D interposer structure in which the multiple interposer structures are stacked; wherein the total capacitance of the deep trench capacitor of the 3D interposer structure is the sum of the capacitances of the deep trench capacitors of the multiple interposer structures; The 3D interposer structure is used to connect the chip module and the packaging substrate.

2. The packaging method according to claim 1, characterized in that: The pre-processing of the mutually stacked interposer structures respectively to at least form matching bonding structures in the mutually stacked interposer structures includes: For the lower interposer structure in the interposer structures stacked on each other, through holes, through hole connection points and bonding pads are formed; for the upper interposer structure in the interposer structures stacked on each other, a bonding pad matching the bonding pad of the lower interposer structure is formed, and the bonding pad is the bonding structure.

3. The packaging method according to claim 2, characterized in that: The method of performing hybrid bonding processing on the stacked interlayer structures by using a bonding structure matching the stacked interlayer structures to form a 3D interlayer structure in which the plurality of interlayer structures are stacked comprises: Bonding the interposer structures stacked on each other via matching bonding pads; After the bonding, an annealing process is performed to diffuse the material of the bonding pad to form an electrical connection between the interposer structures stacked on each other; the material of the bonding pad is a conductive material.

4. The packaging method according to claim 1, characterized in that: The method of connecting the chip module and the packaging substrate by using the 3D interposer structure comprises: Mounting the chip module on the top surface of the 3D interposer structure; The 3D interposer structure with the chip module mounted thereon is mounted on the top surface of the package substrate.

5. The packaging method according to claim 4, characterized in that: After forming the 3D interposer structure and before attaching the chip module to the top surface of the 3D interposer structure, the method further includes: forming a first bump structure on a top surface of the 3D interposer structure, wherein the first bump structure is used to connect the chip module; And, a second bump structure is formed on the bottom surface of the 3D interposer structure, and the second bump structure is used for connecting the packaging substrate.

6. The packaging method according to any one of claims 1 to 5, characterized in that: The plurality of intermediate layer structures include any of the following: multiple interposer wafers; Part of the interposer wafer and part of the interposer chip, wherein the interposer structure stacked on each other includes: interposer wafers stacked on each other, and / or, interposer wafers and interposer chips stacked on each other, and / or, interposer chips stacked on each other; Multiple interposer chips.

7. The packaging method according to claim 6, characterized in that: The interposer structure is an interposer wafer, and the 3D interposer structure is a 3D interposer wafer in which a plurality of interposer wafers are stacked. The method further comprises: After the chip module and the packaging substrate are connected by using the 3D interposer wafer, the 3D interposer wafer connecting the chip module and the packaging substrate is cut into a plurality of packaging units.

8. A packaging structure, characterized in that: include: Package substrate; Chip module; A 3D interposer structure connecting the packaging substrate and the chip module, the 3D interposer structure comprising a plurality of stacked interposer structures, wherein the stacked interposer structures are connected via matching bonding structures; wherein the total capacitance of the deep trench capacitors of the 3D interposer structure is the sum of the capacitances of the deep trench capacitors of the plurality of interposer structures.

9. The packaging structure according to claim 8, characterized in that: Also includes: A first bump structure connecting the chip module and the 3D interposer structure; A second bump structure connecting the packaging substrate and a 3D interposer structure on which a chip module is mounted; and solder balls located on the bottom surface of the packaging substrate.

10. An electronic device, characterized in that: Comprising a packaging structure as described in any one of claims 8-9.

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