Data clock recovery device and method based on fractional frequency division

Abstract

The present invention relates to the technical field of duplex communication, and in particular to a data clock recovery device and method based on fractional frequency division, the device comprising a phase detector, a digital filter, a sigma-delta modulator and a frequency divider, the output end of the phase detector is connected to the input end of the digital filter, the output end of the digital filter is connected to the input end of the sigma-delta modulator, the output end of the sigma-delta modulator is connected to the input end of the frequency divider, the input end of the frequency divider is simultaneously connected to a local high-speed clock signal, the output end of the frequency divider is connected to the input end of the phase detector, and the input end of the phase detector is simultaneously connected to a low-speed input signal. The present invention is based on a digital structure, the circuit is simple, and the complexity of clock recovery of a vehicle-mounted display serdes can be reduced, thereby bringing advantages such as chip power consumption and area.

Description

Technical Field

[0001] The present invention relates to the technical field of duplex communication, and in particular to a data clock recovery device and method based on fractional frequency division. Background Art

[0002] At present, the demand for high-speed data transmission using coaxial cables in the automotive field is increasing rapidly. In order to save cable costs, duplex communication is generally adopted, that is, there are both uplink and downlink signals on the cable. Usually, the uplink signal rate is lower and the downlink signal rate is higher. Figure 1 As shown in the figure, since the cable only transmits data but not clock signals, both the downstream high-speed signal and the upstream low-speed signal need CDR (clock data recovery). The high-speed signal CDR generally adopts a PI (phase interpolator) structure, and the traditional low-speed signal is also based on the PI structure, and its implementation circuit is complex.

[0003] The CDR function is mainly to extract clock information from the input signal. Generally, it is necessary to adjust the phase of the local clock to synchronize the input signal. The phase difference between the local clock and the input signal is 0 after feedback adjustment. Figure 2 As shown in the figure, in the traditional PI (phase interpolator)-based solution, the local high-speed clock phase is adjusted by controlling the phase interpolator. The phase interpolator is an analog circuit with a complex circuit structure. For low-speed input signals, the local high-speed clock also needs to be divided to obtain the recovered clock. The frequency and phase of the recovered clock are the same as the input signal. Summary of the invention

[0004] In view of this, the present invention provides a data clock recovery device and method based on fractional frequency division, which can greatly reduce the complexity of the circuit.

[0005] In order to achieve the aforementioned object, the present invention provides the following technical solutions: A data clock recovery device based on fractional frequency division comprises a phase detector, a digital filter, a sigma-delta modulator and a frequency divider, wherein the output end of the phase detector is connected to the input end of the digital filter, the output end of the digital filter is connected to the input end of the sigma-delta modulator, the output end of the sigma-delta modulator is connected to the input end of the frequency divider, the input end of the frequency divider is simultaneously connected to a local high-speed clock signal, the output end of the frequency divider is connected to the input end of the phase detector, and the input end of the phase detector is simultaneously connected to a low-speed input signal.

[0006] In the above scheme, a sigma-delta modulator is used in combination with a frequency divider to replace the traditional phase interpolator. The sigma-delta modulator is a digital circuit with a much simpler circuit structure. At this time, the filter can also be implemented using a digital circuit. Therefore, the structure of the overall device is simpler than the traditional scheme, greatly reducing the complexity of the circuit.

[0007] In a further optimized scheme, the phase detector adopts a bang bang nonlinear phase detector, including four triggers, three XOR gates and two AND gates. The input low-speed signal and the recovered clock output by the divider are input into the trigger, and then after being processed by the XOR gate and the AND gate, the PE signal and the PL signal with values ​​of 0 or 1 are output.

[0008] In the above scheme, the bang-bang nonlinear phase detector is a fully digital circuit, and the output is a digital signal, which is convenient for subsequent digital circuit integration. The use of this phase detector does not require complex analog circuits, has a simple structure, low power consumption, and occupies a small area. In addition, this structure can effectively suppress noise and improve device stability by binarizing the phase.

[0009] In a further optimized solution, the digital filter adopts a first-order filter. The first-order filter adopted in this solution has a simpler structure than the second-order filter, and the first-order filter can also ensure stable and reliable performance in this solution.

[0010] The digital filter includes three adders and two multipliers. The PE signal and the PL signal are subtracted by an adder to obtain a PD value. The PD value is multiplied by an integral path gain by a multiplier and the result delayed by one beat is accumulated by another adder to obtain the accumulated result. The PD value is multiplied by another multiplier and the proportional path gain and the result is added by another adder to output the control quantity sdm_ctrl.

[0011] The filter in the traditional scheme is a second-order filter, such as Figure 2 In the structure shown, the second-order filter is more complex than the first-order filter of this structure. The filter in this scheme only needs three adders and two multipliers. The multipliers can be implemented by binary left shift. The structure is simple, the hardware resources are small, and the power consumption is low. In terms of performance, this structure is first-order, with high stability and is not prone to oscillation.

[0012] In a further optimized solution, the sigma-delta modulator is a first-order SDM modulator. In this solution, a first-order SDM modulator is used to reduce jitter and ensure performance.

[0013] The first-order SDM modulator includes three adders. The control quantity sdm_ctrl is first added to 2^16 through an adder to become a positive number to obtain an accumulated value. The lower 16 bits of the accumulated value are delayed for one beat and then accumulated with the accumulated value through another adder. The high bits perform int operation and then pass through another device to subtract 1 and output the fractional frequency division value f.

[0014] The general SDM input is a positive number that cannot meet the requirements of this solution. The modulator structure in the above solution makes improvements and innovations to the general first-order SDM, so that the input can be negative, and the function is more advanced. This structure uses 16-bit SDM, with an accuracy of up to 1 / 2^16 and high control accuracy. Moreover, this structure only requires 3 adders to implement. Compared with higher-order SDM, the complexity is much reduced, the delay is reduced, and the power consumption and area are smaller. And from the perspective of CDR performance indicators, this structure has the best jitter indicator.

[0015] In a further optimized solution, an automatic gain control module is also included. The automatic gain control module interacts with the digital filter for data and is used to dynamically adjust the gain of the digital filter to accelerate the convergence speed.

[0016] In the above scheme, by dynamically adjusting the gain of the digital filter, for example, if the digital filter is not locked, a larger gain value is used to achieve fast locking, and if it is already locked, a smaller gain value is used to reduce the bandwidth, reduce noise, and thus reduce the jitter after convergence. Therefore, the above scheme can not only make the CDR converge and lock quickly, but also make the jitter after convergence small. And it adopts automatic control and is easy to operate.

[0017] A data clock recovery method based on fractional frequency division, wherein a phase detector outputs phase difference information according to the difference between the recovered clock and the input signal phase; a digital filter outputs a control quantity sdm_ctrl according to the phase difference information; a sigma-delta modulator outputs a fractional frequency division value f according to the control quantity sdm_ctrl; a frequency divider has a frequency division coefficient of an integer N, and the frequency divider divides the input local high-speed clock signal by N+f times and then outputs the recovered clock.

[0018] In a further optimized scheme, in the process of the digital filter outputting the control amount sdm_ctrl according to the phase difference information, it is detected whether the current data clock recovery has been locked. If not locked, the digital filter is adjusted to use a first gain value; if locked, the digital filter is adjusted to use a second gain value, and the first gain value is greater than the second gain value.

[0019] Compared with the prior art, the present invention is based on a digital structure and has a simple circuit. Compared with the PI method, the circuit complexity is greatly reduced, and the complexity of the clock recovery of the vehicle display serdes can be reduced, thereby bringing advantages such as chip power consumption and area. The present invention is particularly suitable for scenarios where the rate difference between high-speed signals and low-speed signals is large. The low-speed clock data recovery utilizes the existing high-speed clock and fractional frequency division, and the clock jitter is completely acceptable. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The disclosure of the present invention will become more apparent with reference to the accompanying drawings. It should be understood that these drawings are only for illustrative purposes and are not intended to limit the scope of protection of the present invention. In the drawings: Figure 1 A schematic diagram of duplex communication.

[0021] Figure 2 It is a structural diagram of a data clock recovery device with a traditional PI structure.

[0022] Figure 3 Schematic diagram of the structure of the data clock recovery device in embodiment 1 of the present invention.

[0023] Figure 4 Schematic diagram of the circuit of the phase detector in Embodiment 1 of the present invention.

[0024] Figure 5 This is a schematic diagram of recovering a clock signal in Embodiment 1 of the present invention.

[0025] Figure 6 Schematic diagram of the circuit of the filter in Embodiment 1 of the present invention.

[0026] Figure 7 Schematic diagram of the circuit of the SDM modulator in Example 1 of the present invention.

[0027] Figure 8 This is a simulation diagram of the convergence process of the modulation control signal sdm_ctrl in Example 1 of the present invention.

[0028] Fig. 9 This is the clock eye diagram recovered in Example 1 of the present invention.

[0029] Fig.10 Schematic diagram of the structure of the data clock recovery device in embodiment 2 of the present invention.

[0030] Fig.11 Schematic diagram of the circuit of the filter in Embodiment 2 of the present invention. DETAILED DESCRIPTION

[0031] With reference to the accompanying drawings and specific embodiments, the structure, composition, characteristics and advantages of the vehicle-mounted high-speed transmitting circuit of the present invention, including the serializer / deserializer thereof and the use method thereof, will be explained below in an exemplary manner. However, all descriptions should not be used to form any limitations on the present invention.

[0032] Example 1: Please refer to Figure 3 In this embodiment, a data clock recovery device based on fractional frequency division is provided, including a phase detector, a digital filter, a sigma-delta modulator and a frequency divider; the output end of the phase detector is connected to the input end of the digital filter, the output end of the digital filter is connected to the input end of the sigma-delta modulator, the output end of the sigma-delta modulator is connected to the input end of the frequency divider, the input end of the frequency divider is simultaneously connected to a local high-speed clock signal, the output end of the frequency divider is connected to the input end of the phase detector, and the input end of the phase detector is simultaneously connected to a low-speed input signal.

[0033] It is easy to understand that the high-speed signal and low-speed signal described in this article are relative concepts rather than absolute concepts, that is, among the two signals, the transmission rate of one signal is higher than the transmission rate of the other signal, especially when the rate difference is large, such as low speed 100Mbps and high speed 3.2Gbps.

[0034] The input signal provided to the input end of the phase detector is a low-speed signal, for example, the signal is a random NRZ (non-return-to-zero code) modulated signal, or it can be pam4, pam8, etc. The phase detector outputs phase difference information based on the difference between the recovered clock and the input signal phase. In this embodiment, a bang bang nonlinear phase detector is used to output a pe (phase advance) signal and a pl (phase lag) signal, which takes a value of 0 or 1. The digital filter uses a first-order filter to output the control amount sdm_ctrl of the sigma_delta modulator according to the pe information and the pl information. This control amount represents the fractional frequency division value. The sigma-delta modulator uses a first-order SDM modulator to convert the fractional sdm_ctrl into an integer sequence consisting of 0 and 1, that is, to output an integer sequence. The frequency division coefficient of the frequency divider is N (integer frequency division), which is added to the fractional frequency division value f output by the first-order SDM modulator to obtain N+f. The local high-speed clock signal is divided by N+f to output the recovered clock, so the recovered clock frequency = high-speed clock / (N+f).

[0035] See also Figure 4 In this embodiment, the phase detector adopts a bang-bang nonlinear phase detector, including four triggers, three XOR gates and two AND gates. The input low-speed signal and the recovered clock output by the divider are input into the trigger, and then processed by the XOR gate and the AND gate to output PE signal and PL signal with values ​​of 0 or 1.

[0036] See also Figure 6 In this embodiment, the digital filter adopts a first-order filter, and this structure is a proportional integral structure. The digital filter includes three adders and two multipliers. "++" is the addition of the two, "+-" is the subtraction of the two, and the signal corresponding to "+" is subtracted from the signal corresponding to "-". The pe signal and the pl signal are subtracted through an adder to obtain the pd value. Kp is the proportional path gain, and Ki is the integral path gain. The pd value is multiplied by the integral path gain through a multiplier, and then delayed by one beat (Z -1 The result after ) is accumulated by another adder to obtain the accumulated result. The pd value is multiplied by the proportional path gain by another multiplier, and then added to the accumulated result by another adder to output the control amount sdm_ctrl.

[0037] The digital filter may also adopt a higher order filter such as a second order, but the first order filter is easy to control and has good stability, is sufficient for application, and has a simpler structure.

[0038] See also Figure 7 In this embodiment, a first-order SDM modulator is used, including three adders. The adder uses a 16-bit accumulator. The input sdm_ctrl is first added to 2^16 through an adder to make the input a positive number to obtain an accumulated value. The lower 16 bits of the accumulated value are delayed for one beat and then accumulated with the accumulated value through another adder. The high bits perform int operation (round down) and then pass through another adder to subtract 1 and output f.

[0039] The sigma-delta modulator may also adopt a second-order or other high-order modulator, but a high-order modulator may increase the jitter, that is, the first-order modulator may be adopted in this embodiment to reduce the jitter.

[0040] Currently, there are two types of vehicle-mounted serdes signals, high-speed and low-speed, and the rates differ greatly, for example, by 30 times or more. In the past, clock data recovery only had one rate signal, mainly using Figure 2 The structure shown is used for clock data recovery. If there is a high-speed signal, there is a high-speed clock. The present invention aims at low-speed clock data recovery, directly uses the high-speed clock for fractional frequency division, and the sigma-delta modulator cooperates with the frequency divider, so the circuit structure is much simpler.

[0041] When the integer division frequency N of the divider is 80, the recovered clock is as follows Figure 5 As shown, the simulation waveform is as follows Figure 8 As shown in the figure, for the low-speed signal 100Mbps, sdm_ctrl finally converges and fluctuates around 0, indicating that the recovered clock correctly tracks the input signal.

[0042] Fig. 9This is the eye diagram of the final recovered clock. It can be seen that the clock jitter is very small, and the peak-to-peak value of the jitter accounts for 5% of the clock period (limited by the simulation accuracy), which is sufficient to meet the requirements.

[0043] Example 2: Please refer to Fig.10 and Fig.11 The data clock recovery device based on fractional frequency division provided in this embodiment is different from that in Embodiment 1 in that an automatic gain control module is added on the digital filter side.

[0044] like Fig.11 As shown, the automatic gain control module interacts with the digital filter to dynamically adjust the gain of the digital filter to speed up the convergence speed. The adjustment mechanism can be: detect whether the current data clock recovery has been locked, if not locked, adjust the digital filter to use a first gain value; if locked, adjust the digital filter to use a second gain value, and the first gain value is greater than the second gain value. That is, when it is not locked, adjust the digital filter to use a larger gain value to achieve fast locking, and if it is locked, use a smaller gain value to reduce bandwidth, reduce noise, and thus reduce jitter after convergence.

[0045] In this embodiment, Fig.11 As shown in the figure, the int_val signal (the delay value after the pd value is multiplied by the integral path gain) is introduced into the digital filter, and the change of the int_val signal is used to detect whether the CDR is locked. The int_val signal is collected for the first time, and the int_val signal is collected for the second time after a period of time. If the absolute difference between the two collected values ​​is greater than the set threshold, it means that the CDR is not locked, and if the absolute difference between the two collected values ​​is less than or equal to the set threshold, it means that the CDR is locked. That is, the set time period is used as the collection cycle, and the current collection value is subtracted from the last collection value. If the absolute difference is greater than the set threshold, it means that the CDR is not locked, otherwise it means that the CDR is locked.

[0046] The above-described embodiments are only specific implementations of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications, replacements and improvements within the technical scope disclosed by the present invention, and these modifications, replacements and improvements should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A data clock recovery device based on fractional frequency division, characterized in that: The invention comprises a phase detector, a digital filter, a sigma-delta modulator and a frequency divider, wherein the output end of the phase detector is connected to the input end of the digital filter, the output end of the digital filter is connected to the input end of the sigma-delta modulator, the output end of the sigma-delta modulator is connected to the input end of the frequency divider, the input end of the frequency divider is simultaneously connected to a local high-speed clock signal, the output end of the frequency divider is connected to the input end of the phase detector, and the input end of the phase detector is simultaneously connected to a low-speed input signal.

2. The data clock recovery device based on fractional frequency division according to claim 1, characterized in that: The phase detector adopts a bang-bang nonlinear phase detector, which includes four triggers, three XOR gates and two AND gates. The input low-speed signal and the recovered clock output by the divider are input into the trigger, and after being processed by the XOR gate and the AND gate, the PE signal and the PL signal with the value of 0 or 1 are output.

3. The data clock recovery device based on fractional frequency division according to claim 2, characterized in that: The digital filter is a first-order filter.

4. The data clock recovery device based on fractional frequency division according to claim 3, characterized in that: The digital filter includes three adders and two multipliers. The PE signal and the PL signal are subtracted by an adder to obtain a PD value. The PD value is multiplied by an integral path gain by a multiplier and the result delayed by one beat is accumulated by another adder to obtain the accumulated result. The PD value is multiplied by another multiplier and the proportional path gain and the result is added by another adder to output the control quantity sdm_ctrl.

5. The data clock recovery device based on fractional frequency division according to claim 3, characterized in that: The sigma-delta modulator is a first-order SDM modulator.

6. The data clock recovery device based on fractional frequency division according to claim 5, characterized in that: The first-order SDM modulator includes three adders. The control quantity sdm_ctrl is first added to 2^16 through an adder to become a positive number to obtain an accumulated value. The lower 16 bits of the accumulated value are delayed for one beat and then accumulated with the accumulated value through another adder. The high bits perform int operation and then pass through another device to subtract 1 and output the fractional frequency division value f.

7. The data clock recovery device based on fractional frequency division according to any one of claims 1 to 6, characterized in that: It also includes an automatic gain control module, which performs data interaction with the digital filter and is used to dynamically adjust the gain of the digital filter to accelerate the convergence speed.

8. The data clock recovery device based on fractional frequency division according to claim 7, characterized in that: Detect whether the current data clock recovery has been locked. If not, adjust the digital filter to use a first gain value; if locked, adjust the digital filter to use a second gain value, wherein the first gain value is greater than the second gain value.

9. A data clock recovery method based on fractional frequency division, characterized in that: The phase detector outputs phase difference information according to the difference between the recovered clock and the input low-speed signal phase; The digital filter outputs a control value sdm_ctrl according to the phase difference information; the sigma-delta modulator outputs a fractional frequency division value f according to the control value sdm_ctrl; the frequency division coefficient of the frequency divider is an integer N, and the frequency divider divides the input local high-speed clock signal by N+f times and then outputs the recovered clock.

10. The data clock recovery method based on fractional frequency division according to claim 9, characterized in that: In the process of the digital filter outputting the control amount sdm_ctrl according to the phase difference information, it is detected whether the current data clock recovery has been locked. If not locked, the digital filter is adjusted to use the first gain value; if locked, the digital filter is adjusted to use the second gain value, and the first gain value is greater than the second gain value.

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