A test apparatus and method for a gateway device

Abstract

The application discloses a kind of gateway device test device and method, gateway device includes mainboard, AP and CP are arranged on mainboard, test device includes: clear communication module;Password state signal transmission test path, for testing the on-off of password module working state transmission path, state indication interface is connected working state indication unit by first test button ground, when first test button is pressed, working state indication unit is used to indicate the on-off of password module working state transmission path;Destroy key signal transmission test path, for testing the on-off of destroy key path, destroy key interface is connected destroy key switch by second indication unit power supply;Key key signal transmission test path, for testing the on-off of key key interface that mainboard is connected to external password module.This application can realize to gateway device whole machine, working state indicating lamp and external tight interface are tested, without the aid of external tooling, greatly save time, manpower and cost.

Description

Technical Field

[0001] This invention belongs to the field of gateway device testing technology, specifically relating to a testing device and method for gateway devices with military-grade encryption modules. Background Technology

[0002] Most existing gateway devices are equipped with encryption modules to encrypt signals transmitted between the AP (Application Processor) and CP (Communication Processor) of the gateway device.

[0003] With the increasing demand for military-grade encrypted gateways, data transmission between the Access Point (AP) and Content Controller (CP) is impossible under cryptographic module encryption. Data can only be transmitted after encryption and decryption via the cryptographic module. To prevent leaks, the military requires cryptographic modules to be obtained and used by designated personnel and equipment. Manufacturers often lack access to these modules, making it impossible to perform full-device functional testing during gateway production. Therefore, in this situation, testing fixtures are needed to test the motherboard, the entire device, the open-circuit communication module, and external encrypted interfaces separately. This is not only time-consuming and labor-intensive, but also requires different testing fixtures due to the diverse types and forms of encrypted gateways. These fixtures are generally large, difficult to carry, and cost around 1300 yuan per unit. The number of fixtures increases with order quantity, saving time but increasing production costs. Furthermore, these testing fixtures cannot perform bare-metal functionality testing or external interface testing of the gateway device. Summary of the Invention

[0004] In response to the problems mentioned in the background art, one of the objectives of this application is to provide a testing device for gateway devices. This device can test the entire gateway device, the status indicator interface for connecting external cryptographic modules to output working status indicators, the working status indicator unit, the key destruction interface, and the key injection interface by setting up a clear communication module, a password status signal transmission test path, a key destruction interface, and a key injection interface on the motherboard of the gateway device. This eliminates the need for external tooling and greatly saves time, manpower, and costs.

[0005] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0006] This application relates to a testing apparatus for a gateway device, the gateway device including a motherboard, on which an access point (AP) and a connection point (CP) are arranged, and the testing apparatus includes:

[0007] The Mingtong communication module is used to establish a communication connection between the AP and CP during testing.

[0008] A password status signal transmission test path is used to test the continuity of the password module's working status transmission path between the AP and CP. The status indicator interface is grounded and connected to the working status indicator unit through the first test button. When the first test button is pressed, the working status indicator unit is used to indicate the continuity of the password module's working status transmission path. The first test button and the working status indicator unit are both arranged on the motherboard. The status indicator interface is an external interface on the motherboard used to connect the output terminal of the password module to output a signal indicating its working status.

[0009] The key destruction signal transmission test path is used to test the continuity of the key destruction path. The key destruction interface is connected to the power supply and the key destruction switch through the second indicator unit. The second indicator unit is used to issue an indication when the key destruction switch is lightly touched or when the password module destroys the key. The key destruction switch and the second indicator unit are arranged on the motherboard. The key destruction interface is the external interface on the motherboard used to connect to the key destruction interface of the password module.

[0010] The key injection signal transmission test path is used to test the connectivity of the key injection interface of the motherboard that connects to the cryptographic module.

[0011] In some embodiments of this application, the key injection signal transmission test path includes:

[0012] The first key injection signal transmission test path is used to test the continuity of the debugging path where the RS232 level serial port is located.

[0013] The second key injection signal transmission test path is used to test the connectivity of the authentication path where the I2C interface is located.

[0014] The third key injection signal transmission test path is used to test the continuity of the injection path where the USB interface is located.

[0015] In some embodiments of this application, the first key injection signal transmission test path includes:

[0016] A second test button is located on the motherboard and is connected between the serial port transmitter and receiver. During testing, pressing the second test button and judging the continuity between the serial port transmitter and receiver based on the display window on the serial port debugging host computer, which is connected to both the serial port transmitter and receiver, is required. The second key injection signal transmission test path includes:

[0017] The third indicator unit is arranged on the motherboard, and one end of the third indicator unit is connected to the serial data line interface in the I2C bus and the other end is connected to the DC power supply.

[0018] The fourth indicator unit is arranged on the motherboard, and one end of the fourth indicator unit is connected to the serial clock line interface in the I2C bus and the other end is connected to the DC power supply.

[0019] When both the third and fourth indicator units issue indications, the I2C bus interface is normal; the third key injection signal transmission test path includes:

[0020] A fifth indicator unit is arranged on the motherboard, with one end of the fifth indicator unit connected to the positive data terminal of the USB bus and the other end connected to a DC power supply.

[0021] A sixth indicator unit is arranged on the motherboard, with one end of the sixth indicator unit connected to the negative data terminal of the USB bus and the other end connected to a DC power supply.

[0022] When both the fifth and sixth indicator units issue instructions, the USB bus interface is functioning normally.

[0023] In some embodiments of this application, the testing apparatus includes:

[0024] A connector having multiple connection pins;

[0025] One end of the first connection pin is connected to the status indication interface, and the other end is connected to the output terminal of the cryptographic module that outputs a signal indicating its working status;

[0026] One end of the second connection pin is connected to the key destruction interface, and the other end is connected to the key destruction interface of the cryptographic module;

[0027] One end of the third connection pin is connected to the serial port transmitter on the motherboard and the other end is connected to the serial port transmitter of the password module;

[0028] One end of the fourth connection pin is connected to the serial port receiver on the motherboard and the other end is connected to the serial port receiver of the password module.

[0029] One end of the fifth connection pin is connected to the serial data line interface on the motherboard, and the other end is connected to the serial data line interface of the cryptographic module.

[0030] One end of the sixth connection pin is connected to the serial clock line interface on the motherboard, and the other end is connected to the serial clock line interface of the cryptographic module.

[0031] One end of the seventh connection pin is connected to the positive data terminal of the USB bus on the motherboard, and the other end is connected to the positive data terminal of the USB bus of the password module;

[0032] One end of the eighth connection pin is connected to the negative data terminal of the USB bus on the motherboard, and the other end is connected to the negative data terminal of the USB bus of the password module.

[0033] Compared with the prior art, the testing apparatus involved in some embodiments of this application has the following advantages and beneficial effects:

[0034] By adding a communication module, a password status signal transmission test path, a key destruction signal transmission test path, and a key injection signal transmission test path to the motherboard, it is possible to test the entire gateway device, the status indicator interface for connecting external password modules to output working status indicators, the working status indicator unit, the key destruction interface, and the key injection interface simply by arranging the corresponding test path components on the motherboard. This is simple, easy to operate, and requires no external tooling, greatly saving time, manpower, and costs.

[0035] This application also relates to a testing method for a gateway device, which uses the testing apparatus described above to test the gateway device, the testing method comprising:

[0036] S1: Test whether the communication between AP and CP is normal. If yes, proceed to S2. If no, check the motherboard and the communication module between AP and CP, and return to S1.

[0037] S2: Perform signal testing on the external secure interface;

[0038] The test is completed when the working status indicator unit issues an indication when the first test button is pressed, when the second indicator unit issues an indication when the key destruction switch is lightly pressed, and when the key injection signal transmission test channel is connected.

[0039] If the working status indicator unit does not issue an indication when the first test button is pressed, and / or the second indicator unit does not issue an indication when the key destruction switch is lightly pressed, proceed to S3;

[0040] If the key injection signal transmission test path is not connected, proceed to S4;

[0041] S3: Determine if the open communication module between AP and CP is faulty. If yes, replace the open communication module. If no, proceed to S4.

[0042] S4: After determining that the motherboard is faulty and replacing the motherboard, return to S1.

[0043] In some embodiments of this application, the key injection signal transmission test path includes:

[0044] The first key injection signal transmission test path is used to test the continuity of the debugging path where the RS232 level serial port is located.

[0045] The second key injection signal transmission test path is used to test the connectivity of the authentication path where the I2C interface is located.

[0046] The third key injection signal transmission test path is used to test the continuity of the injection path where the USB interface is located.

[0047] The test method for the gateway device also includes testing the key injection signal transmission test path, specifically:

[0048] If at least one of the first key injection signal transmission test path, the second key injection signal transmission test path, and the third key injection signal transmission test path is not connected, it indicates that the key injection signal transmission test path is not connected; otherwise, it indicates that the key injection signal transmission test path is connected.

[0049] In some embodiments of this application, the testing method for the gateway device further includes testing the first key injection signal transmission test path, specifically:

[0050] Press the second test button and determine the continuity between the serial port transmitter and receiver based on the data displayed in the window of the serial port debugging host computer. The serial port debugging host computer is connected to the serial port transmitter and receiver.

[0051] The first key injection signal transmission test path includes a second test button, which is arranged on the motherboard and connected between the serial port transmitter and the serial port receiver.

[0052] In some embodiments of this application, the testing method for the gateway device further includes testing the connectivity of the authentication path where the I2C interface is located by observing whether both the third and fourth indicator units issue indications.

[0053] The second key injection signal transmission test path includes a third indicator unit and a fourth indicator unit, both of which are arranged on the motherboard. One end of the third indicator unit is connected to the serial data line interface in the I2C bus and the other end is connected to a DC power supply. One end of the fourth indicator unit is connected to the serial clock line interface in the I2C bus and the other end is connected to a DC power supply.

[0054] In some embodiments of this application, the testing method for the gateway device further includes testing the continuity of the injection path where the USB interface is located by observing whether both the fifth and sixth indicator units issue indications.

[0055] The third key injection signal transmission test path includes a fifth indicator unit and a sixth indicator unit, both of which are arranged on the motherboard. One end of the fifth indicator unit is connected to the positive data terminal of the USB bus and the other end is connected to a DC power supply. One end of the sixth indicator unit is connected to the negative data terminal of the USB bus and the other end is connected to a DC power supply.

[0056] Other features and advantages of the present invention will become clearer after reading the detailed description of the embodiments of the present invention in conjunction with the accompanying drawings. Attached Figure Description

[0057] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0058] Figure 1 This is a schematic diagram of a gateway device that enables communication between existing APs and CPs via a Mingtong communication module;

[0059] Figure 2 This is a schematic diagram of an embodiment of the testing device proposed in this invention connected to a cryptographic module;

[0060] Figure 3 This is a circuit implementation diagram of the encryption signal transmission test path, the key destruction signal transmission test path, and the key injection signal transmission test path in one embodiment of the test device proposed in this invention;

[0061] Figure 4 This is a schematic diagram of an embodiment of the testing device proposed in this invention, showing the connection between the device and the cryptographic module via a connector.

[0062] Figure 5 This is a flowchart of the testing method proposed in this invention;

[0063] Figure label:

[0064] 100. Mainboard; 110. AP; 120. CP; 130. Mingtong Communication Module; 140. Password Status Signal Transmission Test Path; 150. Destroy Key Signal Transmission Test Path; 151. Destroy Key Switch; 160. Key Injection Signal Transmission Test Path; 200. Password Module; 300. Connector. Detailed Implementation

[0065] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0066] In the description of this application, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0067] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0068] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0069] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0070] The following disclosure provides many different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this invention, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0071] In order to enable testing of the entire gateway device and its external password interface with the external password module 200 when the password module cannot be obtained, this application relates to a testing device for this type of gateway device. The device is used to test the entire device and the external password interface, avoiding the high cost, time and labor costs associated with using external tooling for the gateway device.

[0072] See Figure 1 The gateway device’s motherboard 100 is equipped with AP 110 and CP 120, as well as a communication module 130 that connects AP 110 and CP 120. The communication module 130 is a commonly used communication module that is only responsible for non-private data exchange between AP 110 and CP 120. The communication module 130 can be used to test whether the communication of the whole machine is normal.

[0073] In some embodiments of this application, the communication module 130 can use an internal network port or a USB port to realize data interaction between AP110 and CP120.

[0074] For example, the communication module 130 can be installed on the motherboard 100 via a plug-in method.

[0075] If the communication of the whole machine is abnormal, check the motherboard 100 and the communication module 130. If necessary, replace the motherboard 100 and / or the communication module 130.

[0076] See Figure 2 The mainboard 100 of the gateway device is connected to the cryptographic module 200 through the external cryptographic interface, enabling encrypted data exchange between AP 110 and CP 120 via the cryptographic module 200.

[0077] When cryptographic module 200 is unavailable, low-cost, high-efficiency testing of the external cryptographic interface is a challenging problem.

[0078] In some embodiments of this application, in order to test the external encryption interface, the testing device involved in this application includes, in addition to the open communication module 130, a password status signal transmission test path 140, a key destruction signal transmission test path 150, and a key injection signal transmission test path 160.

[0079] The cryptographic status signal transmission test path 140 is used to test the continuity of the cryptographic module 200's operating status transmission path, which is to be connected between AP 110 and CP 120.

[0080] The key destruction signal transmission test path 150 is used to test the continuity of the key destruction path, which is the path through which the key destruction switch 151 destroys the key of the cryptographic module 200.

[0081] The key injection signal transmission test path 160 is used to test the continuity of the password signal communication interface between the motherboard 100 and the external password module 200.

[0082] In some embodiments of this application, see Figure 2 The password status signal transmission test path 140 involves a status indication interface for the working status of the external password module 200. When the status indication interface is abnormal, the password status signal transmission test path 140 is not connected, and when the password module 200 is connected to the motherboard 100 through the status indication interface, the working status of the password module 200 cannot be indicated.

[0083] In some embodiments of this application, the status indication interface is the external interface of the output terminal A on the motherboard 100 used to connect the password module 200 to output a signal indicating its working status.

[0084] Before testing the status indication interface, it is necessary to ensure that AP 110 and CP 120 can communicate normally through the Mingtong communication module 130; otherwise, the test cannot be performed.

[0085] In this application, the main concern is whether the password status signal transmission test path 140 is a path when it is turned on during the test, and whether the working status indicator unit LED1 can issue an indication.

[0086] When the password status signal transmission test path 140 is open and the working status indicator unit LED1 also issues an indication, it indicates that the status indicator interface is normal.

[0087] Therefore, in order to test the working status indicator unit LED1 and the password status signal transmission test path 140, see [link to relevant documentation]. Figure 3 The first test button S1 and the working status indicator unit LED1 are arranged on the motherboard 100.

[0088] The status indicator interface is connected to one end of the working status indicator unit LED1 and the first test button S1 respectively. The other end of the first test button S1 is grounded. The end of the working status indicator unit LED1 that is not connected to the status indicator interface can be connected to a DC power supply +5.5V. That is, the password status signal transmission test path 140 is a path formed by the DC power supply, the working status indicator unit LED1, the status indicator interface, the first test button S1 and ground connected in series.

[0089] During the testing phase, when the first test button S1 is pressed, the DC power supply powers the working status indicator unit LED1, causing the working status indicator unit LED1 to issue an indication. This indicates that the password status signal transmission test path 140 is open and that the status indicator interface and the working status indicator unit LED1 are normal. Otherwise, it is necessary to check whether the status indicator interface is faulty, whether the first test button S1 is faulty, whether the working status indicator unit LED1 is faulty, and / or whether the communication between AP 110 and CP 120 is normal.

[0090] If the working status indicator unit LED1 does not issue an indication, and the communication between AP 110 and CP 120 is normal (i.e., the communication module 130 is normal), then the status indicator interface may be faulty, the first test button S1 may be faulty, or the working status indicator unit LED1 may be faulty. In this case, replace the motherboard 100 and return it to the factory for repair.

[0091] In some embodiments of this application, the operating status indicator unit LED1 is an LED light. This LED light can be a single-color light or a red-green dual-color light, see [link to relevant documentation]. Figure 3 As shown.

[0092] When the password status signal transmission test path 140 is normal and the working status indicator unit LED1 is normal, when the motherboard 100 is actually connected to the password module 200, the working status indicator unit LED1 can be controlled to issue different indications according to the working status of the password module 200 during actual key injection signal communication.

[0093] For example, when the working status indicator unit LED1 is selected as a red and green dual-color light, the working status indicator unit LED1 can be controlled to not indicate when the password module 200 is not powered on or the authentication stick is not inserted. When the authentication stick is successfully authenticated and in the authentication state, the green light in the working status indicator unit LED1 can be controlled to flash quickly. When a fault occurs, the red light in the working status indicator unit LED1 can be controlled to light up, and so on.

[0094] In some embodiments of this application, see reference 1. Figure 2The external interface involved in the key destruction signal transmission test path 150 is the key destruction interface. When the key destruction interface is abnormal, the key destruction signal transmission test path 150 is not connected, and the key destruction function cannot be completed when the password module 200 is connected to the key destruction switch 151 on the motherboard 100 through the key destruction interface on the motherboard 100.

[0095] In some embodiments of this application, the key destruction interface is an external interface on the motherboard 100 used to connect to the key destruction interface of the cryptographic module 200. When the cryptographic module 200 completes the encrypted data interaction between AP 110 and CP 120, if the key destruction interface receives a key destruction signal from the key destruction switch 151, the real key of the cryptographic module 200 will be destroyed to avoid information leakage.

[0096] To test this key destruction interface, see [link / reference]. Figure 3 A key destruction switch 151 and a second indicator unit LED6 are arranged on the motherboard 100. The key destruction interface is connected to the second indicator unit LED6 and the key destruction switch 151 respectively. When the key destruction switch 151 is pressed lightly, it is grounded. The end of the second indicator unit LED6 that is not connected to the key destruction interface can be connected to a DC power supply +5.5V. That is, the key destruction signal transmission test path 150 is a path formed by the DC power supply, the second indicator unit LED6, the key destruction interface and the key destruction switch 151 connected in series.

[0097] During the testing phase, when the key destruction switch 151 is pressed, the DC power supply powers the second indicator unit LED6, causing the second indicator unit LED6 to issue an indication. This indicates that the key destruction interface and the key destruction switch 151 are normal. Otherwise, it is necessary to check whether the key destruction interface is faulty, whether the key destruction switch 151 is faulty, whether the second indicator unit LED6 is faulty, and / or whether the communication between AP110 and CP 120 is normal.

[0098] If the second indicator unit LED6 does not issue an indication, and the communication between AP 110 and CP 120 is normal (i.e., the communication module 130 is normal), then the key destruction interface may be faulty, the key destruction switch 151 may be faulty, or the second indicator unit LED6 may be faulty. In this case, replace the motherboard 100 and return it to the factory for repair.

[0099] In some embodiments of this application, see Figure 3 The second indicator unit LED6 is an LED light, which can be a single-color light or a dual-color light.

[0100] When the motherboard 100 is tested and ready for factory use, the key destruction interface of the password module 200 is connected to the key destruction interface on the motherboard 100. Pressing the key destruction switch 151 will cause the key destruction interface to be at a low level, thus enabling the password module 200 to destroy the key.

[0101] In some embodiments of this application, see Figure 2 The testing device also includes a key injection signal transmission test path 160 for testing the key injection interface (including an I2C interface for authentication of the gateway device, a USB interface for injection, and a serial port for debugging).

[0102] The key injection interface is the external interface on the motherboard 100 for transmitting key injection signal data with the cryptographic module 200.

[0103] When the key injection signal transmission test path 160 is connected, it indicates that the key injection interface is normal. In this way, when the motherboard 100 is connected to the cryptographic module 200, it can be ensured that the cryptographic module 200 can normally exchange encrypted data between AP 110 and CP 120.

[0104] In some embodiments of this application, to enable the cryptographic module 200 to provide authentication, injection, and debugging functions for the gateway, see [link to relevant documentation]. Figure 3 The key injection interface can include a serial port, a USB interface, and an I2C interface, and these interfaces are all external key interfaces of the motherboard 100.

[0105] In some embodiments of this application, the key injection signal transmission test path 160 includes a first key injection signal transmission test path, used to test the continuity of the debugging path where the RS232 level serial port is located.

[0106] In some embodiments of this application, the key injection signal transmission test path 160 includes a second key injection signal transmission test path, used to test the connectivity of the authentication path where the I2C interface is located.

[0107] In some embodiments of this application, the key injection signal transmission test path 160 includes a third key injection signal transmission test path, used to test the continuity of the injection path where the USB interface is located.

[0108] During testing, AP 110 and CP 120 communicate via open communication module 130. The interface used for communication is an internal interface, such as a network port or USB port. Therefore, even if the open communication module 130 is used for normal communication, there is no communication signal at the external interface.

[0109] In some embodiments of this application, see Figure 3 The first key injection signal transmission test path includes a second test button S2, which is arranged on the motherboard 100 and connected between the serial port transmitter Tx of AP 110 and the serial port receiver Rx of CP 120.

[0110] During testing, press the second test button S2 and use the serial port debugging host computer to check if the window displays the number 1 when the second test button S2 is pressed. If it does, it means that the debugging path of the serial port and the RS232 level serial port is normal. Otherwise, the debugging path of the serial port and / or the RS232 level serial port is abnormal.

[0111] The serial port debugging host computer is connected to the serial port transmitter Tx and the serial port receiver Rx.

[0112] In some embodiments of this application, the second key injection signal transmission test path includes a third indicator unit LED2 and a fourth indicator unit LED3.

[0113] The third indicator unit LED2 and the fourth indicator unit LED3 are both arranged on the motherboard 100. The third indicator unit LED3 indicates the serial data line SDA in the I2C bus, and the fourth indicator unit LED3 indicates the serial clock line SCL in the I2C bus.

[0114] In some embodiments of this application, one end of the third indicator unit LED3 is connected to the serial data line interface SDA in the I2C bus and the other end is connected to a DC power supply (e.g., 5.5V DC arranged on the motherboard 100).

[0115] During testing, a 5.5V DC high level is provided to the third indicator unit LED2. As a result, the path of the serial data line interface SDA in the I2C bus is connected, and the third indicator unit LED2 issues an indication, that is, the serial data line interface SDA in the I2C bus is normal. Otherwise, the third indicator unit LED2 may be faulty, or the serial data line interface SDA in the I2C bus may be faulty.

[0116] In some embodiments of this application, one end of the fourth indicator unit LED3 is connected to the serial clock line interface SCL in the I2C bus and the other end is connected to a DC power supply (e.g., 5.5V DC arranged on the motherboard 100).

[0117] During testing, a 5.5V DC high level is provided to the fourth indicator unit LED3. As a result, the path of the serial clock line interface SCL in the I2C bus is connected, and the fourth indicator unit LED3 issues an indication, that is, the serial clock line interface SCL in the I2C bus is normal. Otherwise, the fourth indicator unit LED3 may be faulty, or the serial clock line interface SCL in the I2C bus may be faulty.

[0118] Only when both the third indicator unit LED2 and the fourth indicator unit LED3 issue an indication can it be said that the I2C bus interface and the authentication path where the I2C interface is located are normal; otherwise, the I2C bus interface and / or the authentication path where the I2C interface is located are abnormal.

[0119] In some embodiments of this application, the third key injection signal transmission test path includes a fifth indicator unit LED4 and a sixth indicator unit LED5.

[0120] The fifth indicator unit LED4 and the sixth indicator unit LED5 are both arranged on the motherboard 100. The fifth indicator unit LED4 indicates the positive data terminal DP in the USB bus, and the sixth indicator unit LED5 indicates the negative data terminal DM in the USB bus.

[0121] In some embodiments of this application, one end of the fifth indicator unit LED4 is connected to the positive data terminal DP of the USB bus and the other end is connected to a DC power supply (e.g., 5.5V DC arranged on the motherboard 100).

[0122] During testing, a 5.5V DC high level is provided to the fifth indicator unit LED4. As a result, the path of the positive data terminal DP in the USB bus is connected, and the fifth indicator unit LED4 issues an indication that the positive data terminal DP in the USB bus is normal. Otherwise, the fifth indicator unit LED4 may be faulty, or the positive data terminal DP in the USB bus may be faulty.

[0123] In some embodiments of this application, one end of the sixth indicator unit LED5 is connected to the negative data terminal DM in the USB bus and the other end is connected to a DC power supply (e.g., 5.5V DC arranged on the motherboard 100).

[0124] During testing, a 5.5V DC high level is provided to the sixth indicator unit LED5. As a result, the path of the negative data terminal DM in the USB bus is connected, and the sixth indicator unit LED5 issues an indication that the negative data terminal DM in the USB bus is normal. Otherwise, the sixth indicator unit LED5 may be faulty, or the negative data terminal DM in the USB bus may be faulty.

[0125] Only when both the fifth indicator unit LED4 and the sixth indicator unit LED5 issue an indication can it be said that the USB bus interface and the injection path where the USB interface is located are normal; otherwise, the USB bus interface and / or the injection path where the USB interface is located are abnormal.

[0126] It should be noted that during testing, the serial data line interface in the I2C bus, the serial clock line interface in the I2C bus, the positive data terminal DP in the USB interface, and the negative data terminal DM in the USB interface are all connected to ground, for example, on the motherboard 100, via test aviation connectors.

[0127] In some embodiments of this application, for ease of testing and installation of the cryptographic module 200, see [link to relevant documentation]. Figure 4 The testing device also includes a connector 300, which has multiple connection pins.

[0128] As described above, the status indicator interface, key destruction interface, serial port transmitter Tx, serial port receiver Rx, serial data line interface SDA, serial clock line interface SCL, data positive terminal DP, and data positive terminal DM can correspond to the first connection pin, second connection pin, third connection pin, fourth connection pin, fifth connection pin, sixth connection pin, seventh connection pin, and eighth connection pin, respectively.

[0129] One end of the first connection pin is connected to the status indicator interface on the motherboard 100, and the other end can be used to connect the motherboard 100 to the output terminal A of the password module 200 after it leaves the factory.

[0130] One end of the second connection pin is connected to the key destruction interface on the motherboard 100, and the other end can be used to connect the motherboard 100 to the key destruction interface of the password module 200 after it leaves the factory.

[0131] One end of the third connection pin is connected to the serial port transmitter Tx on the motherboard 100, and the other end can be used to connect the motherboard 100 to the serial port transmitter Tx of the password module 200 after it leaves the factory.

[0132] One end of the fourth connection pin is connected to the serial port receiver Rx on the motherboard 100, and the other end can be used to connect the motherboard 100 to the serial port receiver Rx of the password module 200 after it leaves the factory.

[0133] One end of the fifth connection pin is connected to the serial data line interface SDA on the motherboard 100, and the other end can be used to connect the motherboard 100 to the serial data line interface SDA of the password module 200 after it leaves the factory.

[0134] One end of the sixth connection pin is connected to the serial clock line interface SCL on the motherboard 100, and the other end can be used to connect the motherboard 100 to the serial clock line interface SCL of the password module 200 after it leaves the factory.

[0135] One end of the seventh connection pin is connected to the positive data terminal DP on the motherboard 100, and the other end can be used to connect the motherboard 100 to the positive data terminal DP of the password module 200 after it leaves the factory.

[0136] One end of the eighth connection pin is connected to the negative data terminal DM on the motherboard 100, and the other end can be used to connect the motherboard 100 to the negative data terminal DM of the password module 200 after it leaves the factory.

[0137] Thus, after the test is completed, the motherboard 100 and the password module 200 can be easily connected using connector 300.

[0138] It should be noted that when the test is completed and the device is shipped from the factory, the Mingtong communication module 130 and the aviation connector on the motherboard 100 need to be removed.

[0139] The removed Mingtong communication module 130 and aviation connector can be reused when testing other motherboards.

[0140] In some embodiments of this application, only low-cost components such as test buttons and LED indicators are added to the motherboard 100, and the entire motherboard 100 and its external interfaces can be tested using existing serial port debugging host computer, Mingtong communication module 130, and aviation connectors. The operation is simple and easy to implement. Since the cost of the components added to the motherboard 100 only increases by 3.5 yuan, and no separate tooling is required, it saves 1296.5 yuan compared to the original test that required external test tooling, which greatly saves costs. In addition, the motherboard 100 can be mass-produced, saving time and improving testing efficiency.

[0141] See Figure 5 The flowchart shows the test device performing tests on the gateway device as a whole and its external secure interface.

[0142] S1: Test whether the communication between AP 110 and CP 120 is normal. If yes, proceed to S2. If no, check the motherboard 100 and the communication module 130, and return to S1.

[0143] The testing methods involved in this application require normal communication between AP 110 and CP 120. As mentioned above, AP 110 and CP 120 communicate openly through open communication module 130.

[0144] S2: Perform signal testing on the external interface.

[0145] In S2, the following tests are required: status indicator interface, key destruction interface, serial port transmitter Tx, serial port receiver Rx, serial data line interface SDA, serial clock line interface SCL, positive data terminal DP, and positive data terminal DM.

[0146] In some embodiments of this application, when the first test button S1 is pressed, the working status indicator unit LED1 issues an indication, indicating that the status indicator interface is normal.

[0147] When the key destruction switch 151 is pressed, the second indicator unit LED6 emits an indication, indicating that the key destruction interface is normal.

[0148] When the second test button S2 is pressed, the serial port debugging host computer window will output the number 1, indicating that the serial port transmitter Tx and the serial port receiver Rx are normal.

[0149] The third indicator unit LED2 indicates that the serial data line interface SDA is normal.

[0150] The fourth indicator unit LED3 all emits an indication, indicating that the serial clock line interface SCL is normal.

[0151] The fifth indicator unit LED4 indicates that the data is positive and DP is normal.

[0152] The sixth indicator unit LED5 indicates that the data is at the positive extreme and DM is normal.

[0153] During the test, the working status indicator units LED1, LED6, LED2, LED3, LED4, and LED5 all issued indications, and the serial port debugging host computer window displayed the number 1 in response to the key press, indicating that the gateway device's data and password signal path functions were normal, and the Mingtong communication module 130, motherboard 100, and external password interface functions were all normal. At this point, the test was completed, and the motherboard 100 was ready for shipment.

[0154] In some embodiments of this application, when the first test button S1 is pressed, the working status indicator unit LED1 does not issue an indication, which may be due to a malfunction of the first test button S1, and / or a malfunction of the status indicator interface, and / or a malfunction of the Mingtong communication module 130, and / or a malfunction of the working status indicator unit LED1.

[0155] Since the first test button S1, the status indicator interface, and the working status indicator unit LED1 are all located on the motherboard 100, it is necessary to confirm whether the motherboard 100 and the communication module 130 are working properly.

[0156] In some embodiments of this application, the second indicator unit LED6 does not issue an indication when the key destruction switch 151 is pressed, which may be due to a malfunction of the key destruction switch 151, and / or a malfunction of the key destruction interface, and / or a malfunction of the open communication module 130, and / or a malfunction of the second indicator unit LED6.

[0157] Since the key destruction switch 151, the key destruction interface, and the second indicator unit LED6 are all located on the motherboard 100, it is necessary to confirm whether the motherboard 100 and the communication module 130 are functioning properly.

[0158] In some embodiments of this application, when the second test button S2 is pressed, the serial port debugging host computer does not output the number 1 in response to the button press. This may be due to a malfunction of the second test button S2, and / or a malfunction of the serial port transmitting end Tx, and / or a malfunction of the serial port receiving end Rx.

[0159] Since the second test button S2, the serial port transmitter Tx, and the serial port receiver Rx are all located on the motherboard 100, it is necessary to confirm whether the motherboard 100 is functioning properly.

[0160] In some embodiments of this application, the third indicator unit LED2 may not issue an indication, possibly due to a fault in the serial data line interface SDA and / or a fault in the third indicator unit LED2.

[0161] Since the serial data line interface SDA and the third indicator unit LED2 are both located on the motherboard 100, it is necessary to confirm whether the motherboard 100 is functioning properly.

[0162] In some embodiments of this application, the fourth indicator unit LED3 fails to issue an indication, which may be due to a fault in the serial clock line interface SCL and / or a fault in the fourth indicator unit LED3.

[0163] Since the serial clock line interface SCL and the fourth indicator unit LED3 are both located on the motherboard 100, it is necessary to confirm whether the motherboard 100 is functioning properly.

[0164] In some embodiments of this application, the fifth indicator unit LED4 does not issue an indication, possibly due to a fault in the positive data terminal DP and / or a fault in the fifth indicator unit LED4.

[0165] Since the positive terminal DP and the fifth indicator unit LED4 are both located on the motherboard 100, it is necessary to confirm whether the motherboard 100 is functioning properly.

[0166] In some embodiments of this application, the sixth indicator unit LED5 does not issue an indication, possibly due to a fault in the negative data terminal DM and / or a fault in the sixth indicator unit LED5.

[0167] Since both the negative data terminal DM and the sixth indicator unit LED5 are located on the motherboard 100, it is necessary to confirm whether the motherboard 100 is functioning properly.

[0168] Therefore, in S2, if the working status indicator unit LED1 does not issue an indication, proceed to S3; if the second indicator unit LED6 does not issue an indication, proceed to S3.

[0169] If the host computer does not output the number 1 in response to the key press, and / or the third indicator unit LED2 does not issue an indication, and / or the fourth indicator unit LED3 does not issue an indication, and / or the fifth indicator unit LED4 does not issue an indication, and / or the sixth indicator unit LED5 does not issue an indication, then proceed to S4.

[0170] S3: Determine if the communication module 130 between AP 110 and CP 120 is faulty. If so, replace the communication module 130. If not, proceed to S4.

[0171] As described in S2, if the working status indicator unit LED1 does not issue an indication, and / or the second indicator unit LED6 does not issue an indication, it is necessary to confirm whether the main board 100 and the communication module 130 are functioning properly.

[0172] S4: Determine that motherboard 100 is faulty, replace motherboard 100 and return to S1.

[0173] In some embodiments of this application, if the working status indicator unit LED1 does not issue an indication and / or the second indicator unit LED6 does not issue an indication, then the motherboard 100 has malfunctioned if the communication module 130 is not faulty.

[0174] When the working status indicator unit LED1 does not issue an indication, the main board 100 malfunctions here, including but not limited to the following malfunctions: first test button S1, working status indicator unit LED1, status indicator interface.

[0175] In some embodiments of this application, when the second indicator unit LED6 does not issue an indication, the motherboard 100 malfunctions, including but not limited to the following malfunctions: key destruction switch 151, second indicator unit LED6, and key destruction interface.

[0176] To determine which part of the motherboard 100 is malfunctioning, it needs to be sent back to the factory for inspection.

[0177] In some embodiments of this application, if the serial port debugging host computer does not output the number 1 with the key press, and / or the third indicator unit LED2 does not issue an indication, and / or the fourth indicator unit LED3 does not issue an indication, and / or the fifth indicator unit LED4 does not issue an indication, and / or the sixth indicator unit LED5 does not issue an indication, then the motherboard 100 has malfunctioned.

[0178] When the host computer does not output the number 1 in response to the button press during serial port debugging, the motherboard 100 is malfunctioning, including but not limited to the following: the second test button S2, the serial port transmitter Tx, and the serial port receiver Rx.

[0179] When the third indicator unit LED2 does not issue an indication, the motherboard 100 is malfunctioning, including but not limited to the following malfunctions: serial data line interface SDA, third indicator unit LED2.

[0180] When the fourth indicator unit LED3 does not issue an indication, the motherboard 100 is malfunctioning, including but not limited to the following malfunctions: serial clock line interface SCL, fourth indicator unit LED3.

[0181] When the fifth indicator unit LED4 does not issue an indication, the mainboard 100 is malfunctioning, including but not limited to the following malfunctions: data positive terminal DP, fifth indicator unit LED4.

[0182] When the sixth indicator unit LED5 does not issue an indication, the mainboard 100 is malfunctioning, including but not limited to the following malfunctions: data negative terminal DM, sixth indicator unit LED5.

[0183] To determine which part of the motherboard 100 is malfunctioning, it needs to be sent back to the factory for inspection.

[0184] After replacing the motherboard 100, return to S1.

[0185] The testing device involved in this application can be used with all physically encrypted gateway devices. It is compact, easy to operate, low in cost, and highly operable.

[0186] Of course, the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A testing apparatus for a gateway device, the gateway device comprising a motherboard, wherein an access point (AP) and a connection processor (CP) are disposed on the motherboard, characterized in that, The testing apparatus includes: The Mingtong communication module is used to establish a communication connection between the AP and CP during testing. A password status signal transmission test path is used to test the continuity of the password module's working status transmission path between the AP and CP. The status indicator interface is grounded and connected to the working status indicator unit through the first test button. When the first test button is pressed, the working status indicator unit is used to indicate the continuity of the password module's working status transmission path. The first test button and the working status indicator unit are both arranged on the motherboard. The status indicator interface is an external interface on the motherboard used to connect the output terminal of the password module to output a signal indicating its working status. The key destruction signal transmission test path is used to test the continuity of the key destruction path. The key destruction interface is connected to the power supply and the key destruction switch through the second indicator unit. The second indicator unit is used to issue an indication when the key destruction switch is lightly touched or when the password module destroys the key. The key destruction switch and the second indicator unit are arranged on the motherboard. The key destruction interface is the external interface on the motherboard used to connect to the key destruction interface of the password module. A key injection signal transmission test path is used to test the connectivity of the key injection interface of the motherboard connecting to the cryptographic module. The key injection signal transmission test path includes: The first key injection signal transmission test path is used to test the continuity of the debugging path where the RS232 level serial port is located and includes a second test button arranged on the motherboard. The second test button is connected between the serial port transmitter and the serial port receiver. During the test, the second test button is pressed, and the continuity between the serial port transmitter and the serial port receiver is determined according to the window displayed on the serial port debugging host computer. The serial port debugging host computer is connected to the serial port transmitter and the serial port receiver. The second key injection signal transmission test path is used to test the connectivity of the authentication path where the I2C interface is located and includes: The third indicator unit is arranged on the motherboard, and one end of the third indicator unit is connected to the serial data line interface in the I2C bus and the other end is connected to the DC power supply. The fourth indicator unit is arranged on the motherboard, and one end of the fourth indicator unit is connected to the serial clock line interface in the I2C bus and the other end is connected to the DC power supply. When both the third indicator unit and the fourth indicator unit issue an indication, the I2C bus interface is normal. The third key injection signal transmission test path is used to test the continuity of the injection path where the USB interface is located and includes: A fifth indicator unit is arranged on the motherboard, with one end of the fifth indicator unit connected to the positive data terminal of the USB bus and the other end connected to a DC power supply. The sixth indicator unit is located on the motherboard, with one end connected to the negative data terminal of the USB bus and the other end connected to a DC power supply. When both the fifth and sixth indicator units issue indications, the USB bus interface is functioning normally.

2. The testing apparatus according to claim 1, characterized in that, The testing apparatus includes: A connector having multiple connection pins; One end of the first connection pin is connected to the status indication interface, and the other end is connected to the output terminal of the cryptographic module that outputs a signal indicating its working status; One end of the second connection pin is connected to the key destruction interface, and the other end is connected to the key destruction interface of the cryptographic module; One end of the third connection pin is connected to the serial port transmitter on the motherboard and the other end is connected to the serial port transmitter of the password module; One end of the fourth connection pin is connected to the serial port receiver on the motherboard and the other end is connected to the serial port receiver of the password module. One end of the fifth connection pin is connected to the serial data line interface on the motherboard, and the other end is connected to the serial data line interface of the cryptographic module. One end of the sixth connection pin is connected to the serial clock line interface on the motherboard, and the other end is connected to the serial clock line interface of the cryptographic module. One end of the seventh connection pin is connected to the positive data terminal of the USB bus on the motherboard, and the other end is connected to the positive data terminal of the USB bus of the password module; One end of the eighth connection pin is connected to the negative data terminal of the USB bus on the motherboard, and the other end is connected to the negative data terminal of the USB bus of the password module.

3. A testing method for a gateway device, comprising testing the gateway device using the testing apparatus described in claim 1 or 2, the testing method comprising: S1: Test whether the communication between AP and CP is normal. If yes, proceed to S2. If no, check the motherboard and the communication module between AP and CP, and return to S1. S2: Perform signal testing on the external secure interface; The test is completed when the working status indicator unit issues an indication when the first test button is pressed, when the second indicator unit issues an indication when the key destruction switch is lightly pressed, and when the key injection signal transmission test channel is connected. If the working status indicator unit does not issue an indication when the first test button is pressed, and / or the second indicator unit does not issue an indication when the key destruction switch is lightly pressed, proceed to S3; If the key injection signal transmission test path is not connected, proceed to S4; S3: Determine if the open communication module between AP and CP is faulty. If yes, replace the open communication module. If no, proceed to S4. S4: After determining that the motherboard is faulty and replacing the motherboard, return to S1.

4. The test method for gateway devices according to claim 3, characterized in that, The test method for the gateway device also includes testing the key injection signal transmission test path, specifically: If at least one of the first key injection signal transmission test path, the second key injection signal transmission test path, and the third key injection signal transmission test path is not connected, it indicates that the key injection signal transmission test path is not connected.

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