SIC IGBT device and preparation method thereof

Abstract

The invention provides an SIC IGBT device and a preparation method thereof. The device comprises a substrate; the collector region of the first doping type is formed above the substrate; the epitaxial layer of the SIC material of the second doping type is formed above the collector region; the base region is formed downwards from the epitaxial layer; the emitting electrode is formed on the base region; the collector region leading-out structure is provided with metal and an insulating structure, the collector region leading-out structure is connected to the collector region from the top of the emitting electrode downwards, and the metal of the collector region leading-out structure is electrically connected with the collector region; and the insulation structure of the collector region lead-out structure is connected with the emitter, the base region and the epitaxial layer so as to realize insulation among metal of the emitter, the base region, the epitaxial layer and the collector region lead-out structure. The technical problem that a traditional SiC IGBT device is basically a high-voltage device and is not suitable for middle and low voltages is urgently needed to be solved by technicians in the field is solved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a SIC IGBT device and a method for preparing the same. Background Art

[0002] As ultra-high voltage power electronic systems put forward higher requirements in terms of high withstand voltage, high power, high switching speed, high operating temperature and small size, the limitations of silicon power devices are becoming more and more obvious. Compared with traditional silicon materials (Si), silicon carbide (SiC) has significant advantages in bandgap width, thermal conductivity, breakdown voltage and electron saturation drift rate. Specifically, the bandgap width of SiC is 3 times that of Si, the thermal conductivity is 4-5 times that of Si, the breakdown voltage is 8-10 times that of Si, and the electron saturation drift rate is 2-3 times that of Si. These advantages make SiC a very promising new semiconductor material with broad application prospects.

[0003] Currently, there are mainly SiC MOSFET devices and diodes, while SiC IGBTs are mainly high-voltage devices with a breakdown voltage generally greater than 10KV.

[0004] Traditional SiC IGBT devices, such as Figure 1 As shown, P-collector region 1-1, N-drift region 1-2, P-type super junction region 1-3, N-type second epitaxy 1-4, gate oxide layer 1-5, gate 1-6, Pwell 1-7, N+ emitter 1-8, dielectric layer 1-9, emitter metal 1-10, P+ collector 1-11, collector metal 1-12.

[0005] Since SIC materials have a wide bandgap and high critical breakdown field strength, the withstand voltage of SIC IGBT devices manufactured according to the thickness allowed by normal processes (above 50μm) is above 4500V. The thicker the thickness, the larger the saturation voltage Vcesat of the IGBT device. Figure 1 As shown, due to the large thickness of the drift region 1 - 2 , the drift region 1 - 2 can already play a supporting role, that is, the drift region 1 - 2 also serves as a substrate.

[0006] Although SiC materials have many advantages, the current process capabilities limit their development. Currently, the thickness of SiC devices is only over 100 microns. In addition, due to the limitation of liquid phase crystal growth technology, the substrate type of SiC materials is N-type, and the development of P-type substrates is relatively lagging. This has led to the fact that the current SiC IGBT devices are mainly high-voltage devices, with a breakdown voltage generally greater than 10KV, and there are no vertical SiC IGBT devices in the medium and low voltage range.

[0007] Therefore, traditional SiC IGBT devices are basically high-voltage devices and are not suitable for medium and low voltages, which is a technical problem that technical personnel in this field urgently need to solve.

[0008] The above information disclosed in the background section is only for enhancing understanding of the background of the present application and therefore it may contain information that does not form the prior art known to a person of ordinary skill in the art. Summary of the invention

[0009] The present application provides a SIC IGBT device and a preparation method thereof. Traditional SiC IGBT devices are basically high-voltage devices and are not suitable for medium and low voltages, which is a technical problem that technical personnel in this field urgently need to solve.

[0010] The present application provides a SIC IGBT device, including:

[0011] substrate;

[0012] A collector region of a first doping type formed above the substrate;

[0013] an epitaxial layer of SIC material of a second doping type formed above the collector region;

[0014] A base region formed downward from the epitaxial layer;

[0015] an emitter formed on the base region;

[0016] A collector lead-out structure having a metal and insulating structure is formed downward from the top of the emitter and connected to the collector region, the metal of the collector lead-out structure is electrically connected to the collector region, and the insulating structure of the collector lead-out structure is connected to the emitter, the base region, and the epitaxial layer to achieve insulation between the emitter, the base region, the epitaxial layer, and the metal of the collector lead-out structure.

[0017] This application also provides the following technical solutions:

[0018] A method for preparing a SIC IGBT device comprises the following steps:

[0019] forming a substrate insulating layer over the substrate;

[0020] forming a collector region of a first doping type on the substrate insulating layer;

[0021] forming an epitaxial layer of a SIC material of a second doping type over the collector region;

[0022] forming a base region downward from the epitaxial layer;

[0023] forming an emitter on the base region;

[0024] A collector lead-out structure having a metal and an insulating structure is formed, wherein the collector lead-out structure is formed downward from the top of the emitter and connected to the collector region, the metal of the collector lead-out structure is electrically connected to the collector region, and the insulating structure of the collector lead-out structure is connected to the emitter, the base region, and the epitaxial layer to achieve insulation between the emitter, the base region, the epitaxial layer, and the metal of the collector lead-out structure.

[0025] Due to the adoption of the above technical solution, this application has the following technical effects:

[0026] The SIC IGBT device of the present application adopts a method of connecting the collector region from the front of the device, and the specific method is a collector region lead-out structure with a metal and an insulating structure. The collector region lead-out structure is formed downward from the top of the emitter 11 to connect to the collector region 3, the metal of the collector region lead-out structure is electrically connected to the collector region 3, and the insulating structure of the collector region lead-out structure is connected to the emitter 11, the base region 8, and the epitaxial layer 5 to achieve insulation between the emitter 11, the base region 8, the epitaxial layer 5, and the metal of the collector region lead-out structure.

[0027] Compared with the traditional SIC IGBT device, the SIC IGBT device of the present application realizes the upward lifting of the collector region, and the collector region is located above the substrate. When the collector region is connected to a positive potential, in the process of injecting holes from the collector region to the emitter, the holes do not need to pass through the substrate, but need to pass through the epitaxial layer to reach the emitter, that is, the thickness of the SIC material that the holes need to pass through is only the thickness of the epitaxial layer. In this way, the breakdown voltage of the SIC IGBT device of the present application can be relatively low, and it is suitable for SIC IGBT devices in the medium and low voltage range.

[0028] The structural form of the SiC IGBT device of the present application is suitable for medium and low voltage SiC IGBT devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0030] Figure 1 Schematic diagram of a traditional SiC IGBT device;

[0031] Figure 2 Schematic diagram of the SIC IGBT device of the present application.

[0032] Reference numerals:

[0033] In the background technology:

[0034] P-collector region 1-1, N-drift region 1-2, P-type super junction region 1-3, N-type second epitaxy 1-4,

[0035] Gate oxide layer 1-5, gate 1-6, Pwell 1-7, N+ emitter 1-8, dielectric layer 1-9,

[0036] Emitter metal 1-10, P+ collector 1-11, collector metal 1-12;

[0037] In this application:

[0038] Substrate 1, substrate insulating layer 2, collector region 3, buffer layer 4, epitaxial layer 5, gate oxide layer 6,

[0039] Gate electrode 7, base region 8, emitter region 9, dielectric layer 10, emitter 11,

[0040] Collector metal insulating layer 12 , collector region contact region 13 , collector metal 14 . DETAILED DESCRIPTION

[0041] In order to make the technical solutions and advantages of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other without conflict.

[0042] In traditional IGBT devices, the collector region is located on the back side of the substrate.

[0043] Embodiment 1

[0044] like Figure 2 As shown, the SIC IGBT device of the present application includes:

[0045] Substrate 1;

[0046] A substrate insulating layer 2, formed on the substrate 1;

[0047] A collector region 3 of a first doping type, formed on the substrate insulating layer 2;

[0048] An epitaxial layer 5 of a second doping type SIC material is formed above the collector region 3;

[0049] A base region 8 formed downward from the epitaxial layer 5;

[0050] An emitter 11, formed on the base region 8;

[0051] A collector lead-out structure having a metal and insulating structure is formed downwardly from the top of the emitter 11 and connected to the collector region 3. The metal of the collector lead-out structure is electrically connected to the collector region 3. The insulating structure of the collector lead-out structure is connected to the emitter 11, the base region 8, and the epitaxial layer 5 to achieve insulation between the emitter 11, the base region 8, the epitaxial layer 5, and the metal of the collector lead-out structure.

[0052] In the SIC IGBT device of the present application, the substrate 1 is the supporting structure of the entire SIC IGBT device, and the front side of the substrate 1 is provided with a substrate insulating layer 2, a collector region 3, an epitaxial layer 5, a base region 8 and an emitter 11 in sequence from bottom to top. The SIC IGBT device of the present application adopts a method of connecting the collector region from the front side of the device, and the specific method is a collector region lead-out structure having a metal and insulating structure. The collector region lead-out structure is formed downward from the top of the emitter 11 to connect to the collector region 3, the metal of the collector region lead-out structure is electrically connected to the collector region 3, and the insulating structure of the collector region lead-out structure is connected to the emitter 11, the base region 8, and the epitaxial layer 5 to achieve insulation between the emitter 11, the base region 8, the epitaxial layer 5 and the metal of the collector region lead-out structure.

[0053] like Figure 1 As shown, the substrate of the conventional SIC IGBT device is composed of Figure 1 The drift region 1-2 also serves as the collector region 1-1, which is arranged on the back side of the substrate. When the collector region is connected to a positive potential, during the process of the collector region 1-1 injecting holes into the N+ emitter 1-8, the holes need to pass through the substrate and the N-type second epitaxy 1-4 before reaching the N+ emitter 1-8. The substrate and the N-type second epitaxy 1-4 are both SIC materials, and the substrate as a supporting structure of the device requires a larger thickness. In this way, the thickness of the SIC material that the holes need to pass through (the sum of the thickness of the substrate and the N-type second epitaxy 1-4) is larger as a whole. In addition, the characteristic of the strong critical breakdown electric field of the SIC material itself leads to a larger breakdown voltage of the traditional SIC IGBT device.

[0054] Compared with the traditional SIC IGBT device, the SIC IGBT device of the present application realizes the upward lifting of the collector region, and the collector region is located above the substrate. When the collector region is connected to a positive potential, in the process of injecting holes from the collector region to the emitter, the holes do not need to pass through the substrate, but need to pass through the epitaxial layer to reach the emitter, that is, the thickness of the SIC material that the holes need to pass through is only the thickness of the epitaxial layer. In this way, the breakdown voltage of the SIC IGBT device of the present application can be relatively low, and it is suitable for SIC IGBT devices in the medium and low voltage range.

[0055] In the SIC IGBT device of the present application, the substrate insulating layer is provided to insulate the collector region 3 of the first doping type from the substrate, so that when the collector region is connected to a positive potential, during the process of injecting holes from the collector region to the emitter, the holes cannot be injected into the substrate due to the presence of the substrate insulating layer 2. If the holes are injected into the substrate, the efficiency of hole injection into the epitaxial layer will be low, thereby making the on-state voltage drop of the device higher.

[0056] The structural form of the SiC IGBT device of the present application is suitable for medium and low voltage SiC IGBT devices.

[0057] In implementation, such as Figure 2 As shown, the collector region lead-out structure includes:

[0058] A collector region contact region 13 of a first doping type, wherein the collector region contact region 13 is formed in the collector region 3; wherein the doping concentration of the collector region contact region 13 is greater than the doping concentration of the collector region 3;

[0059] A collector metal 14 is formed downward from the emitter 11, and the bottom of the collector metal 14 reaches the inner bottom surface of the collector contact region 13;

[0060] A collector metal insulating layer 12 is formed downward from the emitter 11, and the bottom of the collector metal insulating layer 12 reaches the outer top surface of the collector contact area 13;

[0061] The collector metal is the metal of the collector region lead-out structure, and the collector metal insulating layer 12 serves as the insulating structure of the collector region lead-out structure.

[0062] The doping concentration of the collector region contact area 13 is greater than the doping concentration of the collector region 3, so that the contact resistance between the collector metal 14 and the collector region contact area 13 is small. The contact area between the collector region contact area 13 and the collector region 3 is also large. As a result, the resistance of the connection between the first doping type collector region 3, the first doping type collector region contact area 13, and the collector metal 14 is small. The collector metal 14 is connected to the collector region 3 through the collector region contact area 13, and the collector region 3 is connected from the front side of the device.

[0063] In implementation, such as Figure 2 As shown, it also includes:

[0064] A buffer layer 4 of the second doping type is formed on the collector region 3 and below the epitaxial layer 5; correspondingly:

[0065] The collector contact region 13 is also formed in the buffer layer 4, and the collector metal 14 is surrounded by the collector metal insulating layer 12 and the collector contact region 13;

[0066] When the collector region is connected to a positive potential, the collector region 3 and the collector region contact region 13 inject holes into the buffer layer 4 and the epitaxial layer 5 respectively.

[0067] The buffer layer 4 is used to improve the voltage blocking capability of the device and reduce the on-state voltage drop.

[0068] When the buffer layer 4 is provided, the collector region contact area 13 is correspondingly also formed in the buffer layer 4. This ensures that the collector metal 14 is always surrounded by the collector metal insulating layer 12 and the collector region contact area 13. It is possible to avoid direct connection between the buffer layer 4 and the collector metal 14. That is, it is ensured that the collector region metal 14 is only in direct contact with the collector region contact area 13 and not in direct contact with the buffer layer 4.

[0069] In implementation, such as Figure 2 As shown, the collector region lead-out structure further includes:

[0070] A first trench is formed downward from the emitter 11, and the bottom of the first trench reaches the lower surface of the epitaxial layer 5;

[0071] A second trench, wherein the first trench is filled with an insulating material to form an insulating material layer, and a second trench is formed in the middle of the insulating material layer, wherein the bottom of the second trench reaches the upper surface of the substrate insulating layer 2;

[0072] The collector region contact region 13 is formed by implantation on the sidewall of the second trench which is deeper than the first trench, and the collector region contact region 13 is formed in the collector region 3; wherein the doping concentration of the collector region contact region 13 is greater than the doping concentration of the collector region 3;

[0073] The collector metal 14 is filled in the second trench and on the collector contact region 13 , and the portion of the insulating material layer after the second trench is formed serves as the collector metal insulating layer 12 .

[0074] When the collector region is connected to a positive potential, both the collector region 3 and the collector region contact region 13 inject holes into the epitaxial layer 5 .

[0075] The collector contact region 13 is formed by injection, and the doping concentration of the collector contact region 13 is greater than the doping concentration of the collector region 3, so that the contact resistance between the collector metal 14 and the collector contact region 13 is small. The contact area between the collector contact region 13 and the collector region 3 is also large. As a result, the resistance of the connection between the first doping type collector region 3, the first doping type collector contact region 13, and the collector metal 14 is small. The collector metal 14 is connected to the collector region 3 through the collector contact region 13, and the collector region 3 is connected from the front of the device.

[0076] As a more preferred way, the collector metal 14 forms an ohmic contact with the collector region contact region 13. In this way, the contact resistance between the collector metal 14 and the collector region contact region 13 is very small.

[0077] The arrangement of the first trench, the second trench, and the collector metal insulating layer 12 realizes that the collector metal 14 is connected to the collector region 3 through the collector region contact region 13 while the collector metal 14 and the epitaxial layer 5 are insulated.

[0078] Another function of providing the substrate insulating layer is to control the depth of the second trench. Specifically, the bottom of the second trench reaches the upper surface of the substrate insulating layer 2 .

[0079] In implementation, such as Figure 2 As shown, the collector region 3 of the first doping type, the collector region contact region 13 of the first doping type, and the collector metal 14 are connected to connect the collector region 3 out from the top of the SIC IGBT device.

[0080] In implementation, such as Figure 2 As shown, when the buffer layer 4 is set, the corresponding:

[0081] The bottom of the first trench reaches into the buffer layer 4;

[0082] The collector region contact region 13 is also formed in the buffer layer 4, and the sidewall of the second trench deeper than the first trench is completely surrounded by the collector region contact region 13, so that the collector metal 14 is surrounded by the collector metal insulating layer 12 and the collector region contact region 13;

[0083] When the collector region is connected to a positive potential, the collector region 3 and the collector region contact region 13 inject holes into the buffer layer 4 and the epitaxial layer 5 respectively.

[0084] The buffer layer 4 is used to improve the voltage blocking capability of the device and reduce the on-state voltage drop.

[0085] The reason why the bottom of the first trench cannot exceed the buffer layer 4 is that if the first trench exceeds the buffer layer, it will enter the collector region 3. In the process of filling and depositing the insulating material in the first trench to form an insulating material layer and forming the second trench in the middle of the insulating material layer, it is difficult to remove the insulating material layer on the side wall of the collector region 3, resulting in the collector region 3 being unable to be connected to the collector region contact area 13 and the collector metal 14. That is, the collector region 3 cannot be connected.

[0086] The reason why the collector metal 14 is surrounded by the collector metal insulating layer 12 and the collector contact region 13 is that:

[0087] If the buffer layer 4 is directly connected to the collector metal 14 , the collector region 3 and the buffer layer 4 are at the same potential, there is no potential difference at the PN junction, and the collector region contact region 13 will not inject holes.

[0088] Therefore, the SIC IGBT device of the present application adds an injection to form the collector contact region 13 before depositing the collector metal 14, which can avoid direct connection between the buffer layer 4 and the collector metal 14. That is, it is ensured that the collector metal 14 is only in direct contact with the collector contact region 13 and not in direct contact with the buffer layer 4.

[0089] In the implementation, the doping concentration of the collector contact region 13 has a value range of greater than or equal to 10 18 cm -3 Less than or equal to 10 19 cm -3 ;

[0090] The doping concentration of the collector region 3 has a value range of greater than or equal to 10 17 cm -3 Less than or equal to 10 19 cm -3 .

[0091] The doping concentration of the collector contact region 13 is greater than the doping concentration of the buffer layer 4 , so that the contact resistance between the collector metal 14 and the collector contact region 13 is smaller than the contact resistance between the collector metal 14 and the buffer layer 4 directly.

[0092] The collector region doping concentration ensures that the collector region has appropriate injection efficiency.

[0093] Specifically, Figure 2 As shown, the SIC IGBT device of the present application also includes:

[0094] A gate trench is formed in the base region 8 and the epitaxial layer 5;

[0095] A gate oxide layer 6, formed on the bottom and sidewalls of the gate trench;

[0096] A gate electrode 7 formed in the gate oxide layer 6;

[0097] An emitter region 9 of a second doping type is formed on both sides of the gate trench;

[0098] The dielectric layer 10 is formed on the gate electrode 7 .

[0099] Specifically, the base region 8 is a base region 8 of the first doping type.

[0100] Specifically, in the present application, the first doping type is P-type, and the second doping type is N-type.

[0101] The SIC IGBT device of the present application realizes the preparation of SIC IGBT devices in the medium and low voltage range. Compared with SI IGBT devices, the thermal conductivity is 4-5 times that of SI IGBT devices, the heat dissipation effect is good, and it can work at a higher temperature. In addition, compared with lateral SIC IGBT devices, it can reduce the chip area and improve the power density.

[0102] The method for preparing the SIC IGBT device of the present application is characterized by comprising the following steps:

[0103] forming a substrate insulating layer 2 on the substrate 1;

[0104] forming a collector region 3 of a first doping type on the substrate insulating layer 2;

[0105] forming an epitaxial layer 5 of a SIC material of a second doping type on the collector region 3;

[0106] A base region 8 is formed downward from the epitaxial layer 5;

[0107] An emitter 11 is formed on the base region 8;

[0108] A collector lead-out structure having a metal and insulating structure is formed, wherein the collector lead-out structure is formed downward from the top of the emitter 11 and connected to the collector region 3, the metal of the collector lead-out structure is electrically connected to the collector region 3, and the insulating structure of the collector lead-out structure is connected to the emitter 11, the base region 8, and the epitaxial layer 5 to achieve insulation between the emitter 11, the base region 8, the epitaxial layer 5, and the metal of the collector lead-out structure.

[0109] In practice, the method for preparing the SIC IGBT device further includes the following steps:

[0110] forming a buffer layer 4 of a second doping type on the collector region 3 and below the epitaxial layer 5;

[0111] A first trench is formed downward from the emitter 11, and the bottom of the first trench reaches the lower surface of the buffer layer 4;

[0112] forming a second trench, filling and depositing an insulating material in the first trench to form an insulating material layer, forming a second trench in the middle of the insulating material layer, and the bottom of the second trench reaches the upper surface of the substrate insulating layer 2;

[0113] Forming a collector region contact region 13 of a first doping type, forming the collector region contact region 13 by implantation on the sidewall of a portion of the second trench that is deeper than the first trench, and the collector region contact region 13 is formed in the collector region 3; wherein the doping concentration of the collector region contact region 13 is greater than the doping concentration of the collector region 3;

[0114] Forming a collector metal 14, filling the second trench and on the collector contact region 13, the portion of the insulating material layer after the second trench is formed serves as a collector metal insulating layer 12;

[0115] The collector metal is the metal of the collector region lead-out structure, and the collector metal insulating layer 12 serves as the insulating structure of the collector region lead-out structure.

[0116] In chronological order, the method for preparing the SIC IGBT device of the present application comprises the following steps:

[0117] 1. Grow a thin substrate insulating layer 2, such as SiO2 or SiN3, on an N+ type SIC substrate 1;

[0118] 2. Epitaxially grow a P+ layer on the substrate insulating layer 2 to form a collector region 3;

[0119] 3. Growing an N-type layer with a higher doping concentration on the collector region 3 as a buffer layer 4;

[0120] 4. Depositing an N-type epitaxial layer 5 on the buffer layer 4;

[0121] 5. Perform trench etching on the upper surface of the N-type epitaxial layer 5, then grow an oxide layer to form a gate oxide layer 6, and deposit poly to form a gate electrode 7;

[0122] 6. Forming a P-type base region 8 by ion implantation;

[0123] 7. Forming an N+ emitter region 9 by ion implantation;

[0124] 8. Depositing a dielectric layer 10 on the upper surface and depositing metal to form an emitter 11;

[0125] 9. Perform the first trench etching from the upper surface of the emitter 11 to form a first trench, the depth of which reaches the buffer layer 4, and deposit an insulating layer;

[0126] 10. Perform a second etching from the middle of the upper surface of the insulating layer to form a second groove, the depth of which reaches the upper surface of the substrate insulating layer 2;

[0127] 11. Perform ion implantation at the bottom of the trench to form a P+ region as a collector contact region 13; deposit metal in the second trench to form a collector metal 14.

[0128] The simulation data comparison between the SIC IGBT device of the present application and the traditional SIC IGBT device is shown in the following table:

[0129]

[0130]

[0131] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0132] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0133] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0134] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0135] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0136] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A SICIGBT device, characterized in that: include: Substrate (1); A collector region (3) of a first doping type, formed above the substrate (1); An epitaxial layer (5) of SIC material of a second doping type is formed above the collector region (3); A base region (8) formed downward from the epitaxial layer (5); An emitter (11) formed on the base region (8); A collector region lead-out structure having a metal and insulating structure is formed downward from the top of the emitter (11) and connected to the collector region (3); the metal of the collector region lead-out structure is electrically connected to the collector region (3); and the insulating structure of the collector region lead-out structure is connected to the emitter (11), the base region (8), and the epitaxial layer (5) to achieve insulation between the emitter (11), the base region (8), the epitaxial layer (5), and the metal of the collector region lead-out structure.

2. The SICIGBT device according to claim 1, characterized in that: Also includes: A substrate insulating layer (2) formed between the substrate (1) and the collector region (3); The substrate insulating layer (2) is used to insulate the collector region (3) from the substrate (1).

3. The SIC IGBT device according to claim 2, characterized in that: The collector region lead-out structure comprises: A collector region contact region (13) of a first doping type, the collector region contact region (13) being formed in the collector region (3); wherein the doping concentration of the collector region contact region (13) is greater than the doping concentration of the collector region (3); A collector metal (14) is formed downward from the emitter (11), and the bottom of the collector metal (14) reaches the inner bottom surface of the collector contact area (13); A collector metal insulating layer (12) is formed downward from the emitter (11), and the bottom of the collector metal insulating layer (12) reaches the outer top surface of the collector region contact area (13); The collector metal is the metal of the collector region lead-out structure, and the collector metal insulating layer (12) serves as the insulating structure of the collector region lead-out structure.

4. The SICIGBT device according to claim 3, characterized in that: Also includes: A buffer layer (4) of a second doping type is formed on the collector region (3) and below the epitaxial layer (5); correspondingly: The collector region contact region (13) is also formed in the buffer layer (4), and the collector metal (14) is surrounded by the collector metal insulating layer (12) and the collector region contact region (13); When the collector region is connected to a positive potential, the collector region (3) and the collector region contact region (13) inject holes into the buffer layer (4) and the epitaxial layer (5) respectively.

5. The SICIGBT device according to claim 4, characterized in that: The collector region lead-out structure further includes: A first trench is formed downward from the emitter (11), the bottom of the first trench reaches the lower surface of the epitaxial layer (5), and an insulating material is deposited in the first trench to form an insulating material layer; A second groove is formed in the middle of the insulating material layer, and the bottom of the second groove reaches the upper surface of the substrate insulating layer (2); The collector region contact area (13) is formed by injection on the side wall of the second trench which is deeper than the first trench; the collector metal (14) is filled in the second trench and on the collector region contact area (13), and the insulating material layer after the second trench is formed serves as a collector metal insulating layer (12).

6. The SICIGBT device according to claim 5, characterized in that: A collector region (3) of a first doping type, a collector region contact region (13) of a first doping type, and a collector metal (14) are connected to connect the collector region (3) out from the top of the SICIGBT device.

7. The SIC IGBT device according to any one of claims 3 to 5, characterized in that: The doping concentration of the collector contact region (13) has a value range of greater than or equal to 10 18 cm -3 Less than or equal to 10 19 cm -3 ; The doping concentration of the collector region (3) has a value range of greater than or equal to 10 17 cm -3 Less than or equal to 10 19 cm -3 ; Furthermore, the doping concentration of the collector region contact area (13) is greater than the doping concentration of the buffer layer (4).

8. The SICIGBT device according to claim 5, characterized in that: The bottom of the first trench reaches into the buffer layer (4).

9. A method for preparing a SICIGBT device, characterized in that: The steps include: forming a substrate insulating layer (2) on the substrate (1); Forming a collector region (3) of a first doping type on the substrate insulating layer (2); forming an epitaxial layer (5) of a SIC material of a second doping type on the collector region (3); forming a base region (8) downward from the epitaxial layer (5); forming an emitter (11) on the base region (8); A collector region lead-out structure having a metal and an insulating structure is formed, wherein the collector region lead-out structure is formed downward from the top of the emitter (11) and connected to the collector region (3), the metal of the collector region lead-out structure is electrically connected to the collector region (3), and the insulating structure of the collector region lead-out structure is connected to the emitter (11), the base region (8), and the epitaxial layer (5) to achieve insulation between the emitter (11), the base region (8), the epitaxial layer (5), and the metal of the collector region lead-out structure.

10. The method for preparing a SIC IGBT device according to claim 9, characterized in that: The following steps are also included: forming a buffer layer (4) of a second doping type on the collector region (3) and below the epitaxial layer (5); forming a first trench, which is formed downward from the emitter (11), and the bottom of the first trench reaches the lower surface of the buffer layer (4); forming a second trench, filling and depositing an insulating material in the first trench to form an insulating material layer, forming a second trench in the middle of the insulating material layer, the bottom of the second trench reaching the upper surface of the substrate insulating layer (2); Forming a collector region contact region (13) of a first doping type, forming the collector region contact region (13) by implantation on the sidewall of a portion of the second trench that is deeper than the first trench, and the collector region contact region (13) is formed in the collector region (3); wherein the doping concentration of the collector region contact region (13) is greater than the doping concentration of the collector region (3); A collector metal (14) is formed and filled in the second groove and on the collector region contact area (13), and the portion of the insulating material layer after the second groove is formed serves as a collector metal insulating layer (12); wherein the collector metal is the metal of the collector region lead-out structure, and the collector metal insulating layer (12) serves as an insulating structure of the collector region lead-out structure.

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