A method for preparing RF-SOI device, device and electronic equipment

Abstract

The present invention provides a method for preparing an RF-SOI device, a device and an electronic device. The method completes the preparation of a capacitor groove and a capacitor lower plate while preparing an existing charge extraction structure, realizes the sharing of process steps, thereby saving the process steps for preparing the capacitor and reducing the manufacturing cost. In addition, since a first polysilicon layer is provided on the surface of a shallow trench isolation structure corresponding to the capacitor groove, the first polysilicon layer surrounds the capacitor groove. Therefore, by providing a corresponding metal wiring structure on the first polysilicon layer, a ring connection between the outside world and the capacitor lower plate can be formed, which increases the connection between the outside world and the lower plate, thereby improving the stability of the capacitor.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit manufacturing, and in particular to a method for preparing an RF-SOI device, the device and an electronic device. Background Art

[0002] With the development of 5G technology, the demand for high-frequency bands has increased, which has led to an increase in the number of antennas and antenna tuners. In order to meet this demand, more capacitor devices need to be integrated in a given antenna module area. Therefore, it is crucial to integrate more capacitors in a limited area.

[0003] However, in the process of preparing capacitors in RF-SOI (Radio Frequency Silicon On Insulator) devices, the prior art RF-SOI process usually requires the additional setting of multiple photomasks and the addition of multiple process steps, thereby increasing the manufacturing cost.

[0004] Therefore, providing a method for preparing an RF-SOI device that can reduce process steps and lower capacitor manufacturing costs has become a technical problem that the industry urgently needs to solve. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a method for preparing an RF-SOI device, a device and an electronic device, which solves the problem of high manufacturing cost in the process of preparing capacitors in RF-SOI devices in the prior art.

[0006] In order to solve the above technical problems, an embodiment of the present invention provides a method for preparing an RF-SOI device.

[0007] The method includes:

[0008] Providing an SOI substrate, comprising a silicon substrate, a buried oxide layer and a top silicon layer stacked in sequence;

[0009] A device layer is formed in the top silicon layer, and an interlayer dielectric layer is formed on the surface of the device layer, wherein the device layer includes: a shallow trench isolation structure, a source region, a drain region, a gate of the same preset height, and a first polysilicon layer, and includes: a conductive contact layer formed on the surface of the gate, the first polysilicon layer, and the source region and the drain region, wherein the first polysilicon layer covers the surface of the preset shallow trench isolation structure;

[0010] A capacitor trench and a charge extraction trench are simultaneously formed in the SOI substrate, wherein the capacitor trench and the charge extraction trench extend from the top surface of the interlayer dielectric layer to the silicon substrate; wherein the capacitor trench passes through the preset shallow trench isolation structure and the first polysilicon layer surrounds the capacitor trench;

[0011] A second polysilicon layer and a first metal layer are sequentially stacked on the sidewalls and bottoms of the capacitor trench and the charge extraction trench to serve as a lower plate of the capacitor;

[0012] forming a dielectric layer on a surface of the first metal layer corresponding to the capacitor groove and on surfaces of the first metal layer at both sides of the capacitor groove;

[0013] Filling the capacitor trench and the charge extraction trench with a second metal layer to serve as an upper plate of the capacitor;

[0014] A metal wiring structure is formed on the conductive contact layer and the second metal layer.

[0015] Optionally, forming a capacitor trench and a charge extraction trench simultaneously in the SOI substrate specifically includes:

[0016] Forming a patterned first mask layer on the interlayer dielectric layer, the patterned first mask layer comprising a capacitor trench window region, a charge extraction trench window region and a blocking region, wherein the capacitor trench window region corresponds to the preset shallow trench isolation structure, and the charge extraction trench window region corresponds to another shallow trench isolation structure;

[0017] Using the patterned first mask layer as a mask, the interlayer dielectric layer, the first polysilicon layer, the preset shallow trench isolation structure, the buried oxide layer and the silicon substrate in the capacitor trench window area are etched in sequence, and the etching end point stays in the silicon substrate to form the capacitor trench; at the same time, the interlayer dielectric layer, the shallow trench isolation structure, the buried oxide layer and the silicon substrate in the charge extraction trench window area are etched in sequence, and the etching end point stays in the silicon substrate to form the charge extraction trench.

[0018] Optionally, the size of each of the capacitor trench and the charge extraction trench is smaller than the size of the corresponding shallow trench isolation structure.

[0019] Optionally, the size of the capacitor groove is greater than or equal to the size of the charge extraction groove.

[0020] Optionally, forming a dielectric layer on a surface of the first metal layer corresponding to the capacitor groove and on surfaces of the first metal layer on both sides of the capacitor groove specifically includes:

[0021] A patterned second mask layer is formed on the surface of the interlayer dielectric layer, wherein the patterned second mask layer includes a dielectric layer window region and a blocking region; wherein the dielectric layer window region corresponds to the capacitor trench and the surface of the first metal layer on both sides of the capacitor trench;

[0022] Depositing a dielectric layer using the patterned second mask layer as a mask;

[0023] The patterned second mask layer is removed.

[0024] Optionally, forming a metal wiring layer on the conductive contact layer and the second metal layer specifically includes:

[0025] forming at least one first contact hole, wherein a first end of each of the first contact holes is connected to a corresponding conductive contact layer of the first polysilicon layer, and a second end of each of the first contact holes is flush with a surface of the interlayer dielectric layer;

[0026] At least one first metal block, at least one second metal block and a third metal block are formed on the surface of the interlayer dielectric layer, each of the first metal blocks corresponds to one of the first contact holes, and the first metal block is electrically connected to the second end of the corresponding first contact hole, each of the second metal blocks corresponds to one of the capacitor trenches, and the second metal block is electrically connected to the second metal layer in the corresponding capacitor trench; the third metal block is electrically connected to the second metal layer in the charge extraction trench.

[0027] Optionally, the forming of a metal wiring structure on the conductive contact layer and the second metal layer further includes:

[0028] forming a second contact hole, wherein a first end of the second contact hole is connected to a conductive contact layer corresponding to the source region, the drain region, and the surface of the gate, and a second end of the second contact hole is flush with the surface of the interlayer dielectric layer;

[0029] Fourth metal blocks are formed on the surface of the interlayer dielectric layer, each of the fourth metal blocks corresponds to one of the second contact holes, and the fourth metal blocks are electrically connected to the second ends corresponding to the second contact holes.

[0030] Optionally, the silicon substrate is a high-resistance trap-enriched substrate.

[0031] Optionally, the first metal layer includes titanium nitride; the second metal layer includes at least tungsten, titanium, titanium nitride, or a mixture of titanium and titanium nitride.

[0032] An embodiment of the present invention further provides an RF-SOI device, including:

[0033] An SOI substrate, wherein the SOI substrate comprises a silicon substrate, a buried oxide layer and a top silicon layer stacked in sequence;

[0034] A shallow trench isolation structure and a source region and a drain region of a device, wherein the shallow trench isolation structure and the source region and the drain region of the device are both located in the top silicon layer;

[0035] A gate and a first polysilicon layer of a preset height, wherein the gate and the first polysilicon layer of the preset height are both located on the surface of the top silicon layer, and the first polysilicon layer is located on the surface of a preset shallow trench isolation structure;

[0036] An interlayer dielectric layer, the interlayer dielectric layer covering the surface of the top silicon layer;

[0037] A conductive contact layer, wherein the conductive contact layer is respectively located on the surface of the gate, the first polysilicon layer, the source region, and the drain region;

[0038] At least one trench capacitor and a charge extraction structure, wherein the trench capacitor sequentially penetrates the interlayer dielectric layer, the first polysilicon layer, the preset shallow trench isolation structure, the buried oxide layer to the silicon substrate; the charge extraction structure sequentially penetrates the interlayer dielectric layer, the shallow trench isolation structure, the buried oxide layer to the silicon substrate; wherein the first polysilicon layer surrounds the trench capacitor; wherein the trench capacitor comprises a capacitor trench, and a second polysilicon layer, a first metal layer, a dielectric layer and a second metal layer sequentially stacked in the capacitor trench; the charge extraction structure comprises a charge extraction trench, and a second polysilicon layer, a first metal layer and a second metal layer sequentially stacked in the charge extraction trench;

[0039] A metal wiring layer, the metal wiring layer includes a metal wiring structure formed in the interlayer dielectric layer, the metal wiring structure includes: a first contact hole arranged around the trench capacitor and electrically connected to the conductive contact layer on the surface of the first polysilicon layer, and a first metal block connected to the first contact hole, a second contact hole electrically connected to the conductive contact layer on the surface of the gate and the source region and the drain region, and a fourth metal block connected to the second contact hole, and a second metal block and a third metal block respectively connected to the second metal layer in the trench capacitor and the second metal layer in the charge extraction structure.

[0040] An embodiment of the present invention further provides an electronic device, comprising the RF-SOI device.

[0041] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0042] In the preparation method of the RF-SOI device of the technical solution of the present invention, on the one hand, while preparing the existing charge extraction structure, the preparation of the capacitor groove and the capacitor lower plate is completed, and the process steps are shared, thereby saving the process steps for preparing the capacitor and reducing the manufacturing cost. On the other hand, since the surface of the shallow trench isolation structure corresponding to the capacitor groove is provided with a first polysilicon layer, so that the first polysilicon layer surrounds the capacitor groove. Therefore, by arranging the corresponding metal wiring structure on the first polysilicon layer, a ring connection between the outside world and the capacitor lower plate can be formed, which increases the connection between the outside world and the lower plate, thereby improving the stability of the capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 The process of the method for preparing the RF-SOI device provided by the embodiment of the present invention is Figure 1 ;

[0044] Figures 2 to 6 The following are simplified cross-sectional diagrams corresponding to different preparation stages of the method for preparing the RF-SOI device provided in the embodiment of the present invention: Figure 1 ;

[0045] Figure 7 The process of the method for preparing the RF-SOI device provided by the embodiment of the present invention is Figure 2 ;

[0046] Figures 8 to 10 The following are simplified cross-sectional diagrams corresponding to different preparation stages of the method for preparing the RF-SOI device provided in the embodiment of the present invention: Figure 2 ;

[0047] Fig.11 The process of the method for preparing the RF-SOI device provided by the embodiment of the present invention is Figure 3 ;

[0048] Figure 12 to Figure 13 The following are simplified cross-sectional diagrams corresponding to different preparation stages of the method for preparing the RF-SOI device provided in the embodiment of the present invention: Figure 3 ;

[0049] Fig.14 The process of the method for preparing the RF-SOI device provided by the embodiment of the present invention is Figure 4 ;

[0050] Fig.15 The process of the method for preparing the RF-SOI device provided by the embodiment of the present invention is Figure 5 ;

[0051] Figures 16 to 19 The following are simplified cross-sectional diagrams corresponding to different preparation stages of the method for preparing the RF-SOI device provided in the embodiment of the present invention: Figure 4 ;

[0052] Fig. 20 yes Fig.19 A top view of

[0053] Fig.21 The process of the method for preparing the RF-SOI device provided by the embodiment of the present invention is Figure 6 ;

[0054] Figure 22 to Figure 25 The following are simplified cross-sectional diagrams corresponding to different preparation stages of the method for preparing the RF-SOI device provided in the embodiment of the present invention: Figure 5 . DETAILED DESCRIPTION

[0055] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present invention. The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0056] As described in the background art, in the process of preparing capacitors in RF-SOI (Radio Frequency Silicon On Insulator) devices, the prior art RF-SOI process usually requires the additional setting of multiple masks and the addition of multiple process steps, thereby increasing the manufacturing cost.

[0057] In view of this, an embodiment of the present invention provides a new method for preparing an RF-SOI device, the method comprising:

[0058] Providing an SOI substrate, comprising a silicon substrate, a buried oxide layer and a top silicon layer stacked in sequence;

[0059] A device layer is formed in the top silicon layer, and an interlayer dielectric layer is formed on the surface of the device layer, wherein the device layer includes: a shallow trench isolation structure, a source region, a drain region, a gate of the same preset height, and a first polysilicon layer, and includes: a conductive contact layer formed on the surface of the gate, the first polysilicon layer, and the source region and the drain region, wherein the first polysilicon layer covers the surface of the preset shallow trench isolation structure;

[0060] A capacitor trench and a charge extraction trench are simultaneously formed in the SOI substrate, wherein the capacitor trench and the charge extraction trench extend from the top surface of the interlayer dielectric layer to the silicon substrate; wherein the capacitor trench passes through the preset shallow trench isolation structure and the first polysilicon layer surrounds the capacitor trench;

[0061] A second polysilicon layer and a first metal layer are sequentially stacked on the sidewalls and bottoms of the capacitor trench and the charge extraction trench to serve as a lower plate of the capacitor;

[0062] forming a dielectric layer on a surface of the first metal layer corresponding to the capacitor groove and on surfaces of the first metal layer at both sides of the capacitor groove;

[0063] Filling the capacitor trench and the charge extraction trench with a second metal layer to serve as an upper plate of the capacitor;

[0064] A metal wiring structure is formed on the conductive contact layer and the second metal layer.

[0065] Through the above technical means, in the process of preparing the capacitor in the RF-SOI device, the embodiment of the present invention not only saves process steps and reduces the manufacturing cost of the RF-SOI device, but also improves the stability of the capacitor in the RF-SOI device. The specific principle is as follows:

[0066] After completing the preparation of the shallow trench isolation structure and the interlayer dielectric layer in the RF-SOI device, the prior art also prepares a charge extraction structure that penetrates the interlayer dielectric layer, the shallow trench isolation structure, the buried oxide layer and even the silicon substrate to extract the charge accumulated on the surface of the silicon substrate during the device preparation process, thereby avoiding affecting the high-frequency application of the RF-SOI device.

[0067] The first step in preparing the charge extraction structure is to prepare the charge extraction groove. Therefore, in the embodiment of the present invention, while preparing the charge extraction groove, a capacitor groove is also prepared, so as to realize the reuse of the etching process and avoid the additional etching of the capacitor groove, thereby reducing the manufacturing cost of the RF-SOI device. At the same time, after completing the etching of the charge extraction groove, it is necessary to deposit the second polysilicon layer and the first metal layer on the sidewall of the groove. Therefore, while depositing the second polysilicon layer and the first metal layer on the sidewall of the charge extraction groove, the second polysilicon layer and the first metal layer are also deposited on the sidewall of the charge groove, so that the polysilicon layer and the first metal layer serve as the lower plate of the capacitor, thereby realizing the reuse of the deposition process and avoiding the additional deposition of the lower plate of the capacitor, thereby further reducing the manufacturing cost of the RF-SOI device.

[0068] Because the capacitor of the RF-SOI device in the embodiment of the present invention is a trench capacitor, and the capacitor of the RF-SOI device in the prior art is usually a MIM capacitor, that is, a flat capacitor. Therefore, compared with the prior art, the capacitor prepared in the embodiment of the present invention is located at the shallow trench isolation structure and is a trench capacitor, so it has a smaller footprint and does not occupy the device area of ​​the wafer, thereby improving the integration of the capacitor in the RF-SOI device. And because the magnetic field of the MIM capacitor of the RF-SOI device in the prior art is horizontally arranged, it will cause electrical coupling interference to the device in the horizontal position, thereby causing signal distortion. However, since the capacitor prepared in the embodiment of the present invention is a trench capacitor, the magnetic field of the capacitor itself is arranged vertically, and there is no device set in the vertical direction, thereby greatly reducing the electrical coupling interference to the device.

[0069] Furthermore, because a first polysilicon layer is formed on the surface of the preset shallow trench isolation structure corresponding to the capacitor trench, so that the first polysilicon layer surrounds the capacitor trench, a corresponding metal wiring structure is provided on the first polysilicon layer to form an annular connection between the outside world and the lower plate of the capacitor, thereby increasing the connection between the outside world and the lower plate, thereby improving the stability of the capacitor.

[0070] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0071] Figure 1 The process of the method for preparing the RF-SOI device provided by the embodiment of the present invention is Figure 1 .remove Figure 7 , Fig.11 , Fig.14 , Fig.15 , Fig. 20 and Fig.21 outside, Figures 2 to 25They are respectively simplified cross-sectional schematic diagrams corresponding to different preparation stages of the method for preparing an RF-SOI device provided by an embodiment of the present invention.

[0072] Please refer to Figures 1 to 24 The specific steps of the method for preparing the RF-SOI device provided in the embodiment of the present invention include the following:

[0073] S1: Provide an SOI substrate 101, such as Figure 2 shown.

[0074] Specifically, the SOI substrate 101, i.e., a silicon-on-insulator substrate, specifically includes a silicon substrate 1012 at the bottom, a buried oxide layer 1011 in the middle, and a top silicon layer 1013 at the top. The material of the buried oxide layer 1011 may include silicon dioxide, or other materials with insulating properties, which are not limited here. The top silicon layer 1013 is specifically single crystal silicon.

[0075] S2: On the top silicon layer 1013, a device layer 102 and an interlayer dielectric layer 103 are sequentially formed in a direction away from the top silicon layer 1013, such as Figure 3 shown.

[0076] The device layer 102 is specifically a front-end device structure of an RF-SOI device, and specifically includes: a shallow trench isolation structure, a source region, a drain region, a gate of a preset height, and a first polysilicon layer 1021. The shallow trench isolation structure is formed in the top silicon layer 1013, the source region and the drain region of the device are both formed in the top silicon layer 1013 between adjacent shallow trench isolation structures, the gate of a preset height is formed on the surface of the top silicon layer 1013 between the source region and the drain region of the device, and the first polysilicon layer 1021 is formed on the surface of the preset shallow trench isolation structure.

[0077] The device layer 102 further includes a conductive contact layer 1022 , and the conductive contact layer 1022 covers the gate, the source region, the drain region and the surface of the first polysilicon layer 1021 respectively.

[0078] Of course, the specific structure of the device layer 102 may vary according to different types of RF-SOI devices, and is not limited here. At the same time, because the preparation of the device layer 102 is a conventional technical means in the art, it will not be described in detail here.

[0079] The interlayer dielectric layer 103 is used to isolate the device layer 102 from the interconnection layer prepared by the back-end process, and the interlayer dielectric layer 103 specifically covers the surface of the top silicon layer 1013. The material of the interlayer dielectric layer 103 includes, but is not limited to, silicon oxide, silicon nitride, low dielectric constant materials, polymer materials, etc., which are not limited here.

[0080] S3: A capacitor trench and a charge extraction trench are simultaneously formed in the SOI substrate, wherein the capacitor trench and the charge extraction trench extend from the top surface of the interlayer dielectric layer to the silicon substrate; wherein the capacitor trench passes through the preset shallow trench isolation structure and the first polysilicon layer 1021 surrounds the capacitor trench.

[0081] Wherein, in S3, a capacitor trench and a charge extraction trench are simultaneously formed in the SOI substrate, which specifically includes the following steps:

[0082] S31: forming a patterned first mask layer 104 on the surface of the interlayer dielectric layer 103, wherein the patterned first mask layer 104 includes at least one capacitor trench window region 1041, a charge extraction trench window 1042 and a blocking region, wherein the capacitor trench window region 1041 corresponds to the first polysilicon layer 1021, that is, corresponds to the shallow trench isolation structure under the first polysilicon layer 1021, and the charge extraction trench window 1042 corresponds to any other shallow trench isolation structure, such as Figure 4 shown.

[0083] Specifically, forming the first mask layer 104 includes: applying photoresist on the surface of the interlayer dielectric layer 103. Placing a first mask plate on the surface of the photoresist, the first mask plate being provided with the capacitor trench window area 1041 and the charge extraction trench window 1042, and the rest being blocking areas. Exposing the photoresist using the first mask plate as a mask to remove the photoresist located in the capacitor trench window area 1041 and the charge extraction trench window 1042, so as to form the first mask layer 104.

[0084] S32: Using the patterned first mask layer 104 as a mask, the interlayer dielectric layer 103, the first polysilicon layer 1021, the preset shallow trench isolation structure, the buried oxide layer 1011 and the silicon substrate 1012 in the capacitor trench window area 1041 are etched in sequence, and the etching endpoint stays in the silicon substrate 1012 to form the capacitor trench 105. At the same time, the interlayer dielectric layer 103, the shallow trench isolation structure, the buried oxide layer 1011 and the silicon substrate 1012 in the charge extraction trench window 1042 are etched in sequence, and the etching endpoint stays in the silicon substrate 1012 to form the charge extraction trench 106, as shown in FIG. Figure 5 shown.

[0085] Wherein, in step S3, the size of each of the capacitor trench and the charge extraction trench is smaller than the size of the corresponding shallow trench isolation structure.

[0086] Wherein, in step S3, the size of the capacitor groove is greater than or equal to the size of the charge extraction groove. Wherein, the size of the charge extraction groove can be adjusted according to the required resistance value to meet the resistance value required when designing the charge extraction groove. The size of the capacitor groove can be designed according to the required capacitor device. The size of the capacitor groove is smaller than the size of the shallow trench isolation structure and does not occupy the area of ​​the wafer device area. It is not limited here.

[0087] Since the capacitor trench 105 and the charge extraction trench 106 are both completed by the same etching process, and the preparation of the charge extraction trench 106 is an existing technology, an additional etching process for the capacitor trench 105 is avoided, thereby reducing the preparation cost of the RF-SOI device.

[0088] At the same time, the capacitor prepared on the basis of the capacitor trench 105 is a longitudinal trench capacitor and is located at the shallow trench isolation structure position, which can not only reduce the footprint of the capacitor to improve the capacitor integration of the RF-SOI device, but also avoid the electrical coupling interference of the capacitor to the device, so as to improve the performance of the RF-SOI device in high-frequency applications.

[0089] The specific etching process may be wet etching or dry etching. The specific etching process may adopt conventional technical means in the art, which will not be described in detail here.

[0090] S4: A second polysilicon layer 107 and a first metal layer 108 are sequentially formed on the sidewalls of the capacitor trench 105, the sidewalls of the charge extraction trench 106 and the surface of the SOI substrate 101 to serve as the lower plate of the capacitor. Figure 6 shown.

[0091] Since the second polysilicon layer 107 and the first metal layer 108 are deposited on the side walls of the charge extraction groove 106, the second polysilicon layer 107 and the first metal layer 108 are also deposited on the side walls of the charge groove 105, so that the second polysilicon layer 107 and the first metal layer 108 serve as the lower plate of the capacitor, thereby achieving reuse of the deposition process, avoiding additional deposition of the lower plate of the capacitor, and further reducing the manufacturing cost of the RF-SOI device.

[0092] At the same time, because the charge groove 105 is engraved through the first polysilicon layer 1021, the first polysilicon layer 1021 surrounds the charge groove 105, so the deposited second polysilicon layer 107 is in physical contact with the first polysilicon layer 1021. After the first contact hole is subsequently prepared, the first contact hole is indirectly electrically connected to the second polysilicon layer 107 through the first polysilicon layer 1021, and because the first polysilicon layer 1021 is engraved into a ring structure, a plurality of first contact holes can be provided on the conductive contact layer 1022 on the surface of the first polysilicon layer 1021 to form a ring connection between the outside world and the second polysilicon layer 107, thereby increasing the connection between the outside world and the lower plate, thereby improving the stability of the capacitor.

[0093] The first metal layer 108 is specifically titanium nitride.

[0094] S5: forming a dielectric layer on a surface of the first metal layer corresponding to the capacitor trench and on surfaces of the first metal layer at both sides of the capacitor trench.

[0095] in, Figure 7 The process of the method for preparing the RF-SOI device provided by the embodiment of the present invention is Figure 2 .

[0096] Please refer to Figure 7 The specific steps of forming a dielectric layer on the surface of the first metal layer corresponding to the capacitor groove and on the surfaces of the first metal layer on both sides of the capacitor groove in S5 include the following:

[0097] S51: depositing a photoresist coating.

[0098] S52: forming a patterned second mask layer 109 on the surface of the photoresist coating, wherein the patterned second mask layer 109 comprises a dielectric layer window region 1091 and a blocking region; wherein the dielectric layer window region 1091 corresponds to the capacitor trench 105 and the surface of the first metal layer on both sides of the capacitor trench 105, such as Figure 8 shown.

[0099] S53: Using the patterned second mask layer 109 as a mask, photolithography is performed on the photoresist coating in the dielectric layer window region 1091 to expose the capacitor trench 105. Figure 8 shown.

[0100] S54: Depositing a dielectric layer 110, such as Fig. 9 shown.

[0101] Wherein, the thickness of the dielectric layer 110 is between 30 angstroms and 500 angstroms. The dielectric layer 110 is a layer of dielectric in the trench capacitor. The thickness of the dielectric layer is not limited here, and those skilled in the art can select it according to the specific situation. Under the action of the electric field, the dielectric layer 110 can produce polarization phenomenon, so that equal amounts of positive and negative charges are formed inside it to form a dielectric. Therefore, the main function of the dielectric layer 110 is to isolate and act as a medium for storing electrical energy. When the trench capacitor is in a discharge state, the dielectric layer 110 absorbs the charge and stores it. When the trench capacitor needs to release the charge, the dielectric layer 110 will release the stored charge back to the electrode.

[0102] The material of the dielectric layer 110 is specifically aluminum oxide. Of course, other materials with high dielectric constant and good insulation performance can also be used as the material of the dielectric layer, which is not limited here.

[0103] S55: removing the photoresist coating, such as Fig.10 shown.

[0104] S6: Filling the capacitor trench and the charge extraction trench with a second metal layer to serve as an upper plate of the capacitor.

[0105] in, Fig.11 The process of the method for preparing the RF-SOI device provided by the embodiment of the present invention is Figure 3 .

[0106] Please refer to Fig.11 The specific steps of filling the capacitor trench and the charge extraction trench with the second metal layer in S6 include the following:

[0107] S61: Depositing the second metal layer 111, such as Fig.12 shown.

[0108] S62: Grinding the second metal layer 111 until the surface of the interlayer dielectric layer 103 is reached. Fig.13 shown.

[0109] The material of the second metal layer 111 specifically includes tungsten, titanium, titanium nitride, or a mixture of titanium and titanium nitride. Those skilled in the art can select a suitable material as the upper plate according to actual conditions, and no limitation is made here.

[0110] The grinding process in step S62 may be chemical mechanical polishing. Of course, any process that can make the surface of the second metal layer 111 and the interlayer dielectric layer 103 flush is within the protection scope of the present invention and is not limited here.

[0111] S7: forming a metal wiring structure on the conductive contact layer and the second metal layer.

[0112] in, Fig.14 The process of the method for preparing the RF-SOI device provided by the embodiment of the present invention is Figure 4 .

[0113] Please refer to Fig.14 The specific steps of forming a metal wiring structure on the conductive contact layer and the second metal layer in S7 include the following:

[0114] S71: At least one first contact hole is formed, wherein the first end of each of the first contact holes is connected to the corresponding conductive contact layer 1022 of the first polysilicon layer 1021, and a second contact hole is formed, wherein the first end of the second contact hole is connected to the conductive contact layer on the surface of the corresponding source region, the drain region, and the gate, and the second end of each of the first contact hole and the second contact hole is flush with the surface of the interlayer dielectric layer.

[0115] in, Fig.15 The process of the method for preparing the RF-SOI device provided by the embodiment of the present invention is Figure 5 .

[0116] Please refer to Fig.15 The specific steps in step S71 include the following:

[0117] S711: forming a patterned third mask layer 112 on the surface of the interlayer dielectric layer 103, wherein the patterned first mask layer 104 includes at least one first contact hole window region 1121, a second contact hole window region and a blocking region, such as Fig.16 shown.

[0118] The specific process flow in step S71 is similar to that in step S3 and will not be repeated here.

[0119] S712: Using the patterned third mask layer 112 as a mask, etching the first contact hole window area 1121 and the interlayer dielectric layer 103 in the second contact hole window area, and stopping the etching end point at the surface of the first polysilicon layer 1021 to form a plug trench 113, and removing the third mask layer 112, such as Fig.17 shown.

[0120] S713: Depositing the third metal layer 114 so that the third metal layer 114 fills the plug trench 113 to form the first contact hole 115 and the second contact hole. Fig.18 shown.

[0121] It should be noted that the metal material filled in the plug groove 113 and the upper plate of the capacitor are made of the same material.

[0122] S714: Grinding the third metal layer 114 until the surface of the interlayer dielectric layer 103 is formed. Fig.19 and Fig. 20 As shown. Among them, Fig. 20 yes Fig.19 Top view of the .

[0123] As described above, since the second polysilicon layer connected to the first polysilicon layer 1021 is a ring structure, in order to improve the connectivity of the first polysilicon layer 1021, i.e., the lower plate of the capacitor, to the outside world, a plurality of first contact holes and corresponding wires connected to the first polysilicon layer 1021 may be provided. Of course, the number of the first contact holes may be set according to demand, which will not be described in detail here.

[0124] The grinding process in step S714 may also use chemical mechanical polishing. Of course, any process that can make the surface of the third metal layer 114 and the interlayer dielectric layer 103 flush is within the protection scope of the present invention and is not limited here.

[0125] S72: At least one first metal block, at least one second metal block, a third metal block and a fourth metal block are formed on the surface of the interlayer dielectric layer, each of the first metal blocks corresponds to one of the first contact holes, and the first metal block is electrically connected to the second end of the corresponding first contact hole, each of the second metal blocks corresponds to one of the capacitor trenches, and the second metal block is electrically connected to the second metal layer in the corresponding capacitor trench; the third metal block is electrically connected to the second metal layer in the charge extraction trench; each of the fourth metal blocks corresponds to one of the second contact holes, and the fourth metal block is electrically connected to the second end of the corresponding second contact hole.

[0126] Among them, the number of the first metal blocks is the same as the number of the first contact holes, and each of the first metal blocks is electrically connected to a corresponding first contact hole, so that the first metal block serves as a lead-out line of the lower plate of the capacitor. The number of the second metal blocks is the same as the number of the capacitor grooves, and each of the second metal blocks is electrically connected to the second metal layer in the corresponding capacitor groove, so that the second metal layer serves as a lead-out line of the upper plate of the capacitor. The number of the third metal blocks is the same as the number of the charge extraction grooves, and each of the third metal blocks is electrically connected to the second metal layer in a corresponding charge extraction groove, so that the third metal layer serves as a lead-out line of the charge extraction structure. The first metal block, the second metal block, the third metal block and the fourth metal block are metal interconnection layers, and the materials of the metal interconnection layers may include metal materials such as gold, aluminum, copper and silver, which are not limited here.

[0127] in, Fig.21 The process of the method for preparing the RF-SOI device provided by the embodiment of the present invention is Figure 6 .

[0128] Please refer to Fig.21 In step S72, at least one first metal block, at least one second metal block, a third metal block and a fourth metal block are formed on the surface of the interlayer dielectric layer, which specifically includes the following steps:

[0129] S721: Depositing a metal interconnection film 116 on the surface of the interlayer dielectric layer 103, the first contact hole 115, the second contact hole, the trench capacitor, and the charge extraction structure: Fig. 22 shown.

[0130] S722: forming a fourth mask layer 117 on the surface of the metal interconnect film, such as Fig.23 shown.

[0131] S723: Using the fourth mask layer 117 as a mask, etching the metal interconnection film, forming a metal interconnection layer 118 on the surface of the interlayer dielectric layer 103, namely, a first metal block 1181, a second metal block 1182, a third metal block 1183, and a fourth metal block 1184, the metal interconnection layer is electrically connected to the first contact hole and the second contact hole to form a metal interconnection structure, such as Fig.24 shown.

[0132] S724: forming a second interlayer dielectric layer 119 covering the surface of the metal interconnect layer 118 and the surface of the interlayer dielectric layer 103, such as Fig.25 shown.

[0133] The process of forming a metal interconnection layer is a conventional technical means in the art and will not be described in detail here. The metal interconnection structure may also include a first contact hole, a second contact hole, a multi-layer metal interconnection layer connected to the first contact hole and the second contact hole, and a metal through hole connecting the multi-layer metal interconnection layers. Those skilled in the art may select a suitable number of metal interconnection layers and corresponding metal through holes according to actual conditions, and no limitation is made here.

[0134] In summary, the method for preparing the RF-SOI device provided in the embodiment of the present invention utilizes the process of preparing the charge extraction structure in the prior art to simultaneously prepare the capacitor groove and the lower plate of the capacitor, thereby realizing the sharing of process steps, thereby saving the process steps for preparing the capacitor of the present invention and reducing manufacturing costs.

[0135] At the same time, because the capacitor of the RF-SOI device in the embodiment of the present invention is a trench capacitor, and the capacitor of the RF-SOI device in the prior art is usually a MIM capacitor, that is, a flat capacitor. Therefore, compared with the prior art, the capacitor prepared in the embodiment of the present invention is located at the shallow trench isolation structure and is a trench capacitor, which has a smaller footprint and does not occupy the device area of ​​the wafer, thereby improving the integration of the capacitor in the RF-SOI device. And because the magnetic field of the MIM capacitor of the RF-SOI device in the prior art is horizontally arranged, it will cause electrical coupling interference to the device in the horizontal position, thereby causing signal distortion. However, since the capacitor prepared in the embodiment of the present invention is a trench capacitor, the magnetic field of the capacitor itself is arranged vertically, and there is no device set in the vertical direction, thereby greatly reducing the electrical coupling interference to the device.

[0136] In addition, since the surface of the shallow trench isolation structure corresponding to the capacitor trench is provided with a first polysilicon layer, so that the first polysilicon layer surrounds the capacitor trench, the first polysilicon layer is connected by providing a plurality of first contact holes, and since the first polysilicon layer and the second polysilicon layer are in physical contact, an annular connection between the outside world and the lower plate of the capacitor is formed, thereby increasing the connection between the outside world and the lower plate, thereby improving the stability of the capacitor.

[0137] Please refer to Fig.25 The embodiment of the present invention further provides an RF-SOI device, which is manufactured based on the manufacturing method of the RF-SOI device, and the device structure includes:

[0138] SOI substrate 101, wherein the SOI substrate 101 comprises a silicon substrate 1012, a buried oxide layer 1011 and a top silicon layer 1013 stacked in sequence;

[0139] A shallow trench isolation structure and a source region and a drain region of a device, wherein the shallow trench isolation structure and the source region and the drain region of the device are both located in the top silicon layer 1013;

[0140] A gate with a preset height and a first polysilicon layer 1021, wherein the gate with a preset height and the first polysilicon layer 1021 are both located on the surface of the top silicon layer 1013, and the first polysilicon layer 1021 is located on the surface of a preset shallow trench isolation structure;

[0141] An interlayer dielectric layer 103, wherein the interlayer dielectric layer 103 covers the surface of the top silicon layer 1013;

[0142] A conductive contact layer 1022, wherein the conductive contact layer 1022 is respectively located on the surfaces of the gate, the first polysilicon layer 1021, and the source region and the drain region;

[0143] At least one trench capacitor and a charge extraction structure, wherein the trench capacitor sequentially penetrates the interlayer dielectric layer 103, the first polysilicon layer 1021, the preset shallow trench isolation structure, the buried oxide layer 1011 to the silicon substrate 1012; the charge extraction structure sequentially penetrates the interlayer dielectric layer 103, the shallow trench isolation structure, the buried oxide layer 1011 to the silicon substrate 1012; wherein the first polysilicon layer 1021 surrounds the trench capacitor; wherein the trench capacitor comprises a capacitor trench, and a second polysilicon layer 107, a first metal layer 108, a dielectric layer 110 and a second metal layer 111 sequentially stacked in the capacitor trench; the charge extraction structure comprises a charge extraction trench, and a second polysilicon layer 107, a first metal layer 108 and a second metal layer 111 sequentially stacked in the charge extraction trench;

[0144] A metal wiring layer, wherein the metal wiring layer includes a metal wiring structure formed in the interlayer dielectric layer, and the metal wiring structure includes: a first contact hole 115 arranged around the trench capacitor and electrically connected to the conductive contact layer 1022 on the surface of the first polysilicon layer 1021, and a first metal block 1181 connected to the first contact hole, a second contact hole electrically connected to the conductive contact layer 1022 on the surfaces of the gate and the source region and the drain region, and a fourth metal block 1184 connected to the second contact hole, and a second metal block 1182 and a third metal block 1183 respectively connected to the second metal layer 111 in the trench capacitor and the second metal layer 111 in the charge extraction structure.

[0145] Among them, the materials and preparation processes of the SOI substrate 101, the device layer 102, the first metal layer 108, the second metal layer 111, the first contact hole 115, the first metal block, the second metal block, the third metal block and the fourth metal block and the corresponding technical effects are all described above and will not be repeated here.

[0146] An embodiment of the present invention further provides an electronic device, comprising the RF-SOI device.

[0147] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for preparing an RF-SOI device, characterized in that: The method includes: Providing an SOI substrate, comprising a silicon substrate, a buried oxide layer and a top silicon layer stacked in sequence; A device layer is formed in the top silicon layer, and an interlayer dielectric layer is formed on the surface of the device layer, wherein the device layer includes: a shallow trench isolation structure, a source region, a drain region, a gate of the same preset height, and a first polysilicon layer, and includes: a conductive contact layer formed on the surface of the gate, the first polysilicon layer, and the source region and the drain region, wherein the first polysilicon layer covers the surface of the preset shallow trench isolation structure; A capacitor trench and a charge extraction trench are simultaneously formed in the SOI substrate, wherein the capacitor trench and the charge extraction trench extend from the top surface of the interlayer dielectric layer to the silicon substrate; wherein the capacitor trench passes through the preset shallow trench isolation structure and the first polysilicon layer surrounds the capacitor trench; A second polysilicon layer and a first metal layer are sequentially stacked on the sidewalls and bottoms of the capacitor trench and the charge extraction trench to serve as a lower plate of the capacitor; forming a dielectric layer on a surface of the first metal layer corresponding to the capacitor groove and on surfaces of the first metal layer at both sides of the capacitor groove; Filling the capacitor trench and the charge extraction trench with a second metal layer to serve as an upper plate of the capacitor; A metal wiring structure is formed on the conductive contact layer and the second metal layer.

2. The method for preparing the RF-SOI device according to claim 1, characterized in that: Simultaneously forming a capacitor trench and a charge extraction trench in the SOI substrate, specifically comprising: Forming a patterned first mask layer on the interlayer dielectric layer, the patterned first mask layer comprising a capacitor trench window region, a charge extraction trench window region and a blocking region, wherein the capacitor trench window region corresponds to the preset shallow trench isolation structure, and the charge extraction trench window region corresponds to another shallow trench isolation structure; Using the patterned first mask layer as a mask, the interlayer dielectric layer, the first polysilicon layer, the preset shallow trench isolation structure, the buried oxide layer and the silicon substrate in the capacitor trench window area are etched in sequence, and the etching end point stays in the silicon substrate to form the capacitor trench; at the same time, the interlayer dielectric layer, the shallow trench isolation structure, the buried oxide layer and the silicon substrate in the charge extraction trench window area are etched in sequence, and the etching end point stays in the silicon substrate to form the charge extraction trench.

3. The method for preparing the RF-SOI device according to claim 2, characterized in that: The size of each of the capacitor trench and the charge extraction trench is smaller than the size of the corresponding shallow trench isolation structure.

4. The method for preparing the RF-SOI device according to claim 3, characterized in that: The size of the capacitor trench is greater than or equal to the size of the charge extraction trench.

5. The method for preparing the RF-SOI device according to claim 1, characterized in that: Forming a dielectric layer on the surface of the first metal layer corresponding to the capacitor groove and on the surface of the first metal layer on both sides of the capacitor groove specifically includes: A patterned second mask layer is formed on the surface of the interlayer dielectric layer, wherein the patterned second mask layer includes a dielectric layer window region and a blocking region; wherein the dielectric layer window region corresponds to the capacitor trench and the surface of the first metal layer on both sides of the capacitor trench; Depositing a dielectric layer using the patterned second mask layer as a mask; The patterned second mask layer is removed.

6. The method for preparing the RF-SOI device according to claim 1, characterized in that: The forming of a metal wiring structure on the conductive contact layer and the second metal layer specifically includes: forming at least one first contact hole, wherein a first end of each of the first contact holes is connected to a corresponding conductive contact layer of the first polysilicon layer, and a second end of each of the first contact holes is flush with a surface of the interlayer dielectric layer; At least one first metal block, at least one second metal block and a third metal block are formed on the surface of the interlayer dielectric layer, each of the first metal blocks corresponds to one of the first contact holes, and the first metal block is electrically connected to the second end of the corresponding first contact hole, each of the second metal blocks corresponds to one of the capacitor trenches, and the second metal block is electrically connected to the second metal layer in the corresponding capacitor trench; the third metal block is electrically connected to the second metal layer in the charge extraction trench.

7. The method for preparing the RF-SOI device according to claim 6, characterized in that: The method of forming a metal wiring structure on the conductive contact layer and the second metal layer further comprises: forming a second contact hole, wherein a first end of the second contact hole is connected to the conductive contact layer corresponding to the surface of the source region, the drain region, and the gate, and a second end of the second contact hole is flush with the surface of the interlayer dielectric layer; Fourth metal blocks are formed on the surface of the interlayer dielectric layer, each of the fourth metal blocks corresponds to one of the second contact holes, and the fourth metal blocks are electrically connected to the second ends corresponding to the second contact holes.

8. The method for preparing the RF-SOI device according to claim 1, characterized in that: The silicon substrate is a high resistance trap-enriched substrate.

9. The method for preparing the RF-SOI device according to claim 1, characterized in that: The first metal layer includes titanium nitride; the second metal layer includes at least tungsten, titanium, titanium nitride, or a mixture of titanium and titanium nitride.

10. An RF-SOI device, characterized in that: include: An SOI substrate, wherein the SOI substrate comprises a silicon substrate, a buried oxide layer and a top silicon layer stacked in sequence; A shallow trench isolation structure and a source region and a drain region of a device, wherein the shallow trench isolation structure and the source region and the drain region of the device are both located in the top silicon layer; A gate and a first polysilicon layer of a preset height, wherein the gate and the first polysilicon layer of the preset height are both located on the surface of the top silicon layer, and the first polysilicon layer is located on the surface of a preset shallow trench isolation structure; An interlayer dielectric layer, the interlayer dielectric layer covering the surface of the top silicon layer; A conductive contact layer, wherein the conductive contact layer is respectively located on the surface of the gate, the first polysilicon layer, the source region, and the drain region; At least one trench capacitor and a charge extraction structure, wherein the trench capacitor sequentially penetrates the interlayer dielectric layer, the first polysilicon layer, the preset shallow trench isolation structure, the buried oxide layer to the silicon substrate; the charge extraction structure sequentially penetrates the interlayer dielectric layer, the shallow trench isolation structure, the buried oxide layer to the silicon substrate; wherein the first polysilicon layer surrounds the trench capacitor; the trench capacitor comprises a capacitor trench, and a second polysilicon layer, a first metal layer, a dielectric layer and a second metal layer sequentially stacked in the capacitor trench; the charge extraction structure comprises a charge extraction trench, and a second polysilicon layer, a first metal layer and a second metal layer sequentially stacked in the charge extraction trench; A metal wiring layer, the metal wiring layer includes a metal wiring structure formed in the interlayer dielectric layer, the metal wiring structure includes: a first contact hole arranged around the trench capacitor and electrically connected to the conductive contact layer on the surface of the first polysilicon layer, and a first metal block connected to the first contact hole, a second contact hole electrically connected to the conductive contact layer on the surface of each of the gate and the source and drain regions, and a fourth metal block connected to the second contact hole, and a second metal block and a third metal block respectively connected to the second metal layer in the trench capacitor and the second metal layer in the charge extraction structure.

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