Solar cell preparation method and solar cell
By forming marking points and target patterns on the semiconductor substrate and forming isolation trenches in combination with laser etching process, the problem of poor alignment accuracy of the P and N poles of the back contact battery is solved, and higher alignment accuracy and photoelectric conversion efficiency are achieved.
Patent Information
- Application Number
- CN202411112057.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-13
- Publication Date
- 2025-04-01
AI Technical Summary
In the prior art, the alignment accuracy of the P and N poles of the back contact battery is poor and cannot meet the requirements of high-precision alignment.
By forming a plurality of marking points on the first and second regions of the semiconductor substrate, the target geometric center of the target pattern is identified and passed through the target geometric center along the extension direction of the boundary line in the laser etching process, an isolation trench is formed to isolate the first semiconductor layer and the second semiconductor layer.
The alignment accuracy of P and N poles is greatly improved, the problem of poor alignment accuracy in the prior art is solved, and the photoelectric conversion efficiency of solar cells is improved.
Smart Images
Figure CN119744015A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a solar cell and a solar cell. Background Art
[0002] At present, the main direction to improve the back conversion efficiency of back-contact cells (BC-type solar cells) is back patterning, that is, to achieve the P and N poles of the back-contact cell are set on the back of the cell through back patterning and front grid-free. This method improves efficiency very significantly, but the front grid-free also requires the back alignment accuracy to be guaranteed, and the stability of the alignment accuracy requires higher requirements for laser alignment accuracy and metal alignment accuracy.
[0003] In the prior art, the center point of the silicon wafer is usually obtained by grabbing the four edges and four diagonal corners of the silicon wafer, and then appropriate angle compensation is performed to achieve the alignment of the laser P pole, N pole and metallized printed pattern. However, this alignment method is limited by the dimensional accuracy specifications of the silicon wafer and the position of the pattern on the silicon wafer. For back-contact cells that require high-precision alignment, the accuracy is poor and it is no longer suitable.
[0004] Therefore, there is an urgent need for a method to improve the alignment accuracy of the P-pole and the N-pole of a back contact battery. Summary of the invention
[0005] The main purpose of the present invention is to provide a method for preparing a solar cell and a solar cell, so as to solve the problem of poor alignment accuracy between the P pole and the N pole of a back contact cell in the prior art.
[0006] In order to achieve the above-mentioned purpose, according to one aspect of the present invention, a method for preparing a solar cell is provided, comprising: providing a semiconductor substrate, the semiconductor substrate comprising a first region and a second region arranged along a first direction, the first region and the second region being adjacent to each other and having a dividing line; forming a first semiconductor layer on the first region; forming a plurality of marking points on the first semiconductor layer and on the second region; identifying a target pattern corresponding to the plurality of marking points, the target pattern having a target geometric center; forming a second semiconductor layer covering the plurality of marking points on the second region, the second semiconductor layer and the first semiconductor layer having different doping types; using a laser etching process to remove a portion of the second semiconductor layer to the semiconductor substrate, the laser of the laser etching process passing through the target geometric center in an extension direction along the dividing line to form an isolation trench, the isolation trench being used to isolate the first semiconductor layer from the second semiconductor layer.
[0007] Optionally, the step of forming a plurality of marking points includes: using a visual camera to identify a boundary line; using a laser etching process to form a plurality of marking points in the first semiconductor layer and the second region, and positions of the plurality of marking points are determined according to the position of the boundary line.
[0008] Optionally, the step of forming the isolation groove includes: using a visual camera to capture the target pattern and determine the target geometric center of the target pattern; adjusting the laser of the laser etching process so that the laser passes through the target geometric center in the extension direction of the dividing line and forms a preliminary groove on the surface of the second semiconductor layer; using a chemical etching process to continue etching the second semiconductor layer along the preliminary groove to the semiconductor substrate to form an isolation groove.
[0009] Optionally, the plurality of marking points are all arranged outside the dividing line.
[0010] Optionally, the multiple marking points include a first marking point, a second marking point, a third marking point and a fourth marking point, and the first marking point, the second marking point, the third marking point and the fourth marking point are connected in sequence to form a target figure, and the target figure is a rectangle; the first marking point and the second marking point are set on the first area, and the third marking point and the fourth marking point are set on the second area; the line connecting the first marking point and the third marking point is the first diagonal of the rectangle, and the line connecting the second marking point and the fourth marking point is the second diagonal of the rectangle, and the intersection of the first diagonal and the second diagonal is the target geometric center.
[0011] Optionally, a line connecting the second marking point and the third marking point is parallel to the first direction; a distance between the second marking point and the third marking point in the first direction is D1; a width of the isolation trench in the first direction is A1, and D1>A1.
[0012] Optionally, at least one of the plurality of marking points is arranged on the dividing line.
[0013] Optionally, the multiple marking points include a first marking point, a second marking point, a third marking point and a fourth marking point, and the first marking point, the second marking point, the third marking point and the fourth marking point are connected in sequence to form a target figure, and the target figure is a rectangle; the first marking point and the second marking point are set on the dividing line, and the third marking point and the fourth marking point are set on the second area; the line connecting the first marking point and the third marking point is the first diagonal of the rectangle, and the line connecting the second marking point and the fourth marking point is the second diagonal of the rectangle, and the intersection of the first diagonal and the second diagonal is the target geometric center.
[0014] Optionally, a line connecting the second marking point and the third marking point is parallel to the first direction; a distance between the second marking point and the third marking point in the first direction is D1; a width of the isolation trench in the first direction is A1, and D1≤A1.
[0015] According to another aspect of the present application, there is provided a solar cell prepared by any of the above-mentioned solar cell preparation methods, comprising: a semiconductor substrate, comprising a first region and a second region arranged along a first direction, the first region and the second region being adjacent to each other and having a boundary line; a first semiconductor layer, located on the first region; a second semiconductor layer, located on the second region, the first semiconductor layer and the second semiconductor layer having different doping types; an isolation trench, located between the first semiconductor layer and the second semiconductor layer, for isolating the first semiconductor layer and the second semiconductor layer, the boundary line being located in the isolation trench.
[0016] The technical solution of the present invention is applied to provide a method for preparing a solar cell including an isolation groove, which specifically includes: first providing a semiconductor substrate, which may include a first region and a second region adjacent to each other and having a dividing line. Then, a first semiconductor layer may be formed on the first region, and a second semiconductor layer may be formed on the second region, wherein the first semiconductor layer and the second semiconductor layer have different doping types. Among them, in order to isolate the first semiconductor layer and the second semiconductor layer, after forming the first semiconductor layer on the first region, the present application may first form a plurality of marking points on the first semiconductor layer and the second region, and then after identifying the target graphics corresponding to the plurality of marking points, since the target graphics have a target geometric center, a second semiconductor layer covering the plurality of marking points is formed on the second region, and in the step of removing part of the second semiconductor layer to the semiconductor substrate by a laser etching process, by passing the laser in the laser etching process through the target geometric center in the extension direction along the dividing line, an isolation groove may be etched to isolate the first semiconductor layer and the second semiconductor layer. That is, through the present application, since the alignment marks (i.e. the above-mentioned multiple marking points) required for forming the isolation grooves have been identified before the laser etching process, the target geometric center of the target figure corresponding to the above-mentioned multiple marking points can be directly aligned and etched during the laser etching process, and is no longer limited by the dimensional accuracy of the silicon wafer and the position of the marking points in the silicon wafer, thereby greatly improving the alignment efficiency and alignment accuracy, thereby solving the problem of poor alignment accuracy of the P pole and the N pole of the back-contact battery in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] The accompanying drawings constituting a part of the present invention are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the accompanying drawings:
[0018] Figure 1 A schematic cross-sectional structure diagram of a semiconductor substrate having a first semiconductor layer formed thereon according to an embodiment of the present invention is shown;
[0019] Figure 2A plan view showing a plurality of marking points;
[0020] Figure 3 Shown in Figure 1 A schematic cross-sectional structure diagram of a second semiconductor layer formed on the structure shown;
[0021] Figure 4 Shown in Figure 3 A schematic diagram of a cross-sectional structure of a preparatory groove formed on the structure shown;
[0022] Figure 5 Shown in Figure 3 A schematic cross-sectional structure diagram of an isolation trench formed on the structure shown;
[0023] Figure 6 Shown in Figure 5 A schematic diagram of a cross-sectional structure of an aluminum oxide passivation layer formed on the structure shown;
[0024] Figure 7 Shown in Figure 6 A schematic cross-sectional structure diagram of a first electrode and a second electrode formed on the structure.
[0025] The above drawings include the following reference numerals:
[0026] 1000, first area; 2000, second area; 100, marking point; 101, first marking point; 102, second marking point; 103, third marking point; 104, fourth marking point; 200, target geometric center; 10, semiconductor substrate; 20, first semiconductor layer; 201, first passivation layer; 202, first doping layer; 203, first mask; 303, second mask; 204, third mask; 30, second semiconductor layer; 301, second passivation layer; 302, second doping layer; 40, preliminary groove; 50, isolation groove; 60, aluminum oxide passivation layer; 70, first electrode; 80, second electrode. DETAILED DESCRIPTION
[0027] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.
[0028] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.
[0029] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the present invention described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0030] As described in the background technology, the prior art usually adopts the method of grabbing the four edges and four diagonal corners of the silicon wafer to obtain the center point of the silicon wafer, and then performing appropriate angle compensation to achieve the alignment of the laser P pole, N pole and metallized printed graphics. However, this type of alignment method is limited by the dimensional accuracy specifications of the silicon wafer and the position of the graphics on the silicon wafer. For back-contact batteries that require high-precision alignment, the accuracy is poor and it is no longer suitable. In order to solve the problem of poor P-pole and N-pole alignment capabilities of back-contact batteries in the prior art, the present application provides a method for forming a semiconductor structure and a semiconductor structure formed by the above-mentioned method for forming a semiconductor structure.
[0031] In some optional embodiments, a method for forming a semiconductor structure is provided, wherein the semiconductor structure includes an isolation trench, and the method includes: providing a semiconductor substrate 10, wherein the semiconductor substrate 10 includes a first region 1000 and a second region 2000, wherein the first region 1000 and the second region 2000 are adjacent to each other and have a boundary line (not shown in the figure); forming a first semiconductor layer 20 on the first region 1000, such as Figure 1 As shown; forming a plurality of marking points 100 on the first semiconductor layer 20 and the second region 2000; identifying a target pattern corresponding to the plurality of marking points 100, the target pattern having a target geometric center, such as Figure 2 As shown; forming a second semiconductor layer 30 covering the plurality of marking points 100 on the second region 2000, the second semiconductor layer 30 and the first semiconductor layer 20 having different doping types, such as Figure 3 As shown; a laser etching process is used to remove part of the second semiconductor layer 30 to the semiconductor substrate 10, and the laser of the laser etching process passes through the target geometric center along the extension direction of the dividing line to form the isolation groove 50, and the isolation groove 50 is used to isolate the first semiconductor layer 20 and the second semiconductor layer 30, as shown Figure 5 shown.
[0032] It should be noted here that Figure 1 As shown, the semiconductor substrate 10 is not actually divided into adjacent first regions 1000 and second regions 2000 having a dividing line, but is artificially set for the convenience of describing the positional relationship between the first semiconductor layer 20 and the semiconductor substrate 10 and the positional relationship between the second semiconductor layer 30 and the semiconductor substrate 10 .
[0033] Specifically, Figure 1 As shown, the semiconductor substrate 10 may be a silicon wafer. Before the step of forming the first semiconductor layer 20 in the first region 1000 of the semiconductor substrate 10, the semiconductor substrate 10 may be subjected to treatments such as removing a damaged layer, removing surface dirt, and polishing the surface.
[0034] Specifically, Figure 2 As shown, the marking point 100 is a figure with a geometric center. Exemplarily, the figure of the marking point 100 may include but is not limited to a circle, a rectangle, and a regular polygon.
[0035] In addition, in order to simplify the formation process of the marking points 100, the pattern of the plurality of marking points 100 formed on the first semiconductor layer 20 and the pattern of the plurality of marking points 100 formed on the second region 2000 may be the same. Exemplarily, the plurality of marking points 100 on the first semiconductor layer 20 and the second region 2000 may both be rectangular.
[0036] Furthermore, the positions of the plurality of marking points 100 in the first semiconductor layer 20 and the plurality of marking points 100 in the second region 2000 may be arbitrarily set.
[0037] It should be noted that, before forming the above-mentioned multiple marking points, since the first semiconductor layer has been formed on the above-mentioned first region 1000, it can be determined that the isolation trench between the first semiconductor layer and the second semiconductor layer to be formed extends along the above-mentioned dividing line. In the process of forming the multiple marking points, the positions of the multiple marking points 100 can be determined according to the above-mentioned dividing line, and after identifying the target graphics corresponding to the multiple marking points 100, the isolation trench can be determined according to the target geometric center of the above-mentioned multiple marking points 100 by using a laser etching process.
[0038] Correspondingly, after forming the above-mentioned multiple marking points 100, the step of using a laser etching process to determine the isolation groove according to the target geometric center of the above-mentioned multiple marking points 100 can be understood as follows: Figure 2As shown, the above-mentioned multiple marking points 100 are first identified, and then the geometric center of each marking point 100 can be obtained by computer fitting. Then, the target graphics corresponding to the above-mentioned multiple geometric centers can be fitted by computer, and then the target geometric center of the target graphics is obtained, and the laser of the laser etching process is etched along the extension direction of the above-mentioned dividing line through the above-mentioned target geometric center, so as to form the above-mentioned isolation groove 50.
[0039] Optionally, the solar cell may be a back contact cell. On this basis, the first semiconductor layer 20 may be the P pole of the back contact cell, and the second semiconductor layer 30 may be the N pole of the back contact cell; or the first semiconductor layer 20 may be the N pole of the back contact cell, and the second semiconductor layer 30 may be the P pole of the back contact cell.
[0040] In the above embodiment, for a solar cell including an isolation trench, a preparation method thereof may be: first, a semiconductor substrate is provided, and the semiconductor substrate 10 may include a first region 1000 and a second region 2000 that are adjacent to each other and have a boundary line. Then, a first semiconductor layer 20 may be formed on the first region 1000, and a second semiconductor layer 30 may be formed on the second region 2000, and the first semiconductor layer 20 and the second semiconductor layer 30 may have different doping types. Among them, in order to isolate the first semiconductor layer 20 and the second semiconductor layer 30, after forming the first semiconductor layer 20 on the first area 1000, the present application can first form a plurality of marking points 100 on the first semiconductor layer 20 and the second area 2000, and then after identifying the target graphics corresponding to the above-mentioned plurality of marking points 100, since the target graphics has a target geometric center 200, a second semiconductor layer 30 covering the above-mentioned plurality of marking points 100 is formed on the second area 2000. In the step of removing part of the second semiconductor layer 30 to the semiconductor substrate 10 by using a laser etching process, the laser in the laser etching process is passed through the above-mentioned target geometric center 200 in the extension direction along the dividing line, so that an isolation groove 50 can be etched to isolate the first semiconductor layer 20 and the second semiconductor layer 30. That is, through the present application, since the alignment marks (i.e., the above-mentioned multiple marking points 100) required for forming the isolation groove 50 have been identified before the laser etching process, the target geometric center 200 of the target figure corresponding to the above-mentioned multiple marking points 100 can be directly aligned and etched during the laser etching process, without being limited by the dimensional accuracy of the silicon wafer and the position of the marking points 100 in the silicon wafer, thereby greatly improving the alignment efficiency and alignment accuracy, thereby solving the problem of poor alignment accuracy of the P pole and the N pole of the back-contact battery in the prior art.
[0041] The first semiconductor layer 20 and the second semiconductor layer 30 of the solar cell are both located on the same side of the semiconductor substrate 10. The step of forming the first semiconductor layer 20 on the first region 1000 of the semiconductor substrate 10 includes: forming a first semiconductor material layer (not shown in the figure) on a surface of one side of the semiconductor substrate 10; using a first mask 203 to cover the portion of the first semiconductor material layer located in the first region 1000 so that the portion of the first semiconductor material layer located in the second region 2000 is exposed; etching the exposed first semiconductor material layer until the semiconductor substrate 10 is exposed to form the first semiconductor layer 20, such as Figure 1 Furthermore, the exposed second region 2000 may be polished.
[0042] Optionally, the first semiconductor material layer may include a first passivation material layer, a first doped amorphous silicon layer, and other film layers (i.e., the first mask 203) formed during the formation of the first doped amorphous silicon layer. Exemplarily, the first passivation material layer may include but is not limited to a silicon oxide layer, the first doped amorphous silicon layer may include but is not limited to a boron-doped amorphous silicon layer, and the other film layers (i.e., the first mask 203) may include but are not limited to a silicon oxide layer. It should be noted that the first passivation material layer is used to form Figure 1 The first passivation layer 201 and the first doped amorphous silicon layer in the structure shown are used as follows: Figure 1 The first doping layer 202 in the structure shown. In addition, in the step of forming the first semiconductor layer 20, a portion of the first mask 203 corresponding to the second region 2000 is removed by etching.
[0043] In some optional embodiments, the step of forming the above-mentioned marking points includes: Figure 1 and Figure 2As shown, a visual camera is used to identify the above-mentioned dividing line; a laser etching process is used to form a plurality of the above-mentioned marking points 100 on the above-mentioned first semiconductor layer 20 and the above-mentioned second region 2000, and the positions of the above-mentioned plurality of marking points 100 are determined according to the position of the above-mentioned dividing line. In the process of the visual camera identifying the above-mentioned dividing line, the side opposite to the side where the first semiconductor layer 20 is formed on the semiconductor substrate 10 can be illuminated first, and then the visual camera is used to identify the side where the first semiconductor layer 20 is formed, so that the position of the above-mentioned dividing line can be identified. Furthermore, in the process of forming a plurality of marking points 100 by the laser etching process, since the laser etching process can involve a computer fitting process, when the position of the above-mentioned dividing line is known, the positions of the above-mentioned plurality of marking points 100 can be determined by the above-mentioned computer fitting process, so that the target geometric center 200 of the target figure corresponding to the plurality of marking points 100 is located on the above-mentioned dividing line, or the distance between the target geometric center 200 of the target figure corresponding to the plurality of marking points 100 and the above-mentioned dividing line in the first direction is recorded.
[0044] Optionally, the second semiconductor layer 30 may be formed by referring to the preparation process of the first semiconductor layer 20, such as Figure 1 and Figure 3 As shown, after forming a second semiconductor layer 30 covering a plurality of marking points 100 on the second region 2000, the second semiconductor layer 30 on the second region 2000 may include a second doping layer 302 and a second passivation layer 301 located between the semiconductor substrate 10 and the second doping layer 302. Exemplarily, the second passivation layer 301 may be a silicon oxide layer. Since the second doping layer 302 is formed by doping amorphous silicon, the doping process may cause the second doping layer 302 to be formed on the side away from the semiconductor substrate 10 with other film layers (i.e., a second mask 303) different from the second doping layer 302. Exemplarily, the second doping layer 302 may include, but is not limited to, a phosphorus-doped amorphous silicon layer, and the other film layers (i.e., a second mask 303) may include, but are not limited to, a silicon oxide layer. It should be mentioned here that in the process of forming the above-mentioned second semiconductor layer 30, the side of the above-mentioned first semiconductor layer 20 away from the semiconductor substrate 10 will correspondingly form a film layer structure identical to the second semiconductor layer 30 (i.e., the second semiconductor layer 30 and the second mask 303), thereby forming a third mask 204 on the side of the first semiconductor layer 20 away from the semiconductor substrate 10, and the above-mentioned third mask 204 also includes the above-mentioned first mask 203.
[0045] In some optional embodiments, in combination Figure 2 , Figure 4 and Figure 5 As shown, the steps of forming the isolation trench 50 include: using a visual camera to capture the target pattern, and determining the target geometric center 200 of the target pattern, such as Figure 2 As shown; adjust the laser etching process of the laser, so that the laser in the extension direction of the boundary line through the target geometric center 200, and the surface of the second semiconductor layer 30 is formed in the preparation of the groove 40, such as Figure 4 Using a chemical etching process to continue etching the second semiconductor layer 30 along the prepared groove 40 to the semiconductor substrate 10 to form the isolation trench 50, such as Figure 5 shown.
[0046] Specifically, in the present embodiment, in order to form the isolation groove 50, it is first necessary to remove the portion of the second doping layer 302 (i.e., the second mask 303) on the side away from the second passivation layer 301 that corresponds to the isolation groove 50. In the removal step, since the positional relationship between the target geometric center 200 of the target figure corresponding to the plurality of marking points 100 and the aforementioned dividing line has been identified in the process of forming the aforementioned plurality of marking points 100, therefore, on the basis of using a visual camera to capture the target figure corresponding to the plurality of marking points 100 and determining the target geometric center 200 of the target figure, the laser of the laser etching process can be adjusted to pass through the aforementioned target geometric center 200 in the extension direction of the dividing line, so as to remove the portion of the second semiconductor layer 30 (i.e., the second mask 303) that corresponds to the isolation groove 50, thereby forming a preliminary groove 40 on the surface of the second semiconductor layer 30, as shown in FIG. Figure 4 As shown. In the process of etching the second semiconductor layer 30 to the semiconductor substrate 10 along the prepared groove 40 by chemical etching, the remaining second semiconductor layer 30 in the prepared groove 40 can be removed by self-alignment on the basis of the prepared groove 40, so that an isolation groove 50 can be formed between the first semiconductor layer 20 and the second semiconductor layer 30, as shown in FIG. Figure 5 shown.
[0047] In some optional implementations, the above-mentioned multiple marking points are all set outside the above-mentioned dividing line. Figure 2As shown, in the case where the geometric center of the marking point 100 is used to refer to the marking point 100 itself, the multiple marking points 100 may include a first marking point 101, a second marking point 102, a third marking point 103 and a fourth marking point 104, and the first marking point 101, the second marking point 102, the third marking point 103 and the fourth marking point 104 are sequentially connected to form the target figure, and the target figure may be a rectangle; the first marking point 101 and the second marking point 102 are arranged in the On the first area (specifically, the first marking point 101 and the second marking point 102 are arranged on the first semiconductor layer corresponding to the first area), the third marking point 103 and the fourth marking point 104 are arranged on the second area; the line connecting the first marking point 101 and the third marking point 103 is the first diagonal of the rectangle, the line connecting the second marking point 102 and the fourth marking point 104 is the second diagonal of the rectangle, and the intersection of the first diagonal and the second diagonal is the target geometric center 200.
[0048] It should be noted that in this embodiment, since the first marking point 101 and the second marking point 102 are located on the first side of the dividing line, and the third marking point 103 and the fourth marking point 104 are located on the second side of the dividing line, the above-mentioned first side and the second side are the opposite sides of the dividing line in the first direction, so that in the first direction, the target geometric center 200 of the target figure (rectangle) corresponding to the above-mentioned first marking point 101, the second marking point 102, the third marking point 103 and the fourth marking point 104 can be located on the above-mentioned dividing line.
[0049] Optionally, when the first marking point 101, the second marking point 102, the third marking point 103 and the fourth marking point 104 are all set outside the dividing line, the target figures corresponding to the first marking point 101, the second marking point 102, the third marking point 103 and the fourth marking point 104 are rectangles, and the line connecting the second marking point 102 and the third marking point 103 among the multiple marking points is parallel to the first direction, the distance between the second marking point 102 and the third marking point 103 in the first direction can be D1, and the width of the isolation trench in the first direction can be A1, and D1>A1.
[0050] In some other optional embodiments, at least one of the plurality of marking points is arranged on the boundary line. For example, two embodiments in which two of the plurality of marking points are located on the boundary line are given below:
[0051] The first implementation mode is: the above-mentioned multiple marking points include a first marking point 101, a second marking point 102, a third marking point 103 and a fourth marking point 104, and the above-mentioned first marking point 101, the above-mentioned second marking point 102, the above-mentioned third marking point 103 and the above-mentioned fourth marking point 104 are connected in sequence to form the above-mentioned target figure, and the above-mentioned target figure is a rectangle; the above-mentioned first marking point 101 and the above-mentioned second marking point 102 are arranged on the above-mentioned dividing line, and the above-mentioned third marking point 103 and the above-mentioned fourth marking point 104 are arranged on the above-mentioned second area; the line connecting the above-mentioned first marking point 101 and the above-mentioned third marking point 103 is the first diagonal line of the above-mentioned rectangle, the line connecting the above-mentioned second marking point 102 and the above-mentioned fourth marking point 104 is the second diagonal line of the above-mentioned rectangle, and the intersection of the above-mentioned first diagonal line and the above-mentioned second diagonal line is the above-mentioned target geometric center 200.
[0052] It should be noted that in this embodiment, since the first marking point 101 and the second marking point 102 are located on the above-mentioned dividing line, and the third marking point 103 and the fourth marking point 104 are located in the second area, in the above-mentioned first direction, the target geometric center 200 of the target figure (rectangle) corresponding to the above-mentioned first marking point 101, the second marking point 102, the third marking point 103 and the fourth marking point 104 can be located outside the dividing line, but the distance between the target geometric center 200 of the above-mentioned target figure and the above-mentioned dividing line in the first direction can be recorded.
[0053] Optionally, when the first marking point 101 and the second marking point 102 are located on the above-mentioned dividing line, the third marking point 103 and the fourth marking point 104 are located in the second area, the target figures corresponding to the first marking point 101, the second marking point 102, the third marking point 103 and the fourth marking point 104 are rectangles, and the line connecting the second marking point 102 and the third marking point 103 is parallel to the above-mentioned first direction, the line connecting the second marking point 102 and the third marking point 103 is parallel to the above-mentioned first direction, the distance between the second marking point 102 and the third marking point 103 in the above-mentioned first direction is D1, the width of the above-mentioned isolation trench in the above-mentioned first direction is A1, and D1>A1.
[0054] The second implementation method is: the above-mentioned multiple marking points include a first marking point 101, a second marking point 102, a third marking point 103 and a fourth marking point 104, and the above-mentioned first marking point 101, the above-mentioned second marking point 102, the above-mentioned third marking point 103 and the above-mentioned fourth marking point 104 are connected in sequence to form the above-mentioned target figure; the above-mentioned first marking point 101 and the above-mentioned third marking point 103 are arranged on the above-mentioned dividing line, the above-mentioned second marking point 102 is arranged on the first area (specifically, the second marking point 102 is arranged on the first semiconductor layer corresponding to the first area), and the above-mentioned fourth marking point 104 is arranged on the above-mentioned second area; the line connecting the above-mentioned first marking point 101 and the above-mentioned third marking point 103 is the first diagonal line of the above-mentioned target figure, the line connecting the above-mentioned second marking point 102 and the above-mentioned fourth marking point 104 is the second diagonal line of the above-mentioned target figure, and the intersection of the above-mentioned first diagonal line and the above-mentioned second diagonal line is the target geometric center 200 of the above-mentioned target figure.
[0055] Of course, the target figure formed by sequentially connecting the first marking point 101, the second marking point 102, the third marking point 103 and the fourth marking point 104 mentioned above may also be other figures besides a rectangle, such as a parallelogram or a rhombus.
[0056] Furthermore, after the step of forming the isolation trench 50, the Figure 4 The second mask 303 and the third mask 204 in the structure shown in FIG. Figure 5 The structure shown; further, the above-mentioned solar cell preparation method may also include: making an anti-reflection velvet surface on the opposite side of the semiconductor substrate 10 on which the first semiconductor layer 20 is formed, and removing the doped film layer on the opposite side; further, a chemical passivation treatment may be performed on the periphery of the semiconductor structure to form an aluminum oxide passivation layer 60 on the exposed surface of the semiconductor substrate 10 away from the first semiconductor layer 20 and the second semiconductor layer 30, such as Figure 6 further, a silicon nitride passivation layer (not shown in the figure) can be formed on the side of the aluminum oxide passivation layer 60 away from the semiconductor substrate 10, and the silicon nitride passivation layer can play a protective role such as light trapping, corrosion resistance, and reducing sodium ions and water vapor.
[0057] Optionally, the solar cell preparation method may further include: Figure 7 As shown, a first electrode 70 is formed on a side of the first semiconductor layer 20 away from the semiconductor substrate 10; a second electrode 80 is formed on a side of the second semiconductor layer 30 away from the semiconductor substrate 10. The first electrode 70 is disposed in contact with the first semiconductor layer 20, and the second electrode 80 is disposed in contact with the second semiconductor layer 30. The first electrode 70 and the second electrode 80 form ohmic contacts respectively for collecting and conducting current.
[0058] In some optional embodiments, the present application also provides a solar cell prepared by the above-mentioned solar cell preparation method, such as Figure 7 As shown, it includes: a semiconductor substrate 10, including a first region and a second region, the first region and the second region are adjacent to each other and have a dividing line; a first semiconductor layer 20, located on the first region; a second semiconductor layer 30, located on the second region, the first semiconductor layer 20 and the second semiconductor layer 30 have different doping types; an isolation trench 50, located between the first semiconductor layer 20 and the second semiconductor layer 30, for isolating the first semiconductor layer 20 from the second semiconductor layer 30, and the dividing line is located in the isolation trench 50.
[0059] Specifically, the first semiconductor layer 20 may include a first passivation layer 201 and a first doping layer 202 which are stacked, and the second semiconductor layer 30 may include a second passivation layer 301 and a second doping layer 302 which are stacked.
[0060] Optionally, the above-mentioned solar cell may further include a first electrode 70, which is located on a side of the first semiconductor layer 20 away from the semiconductor substrate 10 and is in contact with the first doped layer 202 in the first semiconductor layer 20; the above-mentioned solar cell may further include a second electrode 80, which is located on a side of the second semiconductor layer 30 away from the semiconductor substrate 10 and is in contact with the second doped layer 302 in the second semiconductor layer 30.
[0061] In the above embodiment, since the above solar cell preparation method can improve the alignment accuracy between the first semiconductor layer 20 and the second semiconductor layer 30, the solar cell in this embodiment is prepared by the above preparation method. Compared with the solar cell of the same structure in the prior art, the solar cell has a higher photoelectric conversion efficiency.
[0062] From the above description, it can be seen that the above embodiments of the present invention achieve the following technical effects:
[0063] For a solar cell including an isolation groove, the preparation method thereof may be: first, a semiconductor substrate is provided, and the semiconductor substrate may include a first region and a second region adjacent to each other and having a dividing line. Then, a first semiconductor layer may be formed on the first region, and a second semiconductor layer may be formed on the second region, and the first semiconductor layer and the second semiconductor layer have different doping types. Among them, in order to isolate the first semiconductor layer and the second semiconductor layer, after forming the first semiconductor layer on the first region, the present application may first form a plurality of marking points on the first semiconductor layer and the second region, and then after identifying the target graphics corresponding to the plurality of marking points, since the target graphics have a target geometric center, a second semiconductor layer covering the plurality of marking points is formed on the second region, and in the step of removing part of the second semiconductor layer to the semiconductor substrate by a laser etching process, by passing the laser in the laser etching process through the target geometric center in the extension direction along the dividing line, an isolation groove may be etched to isolate the first semiconductor layer and the second semiconductor layer. That is, through the present application, since the alignment marks (i.e. the above-mentioned multiple marking points) required for forming the isolation grooves have been identified before the laser etching process, the target geometric center of the target figure corresponding to the above-mentioned multiple marking points can be directly aligned and etched during the laser etching process, and is no longer limited by the dimensional accuracy of the silicon wafer and the position of the marking points in the silicon wafer, thereby greatly improving the alignment efficiency and alignment accuracy, thereby solving the problem of poor alignment accuracy of the P pole and the N pole of the back-contact battery in the prior art.
[0064] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.
Claims
1. A method for preparing a solar cell, characterized in that: include: Providing a semiconductor substrate, the semiconductor substrate comprising a first region and a second region arranged along a first direction, the first region and the second region being adjacent to each other and having a boundary line; forming a first semiconductor layer on the first region; forming a plurality of marking points on the first semiconductor layer and the second region; Identifying a target graphic corresponding to the plurality of marking points, the target graphic having a target geometric center; forming a second semiconductor layer covering the plurality of marking points on the second region, wherein the second semiconductor layer and the first semiconductor layer have different doping types; A laser etching process is used to remove part of the second semiconductor layer to the semiconductor substrate, and the laser of the laser etching process passes through the target geometric center in the extension direction along the dividing line to form an isolation trench, and the isolation trench is used to isolate the first semiconductor layer and the second semiconductor layer.
2. The method according to claim 1, characterized in that The step of forming the plurality of marking points comprises: Using a visual camera to identify the dividing line; The plurality of marking points are formed on the first semiconductor layer and the second region by a laser etching process, and positions of the plurality of marking points are determined according to positions of the boundary lines.
3. The method according to claim 1, characterized in that The step of forming the isolation trench comprises: Using a visual camera to capture the target graphic and determine the target geometric center of the target graphic; Adjusting the laser of the laser etching process so that the laser passes through the target geometric center in the extension direction of the boundary line and forms a preliminary groove on the surface of the second semiconductor layer; The second semiconductor layer is continuously etched along the prepared trench to the semiconductor substrate to form the isolation trench.
4. The method according to any one of claims 1 to 3, characterized in that The multiple marking points are all arranged outside the dividing line.
5. The method according to any one of claims 4, characterized in that The multiple marking points include a first marking point, a second marking point, a third marking point and a fourth marking point, the first marking point, the second marking point, the third marking point and the fourth marking point are sequentially connected to form the target figure, and the target figure is a rectangle; The first marking point and the second marking point are set on the first area, and the third marking point and the fourth marking point are set on the second area; The line connecting the first marking point and the third marking point is the first diagonal line of the rectangle, the line connecting the second marking point and the fourth marking point is the second diagonal line of the rectangle, and the intersection of the first diagonal line and the second diagonal line is the geometric center of the target.
6. The method according to claim 5, characterized in that A line connecting the second marking point and the third marking point is parallel to the first direction; The distance between the second marking point and the third marking point in the first direction is D1; The width of the isolation trench in the first direction is A1, and D1>A1.
7. The method according to any one of claims 1 to 3, characterized in that At least one of the plurality of marking points is disposed on the dividing line.
8. The method according to claim 7, characterized in that The multiple marking points include a first marking point, a second marking point, a third marking point and a fourth marking point, the first marking point, the second marking point, the third marking point and the fourth marking point are sequentially connected to form the target figure, and the target figure is a rectangle; The first marking point and the second marking point are arranged on the dividing line, and the third marking point and the fourth marking point are arranged on the second area; The line connecting the first marking point and the third marking point is the first diagonal line of the rectangle, the line connecting the second marking point and the fourth marking point is the second diagonal line of the rectangle, and the intersection of the first diagonal line and the second diagonal line is the geometric center of the target.
9. The method according to claim 8, characterized in that A line connecting the second marking point and the third marking point is parallel to the first direction; The distance between the second marking point and the third marking point in the first direction is D1; The width of the isolation trench in the first direction is A1, and D1≤A1.
10. A solar cell prepared by the solar cell preparation method according to any one of claims 1 to 9, characterized in that: include: A semiconductor substrate, comprising a first region and a second region arranged along a first direction, wherein the first region and the second region are adjacent to each other and have a boundary line; A first semiconductor layer, located on the first region; A second semiconductor layer, located on the second region, wherein the first semiconductor layer and the second semiconductor layer have different doping types; An isolation trench is located between the first semiconductor layer and the second semiconductor layer and is used to isolate the first semiconductor layer from the second semiconductor layer. The boundary line is located in the isolation trench.