Package with backside mounted die and exposed die interconnect and method of manufacturing same

Abstract

A method of manufacturing a semiconductor device includes forming a protection structure over at least one die on a substrate. The protection structure exposes one or more electrical contacts on the first surface of the at least one die. A respective terminal is formed on the one or more electrical contacts exposed by the protective structure. Related packages and methods of manufacture are also discussed.

Description

[0001] Priority claim

[0002] This application claims priority to U.S. patent application serial No. 17 / 848,538 filed in the U.S. Patent and Trademark Office on June 24, 2022, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to semiconductor devices, and more particularly to semiconductor device packaging. Background Art

[0004] Power semiconductor devices such as power amplifiers are used in a variety of applications, such as base stations for wireless communication systems, multi-stage and multi-path amplifiers (e.g., Doherty amplifiers), etc. The signal amplified by the power amplifier typically includes a signal having a modulated carrier whose frequency is in the megahertz (MHz) to gigahertz (GHz) range. For example, circuits requiring high power handling capabilities while operating at high frequencies such as the R-band (0.5-1 GHz), S-band (3 GHz), X-band (10 GHz), Ku-band (12-18 GHz), K-band (18-27 GHz), Ka-band (27-40 GHz), and V-band (40-75 GHz) have become increasingly common. In particular, there is now a high demand for RF transistor amplifiers for amplifying radio frequency ("RF") signals having frequencies of, for example, 500 MHz and higher (including microwave frequencies).

[0005] Many power amplifier designs use semiconductor switching devices as amplifying devices. Examples of these switching devices include power transistor devices such as MOSFET (metal oxide semiconductor field effect transistor), DMOS (double diffused metal oxide semiconductor) transistor, HEMT (high electron mobility transistor), MESFET (metal semiconductor field effect transistor), LDMOS (lateral diffused metal oxide semiconductor) transistor, etc. The power amplifier may also include passive matching networks at the input nodes and output nodes of the active power transistor devices.

[0006] Transistor devices are typically formed as semiconductor integrated circuit chips. Transistor devices can be implemented, for example, in silicon, or using wide bandgap semiconductor materials (i.e., having a bandgap greater than 1.40 eV), such as silicon carbide ("SiC") and group III nitride materials. As used herein, the term "group III nitride" refers to those semiconductor compounds formed between nitrogen and group III elements in the periodic table, typically aluminum (Al), gallium (Ga), and / or indium (In). The term also refers to ternary and quaternary compounds, such as AlGaN and AlInGaN. These compounds have an empirical formula in which one mole of nitrogen is combined with a total of one mole of group III elements.

[0007] Silicon-based RF transistor amplifiers can often be implemented using LDMOS transistors and are able to exhibit high levels of linearity with relatively inexpensive manufacturing. Group III-nitride-based RF amplifiers can often be implemented using HEMTs, primarily for applications requiring high power and / or high frequency operation where LDMOS transistor amplifiers may have inherent performance limitations.

[0008] An RF transistor amplifier may include one or more amplifier stages, each of which is typically implemented as a transistor amplifier. To increase output power and current handling capability, an RF transistor amplifier is typically implemented in a "unit cell" configuration, in which a large number of individual "unit cell" transistors are electrically connected (e.g., in parallel). An RF transistor amplifier may be implemented as a single integrated circuit chip or "die," or may include multiple dies. A die or chip may include a small piece of semiconductor material or other substrate in which electronic circuit elements are fabricated. For example, multiple individual power transistor devices may be formed on a relatively large semiconductor substrate (e.g., by growing epitaxial layers thereon, doping selected regions with dopants, forming insulating layers and metal layers thereon, etc.), and the completed structure may then be cut or singulated (e.g., by sawing or cutting operations) into multiple individual dies. When multiple RF transistor amplifier dies are used, they may be connected in series and / or in parallel.

[0009] RF transistor amplifiers typically include matching circuits, such as impedance matching circuits, designed to improve impedance matching between active transistor dies (e.g., including MOSFET, HEMT, LDMOS, etc.) and transmission lines connected thereto for RF signals at fundamental operating frequencies, and harmonic termination circuits designed to at least partially terminate harmonic products, such as second-order and third-order harmonic products, that may be generated during device operation. Termination of harmonic products also affects the generation of intermodulation distortion products.

[0010] (One or more) RF amplifier transistor dies and impedance matching circuits and harmonic termination circuits can be enclosed in a device package. Integrated circuit packaging can refer to encapsulating one or more dies in a supporting housing or package (e.g., overmold or open cavity packaging) that protects the die from physical damage and / or corrosion and supports electrical contacts for connection to external circuits. The input and output impedance matching circuits in the integrated circuit device package typically include an LC network that provides at least a portion of an impedance matching circuit configured to match the impedance of the active transistor die to a fixed value. The package can include electrical leads to electrically connect the RF amplifier to external circuit elements, such as input and output RF transmission lines and a bias voltage source.

[0011] Some conventional methods of assembling RF power devices may involve assembling a transistor die and some matching network components in a ceramic or overmolded package on a laminate or flange. The transistor die, capacitor, and input / output leads may be interconnected with wires (such as gold wires and / or aluminum wires). The wire bonding-based connections of some conventional semiconductor device packages may introduce or cause several problems. For example, as the operating frequency increases (e.g., above about 5 GHz), the parasitic effects of wire bonding may cause variability in inductance, thereby affecting the design and / or effectiveness of the matching circuit. This wire bonding-based assembly process may also be slow and sequential (e.g., one package is bonded at a time), and the assembly cost may be high (e.g., due to the cost of gold wire and expensive wire bonding machines). Summary of the invention

[0012] According to some embodiments, a method of manufacturing a semiconductor device includes forming a protection structure on at least one tube core on a substrate, wherein the protection structure exposes one or more electrical contacts on a first surface of the at least one tube core, and forming corresponding terminals on the one or more electrical contacts exposed by the protection structure.

[0013] In some embodiments, a second surface of the at least one die is attached to the substrate using a die attach material between the second surface of the at least one die and the substrate, wherein the second surface is opposite the first surface.

[0014] In some embodiments, the die attach material and the substrate include respective thermally conductive materials.

[0015] In some embodiments, the substrate includes an insulating material or a semi-insulating material.

[0016] In some embodiments, the at least one die includes a passivation layer on the first surface, the passivation layer having one or more openings therein exposing the one or more electrical contacts, and the protection structure exposes the passivation layer.

[0017] In some embodiments, the protective structure comprises a molded structure.

[0018] In some embodiments, forming the protection structure includes a film assisted molding process, wherein a film covers the one or more electrical contacts during forming the molded structure.

[0019] In some embodiments, after forming the respective terminals, the substrate is singulated to define a plurality of semiconductor devices such that each semiconductor device includes one or more dies of the at least one die.

[0020] In some embodiments, the substrate has one or more dimensions of about 8 inches to about 12 inches.

[0021] In some embodiments, forming the corresponding terminals includes forming conductive bumps or conductive pillar structures on the one or more electrical contacts.

[0022] In some embodiments, the at least one die is disposed on an interconnect structure, wherein the respective terminals are electrically connected to conductive patterns of the interconnect structure.

[0023] In some embodiments, the at least one die is mounted on the interconnect structure in a flip chip configuration, with the respective terminals on the first surface of the at least one die facing the interconnect structure.

[0024] In some embodiments, the at least one die is located on a first surface of the interconnect structure, and a second surface of the interconnect structure is opposite the first surface and is configured to be mounted on an external device.

[0025] In some embodiments, the second surface of the interconnect structure includes input connections and output connections for a semiconductor device package.

[0026] In some embodiments, a support material is formed between the first surface of the at least one die and the interconnect structure. The support material extends from the corresponding terminal to the periphery of the protection structure.

[0027] In some embodiments, the at least one die includes one or more active transistor devices having a gate connection, a source connection, or a drain connection coupled to a respective terminal.

[0028] In some embodiments, at least one of the gate connection, the source connection, or the drain connection is located on a second surface of the at least one die opposite the first surface and is coupled to one or more conductive via structures extending through the at least one die.

[0029] In some embodiments, the at least one die includes one or more passive electrical components.

[0030] According to some embodiments, a method for manufacturing a semiconductor device package includes forming a protective structure on at least one die, wherein the protective structure exposes a first surface of the at least one die; forming corresponding terminals on the first surface of the at least one die exposed by the protective structure; and mounting the first surface of the at least one die on an interconnect structure in a flip-chip configuration, wherein the corresponding terminals face the interconnect structure and are electrically connected to a conductive pattern thereof.

[0031] In some embodiments, a support material is formed between the first surface of the at least one die and the interconnect structure, wherein the support material extends from the respective terminals to a periphery of the protection structure.

[0032] In some embodiments, the support material includes an underfill material.

[0033] In some embodiments, a second surface of the at least one die is attached to the substrate using a die attach material between the second surface of the at least one die and the substrate, wherein the second surface is opposite the first surface.

[0034] In some embodiments, the protective structure is a first protective structure, and

[0035] A second protection structure is formed on the interconnect structure and the substrate.

[0036] In some embodiments, the second protective structure includes a cover member defining an open cavity on the interconnect structure.

[0037] In some embodiments, the second protective structure includes a molded structure.

[0038] In some embodiments, the support material comprises a portion of the molded structure.

[0039] In some embodiments, the die attach material and the substrate include respective thermally conductive materials, and the second protection structure exposes at least a portion of the substrate.

[0040] In some embodiments, forming the second protection structure includes a laser ablation process or a mechanical grinding process to remove a portion thereof to expose the at least a portion of the substrate.

[0041] In some embodiments, the protective structure comprises a molded structure.

[0042] In some embodiments, forming the protection structure includes a film assisted molding process, wherein a film covers the one or more electrical contacts during forming the molded structure.

[0043] In some embodiments, forming the corresponding terminals includes forming conductive bumps or conductive pillar structures on one or more electrical contacts on the first surface.

[0044] In some embodiments, the at least one die is located on a first surface of the interconnect structure, and a second surface of the interconnect structure is opposite the first surface and is configured to be mounted on an external device.

[0045] In some embodiments, the second surface of the interconnect structure includes input connections and output connections for a semiconductor device package.

[0046] According to some embodiments, a semiconductor device package includes a substrate; at least one tube core, the at least one tube core including a first surface having corresponding terminals thereon and a second surface located on the substrate; a protective structure located on the at least one tube core and the substrate, wherein the protective structure exposes the corresponding terminals on the first surface of the at least one tube core; and a supporting material located on the first surface of the at least one tube core, wherein the supporting material extends from the corresponding terminals to the periphery of the protective structure.

[0047] In some embodiments, the support material includes an underfill layer.

[0048] In some embodiments, the package includes an interconnect structure having the at least one die thereon, wherein the respective terminals are electrically connected to conductive patterns of the interconnect structure.

[0049] In some embodiments, the first surface of the at least one die is positioned on the interconnect structure in a flip chip configuration with the respective terminals facing the interconnect structure.

[0050] In some embodiments, the protection structure is a first protection structure, and a second protection structure is disposed on the interconnect structure and the substrate.

[0051] In some embodiments, the second protective structure includes a cover member defining an open cavity on the interconnect structure.

[0052] In some embodiments, the second protective structure includes a molded structure.

[0053] In some embodiments, the support material comprises a portion of the molded structure.

[0054] In some embodiments, the substrate includes a thermally conductive material, and the second protection structure exposes at least a portion of the substrate.

[0055] In some embodiments, the at least one die includes one or more active transistor devices having a gate connection, a source connection, or a drain connection coupled to a respective terminal.

[0056] In some embodiments, the at least one die includes one or more passive electrical components.

[0057] In some embodiments, the at least one die is a Group III-nitride or silicon carbide based RF transistor amplifier die.

[0058] In some embodiments, the operating frequency of the RF transistor amplifier is in the R-band, S-band, X-band, Ku-band, K-band, Ka-band and / or V-band.

[0059] For those skilled in the art, other devices, apparatuses and / or methods according to some embodiments will be apparent after reviewing the following drawings and detailed description. In addition to any and all combinations of the above embodiments, all such additional embodiments shall also be included in this specification, belong to the scope of the present invention, and be protected by the accompanying claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] Figure 1A is a schematic plan view showing a top metallization structure of a power semiconductor device according to some embodiments of the present disclosure, which is shown by way of example using a high electron mobility transistor.

[0061] Figure 1B It is along Figure 3A A schematic cross-sectional view taken along line BB' of Figure 3A The structure of a unit cell transistor.

[0062] Figure 2A and Figure 2B is a schematic cross-sectional view illustrating an example of a semiconductor device according to some embodiments of the present disclosure.

[0063] Figure 3A , Figure 3B , Figure 3C and Figure 3D is a schematic side view illustrating a method of manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0064] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E and Figure 4F is a schematic plan view illustrating a method of manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0065] Figure 5 is a flow chart illustrating operations of fabricating a semiconductor device according to some embodiments of the present disclosure.

[0066] Fig. 6A , Figure 6B , Figure 6C , Fig.6D , Fig. 6E , Fig. 6F , Figure 6G and Figure 6H is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device using a thin film assisted molding process according to some embodiments of the present disclosure.

[0067] Fig. 7A and Figure 7B is a schematic side view illustrating an example semiconductor device package including a die in a flip-chip configuration according to some embodiments of the present disclosure.

[0068] Fig. 8A and Figure 8B is a schematic side view illustrating an example semiconductor device package in a lead frame configuration according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0069] In the following detailed description, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it will be appreciated by those skilled in the art that the present disclosure can be practiced without these specific details. In some cases, well-known methods, processes, components, and circuits are not described in detail to avoid confusing the present disclosure. It is intended that all embodiments disclosed herein can be implemented individually or combined in any manner and / or combination. Aspects described with respect to an embodiment may be incorporated into different embodiments, although not specifically described relative thereto. That is, all embodiments and / or features of any embodiment may be combined in any manner and / or combination.

[0070] As described above, the wire-bonding-based connections of some conventional semiconductor device packages may introduce or cause several problems. For example, as the operating frequency increases (e.g., above 5 to 6 GHz), the parasitic effects of the wire bonds may cause variability in the inductance, thereby affecting the design and / or effectiveness of the matching network. In addition, during operation, high heat levels may be generated within the (one or more) semiconductor die. If the (one or more) die becomes too hot, the performance of the amplifier (e.g., output power, efficiency, linearity, gain, etc.) may deteriorate and / or the (one or more) die may be damaged.

[0071] Some embodiments of the present invention may arise from the recognition that a flip chip configuration can help alleviate the above-mentioned problems and other problems. As used herein, "flip chip" can refer to a configuration in which pads or terminals or other circuit components of a transistor die are electrically connected through conductive bumps or pillars (rather than through wire bonding), which can allow stacked connections or vertical connections with one or more other circuit elements. For example, a transistor die can have one or more gate terminals, drain terminals, and source terminals, which are located on the same side or surface of the transistor die near the active conductive channel (also referred to as the active surface of the chip herein), which is opposite to the inactive surface of the die (also referred to as the back surface herein). The chip can be "flipped" onto the underlying interconnect structure (i.e., the active surface of the die faces the interconnect structure, and the opposite inactive surface of the die faces away from the interconnect structure) so that one or more terminals on the active surface are electrically connected to the conductive pattern of the interconnect structure.

[0072] Thus, the gate and drain connections may not require bond wires, which may reduce the amount of inductance present in the circuit, thereby reducing parasitic effects associated with packaging and connections. In addition, providing terminals for electrical connections at the active or front surface of the die for mounting in a flip-chip configuration may keep the heat conduction path away from external devices, such as circuit boards or other customer applications.

[0073] Embodiments of the present invention relate to packaging techniques for semiconductor dies (e.g., silicon (Si), silicon carbide (SiC), or gallium nitride (GaN) transistor dies on SiC and / or dies including passive electrical components), which provide a protective structure (e.g., a molded structure) around one or more dies provided on a lead frame or flange or other substrate, so that the die pads or other electrical contacts of (one or more) semiconductor dies are exposed. Electrical interconnects (referred to herein as connection terminals or simply terminals) are provided on the electrical contacts exposed by the protective structure. The terminals can be implemented by conductive pillars (e.g., copper pillars) and / or conductive bumps (e.g., solder bumps). Thus, the resulting semiconductor device can include active and / or passive dies integrated on a substrate or flange and protected by a molded or other protective member, which can be packaged to provide a semiconductor device package, or can be mounted to an external device (e.g., a customer circuit board), and in some embodiments, mounted in a flip-chip configuration.

[0074] Figure 1A is a schematic plan view showing a top metallization structure of a semiconductor chip 110 according to some embodiments of the present disclosure, which is shown by way of example with a high electron mobility transistor (HEMT) die. Figure 1B It is along Figure 1A A schematic cross-sectional view taken along line BB' shows Figure 1AAlthough described herein by way of example with reference to a HEMT, it should be understood that embodiments of the present disclosure are not limited to any particular transistor type and may include, for example, metal oxide semiconductor field effect transistor (MOSFET) embodiments, such as lateral diffused MOSFET (LDMOS) embodiments.

[0075] like Figure 1A and Figure 1B As shown in , the transistor device or die 110 may include a plurality of transistor unit cells or structures 100 connected in parallel to device terminals or electrodes (e.g., input terminals, output terminals, and ground terminals). For example, each of the gate 152, drain 154, and source 156 contacts may extend in a first direction (e.g., an X direction) to define gate, drain, and / or source "fingers" that may be connected by one or more corresponding busses (e.g., a gate bus and a drain bus near the upper surface or active surface 136A of the semiconductor structure 190). In particular, the gate fingers 152 are electrically connected to a common gate manifold 142, and the drain fingers 154 are electrically connected to a common drain manifold 144. The gate manifold or bus 142 is electrically connected to a gate terminal 222, which may be implemented as one or more conductive bumps or pillars, and the drain manifold or bus 144 is electrically connected to a drain terminal 224, which may be implemented as one or more conductive pillars or bumps (as described herein with reference to Figure 2A and Figure 2B Source fingers 156 are electrically connected to source terminals 226 (source terminals 226 may be implemented by one or more conductive bumps or pillars) and / or source bus 146. Electrical contacts 145 on one or more surfaces of die 110 (e.g., die pads; see Figure 2A and Figure 2B ) can be connected to gate, drain and source busses 142, 144 and 146 respectively.

[0076] exist Figure 1A1 , gate fingers 152, drain fingers 154, and source fingers 156 extend parallel to one another, wherein the gate fingers 152 extend from the gate bus 142 in a first direction, and the drain fingers 154 extend from the drain bus 144 in a direction opposite to the first direction. Each gate finger 152 may be positioned between drain fingers 154 and source fingers 156 to define a unit cell 100. The gate fingers 152, drain fingers 154, and source fingers 156 (and the connection busses) may define a portion of the gate, drain, and source connection electrodes of the device, respectively, as defined by the top side metallization structure 140. Since the gate fingers 152 are electrically connected to the common gate bus 142, the drain fingers 154 are electrically connected to the common drain bus 144, and the source fingers 156 are electrically connected together, it can be seen that the unit cell transistors 100 are electrically connected together in parallel. One terminal of the device (eg, source terminal 226 connected to source contact(s) 156 or bus 146 ) may be configured to be coupled to a reference signal, such as, for example, electrical ground.

[0077] like Figure 1B As shown in , semiconductor die 110 may be formed on a substrate 132, such as, for example, a SiC, Si, or sapphire substrate, which in some embodiments may include a back surface or inactive surface 132A that provides a heat dissipation surface HD. Figure 1B In the unit cell structure 100, a channel layer 134 is formed on a substrate 132. A barrier layer 136 is formed on the channel layer 134 opposite to the substrate 132. The channel layer 134 may include, for example, gallium nitride (GaN), and the barrier layer 136 may include, for example, aluminum gallium nitride (AlGaN). The channel layer 134 and the barrier layer 136 may be formed together in a semiconductor layer structure 190 on the substrate 132. A source contact 156 and a drain contact 154 are formed on an upper surface of the barrier layer 136 and are laterally spaced apart from each other. The source contact 156 and the drain contact 154 may form an ohmic contact to the barrier layer 136.

[0078] The gate contact 152 is formed on the upper surface of the barrier layer 136 between the source contact 156 and the drain contact 154. When the HEMT device 110 is biased to be in its conductive or "on" state, a two-dimensional electron gas (2DEG) layer is formed at the junction between the channel layer 134 and the barrier layer 136. The 2DEG layer acts as a highly conductive layer that allows current to flow between the source and drain regions of the device, respectively, below the source contact 156 and the drain contact 154. The source contact 156 can be coupled to a reference signal, such as, for example, a ground voltage.

[0079] In some embodiments, one or more insulating layers 150 may directly contact an upper surface of semiconductor structure 190 (e.g., contacting upper surface 136A of barrier layer 136). One or more insulating layers 150 may serve as a passivation layer for device 110. Electrical contacts 145 may be electrically coupled to gate contact 152, drain contact 154, and / or source contact 156. Die interconnect structures or terminals 225 (e.g., conductive pillars or conductive bumps) may protrude from front surface 112 of die 110 to provide electrical connections between gate contact 152, drain contact 154, and / or source contact 156 and an external device or module. Figure 1A The dielectric layer is not shown in the figure to isolate the various conductive elements of the top side metallization structure 140 from each other to simplify the figure. It should be appreciated that Figure 1A and Figure 1B (and other figures) are highly simplified diagrams, and actual semiconductor devices may include many more unit cells and various circuit systems and elements that are not shown in the simplified diagrams herein.

[0080] Figure 2A and 2B is a schematic cross-sectional diagram illustrating an example of semiconductor devices 200a and 200b according to some embodiments of the present disclosure, the semiconductor devices 200a and 200b including active transistor dies 110a and 110b (collectively 110) on a carrier substrate 260, wherein a protection structure 240 exposes one or more electrical contacts 145 or terminals 225 of the dies 110. The carrier substrate 260 may be configured to provide a lead frame or flange for the semiconductor devices 200a, 200b.

[0081] Substrate 260 can be a base frame or flange formed of a variety of materials. In some embodiments, substrate 260 can include one or more metals or other thermally conductive materials. For example, substrate 260 can be CPC (copper, copper molybdenum, copper laminate) or a copper flange. In some embodiments, substrate 260 can include a metal heat sink as part of a lead frame or metal slug. Thus, substrate 260 can be assembled in a circuit board such as the one shown in FIG. 7A to 8B The substrate 260 may provide improved thermal dissipation of heat generated by the die 110 when packaged in a semiconductor device such as those described herein. For example, the substrate 260 may provide a package-level heat slug configured to pull heat from the die 110 toward an external heat sink. In some packaging configurations, the carrier substrate 260 also serves as an electrical terminal for providing a reference potential (e.g., ground) to the die mounted thereon. In other embodiments, the substrate 260 may include one or more insulating or semi-insulating materials (e.g., Si or SiC) or other materials that may be used in semiconductor processing.

[0082] Figure 2A An example semiconductor device 200a is illustrated in which the terminals 225 of the die 110a are implemented as conductive pillar structures 222, 224, 226 that protrude from a first surface or active surface 212 of the die 110a (adjacent to the active channel 2 (e.g., 2DEG layer)) and a second surface or inactive surface 214 of the die 110a is mounted on a substrate 260. Figure 2B An example semiconductor device 200b is illustrated in which some terminals 225 (e.g., gate and drain terminals) of the die 110b are implemented as conductive bumps 222′, 224′ protruding from a first or active surface 212 of the die 110b, and at least one other terminal 225 (e.g., source terminals 146, 226) is located on a second or inactive surface 214 of the die 110b and coupled to one or more conductive via structures 207 extending through the die 110b to provide a connection to the active surface 212. Various other combinations of terminals 225 implemented by conductive pillars and / or conductive bumps on the first and / or second surfaces of the die 110 may be used in accordance with embodiments of the present disclosure.

[0083] like Figure 2A and Figure 2B As shown in FIG. 1 , the second or inactive surface 214 of the die 110 is attached to the substrate 260 by a die attach material 111. The die attach material 111 may be a thermally conductive die attach layer, such as a eutectic layer, or other thermally conductive adhesive layer. In some embodiments, the semiconductor devices 200a and 200b may be "flipped" (with respect to Figure 2A and 2B ) and attached to a package structure or external circuit board, with the terminals 222, 224, and 226 on one side 212 of the die 210 facing "down" and the growth substrate on the opposite side 214 facing "up", i.e., in a flip-chip configuration. In some embodiments, a support material (herein 121), such as an underfill material or another encapsulant material, mechanically supports the terminals 225 and / or the protective structure 240 along an interface with other package components or external devices.

[0084] Still refer to Figure 2A and Figure 2B, an encapsulating protective structure 240 is formed around the tube core 210. For example, the protective structure 240 can be a dispensed and cured encapsulant or compound, such as a plastic or plastic polymer compound, which is formed to encapsulate one or more surfaces of the tube core (one or more) 110 and the interconnect structure 105, thereby providing environmental protection for the package 200a, 200b. The protective structure 240 is formed or otherwise configured to expose the electrical contacts 145 on the first surface of the tube core (one or more) 110. The thickness of the protective structure 240 can be substantially similar to the thickness of the tube core 210, and can provide improved mechanical support. In some embodiments, the surface of the protective structure 240 can be substantially coplanar with the front surface 212 of the tube core (one or more) 110, 130. In some embodiments, the surface of the protective structure 240 can be recessed or protruding relative to the front surface 212 of the tube core (one or more) 110, 130 facing the interconnect structure 105.

[0085] Although in Figure 2A and Figure 2B 2. The semiconductor die 110 is described with reference to the semiconductor die 110 as comprising an active transistor mounted on the surface of the substrate 260 and protected by the protective structure 240, but it will be understood that the semiconductor die 110 comprising a variety of passive electrical components (shown as 130 in subsequent figures) may be similarly mounted on the surface of the substrate 260 and protected by the protective structure 240. The passive electrical component die 130 may include, for example, resistors, inductors and / or capacitors implemented by discrete devices (e.g., surface mounted devices (SMDs) or integrated passive devices (IPDs) having a thin film substrate such as silicon, alumina or glass). Therefore, the term "die" as used herein may refer to an active component die 110 (e.g., a transistor die) or a passive component die 130 (e.g., a capacitor chip or an IPD). That is, the example semiconductor devices 200a, 200b may include (one or more) active die 110 (e.g., semiconductor die based on Si, III-nitride and / or SiC) or passive die 130 (e.g., IPD) or a combination thereof. Figure 2A and Figure 2B Although described with reference to specific examples, in some embodiments, features of one or more examples may be combined. For example, Figure 2B The conductive via structure 207 can be connected with Figure 2A The conductive pillar 225 is used in combination.

[0086] FIG. 3A to FIG. 3D is a schematic side view illustrating a method of manufacturing a semiconductor device according to some embodiments of the present disclosure. FIG. 4A to FIG. 4Eis a schematic plan view illustrating a method of manufacturing a semiconductor device according to some embodiments of the present disclosure. Figure 5 is a flow chart illustrating operations for fabricating a semiconductor device according to some embodiments of the present disclosure.

[0087] like Figure 3A , Figure 4A and Figure 5 As shown in FIG. 2 , a substrate 260 is provided. The substrate 260 may be a base frame or flange formed of a variety of materials such as a thermally conductive material (e.g., copper) or a thermally insulating material or a semi-insulating material (e.g., Si, SiC). The substrate 260 may be configured to provide a lead frame or flange for a single semiconductor device (e.g., Figure 3A ), or the substrate may be a sheet or panel (e.g., having a rectangular or oval shape in plan view to be compatible with corresponding semiconductor wafer processing) configured to be cut or otherwise singulated into lead frames or flanges for a plurality of semiconductor devices (e.g., Figure 4A For example, the substrate 260 may have a shape and one or more dimensions corresponding to a standard (e.g., 8-inch to 12-inch) wafer shape. In some embodiments, the substrate frame or flange 260 may be prefabricated to include a plurality of substrates 260 (e.g., Figure 4F ), which can simplify subsequent singulation into lead frames or flanges for multiple semiconductor devices (particularly for metal-based substrates 260).

[0088] At block 505, a die attach material 111 (eg, solder or other adhesive material) is provided on the substrate 260 (or on the back surface of the dies 110 and / or 130). In some embodiments, the die attach material 111 may be thermally conductive.

[0089] like Figure 3B , Figure 4B and Figure 5 As shown in , at block 510, one or more dies 110 and / or 130 are attached to substrate 260. The semiconductor die(s) 110 may be active transistor dies, while the die(s) 130 may include one or more passive electrical components. The semiconductor die(s) 110 may include a passivation layer 250 on a first or front surface thereof. The passivation layer 250 may include one or more openings therein that expose electrical contacts 145 on the first surface of the semiconductor die(s) 110 (e.g., a gate bus 142 or a drain bus 144 coupled to the die 110). The second or back surface of the die(s) 110 and / or 130 may be attached to substrate 260 by a die attach material 111.

[0090] like Figure 3C , Figure 4C and Figure 5 As shown in FIG. 5 , at block 515, a protective structure 240 is formed on the semiconductor die (s) 110 and / or 130 and on the die attach material 111 and the substrate 260. The protective structure 240 exposes one or more electrical contacts 145 of the semiconductor die (s) 110 and / or 130. In particular, at Figures 3A to 5 In the example of , the protective structure 240 is implemented by a molded structure (e.g., plastic or plastic polymer compound) formed on the substrate 260 and surrounding the side surfaces of the (one or more) semiconductor dies 110 and / or 130. In some embodiments, the substrate 260 may include one or more openings or mold lock features 262 that improve the adhesion of the molded structure 240 thereon. The protective structure 240 exposes at least a portion of the passivation layer 250 and the electrical contacts 145. For example, the protective structure 240 may be formed by a film assisted molding process, in which the film 630 covers the passivation layer 250 and / or the electrical contacts 145 during the formation of the molded structure, as described below with reference to FIG. 6A to FIG. 6D described.

[0091] like Figure 3D , Figure 4D and Figure 5 As shown in , at frame 520, a corresponding terminal 225 is provided on the electrical contact 145 exposed by the protection structure 240 (and the opening in the passivation layer 250). In some embodiments, the corresponding terminal 225 can be formed as a conductive bump (e.g., a solder ball). In some embodiments, the corresponding terminal 225 can be formed as a conductive column structure (e.g., a Cu column). In (one or more) semiconductor dies 110, the terminal 225 can be coupled to the gate, source or drain connection 142, 144 or 146. In (one or more) semiconductor dies 130, the terminal 225 can be coupled to the input or output connection of the passive electrical component. A semiconductor device 300 including one or more back-side mounted dies 110 and / or 130 and exposed interconnect terminals 225 can thereby be formed.

[0092] like Figure 4E As shown in , in an embodiment where the substrate 260 is a panel or sheet structure, after forming the corresponding terminals 225 on the (one or more) semiconductor dies 110 and / or 130, the substrate 260 is cut or otherwise singulated to define a plurality of semiconductor devices 400. Each semiconductor device 400 includes a portion of the substrate 260 on which one or more of the (one or more) semiconductor dies 110 and / or 130 are mounted.

[0093] Fig. 6A , Figure 6B , Figure 6C and Fig.6Dis a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device using a film assisted molding process according to some embodiments of the present disclosure. In the film assisted molding process, a film or tape covers a passivation layer and / or electrical contacts during formation of a molding structure as a protective structure.

[0094] like Fig. 6A As shown in , a molding device 605 including an upper mold chase 610 and a lower mold chase 620 is opened, and one or more substrates 260 (including one or more dies 110 and / or 130 mounted thereon, respectively) are loaded into the mold chases 610, 620. For example, the substrate 260 may be a sheet or panel including a group or collection of dies 110 and / or 130, which is configured to be singulated into corresponding semiconductor devices, and may be placed (automatically or manually) into the mold chases 610, 620, and clamped or otherwise fixed in the lower mold chase 620, such as by vacuum. The upper mold chase 610 includes a film or tape material 630 loaded therein. The film or tape material 630 is pulled toward the upper mold chase 610, such as by vacuum, so that the film or tape material 630 may conformally extend along the inner surface of the upper mold chase 610.

[0095] like Figure 6B , the molding device 605 is closed by clamping the upper mold frame 610 and the lower mold frame 620 together, so that the adhesive surface of the film or tape material 630 is pressed onto or otherwise contacts the corresponding surface of the tube core 110 and / or 130. More specifically, the adhesive surface of the film or tape material 630 is pressed onto the passivation layer 250 on the first surface or upper surface of the tube core 110 and / or 130. Thus, the film or tape material 630 covers the opening in the passivation layer 250, so that the electrical contact 145 is protected by the film or tape material 630. For example, the film or tape material 630 can conformally extend into the opening in the passivation layer 250 to physically contact the electrical contact 145.

[0096] The film or tape material 630 may have a thickness and / or compressibility configured to at least partially compensate for variations in the depth of the openings in the passivation layer 250 and / or variations in the height of the dies 110 and / or 130. For example, the film or tape material 630 may be configured to compensate for or allow for a tolerance of approximately 20 μm to 50 μm in the height variations between the dies 110 and / or 130. In some embodiments, the film or tape material 630 may have a thickness of approximately 50 μm to 100 μm.

[0097] With the molding device 605 closed and the film or tape material 630 in contact with the upper surface of the die 110 and / or 130 opposite the interconnect structure 105 (or the surface of the passivation layer 250 thereon), a molding compound (e.g., a plastic or polymer compound) is pressed or otherwise introduced into the molding frame to form the protective structure 240. The molding compound covers the surface of the substrate 260 and the side surfaces of the die 110 and / or 130 thereon. The upper surface of the die 110 and / or 130 (or the surface of the passivation layer 250 thereon) is protected by the film or tape material 630, which prevents the molding compound from forming thereon.

[0098] Therefore, if Figure 6C As shown in , when removed from the molding device 605, the substrate or panel 260 includes a plurality of dies 110 and / or 130 with electrical contacts 145 and a passivation layer 250 on the upper surface thereof exposed by the protective structure 240. Fig.6D In some embodiments, corresponding terminals 225 (shown as conductive bumps) are formed on the electrical contacts 145 exposed by the protection structure 240 (and the openings in the passivation layer 250). Fig.6D After the operation, the substrate or panel 260 can be cut or otherwise singulated to define corresponding semiconductor devices 600, each of which includes a portion of the protection structure 240, the substrate 260, and one or more of the (one or more) semiconductor tube cores 110 and / or 130 mounted thereon.

[0099] In another embodiment, Fig. 6E As shown in , a substrate (or panel) 260 including (one or more) semiconductor dies 110 and / or 130 thereon can be mounted on an interconnect structure 105 for packaging, such as a printed circuit board (PCB) or a redistribution layer (RDL) laminate structure. One or more dies 110 and / or 130 can be mounted on the interconnect structure 105 in a flip chip configuration, wherein the corresponding terminals 225 face the surface of the interconnect structure 105 and are electrically connected to its conductive pattern.

[0100] Fig. 6F In the embodiment, a second protective structure 640 (an additional encapsulation molding structure in this example) is formed on the surface of the interconnect structure 105 and on one or more surfaces of the protective structure 240 and the substrate or panel 260. Fig. 6F In the example of Fig.6DThe resulting semiconductor device structure(s) 600 as a whole includes a surface of the substrate or panel 260 that covers the surface opposite the interconnect structure 105. A portion of the second protection structure 640 extends continuously from the terminals 225 and / or the passivation layer 250 of the die 110 and / or 130 to (and beyond) the periphery of the initial (or "first") protection structure 240, serving as a support material or layer 121 to provide mechanical support along the interface between the interconnect structure 105 and the elements 110 / 130, 225, 250 and / or 240 of the semiconductor device structure(s) 600. Although in Fig. 6F 640 is shown as a molded structure, but it will be understood that the second protective structure 640 may alternatively be formed by a cover member (e.g., Fig. 8A The support material or layer 121 may be implemented by defining the open cavity 812 in the second protective structure 640 (841 and 842) or other protective members. In this case, the support material or layer 121 may be a bottom filling material or other layer different from the second protective structure 640.

[0101] like Figure 6G As shown in , a portion of the second protective structure 640 can be removed to expose the surface of the substrate or panel 260 opposite the interconnect structure 105. For example, a mechanical grinding process (e.g., using a rotary or other grinding device) and / or a laser ablation process (using a laser) can be performed to remove a portion of the second protective structure 640. The exposed surface of the substrate or panel 260 can be recessed, protruding, or coplanar with the surface 640s of the second conductive structure 640, depending on the removal process. The surface of the substrate or panel 260 opposite the interconnect structure 105 thus defines a heat dissipation surface exposed by the second protective structure 640. In some embodiments, as Figure 6H As shown in , additional metal or other thermally conductive members 660 may (optionally) be formed on the exposed surface of the substrate or panel 260 to further enhance thermal capacity.

[0102] exist Figure 6G (or 6H), the substrate or panel 260, the protective structure 240, 640, the thermally conductive member 660 (when present), and the underlying interconnect structure 105 can be cut or otherwise singulated to define a corresponding semiconductor device package. Figure 7A-Figure 8B Various examples of semiconductor device packaging are described.

[0103] Fig. 7A and Figure 7B is a schematic side view illustrating example semiconductor device packages 700a and 700b in a flip-chip configuration according to some embodiments of the present disclosure, the example semiconductor device packages 700a and 700b including die(s) 110, 130 disposed on a substrate 260 and having terminals exposed by a protective structure 240. Figure 7A-7BAs shown in FIG. 1 , semiconductor device packages 700 a , 700 b respectively include one or more semiconductor devices (eg, 200 a , 200 b , 300 , 400 , 600 ) as described herein mounted on an interconnect structure 105 .

[0104] The interconnect structure 105 may be a single layer laminate or a multi-layer laminate, such as a PCB or RDL laminate structure, wherein the conductive pattern 107 is implemented as conductive traces and / or vias in or on the PCB or RDL laminate structure. The terminals of the semiconductor die 110 (e.g., gate, drain, and / or source terminals, illustrated as conductive bumps or pillar structures 222, 224, and / or 226) are connected to the front surface or active surface ( Figure 2A-2B 212) and electrically connected to the conductive pattern 107 of the interconnect structure 105 at the first surface of the interconnect structure 105 in a flip chip configuration. The second surface of the interconnect structure 105 opposite to the first surface having the die(s) 110 thereon provides a device configured to be mounted on an external device (such as Figure 7B In some embodiments, input leads or terminals 115A and output leads or terminals 115B and ground leads or terminals 115G (collectively referred to as leads 115) for packages 700a, 700b may be provided on the second surface of the interconnect structure 105. Figure 7A-7B In the example packages 700a, 700b, the interconnect structure 105 is a multilayer laminate including a conductive pattern 107, which may be fabricated using semiconductor processing techniques, such as by depositing conductive layers and / or patterns and insulating layers and / or patterns on a substrate and forming vias and conductive wiring patterns within the structure.

[0105] The (one or more) semiconductor die 110 may include a semiconductor structure (e.g., a Si, SiC and / or GaN-based structure) that defines an active transistor unit cell therein. The packages 700a, 700b may also include a variety of passive electrical components that may include resistors, inductors and / or capacitors implemented as discrete devices (e.g., SMDs or IPDs with thin film substrates such as silicon, alumina or glass) and / or by elements integrated into an interconnect structure (e.g., spiral inductors, laminate-based transmission lines, etc.). The passive electrical components may be configured, for example, to provide impedance matching circuits and / or harmonic termination circuits and may be coupled to corresponding gate 222, drain 224 or source 226 terminals of the (one or more) transistor die 110 (e.g., located between the corresponding terminals 222, 224 or 226 and the input, output or ground connection 115). As Fig. 7AAs shown in , the semiconductor die 130 including one or more passive electrical components is implemented in a flip chip configuration, wherein the corresponding terminals face the interconnect structure and are electrically connected to the conductive pattern. Additionally or alternatively, in some embodiments, the conductive pattern 107 within the interconnect structure 105 may define one or more passive electrical components (shown by way of example as an embedded spiral inductor).

[0106] like Figure 7A-7B , the die(s) 110, 130 are mounted on a first surface of the interconnect structure 105 (with the support material 121 therebetween) in a flip chip configuration, with the respective terminals 222, 224, and / or 226 on the active surface of the die(s) 110 facing the interconnect structure 105 for electrical connection with the conductive pattern 107. The inactive surface of the die(s) 110 faces away from the interconnect structure 105. The passive electrical component die(s) 130 are similarly mounted on the first surface of the interconnect structure 105 in a flip chip configuration, with the back or inactive surface facing away from the interconnect structure 105.

[0107] The protective structure 240 (in this example, a molded structure) provides environmental protection for the die(s) 110, 130. For example, the molded structure 240 may be formed of a dispensed and cured encapsulant or compound (such as a plastic or plastic polymer compound) that encapsulates or otherwise covers one or more surfaces of the die(s) 110, 130 and the interconnect structure 105. The protective structure 240 exposes the terminals 225 of the die(s) 110, 130. In some embodiments, the surface of the protective structure 240 that faces the interconnect structure 105 may be substantially coplanar with the front surface 212 of the die(s) 110, 130. In some embodiments, the surface of the protective structure 240 that faces the interconnect structure 105 may be recessed or protruding relative to the front surface 212 of the die(s) 110, 130 that faces the interconnect structure 105.

[0108] Support material 121 is provided to mechanically support terminals 225 and / or protection structure 240 when terminals 225 and / or protection structure 240 are mounted on the interconnect structure. In particular, support material 121 extends between first surface 212 of die 110 and / or 130 and interconnect structure 105, and between a surface of protection structure 240 and interconnect structure 105. In some embodiments, support material 121 extends (e.g., continuously) from terminals 225 on first surface 212 of die 110 and / or 130 to (or beyond) the periphery of protection structure 240 adjacent to an edge of package 700a, 700b. In some embodiments, such as Figure 7BAs shown in , one or more dimensions of package 700b can extend beyond one or more dimensions of die 110 by about 300 μm or less, so that support material 121 can also extend from terminal 225 to extend beyond die 110 by about 300 μm or less. In some embodiments, support material 121 can be an underfill material or layer. In some embodiments, support material 121 can be a molding compound or structure (e.g., Fig. 6F Although illustrated in packages 700a, 700b as providing mechanical support at the surface of interconnect structure 105 along the interface with semiconductor die(s) 110, 130 and their terminals 225, it will be appreciated that support material 121 may more generally extend along the interface between semiconductor die(s) 110, 130 / terminals 225 / protection structure 240 and other package components or even external devices (e.g., in embodiments where substrate 260 and die(s) 110, 130 are mounted directly on a circuit board or other external device).

[0109] The semiconductor device packages 700a, 700b may be configured to electrically couple the package connections 115 to an external device, such as Figure 7B . The circuit board 3 shown in . The circuit board 3 may include conductive elements or traces on its surface, and the semiconductor device packages 700a, 700b may be configured so that the input connection 115A, the output connection 115B and / or the ground connection 115G are aligned with corresponding ones of the conductive elements on the external circuit board 3 for electrical connection. Although described with reference to the package 700b, it will be understood that the package 700a may be similarly mounted on the circuit board 3 and / or electrically coupled to the circuit board 3.

[0110] exist Figure 7B In the example of , the circuit board 3 also includes an integrated heat dissipation member, illustrated by way of example as a heat conductive coin 6 extending through the circuit board 3 and a heat sink 4 located on a surface of the circuit board 3 opposite to the surface on which the package 700b is mounted. Thus, the example package 700b can be configured to provide one or more thermally conductive paths for dissipating heat away from the external device 3. In particular, heat can be dissipated at the top side of the package 700b through a first thermal path 709, as defined by the thermally conductive substrate 260 on the back surface (e.g., 214) of the (one or more) tube cores 110, 130. Heat can also be dissipated at the bottom side of the package 700b through a second thermal path 709', as defined by the terminal 226, the conductive pattern 107, the ground reference 115G, the coin 6 and the heat sink 4 (which can also provide an electrical path to the ground connection).

[0111] In some embodiments, the circuit board 3 may include additional active and / or passive electronic components. For example, the circuit board 3 may include additional passive electronic components configured to provide input and / or output pre-matching circuits for one or more amplifiers of the package 700b.

[0112] Fig. 8A and Figure 8B is a schematic side view illustrating example semiconductor device packages 800A and 800B in a lead frame configuration according to some embodiments of the present disclosure, the example semiconductor device packages 800A and 800B including die(s) 110, 130 disposed on a substrate 260 and having terminals exposed by a protection structure 240. Figure 8A-B In the example of , the gate terminal and drain terminals 222, 224 of the die 110 are located on the front surface 212, and the source terminal 226 is located on the back surface 214. The source terminal 226 can be mounted on the substrate 260 using, for example, the conductive die attach material 111. The substrate 260 can provide an electrical connection to the source terminal 226 and can also serve as a heat dissipation structure to dissipate heat generated in the die 110. For example, the bottom surface of the substrate 260 can be exposed by the package 800A, 800B as a thermally conductive path. More generally, the substrate 260 can include materials and / or physical orientations configured to assist in thermal management of the package 800A, 800B.

[0113] like Fig. 8A As shown in , the semiconductor device package 800A includes (one or more) tube cores 110, 130 and a substrate 260 encapsulated in an overmolded packaging structure 800A. The package 800A includes a metal gate lead 115A", a metal drain lead 115B", and an interconnect structure 105, the interconnect structure 105 includes a conductive pattern 107 therein and / or thereon, and the conductive pattern 107 provides an electrical connection between the tube cores 110, 130. A protective structure 840 (a plastic overmold in this example) at least partially surrounds the substrate 260, the tube cores 110, 130, the interconnect structure 105, and the leads 115A", 115B" (which are coupled to the interconnect structure 105 by bonding wires 854 in this example). Support material 121 may extend between die 110 and / or 130 and interconnect structure 105 , and between protection structure 240 and interconnect structure 105 (eg, from terminals 225 to a periphery of protection structure 240 ) to provide mechanical support along the interface therebetween.

[0114] Although Fig. 8AThe protective structure 840 shown in is implemented as a molded structure, but the protective structure 840 can also be implemented by a sidewall and cover member that defines an open or air-filled cavity. In some embodiments, the sidewall and / or the cover can be formed of or include an insulating material. For example, the sidewall and / or the cover can be formed of or include a ceramic material. In some embodiments, the sidewall and / or the cover can be formed of, for example, Al2O3. The cover can be glued to the sidewall using epoxy glue. The sidewall 840 can be attached to the surface of the substrate 260, for example by soldering. The gate lead 115A" and the drain lead 115B" can be configured to extend through the sidewall, but embodiments of the present invention are not limited to this.

[0115] like Figure 8B As shown in FIG. 8 , the semiconductor device package 800B and Fig. 8A The semiconductor device package 800A of the present invention is similar to that of the present invention, except that the interconnect structure 105 includes a conductive pattern 107 therein and / or thereon, which provides leads 115A, 115B and provides electrical connections between the tube cores 110, 130 and the leads 115A, 115B. Therefore, the package 800B can be without wire bonding. The package 800B also includes one or more passive components or tube cores 130A, 130B, 130C (e.g., IPD and / or SMD), which are located on the opposite side of the interconnect structure 105 from the tube cores 110, 130. One or more passive components or tube cores 130A, 130B, 130C are covered by a protective structure 840, which exposes their corresponding terminals, similar to the protective structure 240. Thus, the first die(s) 110 and / or 130 having the protection structure 240 exposing their respective terminals are mounted on a first surface of the interconnect structure 105, and the second die(s) 130A, 130B, 130C having the protection structure 840 exposing their respective terminals are mounted on a second surface of the interconnect structure 105 opposite to the first surface. Although shown as a mold compound by way of example, in some embodiments, the protection structure 840 may be implemented by a cover member and sidewalls to define an air-filled or open cavity around the passive components or die 130A, 130B, 130C. Other components of the RF transistor amplifier 800B may be the same as those of the RF transistor amplifier 800A having the same reference numerals, and thus further description thereof will be omitted.

[0116] Matching circuits may also be implemented within any of the packages 800A, 800B, for example, by one or more of the discrete passive components 130, 130A, 130B, 130C and / or by spiral inductors, laminate-based transmission lines, or other passive elements integrated within the interconnect structure 105. The matching circuits may include impedance matching circuits and / or harmonic termination circuits. The impedance matching circuits may be used to match the impedance of the fundamental component of the RF signal input to or output from the die(s) 110 to the impedance at the input or output of the die(s) 110, respectively. The harmonic termination circuits may be used to ground the harmonics of the fundamental RF signal that may be present at the input or output of the die(s) 110.

[0117] Thus, embodiments of the present disclosure may provide corresponding terminals for die-to-leadframe electrical connection (e.g., using conductive pillars or conductive bumps), but the corresponding terminals may be formed after forming a mold or other protective structure around the active or passive component die. Embodiments of the present disclosure may improve thermal transfer of the GaN die by allowing backside cooling through the lead frame flange, and / or may improve RF performance by reducing parasitic loading using copper pillars / solder bumps / bumps instead of wires for die-to-external connection. In some embodiments, a manufacturing method as described herein may attach one or more flip chip dies to a lead frame or other flange with the active side of the die(s) facing up; mold the die(s) and lead frame together so that electrical contacts or die pads are exposed through the molded structure; and then provide die pad interconnect components or terminals (e.g., copper pillars, solder balls, solder bumps) to the exposed electrical contacts or die pads. The manufacturing method may be performed in parallel for a sheet or panel including a plurality of flanges, which may be singulated to define respective semiconductor devices for packaging and / or direct attachment to an external circuit board.

[0118] Embodiments of the present disclosure may be used for higher power / higher frequency RF power products that may benefit from flip chip configurations and top-side cooling. For example, some embodiments of the present disclosure may be used for high power RF transistors for cellular applications or aerospace and defense (A&D) applications, such as RF transistors with 20W or higher average output power for 5G base station applications at 3.5GHz and above. Embodiments of the present disclosure may also allow for low-cost products that are configured to operate at higher frequencies. Although embodiments of the present disclosure have been described herein with reference to specific HEMT structures, the present disclosure should not be construed as being limited to such structures, and the present disclosure may be applied to form many different transistor structures, such as pHEMTs (including GaAs / AlGaAs pHEMTs) and / or GaN MESFETs.

[0119] Various embodiments have been described herein with reference to the accompanying drawings in which example embodiments are shown. However, these embodiments may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure thorough and complete and to fully convey the inventive concept to those skilled in the art. Various modifications to the example embodiments and the general principles and features described herein will be apparent. In the accompanying drawings, the sizes and relative sizes of the layers and regions are not shown to scale and may be exaggerated in some cases for clarity.

[0120] It will be understood that, although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0121] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used herein, the singular forms "a", "an" are intended to also include the plural forms, unless the context clearly indicates otherwise. It will be further understood that the terms "comprise", "include" and / or "comprising" when used herein specify the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or combinations thereof.

[0122] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art to which the present invention belongs. It will be further understood that the terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and the relevant art, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0123] It will be understood that when an element such as a layer, region, or substrate is referred to as being "on another element," "attached to another element," or "extending onto another element," it can be directly on the other element or intervening elements may also be present. Conversely, when an element is referred to as being "directly on another element," "directly attached to another element," or "extending directly onto another element," there are no intervening elements. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or there may be intervening elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0124] Relative terms such as "below" or "above" or "up" or "lower" or "horizontal" or "lateral" or "vertical" may be used herein to describe the relationship of one element, layer or region to another element, layer or region as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0125] Embodiments of the present invention are described herein with reference to cross-sectional illustrations as schematic diagrams of idealized embodiments (and intermediate structures) of the present invention. For the sake of clarity, the thickness of the layers and regions in the figures may be exaggerated. In addition, deviations from the shapes in the figures due to, for example, manufacturing techniques and / or tolerances are expected. Therefore, embodiments of the present invention should not be construed as being limited to the specific shapes of the regions shown herein, but should include shape deviations, for example, caused by manufacturing. The elements illustrated by dotted lines may be optional in the illustrated embodiments.

[0126] The same reference numerals always refer to the same elements. Therefore, the same or similar reference numerals may be described with reference to other drawings, even if they are neither mentioned nor described in the corresponding drawings. Moreover, elements not represented by reference numerals may be described with reference to other drawings.

[0127] In the drawings and specification, typical embodiments of the invention have been disclosed, and although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the appended claims.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: forming a protection structure over at least one die on the substrate, wherein the protection structure exposes one or more electrical contacts on the first surface of the at least one die; as well as Respective terminals are formed on the one or more electrical contacts exposed by the protection structure.

2. The method of claim 1, further comprising: A second surface of the at least one die is attached to the substrate using a die attach material between the second surface of the at least one die and the substrate, wherein the second surface is opposite the first surface. The method of claim 2 , wherein the die attach material and the substrate comprise respective thermally conductive materials. The method of claim 1 , wherein the substrate comprises an insulating material or a semi-insulating material.

5. The method of claim 1, wherein the at least one die comprises a passivation layer on the first surface, the passivation layer having one or more openings therein exposing the one or more electrical contacts, and wherein the protection structure exposes the passivation layer. The method of claim 1 , wherein the protective structure comprises a molded structure.

7. The method of claim 6, wherein forming the protection structure comprises a film assisted molding process, wherein a film covers the one or more electrical contacts during forming the molding structure.

8. The method of claim 1, further comprising: After forming the corresponding terminals, the substrate is singulated to define a plurality of semiconductor devices, Each semiconductor device includes one or more dies among the at least one die.

9. The method of claim 8, wherein the substrate has one or more dimensions of about 8 inches to about 12 inches.

10. The method of claim 1, further comprising: The at least one die is disposed on the interconnect structure, wherein the respective terminals are electrically connected to the conductive patterns of the interconnect structure.

11. The method of claim 10, wherein the at least one die is mounted on the interconnect structure in a flip chip configuration wherein corresponding terminals on the first surface of the at least one die face the interconnect structure.

12. The method of claim 10, wherein the at least one die is located on a first surface of the interconnect structure, and wherein a second surface of the interconnect structure is opposite the first surface and is configured to be mounted on an external device.

13. The method of claim 12, wherein the second surface of the interconnect structure includes input connections and output connections for semiconductor device packaging.

14. The method of claim 11, further comprising: A support material is formed between the first surface of the at least one die and the interconnect structure, wherein the support material extends from the respective terminals to a periphery of the protection structure.

15. The method of any one of claims 1 to 14, wherein the at least one die comprises one or more active transistor devices having a gate connection, a source connection, or a drain connection coupled to a respective terminal.

16. The method of claim 15, wherein at least one of the gate connection, the source connection, or the drain connection is located on a second surface of the at least one die opposite the first surface and is coupled to one or more conductive via structures extending through the at least one die.

17. The method of any one of claims 1 to 14, wherein the at least one die comprises one or more passive electrical components.

18. The method of any preceding claim, wherein forming the respective terminals comprises forming conductive bumps or conductive pillar structures on the one or more electrical contacts.

19. A method for manufacturing a semiconductor device package, the method comprising: forming a protection structure on at least one die, wherein the protection structure exposes a first surface of the at least one die; forming respective terminals on a first surface of the at least one die exposed by the protection structure; as well as The first surface of the at least one die is mounted on the interconnect structure in a flip chip configuration with the respective terminals facing the interconnect structure and electrically connected to the conductive pattern of the interconnect structure.

20. The method of claim 19, further comprising: A support material is formed between the first surface of the at least one die and the interconnect structure, wherein the support material extends from the respective terminals to a periphery of the protection structure.

21. The method of claim 20, wherein the support material comprises an underfill material.

22. The method of claim 20, further comprising: A second surface of the at least one die is attached to the substrate using a die attach material between the second surface of the at least one die and the substrate, wherein the second surface is opposite the first surface.

23. The method of claim 20, wherein the protective structure is a first protective structure, and the method further comprises: A second protection structure is formed on the interconnect structure and the substrate.

24. The method of claim 23, wherein the second protective structure comprises a cover member defining an open cavity on the interconnect structure.

25. The method of claim 23, wherein the second protective structure comprises a molded structure.

26. The method of claim 25, wherein the support material comprises a portion of the molded structure.

27. The method of claim 23, wherein the die attach material and the substrate comprise respective thermally conductive materials, and wherein the second protection structure exposes at least a portion of the substrate.

28. The method of claim 27, wherein forming the second protection structure comprises a laser ablation process or a mechanical grinding process to remove a portion of the second protection structure to expose the at least a portion of the substrate.

29. The method of claim 19, wherein the protective structure comprises a molded structure.

30. The method of claim 29, wherein forming the protection structure comprises a film assisted molding process, wherein a film covers the one or more electrical contacts during forming the molded structure.

31. The method of any one of claims 19 to 30, wherein forming the respective terminals comprises forming conductive bumps or conductive pillar structures on one or more electrical contacts on the first surface.

32. The method of any one of claims 19 to 31, wherein the at least one die is located on a first surface of the interconnect structure, and a second surface of the interconnect structure is opposite the first surface and is configured to be mounted on an external device.

33. The method of claim 32, wherein the second surface of the interconnect structure includes input connections and output connections for semiconductor device packaging.

34. A semiconductor device package, comprising: substrate; at least one die including a first surface having respective terminals thereon and a second surface located on the substrate; the at least one die and a protection structure on the substrate, wherein the protection structure exposes corresponding terminals on the first surface of the at least one die; as well as A support material on the first surface of the at least one die, wherein the support material extends from the respective terminals to a periphery of the protection structure.

35. The semiconductor device package of claim 34, wherein the support material comprises an underfill layer.

36. The semiconductor device package according to claim 34 or 35, further comprising: An interconnect structure having the at least one die thereon, wherein the respective terminals are electrically connected to the conductive patterns of the interconnect structure.

37. The semiconductor device package of claim 36, wherein the first surface of the at least one die is positioned on the interconnect structure in a flip chip configuration with the respective terminals facing the interconnect structure.

38. The semiconductor device package of claim 36, wherein the protection structure is a first protection structure, and the semiconductor device package further comprises: A second protection structure is located on the interconnect structure and the substrate.

39. The semiconductor device package of claim 38, wherein the second protection structure comprises a cover member defining an open cavity on the interconnect structure.

40. The semiconductor device package of claim 38, wherein the second protection structure comprises a molding structure.

41. The semiconductor device package of claim 38, wherein the support material comprises a portion of the mold structure.

42. The semiconductor device package of claim 38, wherein the substrate comprises a thermally conductive material, and wherein the second protection structure exposes at least a portion of the substrate.

43. A semiconductor device package as claimed in any one of claims 34 to 42, wherein the at least one die comprises one or more active transistor devices having a gate connection, a source connection or a drain connection coupled to a respective terminal.

44. A semiconductor device package as claimed in any one of claims 34 to 42, wherein the at least one die comprises one or more passive electrical components.

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