Package with substrate including embedded stacked trench capacitor device

Abstract

A package includes a substrate and an integrated device. The substrate includes: a core layer including a first surface and a second surface; a plurality of core interconnects in the core layer; at least one first dielectric layer coupled to the first surface of the core layer; a first plurality of interconnects in the at least one first dielectric layer; at least one second dielectric layer coupled to the second surface of the core layer; a second plurality of interconnects in the at least one second dielectric layer; and a capacitor structure in the core layer. The capacitor structure includes a first trench capacitor device including a first front side and a first back side; and a second trench capacitor device coupled to the first trench capacitor device, wherein the second trench capacitor device includes a second front side and a second back side.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of non-provisional application S / N. 17 / 878,758 filed in the U.S. Patent Office on August 1, 2022, the entire contents of which are incorporated herein by reference as if fully set forth in its entirety below and for all applicable purposes.

[0003] field

[0004] Various features are directed to a package including a substrate.

[0005] background

[0006] A package may include a substrate and an integrated device. These components are coupled together to provide a package that can perform various electrical functions. There is a need to provide a package with better performance and to reduce the overall size of the package.

[0007] Overview

[0008] Various features are directed to a package including a substrate.

[0009] One example provides a package including a substrate and an integrated device coupled to the substrate. The substrate includes: a core layer including a first surface and a second surface; a plurality of core interconnects located in the core layer; at least one first dielectric layer coupled to the first surface of the core layer; a first plurality of interconnects located in the at least one first dielectric layer; at least one second dielectric layer coupled to the second surface of the core layer; a second plurality of interconnects located in the at least one second dielectric layer; and a capacitor structure located in the core layer. The capacitor structure includes a first trench capacitor device, the first trench capacitor device including a first front side and a first back side; and a second trench capacitor device coupled to the first trench capacitor device, wherein the second trench capacitor device includes a second front side and a second back side.

[0010] Another example provides a device including a package. The package includes a substrate and an integrated device coupled to the substrate. The substrate includes: a core layer including a first surface and a second surface; a plurality of core interconnects located in the core layer; at least one first dielectric layer coupled to the first surface of the core layer; a first plurality of interconnects located in the at least one first dielectric layer; at least one second dielectric layer coupled to the second surface of the core layer; a second plurality of interconnects located in the at least one second dielectric layer; and means for stacked trench capacitors located in the core layer.

[0011] Another example provides a method for manufacturing a substrate. The method provides a capacitor structure, the capacitor structure comprising: a first trench capacitor device, the first trench capacitor device comprising a first front side and a first back side; and a second trench capacitor device coupled to the first trench capacitor device, wherein the second trench capacitor device comprises a second front side and a second back side. The method forms a core layer so that the capacitor structure is located in the core layer. The core layer comprises a first surface and a second surface. The method forms a plurality of core interconnects in the core layer. The method forms at least one first dielectric layer coupled to the first surface of the core layer. The method forms at least one second dielectric layer coupled to the second surface of the core layer. The method forms a first plurality of interconnects in at least one first dielectric layer. The method forms a second plurality of interconnects in at least one second dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Various features, characteristics and advantages will become apparent when the detailed description set forth below is read in conjunction with the accompanying drawings in which like reference numerals designate corresponding features throughout.

[0014] Figure 1 A cross-sectional profile view of a package including a substrate having a stacked capacitor structure is illustrated.

[0015] Figure 2 Illustrated is a cross-sectional profile view of a trench capacitor that may be implemented in a stacked capacitor structure.

[0016] Figure 3 Illustrated is a cross-sectional profile view of a trench capacitor that may be implemented in a stacked capacitor structure.

[0017] Figure 4 A cross-sectional profile view of a package including a substrate having a stacked capacitor structure is illustrated.

[0018] Figure 5 A cross-sectional profile view of a package including a substrate having a stacked capacitor structure is illustrated.

[0019] Figure 6 A cross-sectional profile view of a package including a substrate having a stacked capacitor structure is illustrated.

[0020] Figure 7 A cross-sectional profile view of a package including a substrate having a stacked capacitor structure is illustrated.

[0021] Figure 8 A cross-sectional profile view of a package including a substrate having a stacked capacitor structure is illustrated.

[0022] Fig. 9 A cross-sectional profile view of a package including a substrate having a stacked capacitor structure is illustrated.

[0023] Fig.10 A cross-sectional profile view of a package including a substrate having a stacked capacitor structure is illustrated.

[0024] Fig.11 A cross-sectional profile view of a package including a substrate having a stacked capacitor structure is illustrated.

[0025] Fig.12 A cross-sectional profile view of a package including a substrate having a stacked capacitor structure is illustrated.

[0026] Fig.13A -13F illustrates an exemplary process for fabricating a trench capacitor device.

[0027] Fig.14 An exemplary flow chart illustrating a method for fabricating a trench capacitor device is illustrated.

[0028] Fig.15A -15E illustrates an exemplary process for fabricating a substrate including a stacked capacitor structure.

[0029] Fig.16A -16E illustrates an exemplary process for fabricating a substrate including a stacked capacitor structure.

[0030] Fig.17A -17E illustrates an exemplary process for fabricating a substrate including a stacked capacitor structure.

[0031] Fig.18A -18E illustrates an exemplary process for fabricating a substrate including a stacked capacitor structure.

[0032] Fig.19 An exemplary flow chart of a method for fabricating a substrate including a stacked capacitor structure is illustrated.

[0033] Fig. 20 Various electronic devices are illustrated into which the dies, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein may be integrated.

[0034] Detailed Description

[0035] In the following description, specific details are given to provide a thorough understanding of various aspects of the present disclosure. However, it will be understood by those of ordinary skill in the art that these aspects can be practiced without these specific details. For example, circuits may be shown with block diagrams to avoid burying these aspects in unnecessary details. In other examples, well-known circuits, structures, and techniques may not be shown in detail to avoid burying these aspects of the present disclosure.

[0036] The present disclosure describes a package including a substrate and an integrated device coupled to the substrate. The substrate includes: a core layer including a first surface and a second surface; a plurality of core interconnects located in the core layer; at least one first dielectric layer coupled to the first surface of the core layer; a first plurality of interconnects located in at least one first dielectric layer; at least one second dielectric layer coupled to the second surface of the core layer; a second plurality of interconnects located in at least one second dielectric layer; and a capacitor structure located in the core layer. The capacitor structure includes a first trench capacitor device, the first trench capacitor device including a first front side and a first back side; and a second trench capacitor device coupled to the first trench capacitor device, wherein the second trench capacitor device includes a second front side and a second back side. Using stacked trench capacitor devices helps improve the performance of integrated devices and packages by providing high capacitance density capacitors in the substrate while maintaining and / or reducing the package inductance. Capacitors with higher capacitance density allow for a more compact form factor of the package because these capacitors take up less space but are able to provide the same and / or comparable capacitance as capacitors of larger size. The compact form factor of the stacked trench capacitor devices allows them to be positioned in the core layer of the substrate.

[0037] Exemplary package including a substrate including an embedded stacked trench capacitor device

[0038] Figure 1 A cross-sectional cutaway view of a package 100 including a substrate with an embedded stacked trench capacitor device is illustrated. The package 100 includes a substrate 102 and an integrated device 103. The substrate 102 includes a core layer 120, at least one first dielectric layer 122, at least one second dielectric layer 126, a plurality of core interconnects 121, a first plurality of interconnects 125, a second plurality of interconnects 127, a solder resist layer 140, a solder resist layer 142, a plurality of solder interconnects 150, and a capacitor structure 106.

[0039] Capacitor structure 106 may be a stacked trench capacitor structure (eg, a device for stacked trench capacitors). Figure 1As shown in , the capacitor structure 106 is located in the core layer 120 of the substrate 102. The capacitor structure 106 is laterally surrounded by the core layer 120. The core layer 120 can touch the lateral surface of the capacitor structure 106. The capacitor structure 106 includes at least two trench capacitor devices. For example, the capacitor structure 106 includes a first trench capacitor device 160 and a second trench capacitor device 162. The first trench capacitor device 160 is coupled to the second trench capacitor device 162 through a plurality of solder interconnects 164. Similarly, the second trench capacitor device 162 is coupled to the first trench capacitor device 160 through a plurality of solder interconnects 164. As will be further described below, the interconnects from the first trench capacitor device 160 can be coupled to the interconnects from the second trench capacitor device 162 through the plurality of solder interconnects 164. As will be further described below, the first trench capacitor device 160 can be coupled to the second trench capacitor device 162 through copper-to-copper bonding.

[0040] The first trench capacitor device 160 is located (e.g., vertically located) above the second trench capacitor device 162. However, the second trench capacitor device 162 may be located (e.g., vertically located) above the first trench capacitor device 160. The first trench capacitor device 160 includes a first front side and a first back side. The second trench capacitor device 162 includes a second front side and a second back side. Figure 1 , the first back side of the first trench capacitor device 160 faces the second front side of the second trench capacitor device 162. Thus, the first back side of the first trench capacitor device 160 may be coupled (e.g., electrically coupled) to the second front side of the second trench capacitor device 162. However, in some implementations, the first back side of the first trench capacitor device 160 may be coupled (e.g., electrically coupled) to the second back side of the second trench capacitor device 162 such that the first back side of the first trench capacitor device 160 faces the second back side of the second trench capacitor device 162. More detailed examples of trench capacitor devices are described below at least in Figure 2 and 3 Further described in .

[0041] The core layer 120 includes a first surface (e.g., a top surface) and a second surface (e.g., a bottom surface). The core layer 120 may include a core dielectric layer. A plurality of core interconnects 121 are located in the core layer 120. The plurality of core interconnects 121 may include core through-hole interconnects that extend through the entire thickness of the core layer 120. For example, the core through-hole interconnects may extend between the first surface and the second surface of the core layer 120. As described above, the capacitor structure 106 is located in the core layer 120 of the substrate 102. The lateral surface(s) of the capacitor structure 106 may be in direct contact with the core layer 120. Thus, for example, the lateral surface(s) of the first trench capacitor device 160 and / or the lateral surface(s) of the second trench capacitor device 162 may be in direct contact with the core layer 120. The capacitor structure 106 may have a thickness that is substantially the same as, smaller than, or greater than the thickness of the core layer 120. As described below at least Figures 15A-15E and Figures 16A-16E As further described in , the core layer 120 can be defined by two or more core dielectric layers.

[0042] At least one first dielectric layer 122 is located on the first surface of the core layer 120 and coupled to the first surface of the core layer 120. The at least one first dielectric layer 122 may include a first dielectric layer 122a and a first dielectric layer 122b. The first plurality of interconnects 125 may be located in the at least one first dielectric layer 122. The first plurality of interconnects 125 may be configured to be electrically coupled to the plurality of core interconnects 121 and the capacitor structure 106. Specifically, the first plurality of interconnects 125 may be configured to be coupled (e.g., electrically coupled) to the first trench capacitor device 160 and / or the second trench capacitor device 162.

[0043] At least one second dielectric layer 126 is located below the second surface of the core layer 120 and coupled to the second surface of the core layer 120. The at least one second dielectric layer 126 may include a second dielectric layer 126a and a second dielectric layer 126b. A second plurality of interconnects 127 may be located in the at least one second dielectric layer 126. The second plurality of interconnects 127 may be configured to be electrically coupled to the plurality of core interconnects 121 and the capacitor structure 106. Specifically, the second plurality of interconnects 127 may be configured to be coupled (e.g., electrically coupled) to the first trench capacitor device 160 and / or the second trench capacitor device 162.

[0044] The core layer 120 may include the same material or a different material than the at least one first dielectric layer 122 and / or the at least one second dielectric layer 126. In some implementations, the at least one first dielectric layer 122 and / or the at least one second dielectric layer 126 may include a prepreg.

[0045] Using capacitor structures (e.g., 106) helps improve the performance of integrated devices and packages by providing high capacitance density capacitors in the substrate while maintaining and / or reducing the package inductance. Vertically stacked trench capacitor devices with higher capacitance density allow for a more compact form factor for the package because these trench capacitors take up less space but are able to provide the same and / or comparable capacitance as a single larger size capacitor. In addition, the compact form factor of the stacked trench capacitor devices allows them to be positioned in the core layer 120 of the substrate 102, so that these stacked trench capacitor devices can be placed in locations where other capacitors may not be positioned, resulting in better utilization of space in the package 100.

[0046] The integrated device 103 is coupled to the substrate 102 through the plurality of solder pillar interconnects 130 and / or the plurality of solder interconnects 132. For example, the integrated device 103 may be coupled to the first plurality of interconnects 125 of the substrate 102 through the plurality of solder pillar interconnects 130 and / or the plurality of solder interconnects 132. The integrated device 103 may be configured to be electrically coupled to the capacitor structure 106 (e.g., to the first trench capacitor device 160 and / or the second trench capacitor device 162) through one or more electrical paths including the plurality of solder pillar interconnects 130, the plurality of solder interconnects 132, the first plurality of interconnects 125, the plurality of core interconnects 121, and / or the second plurality of interconnects 127.

[0047] Figure 1 The capacitor structure 106 including two trench capacitor devices is illustrated. However, in some implementations, the capacitor structure 106 may include more than two trench capacitors stacked vertically on top of each other. Different implementations may orient the trench capacitor devices in the same direction or in different directions. Furthermore, the capacitor structure 106 may be positioned differently in the package. Figure 4-12 Other examples of packages having other similar and / or different configurations of capacitor structures are illustrated.

[0048] Exemplary Trench Capacitor Devices

[0049] Figure 2 An example of a trench capacitor device 200 is illustrated. The trench capacitor device 200 includes at least one trench capacitor 201 . Figure 2 Die substrate 202, first conductive layer 212, dielectric layer 214, second conductive layer 216, filler 215, second contact layer 218, first contact layer 230, dielectric layer 240, first capacitor interconnect 250, and second capacitor interconnect 260 are illustrated.

[0050] The trench capacitor device 200 may include one or more trench capacitors 201. The trench capacitor device 200 may include a plurality of trench capacitors 201 that may be configured to be electrically coupled together to provide a trench capacitor device having high capacitance (e.g., high capacitance density). The trench capacitor device 200 may be a device for trench capacitance (e.g., a device for a first trench capacitance, a device for a second trench capacitance). The trench capacitor device 200 may represent a detailed example of a second trench capacitor device 162. Each of the plurality of trench capacitors 201 from the trench capacitor device 200 may be positioned horizontally (e.g., laterally) relative to each other.

[0051] The first conductive layer 212, the dielectric layer 214, the second conductive layer 216, and the filler 215 may be located (i) on the first surface of the die substrate 202 and (ii) in one or more grooves of the die substrate 202. The first conductive layer 212 is located (e.g., formed) (i) on the first surface of the die substrate 202 and (ii) in one or more grooves of the die substrate 202. The dielectric layer 214 is located on the first conductive layer 212. Portions of the dielectric layer 214 may be located in one or more grooves of the die substrate 202. The second conductive layer 216 may be located on the dielectric layer 214. Portions of the second conductive layer 216 may be located in one or more grooves of the die substrate 202. The second contact layer 218 may be located on the second conductive layer 216. The first contact layer 230 may be located on the first conductive layer 212. The dielectric layer 240 may be located over the die substrate 202, the first conductive layer 212, the second contact layer 218, and / or the first contact layer 230. The first capacitor interconnect 250 is coupled to the first contact layer 230. The second capacitor interconnect 260 is coupled to the second contact layer 218. The first capacitor interconnect 250 and the second capacitor interconnect 260 may be located over the dielectric layer 240 and may extend through the dielectric layer 240.

[0052] The trench capacitor device 200 includes a first conductive layer 212, a dielectric layer 214, and a second conductive layer 216. In some implementations, the trench capacitor 201 can be defined by portions of the first conductive layer 212, portions of the dielectric layer 214, and portions of the second conductive layer 216 located in the trenches of the die substrate 202. Note that the trenches of the die substrate 202 are formed in the trenches of the die substrate 202. Figure 2 The grooves in the die substrate 202 may not be visible because the grooves in the die substrate 202 may be filled or partially filled with a material (eg, a solid material). The shape and / or size of the grooves may vary from implementation to implementation. Examples of grooves in the die substrate are shown in FIG. Fig.13A Explanation and description.

[0053] The die substrate 202 may include silicon (Si). The first conductive layer 212 may include N+ silicon. The second conductive layer 216 may include N+ polysilicon. The first conductive layer 212 may include N+ polysilicon, and the second conductive layer 216 may include N+ silicon. Note that different implementations may use different materials and / or different material combinations for the first conductive layer 212 and / or the second conductive layer 216. For example, the first conductive layer 212 and / or the second conductive layer 216 may include P+ silicon, P+ polysilicon, copper (Cu), aluminum (Al), and / or other metals. The dielectric layer 214 may include Al2O3, HfO2, Ta2O5, SiN, and / or combinations thereof. The filler 215 may include Ajinomoto deposited film (ABF) or other similar materials. The second contact layer 218 and / or the first contact layer 230 may include a metal (e.g., copper, aluminum).

[0054] Figure 2 Also illustrated is a circuit diagram that can conceptually represent the trench capacitor 201. A first electrode of the circuit diagram can be a first contact layer 230. A second electrode of the circuit diagram can be a second contact layer 218. As will be further described below, several trench capacitor devices can be configured to be electrically coupled together to provide an effective capacitor with high capacitance (e.g., high capacitance density).

[0055] Figure 3 An example of a trench capacitor device 300 is illustrated. The trench capacitor device 300 includes at least one trench capacitor 201 . Figure 3 Illustrated are die substrate 202, first conductive layer 212, dielectric layer 214, second conductive layer 216, filler 215, second contact layer 218, first contact layer 230, dielectric layer 240, first capacitor interconnect 250, second capacitor interconnect 260, and through substrate via 270. Trench capacitor device 300 is similar to trench capacitor device 200 and, thus, may include the same or similar components as trench capacitor device 200. Trench capacitor device 300 also includes through substrate via 270 extending through die substrate 202.

[0056] exist Figure 3, the through substrate via 270 is coupled to the first conductive layer 212, the first contact layer 230, and / or the first capacitor interconnect 250. However, the through substrate via 270 and / or other through substrate vias (TSVs) may be configured to be coupled (e.g., electrically coupled) to the second conductive layer 216, the second contact layer 218, and / or the second capacitor interconnect 260. In some implementations, the through substrate via 270 and / or other through substrate vias are not directly coupled to the trench capacitor 201 of the trench capacitor device 200. In some implementations, the capacitor interconnect 250 and / or the capacitor interconnect 260 of a particular trench capacitor device (e.g., the first trench capacitor device) may be configured to be coupled to other capacitor interconnects (e.g., 250, 260) of other trench capacitor devices (e.g., the second trench capacitor device) through solder interconnects or through copper-to-copper bonding. In some implementations, the capacitor interconnects 250 and / or capacitor interconnects 260 of a particular trench capacitor device (e.g., a first trench capacitor device) may be configured to be coupled to other through-substrate vias (e.g., 270) of other trench capacitor devices (e.g., a second trench capacitor device) by solder interconnects or by copper-to-copper bonding. In some implementations, the capacitor interconnects 250, capacitor interconnects 260, and / or through-substrate vias 270 of a trench capacitor device may be configured to be coupled to interconnects of a substrate. Thus, when the present disclosure describes one or more interconnects from a substrate being coupled to a capacitor structure, the one or more interconnects from the substrate may be coupled (directly or indirectly by solder interconnects) to the capacitor interconnects 250, capacitor interconnects 260, and / or through-substrate vias 270 of a trench capacitor device of the capacitor structure.

[0057] The trench capacitor device 300 may include one or more trench capacitors 201. The trench capacitor device 300 may include a plurality of trench capacitors 201 that may be configured to be electrically coupled together to provide a trench capacitor device having high capacitance (e.g., high capacitance density). The trench capacitor device 300 may be a device for trench capacitance (e.g., a device for a first trench capacitance, a device for a second trench capacitance). The trench capacitor device 300 may represent a detailed example of the first trench capacitor device 160. Each of the plurality of trench capacitors 201 from the trench capacitor device 300 may be positioned horizontally (e.g., laterally) relative to each other.

[0058] Exemplary package including a substrate including an embedded stacked trench capacitor device

[0059] Figure 4A cross-sectional cutaway view of a package 400 including a substrate with an embedded stacked trench capacitor device is illustrated. The package 400 includes a substrate 402 and an integrated device 103. The substrate 402 includes a core layer 120, at least one first dielectric layer 122, at least one second dielectric layer 126, at least one dielectric layer 124, a plurality of core interconnects 121, a first plurality of interconnects 125, a second plurality of interconnects 127, a solder resist layer 140, a solder resist layer 142, a plurality of solder interconnects 150, and a capacitor structure 106.

[0060] Package 400 is similar to package 100 and thus includes similar components as package 100. Similarly, package 400 can be arranged and / or configured in a manner similar to package 100. Substrate 402 is similar to substrate 102. Capacitor structure 106 can be located in a cavity of core layer 120. Dielectric layer 124 can surround capacitor structure 106 in the cavity of core layer 120. Dielectric layer 124 can touch capacitor structure 106. For example, dielectric layer 124 can touch a sidewall (e.g., a side portion) of capacitor structure 106, a top of capacitor structure 106, and / or a bottom of capacitor structure 106. Capacitor structure 106 can be surrounded (e.g., laterally surrounded) by core layer 120. Dielectric layer 124 can be located in a cavity of core layer 120. Dielectric layer 124 can be located on (e.g., above) a first surface (e.g., a top surface) of core layer 120, and on (e.g., below) a second surface (e.g., a bottom surface) of core layer 120.

[0061] The plurality of interconnects 421 and the plurality of interconnects 423 may be located in, above, and / or below the dielectric layer 124. The plurality of interconnects 421 may be configured to be coupled to the capacitor structure 106 (e.g., interconnects of the capacitor structure 106), the plurality of core interconnects 121, and / or the plurality of interconnects 125. The plurality of interconnects 423 may be configured to be coupled to the plurality of core interconnects 121 and / or the plurality of interconnects 127.

[0062] Capacitor structure 106 may be a stacked trench capacitor structure (eg, a device for stacked trench capacitors). Figure 4As shown in , the capacitor structure 106 is located in the cavity of the core layer 120 of the substrate 102. The cavity of the core layer 120 is filled with a dielectric layer 124. The capacitor structure 106 includes at least two trench capacitor devices. For example, the capacitor structure 106 includes a first trench capacitor device 160 and a second trench capacitor device 162. The first trench capacitor device 160 is coupled to the second trench capacitor device 162 through a plurality of solder interconnects 164. Similarly, the second trench capacitor device 162 is coupled to the first trench capacitor device 160 through a plurality of solder interconnects 164. As will be further described below, the interconnects from the first trench capacitor device 160 can be coupled to the interconnects from the second trench capacitor device 162 through a plurality of solder interconnects 164. As will be further described below, the first trench capacitor device 160 can be coupled to the second trench capacitor device 162 through a copper-to-copper bond.

[0063] The first trench capacitor device 160 is located (eg, vertically located) above the second trench capacitor device 162. The first trench capacitor device 160 includes a first front side and a first back side. The second trench capacitor device 162 includes a second front side and a second back side. Figure 4 , the first back side of the first trench capacitor device 160 faces the second front side of the second trench capacitor device 162. Thus, the first back side of the first trench capacitor device 160 may be coupled (e.g., electrically coupled) to the second front side of the second trench capacitor device 162. However, in some implementations, the first front side of the first trench capacitor device 160 may be coupled (e.g., electrically coupled) to the second front side of the second trench capacitor device 162 such that the first front side of the first trench capacitor device 160 faces the second front side of the second trench capacitor device 162. In some implementations, the first back side of the first trench capacitor device 160 may be coupled to the second back side of the second trench capacitor device 162 such that the first back side of the first trench capacitor device 160 faces the second back side of the second trench capacitor device 162b. In another example of a configuration of a capacitor structure, in some implementations, the first front side of the first trench capacitor device 160 may be coupled to the second back side of the second trench capacitor device 162 such that the first back side of the first trench capacitor device 160 faces the second back side of the second trench capacitor device 162. Figure 2 The trench capacitor device 200 may illustrate a detailed example of the trench capacitor device 162 . Figure 3 The trench capacitor device 300 may illustrate a detailed example of the trench capacitor device 160 .

[0064] The core layer 120 includes a first surface (e.g., a top surface) and a second surface (e.g., a bottom surface). A plurality of core interconnects 121 are located in the core layer 120. The plurality of core interconnects 121 may include core through-hole interconnects extending through the entire thickness of the core layer 120. For example, the core through-hole interconnects may extend between the first surface and the second surface of the core layer 120. The capacitor structure 106 may have a thickness that is approximately the same as, less than, or greater than the thickness of the core layer 120.

[0065] The integrated device 103 is coupled to the substrate 102 through the plurality of solder pillar interconnects 130 and / or the plurality of solder interconnects 132. For example, the integrated device 103 may be coupled to the first plurality of interconnects 125 of the substrate 102 through the plurality of solder pillar interconnects 130 and / or the plurality of solder interconnects 132. The integrated device 103 may be configured to be electrically coupled to the capacitor structure 106 (e.g., to the first trench capacitor device 160 and / or the second trench capacitor device 162) through one or more electrical paths including the plurality of solder pillar interconnects 130, the plurality of solder interconnects 132, the first plurality of interconnects 125, the plurality of core interconnects 121, the second plurality of interconnects 127, the plurality of interconnects 421, and / or the plurality of interconnects 423.

[0066] Figure 5 A cross-sectional cutaway view of a package 500 including a substrate with an embedded stacked trench capacitor device is illustrated. The package 500 includes a substrate 102 and an integrated device 103. The substrate 102 includes a core layer 120, at least one first dielectric layer 122, at least one second dielectric layer 126, a plurality of core interconnects 121, a first plurality of interconnects 125, a second plurality of interconnects 127, a solder resist layer 140, a solder resist layer 142, a plurality of solder interconnects 150, and a capacitor structure 506.

[0067] Package 500 is similar to package 100 and, thus, includes similar components as package 100. Similarly, package 500 may be arranged and / or configured in a similar manner as package 100.

[0068] Capacitor structure 506 may be a stacked trench capacitor structure (eg, a device for stacked trench capacitors). Figure 5 As shown in , the capacitor structure 506 is located in the core layer 120 of the substrate 102. The capacitor structure 506 includes at least two trench capacitor devices. For example, the capacitor structure 506 includes a first trench capacitor device 162a and a second trench capacitor device 162b. The first trench capacitor device 162a is physically coupled to the second trench capacitor device 162b by an adhesive 564. Similarly, the second trench capacitor device 162b is coupled to the first trench capacitor device 162a by an adhesive 564.

[0069] The first trench capacitor device 162a is located (eg, vertically located) above the second trench capacitor device 162b. The first trench capacitor device 162a includes a first front side and a first back side. The second trench capacitor device 162b includes a second front side and a second back side. Figure 5 As shown in FIG. 1 , the first back side of the first trench capacitor device 162a faces the second back side of the second trench capacitor device 162b. Thus, the first back side of the first trench capacitor device 162a can be physically coupled to the second back side of the second trench capacitor device 162b. Figure 2 The trench capacitor device 200 may illustrate a detailed example of the trench capacitor device 162a and / or the trench capacitor device 162b.

[0070] The core layer 120 includes a first surface (e.g., a top surface) and a second surface (e.g., a bottom surface). A plurality of core interconnects 121 are located in the core layer 120. The plurality of core interconnects 121 may include core through-hole interconnects extending through the entire thickness of the core layer 120. For example, the core through-hole interconnects may extend between the first surface and the second surface of the core layer 120. As described above, the capacitor structure 506 is located in the core layer 120 of the substrate 102. The lateral surface(s) of the capacitor structure 506 may be in direct contact with the core layer 120. Thus, for example, the lateral surface(s) of the first trench capacitor device 162a and / or the lateral surface(s) of the second trench capacitor device 162b may be in direct contact with the core layer 120. The capacitor structure 506 may have a thickness that is substantially the same as, less than, or greater than the thickness of the core layer 120.

[0071] The integrated device 103 is coupled to the substrate 102 through the plurality of solder pillar interconnects 130 and / or the plurality of solder interconnects 132. For example, the integrated device 103 may be coupled to the first plurality of interconnects 125 of the substrate 102 through the plurality of solder pillar interconnects 130 and / or the plurality of solder interconnects 132. The integrated device 103 may be configured to be electrically coupled to the capacitor structure 506 (e.g., to the first trench capacitor device 162a and / or the second trench capacitor device 162b) through one or more electrical paths including the plurality of solder pillar interconnects 130, the plurality of solder interconnects 132, the first plurality of interconnects 125, the plurality of core interconnects 121, and / or the second plurality of interconnects 127. In one example, the integrated device 103 may be configured to be electrically coupled to the first trench capacitor device 162a through one or more electrical paths including the plurality of solder pillar interconnects 130, the plurality of solder interconnects 132, and the first plurality of interconnects 125. In another example, the integrated device 103 can be configured to be electrically coupled to the second trench capacitor device 162b via one or more electrical paths including a plurality of solder pillar interconnects 130, a plurality of solder interconnects 132, a first plurality of interconnects 125, a plurality of core interconnects 121 and / or a second plurality of interconnects 127.

[0072] Figure 6 A cross-sectional cutaway view of a package 600 including a substrate with an embedded stacked trench capacitor device is illustrated. The package 600 includes a substrate 102 and an integrated device 103. The substrate 102 includes a core layer 120, at least one first dielectric layer 122, at least one second dielectric layer 126, a plurality of core interconnects 121, a plurality of core interconnects 621, a first plurality of interconnects 125, a second plurality of interconnects 127, a solder resist layer 140, a solder resist layer 142, a plurality of solder interconnects 150, and a capacitor structure 106.

[0073] Package 600 is similar to package 100 and thus includes similar components as package 100. Similarly, package 600 may be arranged and / or configured in a similar manner as package 100. Capacitor structure 106 may have a thickness that is thinner (eg, smaller) than a thickness of core layer 120.

[0074] Capacitor structure 106 may be a stacked trench capacitor structure (eg, a device for stacked trench capacitors). Figure 6 As shown in , the capacitor structure 106 is located in the core layer 120 of the substrate 102. The capacitor structure 106 includes at least two trench capacitor devices. For example, the capacitor structure 106 includes a first trench capacitor device 160 and a second trench capacitor device 162. The first trench capacitor device 160 is coupled to the second trench capacitor device 162 through a plurality of solder interconnects 164. Similarly, the second trench capacitor device 162 is coupled to the first trench capacitor device 160 through a plurality of solder interconnects 164. As will be further described below, the interconnects from the first trench capacitor device 160 can be coupled to the interconnects from the second trench capacitor device 162 through the plurality of solder interconnects 164. As will be further described below, the first trench capacitor device 160 can be coupled to the second trench capacitor device 162 through a copper-to-copper bond.

[0075] The first trench capacitor device 160 is located (eg, vertically located) above the second trench capacitor device 162. The first trench capacitor device 160 includes a first front side and a first back side. The second trench capacitor device 162 includes a second front side and a second back side. Figure 6, the first back side of the first trench capacitor device 160 faces the second front side of the second trench capacitor device 162. Thus, the first back side of the first trench capacitor device 160 can be coupled (e.g., electrically coupled) to the second front side of the second trench capacitor device 162. However, in some implementations, the first front side of the first trench capacitor device 160 can be coupled (e.g., electrically coupled) to the second front side of the second trench capacitor device 162 such that the first front side of the first trench capacitor device 160 faces the second front side of the second trench capacitor device 162. In some implementations, the first back side of the first trench capacitor device 160 can be coupled (e.g., electrically coupled) to the second back side of the second trench capacitor device 162 such that the first back side of the first trench capacitor device 160 faces the second back side of the second trench capacitor device 162. In some implementations, the first front side of the first trench capacitor device 160 can be coupled (e.g., electrically coupled) to the second front side of the second trench capacitor device 162 such that the first front side of the first trench capacitor device 160 faces the second front side of the second trench capacitor device 162.

[0076] The core layer 120 includes a first surface (e.g., a top surface) and a second surface (e.g., a bottom surface). A plurality of core interconnects 121 are located in the core layer 120. The plurality of core interconnects 121 may include core through-hole interconnects extending through the entire thickness of the core layer 120. For example, the core through-hole interconnects may extend between the first surface and the second surface of the core layer 120. As described above, the capacitor structure 106 is located in the core layer 120 of the substrate 102. The lateral surface(s) of the capacitor structure 106 may be in direct contact with the core layer 120. Thus, for example, the lateral surface(s) of the first trench capacitor device 160 and / or the lateral surface(s) of the second trench capacitor device 162 may be in direct contact with the core layer 120.

[0077] As described above, the capacitor structure 106 may have a thickness that is thinner (e.g., smaller) than the thickness of the core layer 120. A plurality of core interconnects 621 may also be located in the core layer 120. The plurality of core interconnects 621 may extend between the capacitor structure 106 and the first surface of the core layer 120. The plurality of core interconnects 621 are configured to be coupled to the capacitor structure 106 and the second plurality of interconnects 125. For example, the plurality of core interconnects 621 are configured to be coupled to the first trench capacitor device 160 and the first plurality of interconnects 125. The plurality of core interconnects 621 are configured to be coupled to the second trench capacitor device 162 through the first trench capacitor device 160 and / or the plurality of solder interconnects 164. The plurality of core interconnects 621 partially extend through the thickness of the core layer 120.

[0078] The integrated device 103 is coupled to the substrate 102 through the plurality of solder pillar interconnects 130 and / or the plurality of solder interconnects 132. For example, the integrated device 103 may be coupled to the first plurality of interconnects 125 of the substrate 102 through the plurality of solder pillar interconnects 130 and / or the plurality of solder interconnects 132. The integrated device 103 may be configured to be electrically coupled to the capacitor structure 106 (e.g., to the first trench capacitor device 160 and / or the second trench capacitor device 162) through one or more electrical paths including the plurality of solder pillar interconnects 130, the plurality of solder interconnects 132, the first plurality of interconnects 125, the plurality of core interconnects 121, the second plurality of interconnects 127, and / or the plurality of core interconnects 621.

[0079] Figure 7 A cross-sectional cutaway view of a package 700 including a substrate with an embedded stacked trench capacitor device is illustrated. The package 700 includes a substrate 102 and an integrated device 103. The substrate 102 includes a core layer 120, at least one first dielectric layer 122, at least one second dielectric layer 126, a plurality of core interconnects 121, a plurality of core interconnects 721, a plurality of core interconnects 723, a first plurality of interconnects 125, a second plurality of interconnects 127, a solder resist layer 140, a solder resist layer 142, a plurality of solder interconnects 150, and a capacitor structure 506.

[0080] Package 700 is similar to package 100 and thus includes similar components as package 100. Similarly, package 700 may be arranged and / or configured in a similar manner as package 100. Capacitor structure 506 may have a thickness that is thinner (eg, smaller) than a thickness of core layer 120.

[0081] Capacitor structure 506 may be a stacked trench capacitor structure (eg, a device for stacked trench capacitors). Figure 7 As shown in FIG. 5 , a capacitor structure 506 is located in the core layer 120 of the substrate 102. The capacitor structure 506 includes at least two trench capacitor devices. For example, the capacitor structure 506 includes a first trench capacitor device 162a and a second trench capacitor device 162b. The first trench capacitor device 162a is coupled to the second trench capacitor device 162b.

[0082] The first trench capacitor device 162a is located (eg, vertically located) above the second trench capacitor device 162b. The first trench capacitor device 162a includes a first front side and a first back side. The second trench capacitor device 162b includes a second front side and a second back side. Figure 7 As shown in FIG. 1 , a first backside of the first trench capacitor device 162 a faces a second backside of the second trench capacitor device 162 b .

[0083] The core layer 120 includes a first surface (e.g., a top surface) and a second surface (e.g., a bottom surface). A plurality of core interconnects 121 are located in the core layer 120. The plurality of core interconnects 121 may include core through-hole interconnects extending through the entire thickness of the core layer 120. For example, the core through-hole interconnects may extend between the first surface and the second surface of the core layer 120. As described above, the capacitor structure 506 is located in the core layer 120 of the substrate 102. The lateral surface(s) of the capacitor structure 506 may be in direct contact with the core layer 120. Thus, for example, the lateral surface(s) of the first trench capacitor device 162a and / or the lateral surface(s) of the second trench capacitor device 162b may be in direct contact with the core layer 120.

[0084] As described above, the capacitor structure 506 may have a thickness that is thinner (e.g., smaller) than the thickness of the core layer 120. A plurality of core interconnects 723 may also be located in the core layer 120. The plurality of core interconnects 723 may extend between the capacitor structure 506 and the second surface of the core layer 120. The plurality of core interconnects 723 are configured to be coupled to the capacitor structure 506 and the second plurality of interconnects 127. For example, the plurality of core interconnects 723 are configured to be coupled to the second trench capacitor device 160b and the second plurality of interconnects 127. The plurality of core interconnects 723 partially extend through the thickness of the core layer 120.

[0085] A plurality of core interconnects 721 may also be located in the core layer 120. The plurality of core interconnects 721 may extend between the capacitor structure 506 and the first surface of the core layer 120. The plurality of core interconnects 721 are configured to couple to the capacitor structure 506 and the first plurality of interconnects 125. For example, the plurality of core interconnects 721 are configured to couple to the first trench capacitor device 162a and the first plurality of interconnects 125. The plurality of core interconnects 721 partially extend through the thickness of the core layer 120.

[0086] The integrated device 103 is coupled to the substrate 102 through the plurality of solder pillar interconnects 130 and / or the plurality of solder interconnects 132. For example, the integrated device 103 may be coupled to the first plurality of interconnects 125 of the substrate 102 through the plurality of solder pillar interconnects 130 and / or the plurality of solder interconnects 132. The integrated device 103 may be configured to be electrically coupled to the capacitor structure 506 (e.g., to the first trench capacitor device 162a and / or the second trench capacitor device 162b) through one or more electrical paths including the plurality of solder pillar interconnects 130, the plurality of solder interconnects 132, the first plurality of interconnects 125, the plurality of core interconnects 121, the second plurality of interconnects 127, the plurality of core interconnects 723, and / or the plurality of core interconnects 721.

[0087] In one example, the integrated device 103 can be configured to be electrically coupled to the first trench capacitor device 162a through one or more electrical paths including the plurality of solder pillar interconnects 130 , the plurality of solder interconnects 132 , the first plurality of interconnects 125 , and / or the plurality of core interconnects 721 .

[0088] In another example, the integrated device 103 can be configured to be electrically coupled to the second trench capacitor device 162b via one or more electrical paths including a plurality of solder pillar interconnects 130, a plurality of solder interconnects 132, a first plurality of interconnects 125, a plurality of core interconnects 121, a second plurality of interconnects 127 and / or a plurality of core interconnects 723.

[0089] Figure 8 A cross-sectional cutaway view of a package 800 including a substrate with an embedded stacked trench capacitor device is illustrated. The package 800 includes a substrate 102 and an integrated device 103. The substrate 102 includes a core layer 120, at least one first dielectric layer 122, at least one second dielectric layer 126, a plurality of core interconnects 121, a plurality of core interconnects 821, a plurality of solder interconnects 864, a first plurality of interconnects 125, a second plurality of interconnects 127, a solder resist layer 140, a solder resist layer 142, a plurality of solder interconnects 150, and a capacitor structure 406.

[0090] Package 800 is similar to package 100 and thus includes similar components as package 100. Similarly, package 800 may be arranged and / or configured in a similar manner as package 100. Capacitor structure 406 may have a thickness that is thinner (eg, smaller) than a thickness of core layer 120.

[0091] Capacitor structure 406 may be a stacked trench capacitor structure (eg, a device for stacked trench capacitors). Figure 8 As shown in FIG. 4 , a capacitor structure 406 is located in the core layer 120 of the substrate 102. The capacitor structure 406 includes at least two trench capacitor devices. For example, the capacitor structure 406 includes a first trench capacitor device 160a and a second trench capacitor device 160b. The first trench capacitor device 160a is coupled to the second trench capacitor device 160b.

[0092] The first trench capacitor device 160a is located (eg, vertically located) above the second trench capacitor device 160b. The first trench capacitor device 160a includes a first front side and a first back side. The second trench capacitor device 160b includes a second front side and a second back side. Figure 8 As shown in FIG. 1 , a first backside of the first trench capacitor device 160 a faces a second frontside of the second trench capacitor device 160 b .

[0093] The core layer 120 includes a first surface (e.g., a top surface) and a second surface (e.g., a bottom surface). The core layer 120 includes two core dielectric layers, a first core dielectric layer 820 and a second core dielectric layer 830. The first core dielectric layer 820 and the second core dielectric layer 830 may include the same material or different materials. A plurality of core interconnects 121 are located in the core layer 120. The plurality of core interconnects 121 may include core through-hole interconnects extending through the entire thickness of the core layer 120 (e.g., through the first core dielectric layer 820 and the second core dielectric layer 830). For example, the core through-hole interconnects may extend between the first surface and the second surface of the core layer 120. As described above, the capacitor structure 406 is located in the core layer 120 of the substrate 102. The capacitor structure 406 may be located in the first core dielectric layer 820. The lateral face(s) of the capacitor structure 406 may be in direct contact with the core layer 120 (e.g., in direct contact with the first core dielectric layer 820). Thus, for example, lateral face(s) of the first trench capacitor device 160a and / or lateral face(s) of the second trench capacitor device 160b may be in direct contact with the core layer 120 (eg, in direct contact with the first core dielectric layer 820).

[0094] As described above, the capacitor structure 406 may have a thickness that is thinner (e.g., smaller) than the thickness of the core layer 120. The plurality of core interconnects 820 may also be located in the first core dielectric layer 820 of the core layer 120. The plurality of core interconnects 821 may extend between the capacitor structure 406 and the first surface of the core layer 120. The plurality of core interconnects 821 are configured to be coupled to the capacitor structure 406 and the first plurality of interconnects 125. For example, the plurality of core interconnects 821 are configured to be coupled to the first trench capacitor device 160a and the first plurality of interconnects 125. The plurality of core interconnects 820 partially extend through the thickness of the first core dielectric layer 820 of the core layer 120.

[0095] The plurality of core interconnects 823 may also be located in the first core dielectric layer 820 and / or the second core dielectric layer 830 of the core layer 120. The plurality of core interconnects 823 may extend between the capacitor structure 406 and the second surface of the core layer 120. The plurality of core interconnects 823 are configured to be coupled to the capacitor structure 406 and the second plurality of interconnects 127. For example, the plurality of core interconnects 823 are configured to be coupled to the second trench capacitor device 160b and the second plurality of interconnects 127. The plurality of core interconnects 823 are configured to be coupled to the second trench capacitor device 160b through the plurality of solder interconnects 864. The plurality of core interconnects 823 extend through the thickness of the second core dielectric layer 830 of the core layer 120.

[0096] Fig. 9Package 900 is illustrated. Package 900 includes substrate 102, integrated device 103, capacitor structure 901, capacitor structure 902, capacitor structure 903, and capacitor structure 905. Capacitor structure 901, capacitor structure 902, capacitor structure 903, and capacitor structure 905 may represent any capacitor structure described in the present disclosure, including capacitor structure 106, capacitor structure 406, and / or capacitor structure 506.

[0097] Fig. 9 It is illustrated that the capacitor structure may be (i) located in the substrate, (ii) coupled to the first surface and / or the second surface of the substrate, and / or (iii) coupled to the back side of the integrated device.

[0098] Capacitor structure 901 is located in core layer 120. Capacitor structure 902 is coupled to a first surface (e.g., top surface) of substrate 102. Capacitor structure 903 is coupled to a second surface (e.g., bottom surface) of substrate 102. Capacitor structure 905 is coupled to the back side of integrated device 103. Capacitor structure 905 may include a plurality of capacitor structures (e.g., 905a, 905b, 905c, 905d) positioned laterally relative to each other. Capacitor structure 905 may be coupled to the back side of integrated device 103 via a plurality of solder interconnects (not shown). Capacitor structure 905 may be configured to be electrically coupled to integrated device 103 via a plurality of through-substrate vias 930 of integrated device 103.

[0099] Fig. 9 1 illustrates an example of how the capacitor structure 901 is embedded in the core layer 120. However, the capacitor structure 901 may be embedded in the core layer 120 in the same manner as described above. Figure 1 and 4 -8 are positioned in the core layer 120 in a manner similar to how the other capacitor structures (eg, 106 , 406 , 506 ) are positioned in the core layer 120 .

[0100] Fig.10Device 1000 is illustrated, which includes package 100, board 1010, integrated device 1020, inductor 1030, and capacitor 1040. Package 100 includes substrate 102, integrated device 103, and capacitor structure 106. Package 100 is coupled to a first surface (e.g., top surface) of board 1010 via a plurality of solder interconnects 150. For example, package 100 is coupled to a plurality of board interconnects 1012 of board 1010 via a plurality of solder interconnects 150. Integrated device 1020 is coupled to the first surface of board 1010. Integrated device 1020 may include a power management integrated circuit (PMIC). Inductor 1030 is coupled to the first surface of board 1010. Inductor 1030 may include a discrete inductor device. Capacitor 1040 is coupled to the first surface of board 1010. Capacitor 1040 may include a discrete capacitor device. Although not shown, other components and / or other capacitors (e.g., input capacitors) may be coupled to board 1010. The integrated device 1020, the inductor 1030, and the capacitor 1040 can be part of a power distribution network (PDN) that is configured to be coupled (e.g., electrically coupled) to the integrated device 103 through the board 1010 and / or the substrate 102. One or more of the capacitors can be decoupling capacitors. In some implementations, the capacitor structure 106 can also be part of the power distribution network for the integrated device 103. Other packages (e.g., 400, 500, 600, 700, 800, 900) described in the present disclosure can be used as Fig.10 The package 100 can be replaced and / or supplemented.

[0101] Fig.11Device 1100 is illustrated, which includes package 100, board 1010, integrated device 1020, inductor 1030, and capacitor 1040. Package 100 includes substrate 102, integrated device 103, and capacitor structure 106. Package 100 is coupled to a first surface (e.g., top surface) of board 1010 through multiple solder interconnects 150. For example, package 100 is coupled to multiple board interconnects 1012 of board 1010 through multiple solder interconnects 150. Integrated device 1020 is coupled to a second surface (e.g., bottom surface) of board 1010. Integrated device 1020 may include a power management integrated circuit (PMIC). Inductor 1030 is coupled to the second surface of board 1010. Inductor 1030 may include a discrete inductor device. Capacitor 1040 is coupled to the second surface of board 1010. Capacitor 1040 may include a discrete capacitor device. Although not shown, other components and / or other capacitors (e.g., input capacitors) may be coupled to board 1010. Integrated device 1020, inductor 1030, and capacitor 1040 may be part of a power distribution network (PDN) that is configured to be coupled (e.g., electrically coupled) to integrated device 103 through board 1010 and / or substrate 102. One or more of the capacitors may be decoupling capacitors. In some implementations, capacitor structure 106 may also be part of a power distribution network for integrated device 103. Other packages (e.g., 400, 500, 600, 700, 800, 900) described in the present disclosure may be used as Fig.10 The package 100 can be replaced and / or supplemented.

[0102] Fig.12Package 1200 is illustrated, which includes substrate 102, integrated device 103, integrated device 1020, inductor 1030, and capacitor 1040. Package 1200 is coupled to a first surface (e.g., top surface) of board 1010 through multiple solder interconnects 150. For example, package 1200 is coupled to multiple board interconnects 1012 of board 1010 through multiple solder interconnects 150. Integrated device 1020 is coupled to a first surface (e.g., top surface) of substrate 102. Integrated device 1020 may include a power management integrated circuit (PMIC). Inductor 1030 is coupled to the first surface of substrate 102. Inductor 1030 may include a discrete inductor device. Capacitor 1040 is coupled to the first surface of substrate 102. Capacitor 1040 may include a discrete capacitor device. Although not shown, other components and / or other capacitors (e.g., input capacitors) may be coupled to board 1010. The integrated device 1020, the inductor 1030, and the capacitor 1040 can be part of a power distribution network (PDN) that is configured to be coupled (e.g., electrically coupled) to the integrated device 103 through the substrate 102. One or more of the capacitors can be decoupling capacitors. In some implementations, the capacitor structure 106 can also be part of the power distribution network for the integrated device 103. Other packages (e.g., 400, 500, 600, 700, 800, 900) described in the present disclosure can include the integrated device 1020, the inductor 1030, and / or the capacitor 1040.

[0103] Figure 1 and 4 -12 illustrates an example of possible locations of one or more capacitor structures including a vertically stacked trench capacitor device. Note that in Figure 1 and 4 -12 may be combined and / or interchanged with each other. For example, a capacitor structure located in a substrate in a specific configuration of a specific figure of the present disclosure may be implemented in a substrate described in another figure of the present disclosure. The present disclosure illustrates a capacitor structure having two stacked trench capacitor devices. However, a capacitor structure (e.g., 106, 406, 506) may include more than two stacked trench capacitor devices. In some implementations, the core layer of the substrate may include a material different from the material of the dielectric layer formed on either side of the core layer. In some implementations, the core layer of the substrate may include the same material as the dielectric layer formed on both sides of the core layer. Figure 1 and 4-12 illustrates capacitor structures implemented with core substrates. However, the capacitor structures described in the present disclosure may be implemented in coreless substrates. Thus, the capacitor structures described in the present disclosure may be implemented in dielectric layers of coreless substrates. Examples of coreless substrates include embedded trace substrates (ETS). When a coreless substrate is used, a cavity may be formed in the coreless substrate to accommodate the capacitor structures. In some implementations, the coreless substrate may be manufactured by forming dielectric layers around the capacitor structures. The coreless substrate may be manufactured by forming dielectric layers and interconnects on a carrier rather than a core layer and decoupling the carrier from the dielectric layers and interconnects once the coreless substrate is manufactured.

[0104] An integrated device (e.g., 103) may include a die (e.g., a bare semiconductor die). An integrated device may include a power management integrated circuit (PMIC). An integrated device may include an application processor. An integrated device may include a modem. An integrated device may include a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, an integrated device based on gallium arsenide (GaAs), a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated device, an integrated device based on silicon (Si), an integrated device based on silicon carbide (SiC), a memory, a power management processor, and / or a combination thereof. An integrated device (e.g., 103) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). An integrated device may include a transistor. An integrated device may be an example of an electrical component and / or an electrical device. In some implementations, an integrated device may be a core particle. A core particle may be manufactured using a process that provides a better yield than other processes used to manufacture other types of integrated devices, which may reduce the overall cost of manufacturing the core particle. For example, a core particle may use a different technology node than another core particle and / or another integrated device. The technology node (e.g., 5nm, 7nm, 10nm) may specify the minimum size of the transistor gate features of the integrated device and / or core particle. Different core particles may have different sizes and / or shapes. Different core particles may be configured to provide different functions. Different core particles may have different interconnect densities (e.g., interconnects with different widths and / or spacings). In some implementations, several core particles may be used to perform the functionality of one or more chips (e.g., one or more integrated devices). Relative to using a single chip to perform all functions of a package, using several core particles that perform several functions can reduce the overall cost of the package.

[0105] The package (e.g., 100, 400, 500, 600, 700, 800, 900, 1200) may be implemented in a radio frequency (RF) package. The RF package may be a radio frequency front end (RFFE) package. The package (e.g., 100, 200) may be configured to provide wireless fidelity (WiFi) communications and / or cellular communications (e.g., 2G, 3G, 4G, 5G). The package (e.g., 100, 400, 500, 600, 700, 800, 900, 1200) may be configured to support a global system for mobile communications (GSM), a universal mobile telecommunications system (UMTS), and / or long term evolution (LTE). The package (e.g., 100, 400, 500, 600, 700, 800, 900, 1200) may be configured to transmit and receive signals having different frequencies and / or communication protocols.

[0106] Having described various trench capacitor devices and substrates having stacked trench capacitor devices, processes and methods for fabricating substrates having stacked trench capacitor devices will now be described below.

[0107] Exemplary Process for Fabricating a Trench Capacitor Device

[0108] Fig.13A -13F illustrates an exemplary process for providing or manufacturing a trench capacitor device. In some implementations, Fig.13A –13F processes can be used to provide or manufacture Figure 3 The trench capacitor device 300 or any trench capacitor device described in the present disclosure.

[0109] It should be noted that Figures 13A-13F The process of one or more stages can be combined to simplify and / or illustrate the process for providing or manufacturing a trench capacitor device including a plurality of stacked capacitors. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more of these processes can be replaced or substituted without departing from the spirit of the present disclosure. However, different implementations can manufacture capacitor structures differently.

[0110] like Fig.13A As shown in , stage 1 illustrates a state after providing a die substrate 202. The die substrate 202 may be a part of a wafer. The die substrate 202 may include silicon (Si).

[0111] Stage 2 illustrates a state after forming a plurality of trenches 1300 in the die substrate 202. Specifically, a plurality of trenches 1300 (e.g., a first trench, a second trench, a third trench) are formed through the first surface of the die substrate 202. Different implementations may form the trenches differently. An etching process (e.g., chemical etching, mechanical etching) and / or a laser process may be used to form the trenches.

[0112] like Fig. 13B , stage 3 illustrates a state after forming (e.g., disposing) a first conductive layer 212 on the first surface of the die substrate 202 and / or in the trench 1300 of the die substrate 202. A deposition process (e.g., chemical vapor deposition) may be used to form the first conductive layer 212. In some implementations, the first conductive layer 212 may include N+ silicon. Other implementations may use different materials and / or different material combinations than the first conductive layer 212.

[0113] Stage 4 illustrates a state after a dielectric layer 214 is formed over the first conductive layer 212. A deposition process may be used to form the dielectric layer 214 over the first conductive layer 212. The dielectric layer 214 may touch the first conductive layer 212. At least a portion of the dielectric layer 214 may be formed in the plurality of trenches 1300. Some portions of the dielectric layer 214 may be located over the first surface of the die substrate 202.

[0114] like Fig. 13C , stage 5 illustrates a state after forming (e.g., disposing) a second conductive layer 216 on the dielectric layer 214. The second conductive layer 216 may be located on the first surface of the die substrate 202 and / or in the trench 1300 of the die substrate 202. A deposition process (e.g., chemical vapor deposition) may be used to form the second conductive layer 216. In some implementations, the second conductive layer 216 may include N+ polysilicon. Other implementations may use different materials and / or different material combinations than the second conductive layer 216.

[0115] Stage 6 illustrates a state after forming filler 215 over second conductive layer 216. Filler 215 may be formed in the trench of die substrate 202. A deposition process may be used to form filler 215 over second conductive layer 216. Filler 215 may be optional.

[0116] like Fig.13D As shown in FIG. 1 , stage 7 illustrates a state after at least one cavity 1309 is formed in the die substrate 202. The cavity 1309 may extend through the die substrate 202. A laser process (eg, a laser ablation process) may be used to form the cavity 1309.

[0117] Stage 8 illustrates a state after forming the through substrate via 270 in the cavity 1309. A plating process may be used to form the through substrate via 270. The through substrate via 270 may or may not be coupled to the first conductive layer 212. In some implementations, the through substrate via 270 may be coupled to another conductive layer (e.g., 216).

[0118] Stage 9 illustrates a state after forming the first contact layer 230 and the second contact layer 218. The first contact layer 230 may be formed over the first conductive layer 212 and / or the through substrate via 270, and the second contact layer 218 may be formed over the second conductive layer 216. The first contact layer 230 and the second contact layer 218 may be formed using a plating process (e.g., an electroplating process).

[0119] like Fig.13E As shown in FIG. 1 , stage 10 illustrates a state after a dielectric layer 240 is formed over the die substrate 202, the first conductive layer 212, the second conductive layer 216, the first contact layer 230, and / or the second contact layer 218. A deposition process may be used to form the dielectric layer 240.

[0120] Stage 11 illustrates a state after forming the plurality of cavities 1320 in the dielectric layer 240. An etching process and / or a laser process may be used to form the plurality of cavities 1320.

[0121] like Fig.13F , stage 12 illustrates a state after forming a first capacitor interconnect 250 and a second capacitor interconnect 260. The first capacitor interconnect 250 may be coupled to the first contact layer 230. The second capacitor interconnect 260 may be coupled to the second contact layer 218. The first capacitor interconnect 250 and the second capacitor interconnect 260 may be formed using a plating process (e.g., an electroplating process).

[0122] Stage 13 illustrates a state after removing portions of the die substrate 202 to thin the die substrate 202. A back grinding process may be used to remove portions of the die substrate 202. Stage 12 and / or stage 13 may illustrate an example of a trench capacitor device including several trench capacitors.

[0123] Exemplary Flowchart of a Method for Fabricating a Trench Capacitor Device

[0124] In some implementations, fabricating a capacitor structure including a plurality of trench capacitors includes several processes. Fig.14 An exemplary flow chart of a method 1400 for providing or fabricating a capacitor structure including a plurality of trench capacitors is illustrated. Fig.14 The method 1400 may be used to provide or manufacture the Figure 3 The trench capacitor device 300 of FIG. 1400 may, however, be used to provide or manufacture any capacitor structure described in the present disclosure.

[0125] It should be noted that Fig.14The process of one or more processes can be combined to simplify and / or illustrate the method for providing or manufacturing a capacitor structure. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more of these processes can be replaced or substituted without departing from the spirit of the present disclosure. However, different implementations can manufacture capacitor structures differently.

[0126] The method provides (at 1405) a die substrate (eg, 202). The die substrate 202 may include silicon (Si). Fig.13A Stage 1 of FIG. 1 illustrates a state after the die substrate 202 is provided.

[0127] The method forms (at 1410) a plurality of trenches. Fig.13A Stage 2 of the embodiment illustrates a state after forming a plurality of trenches 1300 in the die substrate 202. Specifically, a plurality of trenches 1300 (e.g., a first trench, a second trench, a third trench) are formed through the first surface of the die substrate 202. Different implementations may form the trenches differently. An etching process (e.g., chemical etching, mechanical etching) and / or a laser process may be used to form the trenches.

[0128] The method forms (at 1415 ) a first conductive layer over the trenches of the die substrate and / or the first surface of the die substrate. Fig. 13B Stage 3 of 1300 illustrates a state after forming (e.g., disposing) a first conductive layer 212 on the first surface of the die substrate 202 and / or in the trench 1300 of the die substrate 202. A deposition process (e.g., chemical vapor deposition) may be used to form the first conductive layer 212. In some implementations, the first conductive layer 212 may include N+ silicon. Other implementations may use a different material than the first conductive layer 212.

[0129] The method forms (at 1420) a dielectric layer over the first conductive layer. Fig. 13B Stage 4 of illustrative embodiment illustrates a state after a dielectric layer 214 is formed over the first conductive layer 212. A deposition process may be used to form the dielectric layer 214 over the first conductive layer 212. The dielectric layer 214 may touch the first conductive layer 212. At least a portion of the dielectric layer 214 may be formed in the plurality of trenches 1300. Some portions of the dielectric layer 214 may be located over the first surface of the die substrate 202.

[0130] The method forms (at 1425) a second conductive layer over the dielectric layer. Fig. 13CStage 5 of the embodiment illustrates a state after forming (e.g., disposing) a second conductive layer 216 on the dielectric layer 214. The second conductive layer 216 may be located on the first surface of the die substrate 202 and / or in the trench 1300 of the die substrate 202. A deposition process (e.g., chemical vapor deposition) may be used to form the second conductive layer 216. In some implementations, the second conductive layer 216 may include N+ polysilicon. Other implementations may use a different material than the second conductive layer 216.

[0131] The method can optionally form (at 1430) a filler in the trench over the second conductive layer. Fig. 13C Stage 6 of FIG. 2 illustrates a state after forming a filler 215 over the second conductive layer 216. The filler 215 may be formed in the trench of the die substrate 202. A deposition process may be used to form the filler 215 over the second conductive layer 216.

[0132] The method may optionally form (at 1435) a cavity through the die substrate. Fig.13D Stage 7 of 1430 illustrates a state after forming the cavity 1309 through the die substrate 202. An etching process or a laser process may be used to form the cavity 1309 through the die substrate 202. The method forms (at 1435) a through substrate via (e.g., 270) in the cavity 1309. A plating process may be used to form the through substrate via 270. Fig.13D Stage 8 of FIG. 1 illustrates an example of a through-substrate via.

[0133] The method forms (at 1440) first and second conductive layers (eg, contact layers). Fig.13D Stage 9 of FIG. 1 illustrates a state after forming the first contact layer 230 and the second contact layer 218. The first contact layer 230 may be formed over the first conductive layer 212 and / or the through substrate via 270, and the second contact layer 218 may be formed over the second conductive layer 216. The first contact layer 230 and the second contact layer 218 may be formed using a plating process (e.g., an electroplating process).

[0134] The method forms (at 1445) a dielectric layer 240 over the die substrate 202, the first conductive layer 212, the second conductive layer 216, the first contact layer 230, and / or the second contact layer 218. A deposition process may be used to form the dielectric layer 240. The method may form (at 1445) a cavity in the dielectric layer 240. Fig.13E Stages 10 and 11 of the drawings illustrate the state after forming a dielectric layer and forming a cavity in the dielectric layer.

[0135] The method forms (at 1450 ) interconnects in one or more cavities (eg, 1320 ) of the dielectric layer 240 . Fig.13FStage 12 of illustrates an example of forming interconnects (eg, 250 and 260). In some implementations, the method may thin a portion of the die substrate. Fig.13F Stage 13 of the present invention illustrates an example of thinning the die substrate.

[0136] The method may be performed on a wafer to form a plurality of trench capacitor devices that can be singulated. In some implementations, a first wafer including a plurality of first trench capacitor devices is coupled to a plurality of second trench capacitor devices via a plurality of solder interconnects or adhesives, and the coupled wafer is singulated into individual capacitor structures including first trench capacitor devices vertically stacked on top of second trench capacitor devices. In some implementations, the wafer is singulated and then the individual trench capacitors are vertically stacked on top of each other. As described above, some implementations may include more than two vertically stacked trench capacitors.

[0137] Exemplary process for making a substrate including a stacked trench capacitor device

[0138] Figures 15A-15E Exemplary processes for providing or manufacturing a substrate including a stacked trench capacitor are described. In some implementations, Fig.15A –15E processes can be used to provide or manufacture Figure 6 or other substrates described in the present disclosure.

[0139] It should be noted that Figures 15A-15E The process of one or more stages can be combined to simplify and / or clarify the process for providing or manufacturing the substrate. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more of these processes can be replaced or substituted without departing from the spirit of the present disclosure. Different implementations can manufacture the substrate differently.

[0140] like Fig.15A As shown in , stage 1 illustrates a state after providing a carrier 1500. The carrier 1500 may include a tape.

[0141] Stage 2 illustrates a state after coupling the capacitor structure 106 to the carrier 1500. The capacitor structure 106 may be placed on the carrier 1500. As an alternative or in addition to the capacitor structure 106, other capacitor structures (eg, 406, 506) may be coupled to the carrier 1500.

[0142] Stage 3 illustrates a state after a dielectric layer 1510 is formed over the carrier 1500 and the capacitor structure 106. A cavity 1512 is present in the dielectric layer 1510 over the capacitor structure 106. The cavity 1512 is formed so that in a subsequent pressing of the dielectric layer 1510, the dielectric layer 1510 does not damage the capacitor structure 106. A deposition and / or twisting process may be used to form the dielectric layer 1510.

[0143] Stage 4 illustrates a state after the dielectric layer 1510 is pressed, which compresses the dielectric layer 1510. The dielectric layer 1510 is formed around the capacitor structure 106. Examples of the dielectric layer 1510 include glass, prepreg, and / or Ajinomoto built-up film (ABF).

[0144] like Fig. 15B , stage 5 illustrates a state after decoupling the carrier 1500 from the dielectric layer 1510 and the capacitor structure 106. For example, when the carrier 1500 includes a tape, the carrier 1500 may be de-taped from the dielectric layer 1510 and the capacitor structure 106. A cleaning process (e.g., plasma cleaning) may be performed on the dielectric layer 1510 and the capacitor structure 106 after removing the carrier 1500.

[0145] Stage 6 illustrates a state after dielectric layer 1520 is formed on dielectric layer 1510 and capacitor structure 106. Dielectric layer 1520 may include prepreg. Deposition and / or lamination processes may be used to form dielectric layer 1520. Dielectric layer 1520 may be formed on a surface of dielectric layer 1510 and / or a surface of capacitor structure 106. Note that forming dielectric layer 1520 may be optional. Thus, in some implementations, dielectric layer 1520 is not formed or provided.

[0146] Stage 7 illustrates a state after forming a plurality of cavities 1522 in the dielectric layer 1510. The plurality of cavities 1522 may be formed using an etching process (eg, a photo-etching process) and / or a laser process. The plurality of cavities 1522 may expose interconnections of the capacitor structure 106.

[0147] Stage 8 illustrates a state after a plurality of cavities 1524 are formed in dielectric layer 1510 and dielectric layer 1520. Multiple cavities 1524 may be formed by an etching process, a laser process, and / or a drilling process. Multiple cavities 1524 may be formed by one or more etching processes (e.g., a photolithography process). For example, multiple cavities 1524 may be formed through a first surface of dielectric layer 1510 and through a second surface of dielectric layer 1520. Dielectric layer 1510 and / or dielectric layer 1520 may be represented as core layer 120. Dielectric layer 1510 and / or dielectric layer 1520 may include prepreg.

[0148] Stage 9 illustrates a state after forming a plurality of core interconnects in the plurality of cavities 1522 and the plurality of cavities 1524. For example, a plurality of core interconnects 121 may be formed in the plurality of cavities 1524. The plurality of core interconnects 121 may be an example of a first plurality of core interconnects. A second plurality of core interconnects 1521 may be formed in the plurality of cavities 1522. The second plurality of core interconnects 1521 may extend through a portion of the dielectric layer 1510. The second plurality of core interconnects 1521 may extend between a surface (e.g., a top surface) of the dielectric layer 1510 and the capacitor structure 106. The second plurality of core interconnects 1521 is coupled to the capacitor structure 106. The second plurality of core interconnects 1521 may be considered as a portion of the plurality of core interconnects 121. A plating process may be used to form the plurality of core interconnects 121 and the second plurality of core interconnects 1521. However, different implementations may use different processes to form the plurality of core interconnects 121 and / or the second plurality of core interconnects 1521. The plurality of core interconnects 121 may include core vias located in the dielectric layer 1510 and the dielectric layer 1520. The second plurality of core interconnects 1521 may include core vias located in the dielectric layer 1510. Stage 9 also illustrates a state after forming a plurality of interconnects 1523 over a first surface (e.g., top surface) of the dielectric layer 1510. The plurality of interconnects 1523 may be coupled to the plurality of core interconnects 121 and the second plurality of core interconnects 1521. The plurality of interconnects 1523 may be configured to be coupled to the capacitor structure 106 through the second plurality of core interconnects 1521. Stage 9 also illustrates a state after forming a plurality of interconnects 1503 over (e.g., below) a second surface (e.g., bottom surface) of the dielectric layer 1520. If the dielectric layer 1520 is not present, the plurality of interconnects 1503 are formed over a second surface (e.g., bottom surface) of the dielectric layer 1510. The plurality of interconnects 1503 may be coupled to the plurality of core interconnects 121. A patterning process, a stripping process, and / or a plating process may be used to form the plurality of interconnects 1503 and the plurality of interconnects 1523. Stage 9 illustrates the capacitor structure 106 located in the dielectric layer 1510 .

[0149] like Fig. 15C As shown in , stage 10 illustrates a state after forming a dielectric layer 122a on a first surface of the core layer 120 and a dielectric layer 126a on a second surface of the core layer 220. The core layer 120 may represent a dielectric layer 1510 and / or a dielectric layer 1520. A deposition process and / or a lamination process may be used to form the dielectric layers 122a and 126a. The dielectric layers 122a and 126a may include prepregs (e.g., prepreg layers). Stage 10 illustrates a capacitor structure 106 located in the core layer 120. Stage 11 illustrates a state after forming a plurality of cavities 1542 in the dielectric layer 122a and a plurality of cavities 1546 in the dielectric layer 126a. An etching process (e.g., a photoetching process) and / or a laser process (e.g., laser drilling, laser ablation) may be used to form the plurality of cavities 1542 and the plurality of cavities 1546.

[0150] Stage 12 illustrates a state after forming a plurality of interconnects 1525 over the dielectric layer 122a and the plurality of cavities 1542 and coupling them to the dielectric layer 122a and the plurality of cavities 1542. The plurality of interconnects 1525 may be coupled to the plurality of interconnects 1523. Stage 12 also illustrates a state after forming a plurality of interconnects 1527 over the dielectric layer 126a and the plurality of cavities 1546 and coupling them to the dielectric layer 126a and the plurality of cavities 1546. The plurality of interconnects 1527 may be coupled to the plurality of interconnects 1503. A patterning process, a stripping process, and / or a plating process may be used to form the plurality of interconnects 1525 and the plurality of interconnects 1527.

[0151] like Fig.15D , stage 13 illustrates a state after dielectric layer 122b is formed over the first surface of dielectric layer 122a and coupled to the first surface of dielectric layer 122a and dielectric layer 126b is formed over the second surface of dielectric layer 126a and coupled to the second surface of dielectric layer 126a. Deposition processes and / or lamination processes may be used to form dielectric layers 122b and 126b. Dielectric layers 122b and 126b may include prepreg (e.g., prepreg layers).

[0152] Stage 14 illustrates a state after forming a plurality of cavities 1544 in dielectric layer 122b and a plurality of cavities 1548 in dielectric layer 126b. An etching process and / or a laser process (eg, laser drilling, laser ablation) may be used to form the plurality of cavities 1544 and the plurality of cavities 1548.

[0153] Stage 15 illustrates a state after forming a plurality of interconnects 1545 over dielectric layer 122b and a plurality of cavities 1544 and coupling them to dielectric layer 122b and a plurality of cavities 1544. The plurality of interconnects 1545 may be coupled to the plurality of interconnects 1525. Stage 12 also illustrates a state after forming a plurality of interconnects 1547 over dielectric layer 126b and a plurality of cavities 1548 and coupling them to dielectric layer 126b and a plurality of cavities 1548. The plurality of interconnects 1547 may be coupled to the plurality of interconnects 1527. A patterning process, a stripping process, and / or a plating process may be used to form the plurality of interconnects 1545 and the plurality of interconnects 1547. Note that the plurality of interconnects 1545 and the plurality of interconnects 1547 may be formed by repeating the process described above. Fig.15D Stages 13-15 are used to form additional dielectric layers and additional interconnects.

[0154] like Fig.15EAs shown in , stage 16 illustrates a state after forming solder resist layer 140 on the surface of dielectric layer 122b and solder resist layer 142 on the surface of dielectric layer 126b. Multiple interconnects 125 may represent multiple interconnects 1525, multiple interconnects 1545, and / or multiple interconnects 1523. Multiple interconnects 127 may represent multiple interconnects 1527, multiple interconnects 1547, and / or multiple interconnects 1503.

[0155] Stage 17 illustrates a state after the plurality of solder interconnects 150 are coupled to the substrate 102. A solder reflow process may be used to couple the plurality of solder interconnects 150 to the plurality of interconnects 127.

[0156] Exemplary process for making a substrate including a stacked trench capacitor device

[0157] Figures 16A-16E Exemplary processes for providing or manufacturing a substrate including a stacked trench capacitor are described. In some implementations, Fig.16A –16E processes can be used to provide or manufacture Figure 7 or other substrates described in the present disclosure.

[0158] It should be noted that Figures 16A-16E The process of one or more stages can be combined to simplify and / or clarify the process for providing or manufacturing the substrate. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more of these processes can be replaced or substituted without departing from the spirit of the present disclosure. Different implementations can manufacture the substrate differently.

[0159] like Fig.16A As shown in , stage 1 illustrates a state after providing a carrier 1500. The carrier 1500 may include a tape.

[0160] Stage 2 illustrates a state after coupling capacitor structure 506 to carrier 1500. Capacitor structure 506 may be placed on carrier 1500. As an alternative or in addition to capacitor structure 506, other capacitor structures (eg, 106, 406) may be coupled to carrier 1500.

[0161] Stage 3 illustrates a state after providing a dielectric layer 1510 over the carrier 1500 and the capacitor structure 506. A cavity 1512 is present in the dielectric layer 1510 over the capacitor structure 506. The cavity 1512 is formed so that in a subsequent pressing of the dielectric layer 1510, the dielectric layer 1510 does not damage the capacitor structure 506. A deposition and / or twisting process may be used to form the dielectric layer 1510.

[0162] Stage 4 illustrates the state after the dielectric layer 1510 is pressed, which compresses the dielectric layer 1510. The dielectric layer 1510 is formed around the capacitor structure 506.

[0163] Stage 5 illustrates a state after decoupling the carrier 1500 from the dielectric layer 1510 and the capacitor structure 506. For example, when the carrier 1500 includes a tape, the carrier 1500 may be de-taped from the dielectric layer 1510 and the capacitor structure 506. A cleaning process (e.g., plasma cleaning) may be performed on the dielectric layer 1510 and the capacitor structure 506 after removing the carrier 1500.

[0164] Stage 6 illustrates a state after dielectric layer 1520 is formed on dielectric layer 1510 and capacitor structure 506. Dielectric layer 1520 may include prepreg. Deposition and / or lamination processes may be used to form dielectric layer 1520. Dielectric layer 1520 may be formed on a surface of dielectric layer 1510 and / or a surface of capacitor structure 506.

[0165] like Fig. 16B , stage 7 illustrates a state after forming a plurality of cavities 1522 in the dielectric layer 1510. The plurality of cavities 1522 may be formed by an etching process (eg, a photo-etching process) and / or a laser process. The plurality of cavities 1522 may expose interconnections of the capacitor structure 506.

[0166] Stage 8 illustrates a state after forming a plurality of cavities 1524 in the dielectric layer 1520. The plurality of cavities 1524 may be formed by a laser process and / or a drilling process. The plurality of cavities 1524 may be formed by one or more etching processes (e.g., a photo-etching process). For example, the plurality of cavities 1524 may be formed through the surface of the dielectric layer 1520. Some of the plurality of cavities 1524 may expose a portion of the capacitor structure 506. For example, the plurality of cavities 1524 may expose the interconnections of the capacitor structure 506.

[0167] Stage 9 illustrates a state after forming a plurality of cavities 1534 in dielectric layer 1510 and / or dielectric layer 1520. The plurality of cavities 1534 may be formed by a laser process and / or a drilling process. The plurality of cavities 1534 may be formed by one or more etching processes (e.g., a photo-etching process). For example, the plurality of cavities 1534 may be formed through the first surface of dielectric layer 1510 and / or through the second surface of dielectric layer 1520. The plurality of cavities 1534 may be aligned with at least some of the plurality of cavities 1524. The plurality of cavities 1534 may include at least some of the plurality of cavities 1524.

[0168] Stage 10 illustrates a state after a plurality of core interconnects are formed in a plurality of cavities 1522, a plurality of cavities 1524, and a plurality of cavities 1534. For example, a plurality of core interconnects 121 may be formed in a plurality of cavities 1534. A plurality of core interconnects 121 may be an example of a first plurality of core interconnects. A second plurality of core interconnects 1521a may be formed in a plurality of cavities 1522. A second plurality of core interconnects 1521a may extend through a portion of a dielectric layer 1510. A second plurality of core interconnects 1521a may extend between a surface (e.g., a top surface) of a dielectric layer 1510 and a capacitor structure 506. A second plurality of core interconnects 1521a is coupled to the capacitor structure 506. A second plurality of core interconnects 1521a may be considered as a portion of a plurality of core interconnects 121. A third plurality of core interconnects 1521b may be formed in a plurality of cavities 1524. A third plurality of core interconnects 1521b may extend through a portion of a dielectric layer 1510 and / or a dielectric layer 1520. The third plurality of core interconnects 1521b may extend between a surface (e.g., bottom surface) of the dielectric layer 1520 and the capacitor structure 506. The third plurality of core interconnects 1521b is coupled to the capacitor structure 506. The third plurality of core interconnects 1521b may be considered as part of the plurality of core interconnects 121. A plating process may be used to form the plurality of core interconnects 121, the second plurality of core interconnects 1521a, and / or the third plurality of core interconnects 1521b. However, different implementations may use different processes to form the plurality of core interconnects 121, the second plurality of core interconnects 1521a, and / or the third plurality of core interconnects 1521b. The plurality of core interconnects 121 may include core through-holes located in the dielectric layer 1510 and the dielectric layer 1520. The second plurality of core interconnects 1521a may include core through-holes located in the dielectric layer 1510. The third plurality of core interconnects 1521b may include core through-holes located in the dielectric layer 1510 and / or the dielectric layer 1520. The dielectric layer 1510 and / or the dielectric layer 1520 may be denoted as a core layer 120 .

[0169] Stage 10 also illustrates a state after forming a plurality of interconnects 1523 over a first surface (e.g., top surface) of dielectric layer 1510. Multiple interconnects 1523 may be coupled to multiple core interconnects 121 and a second plurality of core interconnects 1521a. Multiple interconnects 1523 may be configured to be coupled to capacitor structure 506 through second plurality of core interconnects 1521a. Stage 10 also illustrates a state after forming multiple interconnects 1503 over (e.g., below) a second surface (e.g., bottom surface) of dielectric layer 1520. Multiple interconnects 1503 may be coupled to multiple core interconnects 121 and a third plurality of core interconnects 1521b. Multiple interconnects 1503 may be configured to be coupled to capacitor structure 506 through third plurality of core interconnects 1521b. Patterning processes, stripping processes, and / or plating processes may be used to form multiple interconnects 1503 and / or multiple interconnects 1523. Stage 10 illustrates capacitor structure 506 located in dielectric layer 1510.

[0170] like Fig. 16C As shown in , stage 11 illustrates a state after dielectric layer 122a is formed on the first surface of core layer 120 and dielectric layer 126a is formed on the second surface of core layer 220. Core layer 120 may represent dielectric layer 1510 and / or dielectric layer 1520. Deposition process and / or lamination process may be used to form dielectric layers 122a and 126a. Dielectric layers 122a and 126a may include prepreg (e.g., prepreg layer). Stage 11 illustrates capacitor structure 506 located in core layer 120.

[0171] Stage 12 illustrates a state after forming a plurality of cavities 1542 in dielectric layer 122a and forming a plurality of cavities 1546 in dielectric layer 126a. An etching process (e.g., a photo-etching process) and / or a laser process (e.g., laser drilling, laser ablation) may be used to form the plurality of cavities 1542 and the plurality of cavities 1546.

[0172] Stage 13 illustrates a state after forming a plurality of interconnects 1525 over the dielectric layer 122a and the plurality of cavities 1542 and coupling them to the dielectric layer 122a and the plurality of cavities 1542. The plurality of interconnects 1525 may be coupled to the plurality of interconnects 1523. Stage 12 also illustrates a state after forming a plurality of interconnects 1527 over the dielectric layer 126a and the plurality of cavities 1546 and coupling them to the dielectric layer 126a and the plurality of cavities 1546. The plurality of interconnects 1527 may be coupled to the plurality of interconnects 1503. A patterning process, a stripping process, and / or a plating process may be used to form the plurality of interconnects 1525 and the plurality of interconnects 1527.

[0173] like Fig.16D As shown in FIG. 1 , stage 14 illustrates a state after dielectric layer 122b is formed over the first surface of dielectric layer 122a and coupled to the first surface of dielectric layer 122a, and dielectric layer 126b is formed over the second surface of dielectric layer 126a and coupled to the second surface of dielectric layer 126a. Deposition processes and / or lamination processes may be used to form dielectric layers 122b and 126b. Dielectric layers 122b and 126b may include prepregs (e.g., prepreg layers).

[0174] Stage 15 illustrates a state after forming a plurality of cavities 1544 in dielectric layer 122b and a plurality of cavities 1548 in dielectric layer 126b. An etching process and / or a laser process (eg, laser drilling, laser ablation) may be used to form the plurality of cavities 1544 and the plurality of cavities 1548.

[0175] Stage 16 illustrates a state after forming a plurality of interconnects 1545 over dielectric layer 122b and a plurality of cavities 1544 and coupling them to dielectric layer 122b and a plurality of cavities 1544. The plurality of interconnects 1545 may be coupled to the plurality of interconnects 1525. Stage 12 also illustrates a state after forming a plurality of interconnects 1547 over dielectric layer 126b and a plurality of cavities 1548 and coupling them to dielectric layer 126b and a plurality of cavities 1548. The plurality of interconnects 1547 may be coupled to the plurality of interconnects 1527. A patterning process, a stripping process, and / or a plating process may be used to form the plurality of interconnects 1545 and the plurality of interconnects 1547. Note that the plurality of interconnects 1545 and the plurality of interconnects 1547 may be formed by repeating the process described above. Fig.16D Stages 14-16 are used to form additional dielectric layers and additional interconnects.

[0176] like Fig.16E As shown in , stage 17 illustrates a state after forming solder resist layer 140 on the surface of dielectric layer 122b and solder resist layer 142 on the surface of dielectric layer 126b. Multiple interconnects 125 may represent multiple interconnects 1525, multiple interconnects 1545, and / or multiple interconnects 1523. Multiple interconnects 127 may represent multiple interconnects 1527, multiple interconnects 1547, and / or multiple interconnects 1503.

[0177] Stage 18 illustrates a state after the plurality of solder interconnects 150 are coupled to the substrate 102. A solder reflow process may be used to couple the plurality of solder interconnects 150 to the plurality of interconnects 127.

[0178] Exemplary process for making a substrate including a stacked trench capacitor device

[0179] Figures 17A-17E Exemplary processes for providing or manufacturing a substrate including a stacked trench capacitor are described. In some implementations, Fig.17A –17E processes can be used to provide or manufacture Figure 8 or other substrates described in the present disclosure.

[0180] It should be noted that Figures 17A-17E The process of one or more stages can be combined to simplify and / or clarify the process for providing or manufacturing the substrate. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more of these processes can be replaced or substituted without departing from the spirit of the present disclosure. Different implementations can manufacture the substrate differently.

[0181] like Fig.17A As shown in FIG, stage 1 illustrates a state after providing a core dielectric layer 830. The core dielectric layer 830 may include a metal layer (eg, seed layer) on a first surface of the core dielectric layer 830 and a metal layer (eg, seed layer) on a second surface of the core layer.

[0182] Stage 2 illustrates the state after a plurality of core interconnects 823 are formed in the core dielectric layer 830. A plurality of core interconnects 823 may be formed by forming a cavity in the core dielectric layer 830 and forming a plurality of core interconnects 823 in the cavity of the core dielectric layer 830. A plurality of core interconnects 823 may also be formed on the surface(s) of the core dielectric layer 830. A laser process may be used to form a cavity in the core dielectric layer 830. A plating process may be used to form a plurality of core interconnects 823. A plurality of core interconnects 823 may include a core interconnect 823a (e.g., a core pad interconnect), a core interconnect 823b (e.g., a core through-hole interconnect), and a core interconnect 823c. As will be further described below, in some implementations, a core interconnect 823c may be considered an interconnect located outside the core layer. In some implementations, a core interconnect 823c is not formed during this stage. Thus, in some implementations, after stage 2, the core dielectric layer 830 may include the core interconnect 823a and the core interconnect 823b but not the core interconnect 823c.

[0183] Stage 3 illustrates a state after the capacitor structure 406 is coupled to the core dielectric layer 830 via the plurality of solder interconnects 864. A reflow process may be used to couple the capacitor structure 406 to the plurality of core interconnects 823. As an alternative or in addition to the capacitor structure 406, other capacitor structures (e.g., 106, 506) may be coupled to the core dielectric layer 830.

[0184] Stage 4 illustrates a state after forming the core dielectric layer 820 over the core dielectric layer 830 and the capacitor structure 406. A deposition process, a twisting process, and / or a pressing process may be used to form the core dielectric layer 820. The core dielectric layer 820 surrounds the capacitor structure 406. The core dielectric layer 820 may include a prepreg.

[0185] like Fig. 17B , stage 5 illustrates a state after forming a plurality of cavities 1720 in the core dielectric layer 820 and over the capacitor structure 406. The plurality of cavities 1720 may expose interconnects from the capacitor structure 406. An etching process and / or a laser ablation process may be used to form the plurality of cavities 1720.

[0186] Stage 6 illustrates a state after forming a plurality of cavities 1730 in the core dielectric layer 820 and the core dielectric layer 830 using an etching process, a laser process, and / or a drilling process. The plurality of cavities 1730 may extend through the core dielectric layer 820 and the core dielectric layer 830.

[0187] Stage 7 illustrates a state after a plurality of core interconnects 121 are formed in a plurality of cavities 1720 and / or a plurality of cavities 1730. For example, a plurality of core interconnects 121 may be formed in a plurality of cavities 1730. A plurality of core interconnects 121 may be an example of a first plurality of core interconnects. A plurality of core interconnects 821 may be formed between a capacitor structure 406 and a plurality of interconnects 1523. A plurality of interconnects 1523 may be coupled to interconnects of a capacitor structure 406 through a plurality of core interconnects 821. A plurality of core interconnects 821 may be located in a core dielectric layer 820. A plating process may be used to form a plurality of core interconnects 121 and a plurality of core interconnects 821. However, different implementations may use different processes to form a plurality of core interconnects 121 and / or a plurality of core interconnects 821. A first plurality of core interconnects 121 may include core vias located in a core dielectric layer 820 and a core dielectric layer 830.

[0188] Stage 7 also illustrates a state after forming a plurality of interconnects 1523 over a first surface (e.g., top surface) of the core dielectric layer 820. The plurality of interconnects 1523 may be coupled to the plurality of core interconnects 121. Stage 7 also illustrates a state after forming a plurality of interconnects 1503 over (e.g., below) a second surface (e.g., bottom surface) of the core dielectric layer 830. The plurality of interconnects 1503 may be coupled to the plurality of core interconnects 121. The plurality of interconnects 1503 may be coupled to the interconnects of the capacitor structure 406 through the plurality of core interconnects 823. A patterning process, a stripping process, and / or a plating process may be used to form the plurality of interconnects 1503 and the plurality of interconnects 1523. Stage 7 illustrates the capacitor structure 406 located in the core dielectric layer 820.

[0189] like Fig. 17C As shown in FIG. 8 , stage 8 illustrates a state after dielectric layer 122a is formed on a first surface of core dielectric layer 820 and dielectric layer 126a is formed on a second surface of core dielectric layer 830. Core layer 120 may represent core dielectric layer 820 and core dielectric layer 830. Deposition processes and / or lamination processes may be used to form dielectric layers 122a and 126a. Dielectric layers 122a and 126a may include prepreg (e.g., prepreg layers). Stage 8 illustrates capacitor structure 406 located in core layer 120.

[0190] Stage 9 illustrates a state after forming a plurality of cavities 1542 in dielectric layer 122a and forming a plurality of cavities 1546 in dielectric layer 126a. An etching process and / or a laser process (eg, laser drilling, laser ablation) may be used to form the plurality of cavities 1542 and the plurality of cavities 1546.

[0191] Stage 10 illustrates a state after forming a plurality of interconnects 1525 over the dielectric layer 122a and the plurality of cavities 1542 and coupling them to the dielectric layer 122a and the plurality of cavities 1542. The plurality of interconnects 1525 may be coupled to the plurality of interconnects 1523. Stage 9 further illustrates a state after forming a plurality of interconnects 1527 over the dielectric layer 126a and the plurality of cavities 1546 and coupling them to the dielectric layer 126a and the plurality of cavities 1546. The plurality of interconnects 1527 may be coupled to the plurality of interconnects 1503 and / or the plurality of core interconnects 823. A patterning process, a stripping process, and / or a plating process may be used to form the plurality of interconnects 1525 and the plurality of interconnects 1527.

[0192] like Fig.17D As shown in FIG. 1 , stage 11 illustrates a state after dielectric layer 122b is formed over a first surface of dielectric layer 122a and coupled to the first surface of dielectric layer 122a and dielectric layer 126b is formed over a second surface of dielectric layer 126a and coupled to the second surface of dielectric layer 126a. Deposition processes and / or lamination processes may be used to form dielectric layers 122b and 126b. Dielectric layers 122b and 126b may include prepregs (e.g., prepreg layers).

[0193] Stage 12 illustrates a state after forming a plurality of cavities 1544 in dielectric layer 122b and a plurality of cavities 1548 in dielectric layer 126b. An etching process and / or a laser process (eg, laser drilling, laser ablation) may be used to form the plurality of cavities 1544 and the plurality of cavities 1548.

[0194] Stage 13 illustrates a state after forming a plurality of interconnects 1545 over dielectric layer 122b and a plurality of cavities 1544 and coupling them to dielectric layer 122b and a plurality of cavities 1544. The plurality of interconnects 1545 may be coupled to the plurality of interconnects 1525. Stage 13 also illustrates a state after forming a plurality of interconnects 1547 over dielectric layer 126b and a plurality of cavities 1548 and coupling them to dielectric layer 126b and a plurality of cavities 1548. The plurality of interconnects 1547 may be coupled to the plurality of interconnects 1527. A patterning process, a stripping process, and / or a plating process may be used to form the plurality of interconnects 1545 and the plurality of interconnects 1547. Note that the plurality of interconnects 1545 and the plurality of interconnects 1547 may be formed by repeating the process described above. Fig.17D Stages 11-13 are used to form additional dielectric layers and additional interconnects.

[0195] like Fig.17EAs shown in , stage 14 illustrates a state after forming solder resist layer 140 over the surface of dielectric layer 122b and solder resist layer 142 over the surface of dielectric layer 126b. Multiple interconnects 125 may represent multiple interconnects 1525, multiple interconnects 1545, and / or multiple interconnects 1523. Multiple interconnects 127 may represent multiple interconnects 1527, multiple interconnects 1547, multiple interconnects 1503, and / or interconnects located in dielectric layer 126a from multiple core interconnects 823.

[0196] Stage 15 illustrates a state after the plurality of solder interconnects 150 are coupled to the substrate 102. A solder reflow process may be used to couple the plurality of solder interconnects 150 to the plurality of interconnects 127.

[0197] Exemplary process for making a substrate including a stacked trench capacitor device

[0198] Figures 18A-18E Exemplary processes for providing or manufacturing a substrate including a stacked trench capacitor are described. In some implementations, Fig.18A –18E processes can be used to provide or manufacture Figure 4 or other substrates described in the present disclosure.

[0199] It should be noted that Figures 18A-18E The process of one or more stages can be combined to simplify and / or clarify the process for providing or manufacturing the substrate. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more of these processes can be replaced or substituted without departing from the spirit of the present disclosure. Different implementations can manufacture the substrate differently.

[0200] like Fig.18A As shown in , stage 1 illustrates a state after providing a core layer 120 including a plurality of core interconnects 121. The core layer 120 may be a core dielectric layer. The plurality of core interconnects 121 include core interconnects 121 extending through the thickness of the core layer 120a and interconnects located on a first surface and a second surface of the core layer 120. The core layer 120 and the plurality of core interconnects 121 may be manufactured using an etching process, a patterning process, a lift-off process, and / or a plating process.

[0201] Stage 2 illustrates a state after at least one cavity 1800 is formed through the core layer 120. A laser process and / or a drilling process may be used to form the at least one cavity 1800.

[0202] Stage 3 illustrates a state after coupling the core layer 120 and the plurality of core interconnects 121 to the carrier 1810 and / or tape. The carrier 1810 may include a tape.

[0203] Stage 4 illustrates a state after coupling the capacitor structure 106 to the carrier 1810 through the cavity 1800 of the core layer 120. The capacitor structure 106 may be placed through the cavity 1800 and on the carrier 1810.

[0204] Stage 5 illustrates a state after a dielectric layer 1820 is formed over the top surfaces of the capacitor structure 106, the core layer 120, and the plurality of core interconnects 121. The dielectric layer 1820 may be formed in the cavity 1800 of the core layer 120. A deposition and / or lamination process may be used to form the dielectric layer 1820. The dielectric layer 1820 may include a prepreg. The dielectric layer 1820 may include the same material as the core layer 120.

[0205] like Fig.18B , stage 6 illustrates a state after decoupling the carrier 1810 from the core layer 120, the capacitor structure 106, the dielectric layer 1820, and the plurality of core interconnects 121. For example, the carrier 1810 may be de-taped from the core layer 120, the capacitor structure 106, the dielectric layer 1820, and the plurality of core interconnects 121. A cleaning process (e.g., plasma cleaning) may be performed on the core layer 120, the dielectric layer 1820, and the capacitor structure 106 after removing the carrier 1810.

[0206] Stage 7 illustrates a state after a dielectric layer 1830 is formed over the bottom surface of the capacitor structure 106, the core layer 120a, and the plurality of core interconnects 121. A deposition and / or lamination process may be used to form the dielectric layer 1830. The dielectric layer 1830 may include a prepreg. The dielectric layer 1830 may be similar or identical to the core layer 120 and / or the dielectric layer 1820. Stage 7 illustrates that the capacitor structure 106 is surrounded (e.g., laterally surrounded) and touched by the dielectric layer 1820 and the dielectric layer 1830. The capacitor structure 106 is laterally positioned relative to the core layer 120.

[0207] Stage 8 illustrates a state after forming a plurality of cavities 1822 and a plurality of cavities 1832 in dielectric layer 124. Dielectric layer 124 may represent dielectric layer 1820 and / or dielectric layer 1830. A plurality of cavities 1822 may be formed through a first surface (e.g., top surface) of dielectric layer 124, and a plurality of cavities 1832 may be formed through a second surface (e.g., bottom surface) of dielectric layer 124. A plurality of cavities 1822 may expose interconnections from capacitor structure 106 and interconnections from among a plurality of core interconnects 121. A plurality of cavities 1832 may expose interconnections from among a plurality of core interconnects 121.

[0208] Stage 9 illustrates a state after forming a plurality of interconnects 1823 on (e.g., over) a first surface (e.g., top surface) of dielectric layer 124 and in dielectric layer 124. Some interconnects from plurality of interconnects 1823 may be located in plurality of cavities 1822. Plurality of interconnects 1823 may be coupled to plurality of core interconnects 121. Plurality of interconnects 1823 may be configured to couple to interconnects from capacitor structure 106.

[0209] Stage 9 also illustrates a state after forming a plurality of interconnects 1833 on (e.g., below) the second surface (e.g., bottom surface) of dielectric layer 124 and in dielectric layer 124. Some interconnects from the plurality of interconnects 1833 may be located in plurality of cavities 1832. The plurality of interconnects 1833 may be coupled to the plurality of core interconnects 121. A patterning process, a lift-off process, and / or a plating process may be used to form the plurality of interconnects 1823 and / or the plurality of interconnects 1833.

[0210] like Fig. 18C As shown in FIG. 1 , stage 10 illustrates a state after dielectric layer 122a is formed on (e.g., above) a first surface (e.g., top surface) of dielectric layer 124 and dielectric layer 126a is formed on (e.g., below) a second surface (e.g., bottom surface) of dielectric layer 124. A deposition process and / or a lamination process may be used to form dielectric layers 122a and 126a. Dielectric layers 122a and 126a may include prepreg (e.g., prepreg layers).

[0211] Stage 11 illustrates a state after forming a plurality of cavities 1542 in dielectric layer 122a and forming a plurality of cavities 1546 in dielectric layer 126a. An etching process (e.g., a photo-etching process) and / or a laser process (e.g., laser drilling, laser ablation) may be used to form the plurality of cavities 1542 and the plurality of cavities 1546.

[0212] Stage 12 illustrates a state after forming a plurality of interconnects 1525 over the dielectric layer 122a and the plurality of cavities 1542 and coupling them to the dielectric layer 122a and the plurality of cavities 1542. The plurality of interconnects 1525 may be coupled to the plurality of interconnects 1823. Stage 12 also illustrates a state after forming a plurality of interconnects 1527 over the dielectric layer 126a and the plurality of cavities 1546 and coupling them to the dielectric layer 126a and the plurality of cavities 1546. The plurality of interconnects 1527 may be coupled to the plurality of interconnects 1833. A patterning process, a stripping process, and / or a plating process may be used to form the plurality of interconnects 1525 and the plurality of interconnects 1527.

[0213] like Fig.18D, stage 13 illustrates a state after dielectric layer 122b is formed over the first surface of dielectric layer 122a and coupled to the first surface of dielectric layer 122a and dielectric layer 126b is formed over the second surface of dielectric layer 126a and coupled to the second surface of dielectric layer 126a. Deposition processes and / or lamination processes may be used to form dielectric layers 122b and 126b. Dielectric layers 122b and 126b may include prepreg (e.g., prepreg layers).

[0214] Stage 14 illustrates a state after forming a plurality of cavities 1544 in dielectric layer 122b and a plurality of cavities 1548 in dielectric layer 126b. An etching process and / or a laser process (eg, laser drilling, laser ablation) may be used to form the plurality of cavities 1544 and the plurality of cavities 1548.

[0215] Stage 15 illustrates a state after forming a plurality of interconnects 1545 over dielectric layer 122b and a plurality of cavities 1544 and coupling them to dielectric layer 122b and a plurality of cavities 1544. The plurality of interconnects 1545 may be coupled to the plurality of interconnects 1525. Stage 12 also illustrates a state after forming a plurality of interconnects 1547 over dielectric layer 126b and a plurality of cavities 1548 and coupling them to dielectric layer 126b and a plurality of cavities 1548. The plurality of interconnects 1547 may be coupled to the plurality of interconnects 1527. A patterning process, a stripping process, and / or a plating process may be used to form the plurality of interconnects 1545 and the plurality of interconnects 1547. Note that the plurality of interconnects 1545 and the plurality of interconnects 1547 may be formed by repeating the process described above. Fig.18D Stages 13-15 are used to form additional dielectric layers and additional interconnects.

[0216] like Fig.18E As shown in , stage 16 illustrates a state after forming solder resist layer 140 on the surface of dielectric layer 122b and solder resist layer 142 on the surface of dielectric layer 126b. Multiple interconnects 125 may represent multiple interconnects 1525, multiple interconnects 1545, and / or multiple interconnects 1823. Multiple interconnects 127 may represent multiple interconnects 1527, multiple interconnects 1547, and / or multiple interconnects 1833.

[0217] Stage 17 illustrates a state after the plurality of solder interconnects 150 are coupled to the substrate 102. A solder reflow process may be used to couple the plurality of solder interconnects 150 to the plurality of interconnects 127.

[0218] Exemplary Flowchart of a Method for Making a Substrate Stack Trench Capacitor

[0219] In some implementations, manufacturing the substrate includes several processes. Fig.19 An exemplary flow chart of a method 1900 for providing or manufacturing a substrate is illustrated. In some implementations, Fig.19The method 1900 may be used to provide or manufacture Figure 6 However, Fig.19 The method 1900 can be used to manufacture any substrate in the present disclosure.

[0220] It should be noted that Fig.19 The method 1900 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a substrate. In some implementations, the order of the processes may be changed or modified.

[0221] The method provides (at 1905) a capacitor structure (e.g., 106, 406, 506) comprising (i) a first trench capacitor device comprising a first front side and a first back side, and (ii) a second trench capacitor device comprising a second front side and a second back side. Examples of trench capacitors include trench capacitor device 200 and / or trench capacitor device 300.

[0222] The method forms (at 1910) a core layer (e.g., 120) such that the capacitor structure is positioned in the core layer, wherein the core layer includes a first surface and a second surface. An example of forming the core layer includes at least (i) Fig.15A and 15B Stages 3 to 6, (ii) Fig.16A Stages 3 to 6 of Fig.17A The following are explained and shown in stages 2 to 4 of FIG.

[0223] The method forms (at 1915) a plurality of core interconnects (e.g., 121) in a core layer (e.g., 120). Forming the plurality of core interconnects includes forming a plurality of cavities in the core layer. An etching process and / or a laser process or a drilling process may be used to form the cavities. The plurality of cavities may pass through the core layer 120.

[0224] The method forms (at 1920) at least one first dielectric layer (e.g., 122) coupled to the first surface of the core layer and forms (at 1920) at least one second dielectric layer (e.g., 126) coupled to the second surface of the core layer. Forming the first dielectric layer and the second dielectric layer may include deposition, twisting, and / or lamination processes.

[0225] The method forms (at 1925) a first plurality of interconnects (e.g., 125) in at least one first dielectric layer, and forms (at 1925) a second plurality of interconnects (e.g., 127) in at least one second dielectric layer. Forming the plurality of interconnects may include forming a plurality of cavities in the dielectric layer and forming interconnects in the plurality of cavities in the dielectric layer. A patterning process, a lift-off process, and / or a plating process may be used to form the plurality of interconnects. A laser process (e.g., laser drilling, laser ablation) may be used to form the plurality of cavities in the dielectric layer.

[0226] The method forms (at 1930) a solder resist layer (e.g., 140, 142) over at least one first dielectric layer (e.g., 122) and / or at least one second dielectric layer (e.g., 126). Deposition and / or lamination processes may be used to form the solder resist layer.

[0227] The method may couple (at 1935) a plurality of solder interconnects (eg, 150) to a substrate (eg, 102, 402). For example, a reflow solder process may be used to couple the plurality of solder interconnects 150 to the plurality of interconnects 127 of the substrate 102.

[0228] Exemplary Electronic Devices

[0229] Fig. 20 Various electronic devices that may be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-package (PoP), system-in-package (SiP), or systems-on-chip (SoC) are illustrated. For example, a mobile phone device 2002, a laptop computer device 2004, a fixed location terminal device 2006, a wearable device 2008, or a motor vehicle 2010 may include a device 2000 as described herein. The device 2000 may be, for example, any of the devices and / or integrated circuit (IC) packages described herein. Fig. 20 The devices 2002, 2004, 2006, and 2008, and the vehicle 2010 illustrated in the figure are merely exemplary. Other electronic devices can also feature the device 2000, including, but not limited to, a group of devices (e.g., electronic devices) including: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), devices enabled with a global positioning system (GPS), navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading equipment), communication devices, smart phones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0230] Figure 1-12, 13A-13F, 14A-14E, 15A-15E, 16A-16E, 17A-17E, 18A-18E, and / or 19-20. One or more of the components, processes, features, and / or functions illustrated in the embodiments of the present invention may be rearranged and / or combined into a single component, process, feature, or function, or may be implemented in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from the present disclosure. It should also be noted that the components, processes, and / or functions in the present disclosure are not limited to the components, processes, and / or functions described in the embodiments of the present invention. Figure 1-12 , 13A-13F, 14A-14E, 15A-15E, 16A-16E, 17A-17E, 18A-18E, and / or 19-20 and their corresponding descriptions are not limited to dies and / or ICs. In some implementations, Figure 1 -12, 13A-13F, 14A-14E, 15A-15E, 16A-16E, 17A-17E, 18A-18E, and / or 19-20 and their corresponding descriptions may be used to manufacture, create, provide, and / or produce devices and / or integrated devices. In some implementations, the device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC package), a wafer, a semiconductor device, a package-on-package (PoP) device, a heat sink, and / or an interposer.

[0231] Note that the drawings in this disclosure may represent actual representations and / or conceptual representations of various components, assemblies, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some instances, the drawings may not be to scale. In some instances, for clarity, not all components and / or parts are shown. In some instances, the positioning, location, size, and / or shape of the various components and / or assemblies in the drawings may be exemplary. In some implementations, the various components and / or parts in the drawings may be optional.

[0232] The wording "exemplary" is used herein to mean "serving as an example, instance, or illustration". Any implementation or aspect described herein as "exemplary" is not necessarily to be interpreted as superior or superior to other aspects of the present disclosure. Likewise, the term "aspect" does not require that all aspects of the present disclosure include the discussed features, advantages, or modes of operation. The term "coupling" is used herein to refer to a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, objects A and C can still be considered to be coupled to each other - even if they are not in direct physical contact with each other. The term "electrical coupling" may mean that two objects are directly or indirectly coupled together so that current (e.g., signal, power, ground) can be transferred between the two objects. Two electrically coupled objects may or may not have current transfer between the two objects. The use of the terms "first", "second", "third", and "fourth" (and / or anything higher than the fourth) is arbitrary. Any component described may be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component may be a first component, a second component, a third component, or a fourth component. The term "encapsulation" means that an object may partially encapsulate or completely encapsulate another object. The terms "top" and "bottom" are arbitrary. A component located at the top may be above a component located at the bottom. A top component may be considered a bottom component and vice versa. As described in the present disclosure, a first component located "above" a second component may mean that the first component is located above or below the second component, depending on how the bottom or top is arbitrarily defined. In another example, a first component may be located above (e.g., above) a first surface of a second component, and a third component may be located above (e.g., below) a second surface of the second component, wherein the second surface is opposite to the first surface. Further note that the term "above" as used in the context of a component being located above another component in this application may be used to indicate that a component is on and / or in another component (e.g., on the surface of a component or embedded in a component). Thus, for example, a first component is above a second component may mean: (1) the first component is above the second component, but not directly contacting the second component; (2) the first component is on the second component (e.g., on the surface of the second component); and / or (3) the first component is in the second component (e.g., embedded in the second component). A first component that is "in" a second component may be partially in the second component or completely in the second component. As used in this disclosure, the term "about 'value X'" or "approximately value X" means within ten percent of 'value X'. For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9-1.1.

[0233] In some implementations, interconnection is an element or component that allows or facilitates electrical connection between two points, elements and / or components in a device or package. In some implementations, interconnection may include traces, through-holes, pads, pillars, metallization layers, redistribution layers, and / or under-bump metallization (UBM) layers / interconnections. In some implementations, interconnection may include a conductive material that can be configured to provide an electrical path for a signal (e.g., a data signal), grounding, and / or power. Interconnection may include more than one element or component. Interconnection may be defined by one or more interconnections. Interconnection may include one or more metal layers. Interconnection may be part of a circuit. Different implementations may use different processes and / or procedures to form interconnection. In some implementations, chemical vapor deposition (CVD) processes, physical vapor deposition (PVD) processes, sputtering processes, spraying, and / or electroplating processes may be used to form interconnection.

[0234] It should also be noted that the various disclosures contained herein may be described as processes depicted as flow charts, flow diagrams, structure diagrams, or block diagrams. Although a flow chart may describe an operation as a sequential process, many operations may be performed in parallel or concurrently. In addition, the order of the operations may be rearranged. A process terminates when its operations are completed.

[0235] Further examples are described below to facilitate understanding of the present disclosure.

[0236] Aspect 1: A package includes a substrate and an integrated device coupled to the substrate. The substrate includes: a core layer including a first surface and a second surface, a plurality of core interconnects located in the core layer, at least one first dielectric layer coupled to the first surface of the core layer, a first plurality of interconnects located in the at least one first dielectric layer, at least one second dielectric layer coupled to the second surface of the core layer, a second plurality of interconnects located in the at least one second dielectric layer, and a capacitor structure located in the core layer. The capacitor structure includes a first trench capacitor device, the first trench capacitor device including a first front side and a first back side, and a second trench capacitor device coupled to the first trench capacitor device, wherein the second trench capacitor device includes a second front side and a second back side.

[0237] Aspect 2: The package of aspect 1, wherein the second trench capacitor device is located above the first trench capacitor device.

[0238] Aspect 3: The package of aspects 1 to 2, wherein a first backside of the first trench capacitor device is coupled to a second backside of the second trench capacitor device.

[0239] Aspect 4: The package of aspects 1 to 2, wherein the first backside of the first trench capacitor device is coupled to the second frontside of the second trench capacitor device.

[0240] Aspect 5: The package of aspects 1 to 4, wherein the second trench capacitor device is coupled to the first trench capacitor device by a plurality of solder interconnects.

[0241] Aspect 6: The package of aspects 1 to 4, wherein the second trench capacitor device is coupled to the first trench capacitor device by a copper-to-copper bond.

[0242] Aspect 7: The package of aspects 1 to 6, wherein the plurality of core interconnects includes a first core interconnect between the capacitor structure and the first surface of the core layer, and wherein the first core interconnect is coupled to the capacitor structure and the first plurality of interconnects.

[0243] Aspect 8: The package of aspect 7, wherein the plurality of core interconnects further includes a second core interconnect between the capacitor structure and the second surface of the core layer, and wherein the second core interconnect is coupled to the capacitor structure and the first plurality of interconnects.

[0244] Aspect 9: The package of aspects 1 to 6, wherein the plurality of core interconnects includes a core interconnect between the capacitor structure and the second surface of the core layer, and wherein the core interconnect is coupled to the capacitor structure and the second plurality of interconnects.

[0245] Aspect 10: The package of aspects 1 to 9, wherein the integrated device is configured to be electrically coupled to a capacitor structure in the core layer.

[0246] Aspect 11: The package of aspects 1 to 10, wherein the capacitor structure comprises three or more vertically stacked trench capacitor devices.

[0247] Aspect 12: The package of aspects 1 to 11, wherein the capacitor structure is configured to function as a decoupling capacitor and a power management integrated circuit (PMIC) output capacitor.

[0248] Aspect 13: The package of aspects 1 to 12, further comprising another capacitor structure coupled to the first surface of the substrate or the second surface of the substrate.

[0249] Aspect 14: An apparatus comprising a package. The package comprises a substrate and an integrated device coupled to the substrate. The substrate comprises: a core layer comprising a first surface and a second surface, a plurality of core interconnects located in the core layer, at least one first dielectric layer coupled to the first surface of the core layer, a first plurality of interconnects located in the at least one first dielectric layer, at least one second dielectric layer coupled to the second surface of the core layer, a second plurality of interconnects located in the at least one second dielectric layer, and means for a stacked trench capacitor located in the core layer.

[0250] Aspect 15: An apparatus as in Aspect 14, wherein the means for stacking trench capacitors comprises means for a first trench capacitor and means for a second trench capacitor coupled to the means for the first trench capacitor, wherein the means for the second trench capacitor is located above the means for the first trench capacitor.

[0251] Aspect 16: The apparatus of aspect 15, wherein the first backside of the means for the first trench capacitor is coupled to the second backside of the means for the second trench capacitor.

[0252] Aspect 17: The apparatus of aspect 15, wherein the first back surface of the means for the first trench capacitor is coupled to the second front surface of the means for the second trench capacitor.

[0253] Aspect 18: The apparatus of aspects 15 to 17, wherein the means for the second trench capacitance is coupled to the means for the first trench capacitance by a plurality of solder interconnects.

[0254] Aspect 19: The apparatus of aspects 15 to 17, wherein the means for the second trench capacitance is coupled to the means for the first trench capacitance by a copper-to-copper bond.

[0255] Aspect 20: An apparatus as in aspects 14 to 19, wherein the plurality of core interconnects includes a first core interconnect located between the means for capacitors, the means for stacked trench capacitors and the first surface of the core layer, and wherein the first core interconnect is coupled to the means for stacked trench capacitors and the first plurality of interconnects.

[0256] Aspect 21: The apparatus of aspect 20, wherein the plurality of core interconnects further comprises a second core interconnect located between the means for stacking trench capacitors and the second surface of the core layer, and wherein the second core interconnect is coupled to the means for stacking trench capacitors and the second plurality of interconnects.

[0257] Aspect 22: A device as in Aspects 14 to 21, wherein the device is selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

[0258] Aspect 23: A method for manufacturing a substrate. The method provides a capacitor structure, the capacitor structure including a first trench capacitor device and a second trench capacitor device coupled to the first trench capacitor device, the first trench capacitor device including a first front side and a first back side, wherein the second trench capacitor device includes a second front side and a second back side. The method forms a core layer so that the capacitor structure is positioned in the core layer, wherein the core layer includes a first surface and a second surface. The method forms a plurality of core interconnects in the core layer. The method forms at least one first dielectric layer coupled to the first surface of the core layer. The method forms at least one second dielectric layer coupled to the second surface of the core layer. The method forms a first plurality of interconnects in at least one first dielectric layer. The method forms a second plurality of interconnects in at least one second dielectric layer.

[0259] Aspect 24: The method of aspect 23, wherein the second trench capacitor device is located above the first trench capacitor device.

[0260] Aspect 25: The method of aspects 23 to 24, wherein a first backside of the first trench capacitor device is coupled to a second backside of the second trench capacitor device.

[0261] Aspect 26: The method of aspects 23 to 24, wherein the first backside of the first trench capacitor device is coupled to the second frontside of the second trench capacitor device.

[0262] Aspect 27: The method of aspects 23 to 26, wherein the second trench capacitor device is coupled to the first trench capacitor device by a plurality of solder interconnects.

[0263] Aspect 28: The method of aspects 23 to 26, wherein the second trench capacitor device is coupled to the first trench capacitor device by a copper-to-copper bond.

[0264] Aspect 29: The method of aspects 23 to 28, wherein the plurality of core interconnects includes a first core interconnect located between the capacitor structure and the first surface of the core layer, and wherein the first core interconnect is coupled to the capacitor structure and the first plurality of interconnects.

[0265] Aspect 30: The method of aspect 29, wherein the plurality of core interconnects further includes a second core interconnect located between the capacitor structure and the second surface of the core layer, and wherein the second core interconnect is coupled to the capacitor structure and the second plurality of interconnects.

[0266] Aspect 31: A package comprising a coreless substrate and an integrated device coupled to the coreless substrate. The coreless substrate comprises at least one dielectric layer, a plurality of interconnects in the at least one dielectric layer, and a capacitor structure in the at least one dielectric layer. The capacitor structure comprises a first trench capacitor device and a second trench capacitor device coupled to the first trench capacitor device, the first trench capacitor device comprising a first front side and a first back side, wherein the second trench capacitor device comprises a second front side and a second back side.

[0267] Aspect 32: The package of aspect 31, wherein the second trench capacitor device is located above the first trench capacitor device.

[0268] Aspect 33: The package of aspects 31 to 32, wherein a first backside of the first trench capacitor device is coupled to a second backside of the second trench capacitor device.

[0269] Aspect 34: The package of aspects 31 to 32, wherein the first backside of the first trench capacitor device is coupled to the second frontside of the second trench capacitor device.

[0270] Aspect 35: The package of aspects 31 to 34, wherein the second trench capacitor device is coupled to the first trench capacitor device by a plurality of solder interconnects.

[0271] Aspect 36: The package of aspects 31 to 34, wherein the second trench capacitor device is coupled to the first trench capacitor device by a copper-to-copper bond.

[0272] The various features of the present disclosure described herein may be implemented in different systems without departing from the present disclosure. It should be noted that the above aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of the various aspects of the present disclosure is intended to be illustrative rather than limiting the scope of the appended claims. Thus, the teachings of the present disclosure may be readily applied to other types of devices, and many substitutions, modifications, and variations will be apparent to those skilled in the art.

Claims

1. A package comprising: A substrate, comprising: a core layer comprising a first surface and a second surface; A plurality of cores in the core layer are interconnected; at least one first dielectric layer coupled to the first surface of the core layer; a first plurality of interconnects disposed in the at least one first dielectric layer; at least one second dielectric layer coupled to the second surface of the core layer; a second plurality of interconnects located in the at least one second dielectric layer; and a capacitor structure in the core layer, wherein the capacitor structure comprises: a first trench capacitor device comprising a first front side and a first back side; and a second trench capacitor device coupled to the first trench capacitor device, wherein the The second trench capacitor device includes a second front side and a second back side; and An integrated device is coupled to the substrate.

2. The package of claim 1, wherein the second trench capacitor device is located above the first trench capacitor device.

3. The package of claim 1, wherein a first backside of the first trench capacitor device is coupled to a second backside of the second trench capacitor device. 4 . The package of claim 1 , wherein a first backside of the first trench capacitor device is coupled to a second frontside of the second trench capacitor device.

5. The package of claim 1, wherein the second trench capacitor device is coupled to the first trench capacitor device by a plurality of solder interconnects.

6. The package of claim 1, wherein the second trench capacitor device is coupled to the first trench capacitor device by a copper-to-copper bond.

7. The package according to claim 1, wherein the plurality of core interconnects comprises a first core interconnect between the capacitor structure and a first surface of the core layer, and Wherein the first core interconnect is coupled to the capacitor structure and the first plurality of interconnects.

8. The package according to claim 7, wherein the plurality of core interconnects further comprises a second core interconnect between the capacitor structure and a second surface of the core layer, and Wherein the second core interconnect is coupled to the capacitor structure and the first plurality of interconnects.

9. The package according to claim 1, wherein the plurality of core interconnects includes a core interconnect between the capacitor structure and the second surface of the core layer, and Wherein the core interconnect is coupled to the capacitor structure and the second plurality of interconnects.

10. The package of claim 1, wherein the integrated device is configured to be electrically coupled to the capacitor structure in the core layer.

11. The package of claim 1 wherein the capacitor structure comprises three or more vertically stacked trench capacitor devices.

12. The package of claim 1, wherein the capacitor structure is configured to function as a decoupling capacitor and a power management integrated circuit (PMIC) output capacitor.

13. The package of claim 1, further comprising another capacitor structure coupled to the first surface of the substrate or the second surface of the substrate.

14. A device comprising: Package, including: A substrate, comprising: a core layer comprising a first surface and a second surface; A plurality of cores in the core layer are interconnected; at least one first dielectric layer coupled to the first surface of the core layer; a first plurality of interconnects disposed in the at least one first dielectric layer; at least one second dielectric layer coupled to the second surface of the core layer; a second plurality of interconnects located in the at least one second dielectric layer; and means for stacked trench capacitors in said core layer; and An integrated device is coupled to the substrate.

15. The apparatus of claim 14, wherein the means for stacking trench capacitors comprises: means for a first trench capacitor; as well as Means for a second trench capacitance coupled to the means for a first trench capacitance, wherein the means for a second trench capacitance is located above the means for a first trench capacitance.

16. The apparatus of claim 15, wherein a first backside of the means for a first trench capacitor is coupled to a second backside of the means for a second trench capacitor.

17. The apparatus of claim 15, wherein a first back surface of the means for a first trench capacitor is coupled to a second front surface of a second trench capacitor.

18. The apparatus of claim 15, wherein the means for a second trench capacitor is coupled to the means for a first trench capacitor by a plurality of solder interconnects.

19. The apparatus of claim 15, wherein the means for a second trench capacitor is coupled to the means for a first trench capacitor by a copper-to-copper bond.

20. The apparatus of claim 14, wherein the plurality of core interconnects comprises a first core interconnect between the means for capacitor, the means for stacked trench capacitor and the first surface of the core layer, and Wherein the first core interconnect is coupled to the means for stacking trench capacitors and the first plurality of interconnects.

21. The device according to claim 20, wherein the plurality of core interconnects further comprises a second core interconnect located between the means for stacking trench capacitors and the second surface of the core layer, and Wherein the second core interconnect is coupled to the means for stacked trench capacitors and the second plurality of interconnects.

22. The device of claim 14, wherein the device is selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

23. A method for manufacturing a substrate, comprising: A capacitor structure is provided, the capacitor structure comprising: a first trench capacitor device comprising a first front side and a first back side; and a second trench capacitor device coupled to the first trench capacitor device, wherein the second trench capacitor device includes a second front side and a second back side; forming a core layer such that the capacitor structure is positioned in the core layer, wherein the core layer includes a first surface and a second surface; forming a plurality of core interconnects in the core layer; forming at least one first dielectric layer coupled to the first surface of the core layer; forming at least one second dielectric layer coupled to the second surface of the core layer; forming a first plurality of interconnects in the at least one first dielectric layer; and A second plurality of interconnects are formed in the at least one second dielectric layer.

24. The method of claim 23, wherein the second trench capacitor device is located above the first trench capacitor device.

25. The method of claim 23, wherein a first backside of the first trench capacitor device is coupled to a second backside of the second trench capacitor device.

26. The method of claim 23, wherein a first backside of the first trench capacitor device is coupled to a second frontside of the second trench capacitor device.

27. The method of claim 23, wherein the second trench capacitor device is coupled to the first trench capacitor device by a plurality of solder interconnects.

28. The method of claim 23, wherein the second trench capacitor device is coupled to the first trench capacitor device by a copper-to-copper bond.

29. The method of claim 23, wherein the plurality of core interconnects includes a first core interconnect located between the capacitor structure and the first surface of the core layer, and Wherein the first core interconnect is coupled to the capacitor structure and the first plurality of interconnects.

30. The method of claim 29, wherein the plurality of core interconnects further comprises a second core interconnect located between the capacitor structure and the second surface of the core layer, and Wherein the second core interconnect is coupled to the capacitor structure and the second plurality of interconnects.

31. A package comprising: A coreless substrate, comprising: at least one dielectric layer; a plurality of interconnects disposed in the at least one dielectric layer; a capacitor structure in the at least one dielectric layer, wherein the capacitor structure comprises: a first trench capacitor device comprising a first front side and a first back side; and a second trench capacitor device coupled to the first trench capacitor device, wherein the The second trench capacitor device includes a second front side and a second back side; and An integrated device is coupled to the coreless substrate.

32. The package of claim 31 wherein the second trench capacitor device is located above the first trench capacitor device.

33. The package of claim 31 wherein a first backside of the first trench capacitor device is coupled to a second backside of the second trench capacitor device.

34. The package of claim 31, wherein a first backside of the first trench capacitor device is coupled to a second frontside of the second trench capacitor device.

35. The package of claim 31, wherein the second trench capacitor device is coupled to the first trench capacitor device by a plurality of solder interconnects.

36. The package of claim 31 wherein the second trench capacitor device is coupled to the first trench capacitor device by a copper-to-copper bond.

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