Method, device, medium and product for processing tasks to be performed in a servo system

Abstract

The present invention relates to a method, device, medium and product for processing tasks to be executed in a servo system. The method is executed by a multi-core processor, and the multi-core processor includes multiple cores sharing a shared memory space. The method includes obtaining tasks to be executed in the servo system, and the tasks to be executed include multiple subtasks. The method also includes allocating multiple subtasks to multiple cores based on the real-time properties of the multiple subtasks and / or the task amounts corresponding to the multiple subtasks. In addition, the method also includes that when a first core among the multiple cores obtains access rights to the shared memory space, the first core executes the corresponding first subtask and stores the determined first subtask data in the shared memory space of the multi-core processor. In this way, the parallel processing capability of the multi-core processor can be used to efficiently execute various tasks in the servo system, thereby improving the execution efficiency of the tasks.

Description

Technical Field

[0001] The present invention relates to the field of industrial control, and more particularly, to a method, a device, a medium and a product for processing a task to be performed in a servo system. Background Art

[0002] A servo system is generally a feedback control system used to accurately follow or reproduce a process. For example, a servo system is an automatic control system that enables the output controlled quantities such as the position, orientation, and state of an object to follow any changes in the input target (or given value). In the field of automated control, the servo control method can directly determine the motion accuracy and effect of the equipment. So how to accurately and efficiently perform servo control tasks becomes the key.

[0003] Traditional methods for processing servo system tasks mainly include using a single-core architecture consisting of a microprocessor or a dedicated chip to perform servo system tasks. For complex control tasks and higher precision working conditions, more costs and resources need to be invested in a single-core architecture to complete complex control tasks.

[0004] In summary, the traditional methods for processing servo system tasks have the following shortcomings: the scope of application is relatively limited, not only a large amount of cost and resources are consumed, but also the task execution efficiency is not high. Summary of the invention

[0005] The embodiment of the present invention proposes a method for processing tasks to be executed in a servo system, which can utilize the parallel processing capability of a multi-core processor to efficiently execute various tasks in the servo system, thereby improving the execution efficiency of the tasks.

[0006] In a first aspect of the present invention, a method for processing tasks to be executed in a servo system is provided. The method is performed by a multi-core processor, and the multi-core processor includes multiple cores sharing a shared memory space. The method includes obtaining the tasks to be executed in the servo system, and the tasks to be executed include multiple subtasks. The method also includes allocating the multiple subtasks to the multiple cores based on the real-time properties of the multiple subtasks and / or the task amounts corresponding to the multiple subtasks. In addition, the method also includes, when a first core among the multiple cores obtains access rights to the shared memory space, the first core executes the corresponding first subtask and stores the determined first subtask data in the shared memory space of the multi-core processor.

[0007] In a second aspect of the present invention, a computing device is provided. The computing device includes one or more processors; and a storage device for storing one or more programs, when the one or more programs are executed by the one or more processors, the one or more processors implement the method provided according to the first aspect of the present invention.

[0008] In a third aspect of the present invention, a multi-core processor is provided, the multi-core processor is used to implement the method provided according to the first aspect of the present invention, the multi-core processor comprises a plurality of cores, a spin lock and a shared memory space, wherein: a core among the plurality of cores is connected to the shared memory space via a communication bus. The spin lock is used to control the plurality of cores to access the shared memory space within a preset time period. The plurality of cores are connected to the corresponding plurality of memory spaces via the communication bus.

[0009] In a fourth aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer-executable instructions, wherein the computer-executable instructions are executed by a processor to implement the method provided according to the first aspect of the present invention.

[0010] According to a fifth aspect of the present invention, there is provided a computer program product, comprising machine executable instructions, which, when executed, enable a machine to perform the method provided by the first aspect of the present invention.

[0011] It should be understood that the contents described in the summary of the invention are not intended to limit the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other features, advantages and aspects of the embodiments of the present invention will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements, wherein:

[0013] Figure 1 A schematic diagram illustrating an example environment in which various embodiments of the present invention may be implemented;

[0014] Figure 2 A system architecture diagram of a multi-core processor according to some embodiments of the present invention is shown;

[0015] Figure 3 A flow chart of a method 300 for processing a task to be performed in a servo system according to some embodiments of the present invention is shown;

[0016] Figure 4 A schematic diagram showing parallel processing of servo dual closed-loop control tasks according to some embodiments of the present invention is shown;

[0017] Figure 5 A schematic diagram showing multi-core parallel processing tasks according to some embodiments of the present invention is shown;

[0018] Figure 6 A block diagram showing an apparatus for a method of processing a task to be performed in a servo system according to some embodiments of the present invention; and

[0019] Figure 7 A block diagram is shown of a device in which various embodiments of the present invention may be implemented. DETAILED DESCRIPTION

[0020] Embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be construed as being limited to the embodiments described herein, which are instead provided for a more thorough and complete understanding of the present invention. It should be understood that the drawings and embodiments of the present invention are only for exemplary purposes and are not intended to limit the scope of protection of the present invention.

[0021] In the description of the embodiments of the present invention, the term "including" and similar terms should be understood as open inclusion, that is, "including but not limited to". The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc. may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0022] As mentioned above, in the field of automation control, the servo system control task can be performed using a microprocessor + FPGA. However, the microprocessor or FPGA usually exchanges data through the SPI interface. Limited by the SPI communication rate, it cannot really save resources, reduce costs, and perform efficient multi-core parallel computing. Moreover, the hardware complexity and cost have not been significantly improved, and the computing pressure is still concentrated on a single processor.

[0023] To this end, an embodiment of the present invention proposes a method for processing tasks to be executed in a servo system. The method is executed by a multi-core processor, and the multi-core processor includes multiple cores sharing a shared memory space. The method includes obtaining tasks to be executed in the servo system, and the tasks to be executed include multiple subtasks. The method also includes allocating multiple subtasks to multiple cores based on the real-time nature of the multiple subtasks and / or the task amounts corresponding to the multiple subtasks. In addition, the method also includes, when a first core among the multiple cores obtains access rights to the shared memory space, the first core executes the corresponding first subtask and stores the determined first subtask data in the shared memory space of the multi-core processor.

[0024] In this way, the tasks to be executed are divided into multiple subtasks, and the parallel processing capabilities of multi-core processors can be used to efficiently execute various tasks in the servo system, thereby significantly improving the overall performance of the system. At the same time, through reasonable shared memory management and synchronization mechanisms, the integrity and consistency of data can be ensured, and the security and reliability of data interaction between cores can be guaranteed.

[0025] Figure 1 1 is a schematic diagram of an example environment 100 in which various embodiments of the present invention may be implemented. Figure 1 As shown, in the environment 100, there are tasks to be executed 102 and a multi-core processor 106. The task to be executed 102 includes multiple subtasks 104, such as subtask 104-1, subtask 104-2 and subtask 104-3. The multi-core processor 106 may include multiple cores (such as core 108, core 110 and core 112), and shared memory space 114 connected to the multiple cores. It should be noted that the number of cores in the multi-core processor 106 can be set according to actual conditions, for example, it can be 4, 5, 6, etc.

[0026] In some embodiments, the number of cores may be determined based on the number of subtasks 104. Figure 1 As shown, when the number of subtasks 104 is 3, the number of cores can be set to 3. In other embodiments, the number of subtasks 104 can also be an integer multiple of the number of cores. For example, when the number of subtasks 104 is 9, the number of cores can be 3, and each subtask 104 can be assigned to the task queue of the corresponding core, for example, subtask 1, subtask 2, and subtask 3 are assigned to core 1, and core 1 executes the three subtasks in sequence.

[0027] In some embodiments of the present invention, the task to be executed 102 can be an independent, executable code unit. The task to be executed can have a clear goal or function, and the goal can be completed or the function can be realized by executing the code unit, such as processing data, performing calculations, etc. The execution of the task can be a part of the program code operation. It can be understood that in order to improve the execution efficiency of the task to be executed 102 and improve the utilization rate of the kernel resources, the task to be executed 102 can be split into multiple subtasks 104, which are run in parallel by multiple kernels to execute the multiple subtasks 104.

[0028] In some embodiments of the present invention, in order to avoid conflicts caused by multiple cores writing or reading data in the shared memory space 114 at the same time, affecting the integrity and consistency of the data, the access rights of the shared memory space 114 can be opened to different cores at different times. For example, a spin lock can be used to ensure that only one core can access the shared memory space 114 at the same time. For example, when a core occupies the spin lock, if another core wants to access the shared memory space 114, it will first try to acquire the mutex lock. If the spin lock is already held by another core, the current core will wait until the lock is released.

[0029] In this way, the tasks to be executed are divided into multiple subtasks, and the parallel processing capabilities of multi-core processors can be used to efficiently execute various tasks in the servo system, thereby significantly improving the overall performance of the system. At the same time, through reasonable shared memory management and synchronization mechanisms, the integrity and consistency of data can be ensured, and the security and reliability of data interaction between cores can be guaranteed.

[0030] Figure 2 FIG. 1 shows a system architecture diagram of a multi-core processor according to some embodiments of the present invention. Figure 2 As shown, the multi-core processor 200 may include multiple cores such as CPU1, CPU2, CPU3 and CPU4. Each core can independently execute different subtasks, such as CPU1 can be used to execute subtask 1, CPU2 can be used to execute subtask 2, CPU3 can be used to execute subtask 3, and CPU4 can be used to execute subtask 4.

[0031] In some embodiments, the multi-core processor 200 can allocate different storage spaces for different cores. For example, the local memory space corresponding to CPU1 can be memory M1, the local memory space corresponding to CPU2 can be memory M2, the local memory space corresponding to CPU3 can be memory M3, and the local memory space corresponding to CPU4 can be memory M4. These local memories can be used to store temporary data generated by each core when executing a subtask. In order to ensure the consistency and integrity of the task, the multi-core processor 200 can provide a shared shared memory M0 for multiple cores. Multiple cores can access the shared memory M0 in different time periods to achieve data interaction and sharing. For example, CPU1 can read data from the shared memory M0 (the read data can be data written to the shared memory M0 by other CPUs), and can also write data to the shared memory M0.

[0032] like Figure 2As shown, the role of the spin lock is to ensure that each CPU can access and write data in the shared memory M0 at the correct time. For example, CPU1 can acquire the spin lock, and when the spin lock is not occupied, the CPU1 can successfully acquire the spin lock. While holding the spin lock, CPU1 can normally execute subtask 1 and write the subtask data determined by executing subtask 1 into the shared memory M0, or access the shared memory M0 to read the required data during the execution of subtask 1. When other cores try to acquire the spin lock, they will find that the lock is occupied, so other cores can wait or spin (that is, keep trying to acquire the lock) until the spin lock is released by CPU1.

[0033] In other embodiments, CPU1 can also normally execute subtask 1 and write the subtask data determined by executing subtask 1 into local memory M1 without obtaining the spin lock. When CPU1 obtains the spin lock, the subtask data stored in local memory M1 can be written into shared memory M0, thereby achieving data synchronization and sharing, and ensuring data consistency and integrity.

[0034] It can be understood that a multi-core processor system can achieve efficient parallel processing and data consistency management by allocating local memory to each core and providing shared memory, as well as using synchronization mechanisms such as spin locks. This architecture enables a multi-core processor system to process multiple subtasks simultaneously and share data securely between different cores.

[0035] Figure 3 FIG. 3 is a flow chart showing a method 300 for processing a task to be performed in a servo system according to some embodiments of the present invention. The method 300 may be performed by Figure 1 The multi-core processor 106 shown in Figure 2 The multi-core processor 200 shown executes. Figure 3 As shown, in box 302, method 300 may include obtaining a task to be performed in a servo system, wherein the task to be performed includes a plurality of subtasks. The servo system may be an automatic control system that utilizes the action of a certain component (such as a control rod) to make the state of the system reach or approach a predetermined value, and can compare the desired state (desired value) with the actual state (actual value), and adjust the control component according to their difference. The servo system may include a controller, a power amplifier, an actuator, and a detection device (such as a position detector and a speed detector). The servo system involves a variety of control tasks, such as servo dual closed-loop control tasks, servo motion control tasks (such as motion trajectory planning), etc. The dual closed loops in the servo dual closed-loop control may be a position loop and a speed loop.

[0036] In some embodiments of the present invention, the task to be performed refers to a group of operations or actions that need to be performed by the servo system. The task to be performed can be composed of program codes for guiding the operation of the servo system. In some embodiments, the task to be performed can be split into multiple subtasks according to the execution requirements of the task and the actual application scenario, so that the operation of the servo system can be controlled more finely. For example, the multiple independent steps or stages contained in the task to be performed can be split into multiple subtasks. In one example, when the task to be performed of the servo system is a task to control the movement of a mechanical arm, the task can be split into a speed control subtask and a position control subtask. Among them, the speed control subtask can be to control the movement speed of the mechanical arm through a speed loop during the movement of the mechanical arm. The position control subtask can be to control the movement trajectory of the mechanical arm through an unknown loop during the movement of the mechanical arm.

[0037] In box 304, method 300 may include allocating multiple subtasks to multiple cores based on the real-time performance of multiple subtasks and / or the task volume corresponding to the multiple subtasks. It is understood that the multiple cores in the multi-core processor may be the same or different. In some embodiments, the resource utilization of the multiple cores, the corresponding local memory space, and the processing performance of the cores may be different. The execution requirements of multiple tasks are also different, for example, subtask 1 and subtask 2 have different requirements for real-time performance. Or the amount of data generated by subtask 1 and subtask 2 during execution is also different. On this basis, the subtasks can be reasonably allocated to different cores according to the real-time performance or task volume of the subtasks. For example, in the case where the task volume of the subtask is large (the amount of data generated during execution is large), the subtask can be allocated to the core with a larger memory space. In some embodiments, tasks can be dynamically allocated to the most suitable core according to the current state of the multi-core processor and the actual needs of the task.

[0038] In block 306, method 300 may include, in the case where a first kernel among multiple kernels obtains access rights to the shared memory space, executing the corresponding first subtask by the first kernel and storing the determined first subtask data in the shared memory space of the multi-core processor. It is understood that the shared memory space allows data to be shared between different kernels. When the first kernel needs to access the shared memory space to perform a specific subtask and store related data, it is necessary to effectively control its access rights to the shared memory space to prevent data conflicts, data corruption, or data inconsistency. Among them, there may be multiple ways to control access rights, for example, different kernels may be controlled to access the shared memory space at different times by using a spin lock. Among them, a spin lock (e.g., a mutex) may be a synchronization mechanism for controlling multiple kernels to access a shared resource (e.g., a shared memory space). Its main function is to ensure that at any time, only one kernel can access the shared memory space, thereby avoiding data competition and inconsistency problems.

[0039] In some embodiments of the present invention, the control method of access rights can be determined according to the type of subtask. For example, the type of subtask is different, and there are differences in determining the spin lock that needs to be acquired. In one example, the subtask can be a task to read data, and the spin lock is a write data lock; the subtask can be a task to read data, and the spin lock is a read data lock. In other embodiments, the control method of access rights can also be atomic operations, semaphores, etc.

[0040] In this way, the tasks to be executed are divided into multiple subtasks, and the parallel processing capabilities of multi-core processors can be used to efficiently execute various tasks in the servo system, thereby significantly improving the overall performance of the system. At the same time, through reasonable shared memory management and synchronization mechanisms, the integrity and consistency of data can be ensured, and the security and reliability of data interaction between cores can be guaranteed.

[0041] As you can understand, a read-write lock such as a read data lock allows multiple cores to read shared resources at the same time, but write operations are mutually exclusive. In this way, when the first core needs to write to the shared memory, it can obtain a write data lock, which will prevent all other cores from reading or writing to the shared memory. When the first core only needs to read the shared memory space, it can obtain a read data lock, which allows other cores to read at the same time, but prevents writing.

[0042] In some embodiments of the present invention, different types of tasks or different degrees of parallel splitting of tasks may result in different ways of splitting tasks and different numbers of splitting. For example, if the data dependency between data elements in a task is strong, the degree of parallel splitting of the task is low, and the number of splits of the task to be executed will be small. In some embodiments, the dependency between subtasks or the degree of task association between subtasks may also affect the order in which the kernel executes tasks, such as the order in which the kernel acquires spin locks. For example, the execution order of subtasks may be determined based on the dependency between subtasks. In one example, during the execution of subtask 1, it is necessary to assist the kernel in executing subtask 1 based on the data of subtask 2. Then, kernel 2 may first execute subtask 2 and write the corresponding data into the shared memory space. In this way, kernel 1 may read the required data by accessing the shared memory space, thereby smoothly executing subtask 1.

[0043] In some embodiments, in order to improve the efficiency and accuracy of task splitting, different splitting methods or splitting numbers can be preset for different types of tasks. The type of task can be determined based on factors such as the complexity, urgency, and scale of the task. Taking complexity as an example, for tasks with a higher complexity (e.g., greater than a preset complexity), a larger number of splits (e.g., greater than a preset number threshold) can be set to decompose the task into easier-to-execute subtasks and reduce the difficulty of kernel execution; and for tasks with a lower complexity (e.g., less than a preset complexity), a smaller number of splits (e.g., less than a preset number threshold) can be set to reduce the time and resource consumption during task splitting. Alternatively, for tasks with a low degree of urgency, the task can be split into multiple smaller subtasks, which are processed by multiple kernels to improve the processing efficiency of the task to be executed. On this basis, in some embodiments, the preset splitting method and the preset number of splits can be determined based on the similarity between the task to be executed and multiple preset types of tasks.

[0044] In this way, the task splitting method can be flexibly selected according to the task type, thereby improving the flexibility and execution efficiency of each core in processing tasks.

[0045] In some embodiments, a multi-core processor can allocate memory spaces of different sizes to different cores. The amount of data, processing complexity, and expected execution time required for different subtasks are different. For example, the memory size required when the program code corresponding to a subtask is executed is different. When the execution time of a task is long and the data to be processed is large, the corresponding task volume is also large. On this basis, for cores with sufficient memory space and low current load, subtasks with larger task volumes can be allocated to them first. For example, 100M of memory space can be allocated to core 1, 200M of memory space can be allocated to core 2, and 300M of memory space can be allocated to core 3. For example, when the data processing volume corresponding to subtask 1 is 240M, subtask 1 can be allocated to core 3, and core 3 executes subtask 1. In other words, the task volume corresponding to the subtask is proportional to the size of the kernel's memory space. The larger the task volume corresponding to the subtask, the larger the memory required, and the larger the memory space corresponding to the kernel used to execute the subtask should be.

[0046] It is understandable that as the system environment and task requirements change, the memory space corresponding to the core or the task volume corresponding to the task may be constantly changing. Therefore, it is necessary to flexibly adjust the size of the memory space allocated to different cores by the multi-core processor or flexibly adjust the task allocation strategy.

[0047] In this way, the computing resources and storage resources of the multi-core processor can be reasonably utilized, and on the other hand, the overall performance of the multi-core processor and the efficiency of the multi-core processor in executing tasks to be executed can be improved.

[0048] In some embodiments, different subtasks have different requirements for real-time performance. For example, subtask 1 has a high real-time performance requirement (for example, higher than a preset delay threshold), and needs to efficiently execute subtask 1 in a shorter time; while subtask 2 has a low real-time performance requirement (for example, lower than a preset delay threshold), and does not have specific requirements for the completion time of the task. In addition, the processing performance (processing speed, delay, throughput) corresponding to different cores may also be different, for example, the processing efficiency of core 1 is greater than the processing efficiency of core 2. On this basis, different subtasks can be assigned to different cores according to the real-time performance requirements of the subtasks. For example, for subtasks such as batch data processing and log recording that do not have specific requirements for completion time, they can be assigned to a core with sufficient memory space but low processing efficiency, and the subtask will be executed by the core. For subtasks such as sensor data processing in the control system and communication data packet processing that have high real-time requirements, they can be assigned to cores with high processing efficiency, which have faster processing speeds, lower delays, and higher data throughput.

[0049] In some embodiments, in order to more accurately allocate subtasks, a variety of factors may be considered to determine the priority of the subtasks. For example, the priority of the subtask may be determined based on the task volume and real-time performance of the subtask. For example, the priorities of multiple subtasks may be determined based on the task volume, the weight value corresponding to the task volume, the real-time performance, and the weight value corresponding to the real-time performance. The weight value corresponding to the task volume may be used to characterize the importance of the task volume. The weight value may be a specific numerical value such as 0.9, or a weight level such as primary, advanced, and the like. Similarly, the weight value corresponding to the real-time performance may be used to characterize the importance of the real-time performance.

[0050] In some embodiments, in order to determine the allocation result of the subtask more quickly and directly, the priority of the kernel can also be determined in combination with multiple factors. For example, the priority of the kernel can be determined according to the weights and values ​​of the remaining memory space, read and write speed, and communication bandwidth of the kernel. Among them, the kernel priority is used to indicate the processing capacity and processing efficiency of the kernel. The higher the priority, the more remaining memory space of the kernel or the faster the read and write speed. After determining the priority of the kernel and the priority of the subtask, subtasks of different priorities can be assigned to kernels of different priorities. For example, in one example, the priority of subtask 1 is 1, the priority of subtask 2 is 5, and the priority of subtask 3 is 8. Subtask 3 has the highest priority and subtask 1 has the lowest priority. The priority of kernel 1 is 4, the priority of kernel 2 is 6, and the priority of kernel 3 is 2. The priority of kernel 2 is the highest and the priority of kernel 3 is the lowest. In this way, subtask 1 can be assigned to kernel 3, and kernel 3 executes subtask 1. Subtask 3 is assigned to kernel 2, and kernel 2 executes subtask 3. Subtask 2 is assigned to kernel 1, and kernel 1 executes subtask 2.

[0051] In this way, by comprehensively considering various factors, the processing efficiency of the tasks to be executed can be maximized while ensuring the utilization of computing resources.

[0052] It can be understood that if a high-priority subtask has a hardware failure in the core executing the subtask for some reason, such as a hardware failure in the core executing the subtask, the subtask can be migrated to a core with a lower priority level for execution. If a low-priority subtask occupies too many resources and affects the overall performance of the system, it can be suspended or migrated to another core with lower processing efficiency for execution. In other words, the execution or allocation process of subtasks is dynamic and can be continuously adjusted according to actual conditions, thereby improving the execution flexibility and reliability of the tasks to be executed.

[0053] In some embodiments, in order to better determine the execution state of the kernel and provide a reliable basis for whether to release the spin lock later, a state identifier can be assigned to the subtask to track the execution state of the task (such as to be executed, executing, completed, etc.). For example, different numbers can be used to represent the execution state of the subtask. In one example, the number 1 can be used to represent that the subtask is in a to-be-executed state, the number 2 can be used to represent that the subtask is in an executing state, and the number 3 can be used to represent that the subtask is in a completed state.

[0054] In some embodiments of the present invention, when the number of subtasks obtained by splitting is greater than the number of cores, a core can execute multiple subtasks. On this basis, in order to improve the execution efficiency and flexibility of tasks, the task queue of the core can be sorted according to the priority of the subtasks to ensure that high-priority tasks can be executed first. For example, the next task to be executed by the core can be determined based on the execution status and priority of the subtasks in the task queue. In one example, the task queue of core A is subtask m (executed, priority 9), subtask n (to be executed, priority 5), and subtask i (to be executed, priority 7), and it can be determined that the next subtask to be executed by core A can be subtask i.

[0055] In this way, high-priority tasks can be prioritized, so that critical or urgent needs can be responded to more quickly, improving the overall system processing speed. At the same time, arranging tasks according to task status can avoid wasting system resources, ensure that resources are used effectively, and further optimize resource allocation.

[0056] In some embodiments of the present invention, the kernel needs to obtain access rights to the shared memory space before executing the corresponding subtask. For example, the kernel can access the shared memory space by acquiring a spin lock. For example, after acquiring the spin lock, CPU1 can read the data in the shared memory space or write the data determined by the execution task into the shared memory space. The kernel can release the spin lock after executing the subtask.

[0057] It can be understood that in order to improve the efficiency of parallel processing and the efficiency of task completion, if the spin lock is occupied or in a non-idle state, the kernel can first execute the subtask and store the data determined in the execution task in the local memory space corresponding to the kernel. For example, without acquiring the spin lock, CPU1 can first execute subtask 1 and cache the data in the execution process to the local memory space allocated to it by the multi-core processor. The local memory space only opens access rights such as read permission or write permission to CPU1. It can be understood that the spin lock can be applied all the time during the execution of the subtask by CPU1, or the spin lock can be applied after the subtask is executed. After CPU1 acquires the spin lock, the data cached in the local memory space can be stored in the shared memory space.

[0058] Figure 4 FIG. 2 shows a schematic diagram of parallel processing of servo dual closed-loop control tasks according to some embodiments of the present invention. Figure 4 As shown, the task to be executed may be a dual closed-loop control task of a servo system. The task to be executed may be divided into four subtasks, which are processed by four different cores in a multi-core processor, respectively. The four cores may be CPU1, CPU2, CPU3, and CPU4.

[0059] like Figure 4 As shown, in step 1, when the spin lock is in an idle state or unoccupied state, the CPU4 of the multi-core processor can obtain the spin lock and execute the corresponding subtask. For example, CPU4 can read the dq voltage set value and the motor angle value stored in the shared memory space. After reading the corresponding data, CPU4 can release the spin lock so that other cores can obtain the permission to access the shared memory space. CPU4 can use the space vector pulse width modulation (SVPWM) contained therein to determine the pulse width modulation (PWM) duty cycle based on the dq voltage set value and the motor angle value. Among them, the PWM duty cycle refers to the ratio of the high level time in the pulse wave to the total cycle. The PWM duty cycle can control the analog signal to determine the amount of energy flowing to the load and the output power size.

[0060] like Figure 4 As shown, in step 2, CPU3 can acquire the spin lock and execute the corresponding subtask after CPU4 releases the spin lock. For example, CPU3 reads the q-axis current given value i stored in the shared memory space. qref And the motor angle value. It can be understood that CPU3 can also obtain the three-phase current of the peripheral and perform Clark-Park transformation, so as to calculate the feedback current value of the dq axis and the q axis voltage given value u qref CPU3 determines the feedback current value and the q-axis voltage given value u qrefAfter that, it can be written into the data area of ​​the shared memory space, and the spin lock is automatically released after the writing is completed.

[0061] In some embodiments, in step 3, CPU2 may acquire a spin lock and read the d-axis feedback current i by accessing the shared memory space. dfdb Based on the d-axis feedback current i dfdb The d-axis voltage given value u can be calculated dref CPU2 can set the d-axis voltage to a given value u dref Write to the data area of ​​the shared memory space, and the spin lock is automatically released after writing. In step 4, CPU1 can acquire the spin lock and execute the corresponding subtask after the spin lock is released. For example, CPU1 can read the q-axis feedback current i by accessing the shared memory space. qfdb In some embodiments, CPU1 can also obtain the motor speed and angle of the peripheral device to perform PI calculation. After the calculation is completed, the q-axis current can be given as i qref The motor angle value is written into the data area of ​​the shared memory space. After writing is completed, the spin lock is automatically released. By looping steps 1 to 4, the servo double closed-loop control task can be completed.

[0062] It should be noted that the present invention does not limit the number of splits of the task to be executed. In actual application, other numbers of concurrent cores can be selected according to different requirements. How to divide the task to be executed into multiple subtasks is not specifically limited here, and can be determined according to specific circumstances.

[0063] In this way, the dual closed-loop control task of the servo system can be split into multiple subtasks, so that the parallel computing capability of the multi-core processor can be fully utilized, making the execution of the task more efficient and more reliable.

[0064] Figure 5 FIG. 4 is a schematic diagram showing a multi-core parallel processing task according to some embodiments of the present invention. Figure 5 As shown, CPU1, CPU2, CPU3 and CPU4 can process multiple subtasks respectively and write corresponding data into the shared memory space or read corresponding data from the shared memory space. For the specific process, please refer to Figure 4 The processing process of each kernel in the present invention will not be repeated here.

[0065] like Figure 5As shown, the time for CPU to calculate using PI controller is generally 0.65μs, the time for CPU to perform Clark-Park is generally 2.35μs, the time for CPU1 to calculate using load observer is generally 1.2μs, and the time for CPU4 to calculate PWM duty cycle using SVPWM is generally 1μs. In addition, the time consumed by different cores each time they occupy spin locks, release spin locks, read a byte from shared memory space, or write a byte can be considered as Nns. On this basis, the time required for using a multi-core processor to process multiple subtasks in parallel can be (5.2+0.022N)μs. The time required for a single core to execute tasks serially in the related art is generally 0.65*3+2.35+1.2+1=6.5μs. In other words, compared with the method of single-core serial execution of tasks, the method of splitting tasks and having multi-core processors execute multiple subtasks in parallel can greatly improve processing efficiency.

[0066] In some embodiments of the present invention, when the chip main frequency is 240Mhz, the occupation-release read-write time is one clock beat, and N can be 4.17. Then the parallel time is 5.2+0.022*4.17=5.29174μs, and the serial time is 6.5μs. On this basis, splitting the task and executing multiple subtasks in parallel by a multi-core processor can improve the processing efficiency by (6.5-5.29174) / 6.5=18.59%.

[0067] In addition, in some embodiments, the calculation speed of Clark-Park can be improved when there is a trigonometric function hardware acceleration unit. If the accelerated time is 0.5 μs, the time required for serial calculation of a single-core CPU is: 0.65*3+0.5+1.2+1=4.65 μs, and the parallel calculation time is: 3.5+0.017*4.17=3.57 μs, and the percentage improvement compared to the serial time is: (4.65-3.57) / 4.65=23.2%. In other words, the efficiency of multi-core processors can be greatly improved when processing the control tasks of the servo system in parallel.

[0068] Figure 6 FIG. 6 is a block diagram of an apparatus 600 for processing a task to be performed in a servo system according to some embodiments of the present invention. Figure 6As shown, the device 600 includes a to-be-executed task acquisition unit 602, which is configured to acquire the to-be-executed tasks in the servo system, and the to-be-executed tasks include multiple subtasks. The device 600 also includes a subtask allocation unit 604, which is configured to allocate the multiple subtasks to the multiple cores based on the real-time nature of the multiple subtasks and / or the task amounts corresponding to the multiple subtasks. The device 600 also includes a subtask execution unit 606, which is configured to execute the corresponding first subtask by the first core among the multiple cores and store the determined first subtask data in the shared memory space of the multi-core processor when the first core among the multiple cores obtains the access right to the shared memory space.

[0069] In some embodiments of the present invention, the subtask allocation unit 604 is also configured to: allocate multiple subtasks to multiple cores based on the size of the memory space and the task volume corresponding to the multiple subtasks, and the size of the memory space corresponding to the core is positively correlated with the task volume of the subtasks allocated to the core.

[0070] In some embodiments of the present invention, the subtask allocation unit 604 is further configured to allocate the multiple subtasks to the multiple cores based on the comparison result between the real-time requirements corresponding to the multiple subtasks and the preset latency threshold.

[0071] In some embodiments of the present invention, the apparatus 600 further includes a subtask splitting unit configured to determine a plurality of subtasks by splitting the task to be executed based on the type of the task to be executed and the degree of parallel splitting of the task to be executed.

[0072] In some embodiments of the present invention, the subtask allocation unit 604 is further configured to allocate the multiple subtasks to the multiple cores based on the task association degree between the multiple subtasks.

[0073] In some embodiments of the present invention, the subtask execution unit 606 is also configured as: a first kernel among multiple kernels applies for access rights to a shared memory space from a spin lock of a multi-core processor; when it is determined that the spin lock is in an idle state, access rights are opened to the first kernel; and when the first kernel obtains access rights, the first kernel executes the corresponding first subtask and writes the first subtask data to the shared memory space or reads the corresponding data from the shared memory space.

[0074] In some embodiments of the present invention, the subtask execution unit 606 is also configured to: when the first kernel does not obtain access rights, the first kernel executes the first subtask and writes the first subtask data into the first memory space corresponding to the first kernel; and when the first kernel obtains access rights, the first kernel writes the data in the first memory space into the shared memory space.

[0075] In some embodiments of the present invention, the subtask execution unit 606 is also configured to: determine a dependency relationship between a first subtask and a plurality of subtasks; in response to a dependency relationship between the first subtask and a second subtask among the plurality of subtasks, obtain second subtask data from the shared memory space by the first kernel while obtaining access rights to the shared memory space, the second subtask data being determined based on when the second kernel executes the second subtask; and execute the first subtask by the first kernel based on the second subtask data and store the determined first task subdata to the shared memory space.

[0076] In some embodiments of the present invention, the apparatus 600 further includes: when the second kernel obtains access rights to the shared memory space, the second kernel stores the second subtask data determined by executing the second subtask in the shared memory space and releases the access rights to the spin lock.

[0077] It can be understood that by using the device 600 of the present invention, at least one of the advantages that can be achieved by the method or process described above can be achieved.

[0078] Figure 7 Schematic block diagram of an example device 700 that can be used to implement embodiments of the present invention is shown. Figure 7 As shown, device 700 includes a computing unit (i.e., CPU 701), which can perform various appropriate actions and processes according to computer program instructions stored in a read-only memory (i.e., ROM 702) or loaded from a storage unit 708 into a random access memory (i.e., RAM 703). In RAM 703, various programs and data required for the operation of device 700 can also be stored. CPU 701, ROM 702, and RAM 703 are connected to each other via a bus 704. An input / output interface (i.e., I / O interface 705) is also connected to bus 704.

[0079] A number of components in the device 700 are connected to the I / O interface 705, including: an input unit 706, such as a keyboard, a mouse, etc.; an output unit 707, such as various types of displays, speakers, etc.; a storage unit 708, such as a disk, an optical disk, etc.; and a communication unit 709, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 709 allows the device 700 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0080] CPU 701 can be various general and / or special processing components with processing and computing capabilities. Some examples of CPU 701 include, but are not limited to, central processing units (CPUs), graphics processing units (GPUs), various special artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 701 performs the various methods and processes described above, such as method 300. For example, in some embodiments, method 300 may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 708. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 700 via ROM 702 and / or communication unit 707. When the computer program is loaded into RAM 703 and executed by CPU 701, one or more steps of method 300 described above may be performed. Alternatively, in other embodiments, CPU 701 may be configured to execute method 300 in any other appropriate manner (e.g., by means of firmware).

[0081] The functions described above herein may be performed at least in part by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chip systems (SOCs), load programmable logic devices (CPLDs), and the like.

[0082] The program code for implementing the method of the present invention can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code can be executed entirely on the machine, partially on the machine, partially on the machine as a stand-alone software package and partially on a remote machine, or entirely on a remote machine or server.

[0083] In the context of the present invention, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In addition, although each operation is depicted in a specific order, this should be understood as requiring such operations to be performed in the specific order shown or in a sequential order, or requiring that all illustrated operations should be performed to obtain the desired result. In certain environments, multitasking and parallel processing may be advantageous. Similarly, although several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of the present invention. Certain features described in the context of a separate embodiment may also be implemented in a single implementation in combination. On the contrary, the various features described in the context of a single implementation may also be implemented in multiple implementations individually or in any suitable sub-combination.

[0084] Although the subject matter has been described in language specific to structural features and / or methodological logical actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. On the contrary, the specific features and actions described above are merely example forms of implementing the claims.

Claims

1. A method for processing a task to be performed in a servo system, characterized in that: The method is performed by a multi-core processor, wherein the multi-core processor includes a plurality of cores sharing a shared memory space, including: Acquire a task to be executed in the servo system, wherein the task to be executed includes a plurality of subtasks; Allocating the multiple subtasks to the multiple cores based on the real-time performance of the multiple subtasks and / or the task amounts corresponding to the multiple subtasks; and When a first core among the multiple cores obtains access rights to the shared memory space, the first core executes the corresponding first subtask and stores the determined first subtask data in the shared memory space of the multi-core processor.

2. The method according to claim 1, characterized in that The multi-core processor allocates corresponding memory space to the multiple cores, and allocating the multiple subtasks to the multiple cores includes: Based on the size of the memory space and the task amounts corresponding to the multiple subtasks, the multiple subtasks are allocated to the multiple cores, and the size of the memory space corresponding to the core is positively correlated with the task amount of the subtasks allocated to the core.

3. The method according to claim 1, characterized in that: Allocating the plurality of subtasks to the plurality of cores comprises: Based on the comparison result between the real-time requirements corresponding to the multiple subtasks and the preset latency threshold, the multiple subtasks are allocated to the multiple cores.

4. The method according to claim 1, characterized in that: Also includes: The plurality of subtasks are determined by splitting the task to be executed based on the type of the task to be executed and the degree of parallel splitting of the task to be executed.

5. The method according to claim 1, characterized in that Allocating the plurality of subtasks to the plurality of cores comprises: The plurality of subtasks are allocated to the plurality of cores based on the task correlation degree between the plurality of subtasks.

6. The method according to claim 1, characterized in that The first core executing the corresponding first subtask and storing the determined first subtask data in the shared memory space of the multi-core processor includes: Applying, by a first core among the multiple cores, for access rights to the shared memory space from a spin lock of the multi-core processor; If it is determined that the spin lock is in an idle state, granting access rights to the first kernel; and When the first kernel obtains the access permission, the first kernel executes the corresponding first subtask and writes the first subtask data into the shared memory space or reads the corresponding data from the shared memory space.

7. The method according to claim 6, characterized in that The first core executing the corresponding first subtask and storing the determined first subtask data in the shared memory space of the multi-core processor includes: In a case where the first core does not obtain the access permission, the first core executes the first subtask and writes the first subtask data into a first memory space corresponding to the first core; and When the first kernel obtains the access permission, the first kernel writes the data in the first memory space into the shared memory space.

8. The method according to claim 6, wherein the first core executes the corresponding first subtask and stores the determined first subtask data in the shared memory space of the multi-core processor, comprising: Determining a dependency relationship between the first subtask and the plurality of subtasks; In response to a dependency relationship between the first subtask and a second subtask among the plurality of subtasks, the first kernel acquires second subtask data from the shared memory space when obtaining access rights to the shared memory space, wherein the second subtask data is determined based on when the second kernel executes the second subtask; as well as The first kernel executes the first subtask based on the second subtask data and stores the determined first task subdata in the shared memory space.

9. The method according to claim 8, further comprising: When the second kernel obtains the access right to the shared memory space, the second kernel stores the second subtask data determined by executing the second subtask in the shared memory space and releases the access right to the spin lock.

10. A multi-core processor, the multi-core processor being used to implement the method according to any one of claims 1 to 9, the multi-core processor comprising a plurality of cores, a spin lock and a shared memory space, wherein: A core among the plurality of cores is connected to the shared memory space via a communication bus; The spin lock is used to control the multiple cores to access the shared memory space within a preset time period; as well as The multiple cores are connected to the corresponding multiple memory spaces through the communication bus.

11. A computing device, characterized in that: include: at least one processor; as well as A memory coupled to the at least one processor and having instructions stored thereon, the instructions, when executed by the at least one processor, causing the apparatus to perform the method according to any one of claims 1-9.

12. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a machine, the method according to any one of claims 1 to 9 is performed.

13. A computer program product, characterized in that The invention comprises machine executable instructions which, when executed, cause a machine to perform the method according to any one of claims 1 to 10.

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