Processor, configuration method for processor and electronic device

Abstract

The embodiment of the invention provides a processor, a configuration method for the processor and an electronic device. The processor includes a plurality of processor cores, where the plurality of processor cores are configured in a plurality of regions; and a control unit configured to control the processor to operate in a first operation mode or a second operation mode among the plurality of operation modes, and, in response to the processor operating in the first operation mode, the plurality of regions each execute an independent processing task, and the plurality of regions implement communication isolation and power supply isolation from each other, and the plurality of regions each execute a second operation mode. In response to the processor operating in the second mode of operation, the plurality of regions cooperatively perform a common processing task, and the plurality of regions implement power isolation and dissociate communication isolation from each other. The processor can be switched between different operation modes, so that high-performance computing services and cloud computing services with reduced explosion radii can be respectively provided in the different modes.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a processor, a configuration method for the processor, and an electronic device including the processor. Background Art

[0002] Cloud computing refers to a system with extremely high computing power formed through computer networks (such as the Internet). Cloud computing can store and aggregate related resources and can be configured on demand to provide personalized services to users. Cloud computing is the result of the hybrid evolution and leap of computer technologies such as distributed computing, utility computing, load balancing, parallel computing, network storage, hot backup redundancy and virtualization.

[0003] In the cloud computing application scenario of processors, with the development of cloud computing technology, more and more information services are transferred to the cloud. Through cloud computing, the utilization rate of hardware facilities such as processors can be greatly improved. In cloud computing, tenants can use cloud services on the cloud computing platform to meet their needs by renting cloud resources. The other side of the improvement of hardware utilization is that multiple tenants share the same hardware equipment. When the hardware equipment fails, the services of multiple tenants will be affected at the same time. For example, in the process of cloud computing, the cloud computing system may be affected due to the failure of the central processing unit (CPU) or other hardware. The range of cloud computing systems affected by the failure of CPU or other hardware can be called the explosion radius. With the advancement of chip technology and design, the number of cores, storage subsystems and input / output (IO) subsystems integrated in a single CPU continues to increase, which can support the needs of more and more tenants. In the cloud, the explosion radius needs to be reduced as much as possible.

[0004] However, with the advancement of chip technology and design, the number of cores, storage subsystems, and IO subsystems integrated in a single processor continues to increase, which also brings the problem of increasing explosion radius to the processor. Summary of the invention

[0005] According to at least one embodiment of the present disclosure, a processor is provided, which includes: multiple processor cores, wherein the multiple processor cores are configured in multiple regions; a control unit, configured to control the processor to operate in a first operating mode or a second operating mode among multiple operating modes, and, in response to the processor operating in the first operating mode, the multiple regions each perform an independent processing task, and the multiple regions achieve communication isolation and power supply isolation from each other, and, in response to the processor operating in the second operating mode, the multiple regions collaboratively perform common processing tasks, and the multiple regions achieve the power supply isolation and release the communication isolation from each other.

[0006] For example, in the processor according to an embodiment of the present disclosure, in response to the processor operating in the first operation mode, the plurality of regions are each powered by an independent power supply and each performs a reset operation via an independent power state signal and a reset signal.

[0007] For example, in the processor according to an embodiment of the present disclosure, each of the multiple areas includes an input / output subsystem, a storage subsystem, and a portion of the multiple processor cores.

[0008] For example, in a processor according to an embodiment of the present disclosure, each of the multiple regions includes a connection switch, and each region includes multiple core particles, wherein the connection switch includes a first connection switch and a second connection switch, the first connection switch is configured to perform intra-region communication and the second connection switch is configured to perform cross-region communication.

[0009] For example, in the processor according to an embodiment of the present disclosure, the intra-region communication includes communication between chiplets located in the same region.

[0010] For example, in the processor according to an embodiment of the present disclosure, the cross-region communication includes communication between chiplets located in different regions.

[0011] For example, in the processor according to an embodiment of the present disclosure, the second connection switch is configured to achieve the communication isolation by disabling cross-region communication.

[0012] For example, in the processor according to an embodiment of the present disclosure, in response to the processor operating in the second operation mode, the plurality of regions are powered by a common power supply and are reset by a common power state signal and a reset signal.

[0013] For example, in the processor according to an embodiment of the present disclosure, the second connection switch is configured to release the communication isolation by enabling cross-region communication.

[0014] For example, in the processor according to an embodiment of the present disclosure, in response to the processor operating in the second operation mode, the multiple areas jointly perform one or more of a connection or disconnection operation with a power supply, a reset operation, and an initialization operation.

[0015] For example, in the processor according to an embodiment of the present disclosure, in response to the processor operating in the first operation mode, the multiple areas independently perform one or more of connection or disconnection operations with the power supply, reset operations, and initialization operations.

[0016] For example, in the processor according to an embodiment of the present disclosure, the connection switch is configured to be implemented through chiplet-to-chiplet communication.

[0017] For example, in a processor according to an embodiment of the present disclosure, the control unit includes a system control unit configured in each of the multiple areas, and the system control unit includes: a configuration register configured to store configuration information of the corresponding area, the configuration information including configuration information indicating one of multiple operating modes, wherein the processor will operate in the one operating mode; a clock generation module configured to generate a clock signal for the components included in the corresponding area based on the configuration information and a reference clock signal; a reset generation module configured to generate a reset signal for the components included in the corresponding area based on the configuration information, a power status signal and a reset signal; and a process management module configured to perform power management functions, reset management functions, configuration initialization management functions and continuous system management functions.

[0018] For example, in the processor according to an embodiment of the present disclosure, the power management function includes monitoring and managing the power supply and power failure of the power supply during the reset operation of the processor; the reset management function includes controlling the orderly release of the reset operation of the components included in the corresponding area; the configuration initialization management function includes performing initialization configuration on the components according to the configuration information after the orderly release of the reset operation of the components included in the corresponding area; the continuous system management function includes performing power consumption monitoring and temperature monitoring on the processor during the operation of the processor.

[0019] For example, in the processor according to an embodiment of the present disclosure, in response to the processor operating in the first operating mode, the system control unit included in each of the multiple areas is enabled, and in response to the processor operating in the second operating mode, the system control unit included in one of the multiple areas is enabled, and the system control units included in the remaining areas of the multiple areas are disabled.

[0020] For example, in a processor according to an embodiment of the present disclosure, the processor is configured to operate in one of the multiple operating modes based on one or more of configuration information stored in a configuration register, a general-purpose input / output port, and a one-time programmable memory identifier.

[0021] For example, in the processor according to the embodiment of the present disclosure, the processor is implemented by a system on chip or a chiplet group.

[0022] According to at least one embodiment of the present disclosure, an electronic device is provided, and the electronic device includes the processor of any one of the above embodiments.

[0023] According to at least one embodiment of the present disclosure, a configuration method for a processor is provided, the configuration method comprising: configuring multiple processor cores of the processor in multiple regions; operating the processor in a first operating mode or a second operating mode among multiple operating modes, wherein, in the first operating mode, the multiple regions are used to each perform an independent processing task, and the multiple regions are communicationally isolated and power-isolated from each other, and in the second operating mode, the multiple regions are used to collaboratively perform a common processing task, and the multiple regions are power-isolated from each other and communication isolation is released. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description in conjunction with the accompanying drawings, in which:

[0025] Figure 1 is a schematic diagram of a processor;

[0026] Figure 2 It is a schematic diagram of cold reset and warm reset;

[0027] Figure 3 is a schematic diagram of a processor according to at least one embodiment of the present disclosure;

[0028] Figure 4 is another schematic diagram of a processor according to at least one embodiment of the present disclosure;

[0029] Figure 5A is a schematic diagram of a system control unit according to at least one embodiment of the present disclosure;

[0030] Figure 5B is a schematic diagram of a process management module according to at least one embodiment of the present disclosure;

[0031] Figure 6 is a schematic diagram of an implementation of a processor according to at least one embodiment of the present disclosure;

[0032] Fig. 7Ais a schematic diagram of a processor operating in a first operation mode according to at least one embodiment of the present disclosure;

[0033] Figure 7B is a schematic diagram of a processor operating in a second operation mode according to at least one embodiment of the present disclosure;

[0034] Figure 8 is a configuration method for a processor according to at least one embodiment of the present disclosure; and

[0035] Fig. 9 An electronic device including a processor according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] Before proceeding to the following detailed description, it may be advantageous to set forth the definitions of certain words and phrases used throughout this disclosure. The terms "include" and "comprises" and their derivatives mean including but not limited to. The term "or" is inclusive, meaning and / or. The phrase "associated with..." and its derivatives mean including, included within, interconnected, contained, contained within, connected or connected with, coupled or coupled with, communicated with, coordinated, interwoven, parallel, close, bound or bound with, having, having attributes, having a relationship or having a relationship with, etc. The term "controller" refers to any device, system, or part thereof that controls at least one operation. Such a controller may be implemented with hardware, or a combination of hardware and software and / or firmware. The functions associated with any particular controller may be centralized or distributed, whether local or remote. The phrase "at least one", when used with a list of items, means that different combinations of one or more of the listed items may be used, and only one item in the list may be required. For example, “at least one of A, B, and C” includes any one of the following combinations: A, B, C, A and B, A and C, B and C, A, B, and C.

[0037] Definitions for other specific words and phrases are provided throughout this disclosure. Those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior and future uses of such defined words and phrases.

[0038] The various embodiments of the principles of the present disclosure described below in conjunction with the accompanying drawings are only for illustration, and should not be interpreted as limiting the scope of the present disclosure in any way. It will be appreciated by those skilled in the art that the principles of the present disclosure can be implemented in any appropriately arranged system or device. In some cases, the actions described in the specification can be performed in different orders, and the desired results can still be achieved. In addition, the process depicted in the accompanying drawings does not necessarily require the specific order shown or the sequential order to achieve the desired results. In a specific embodiment, multitasking and parallel processing may be advantageous.

[0039] Figure 1 A schematic diagram of a processor.

[0040] Figure 1 A processor, such as a CPU chip, is shown. Figure 1 As shown, the processor includes multiple processor cores, one or more storage subsystems, one or more IO subsystems and a bus. Figure 1 In the processor shown, the processor core, the storage subsystem and the IO subsystem can be interconnected through a bus. The processor core can generally include multiple levels of cache (e.g., Level 1 data cache (L1D$), Level 1 instruction cache (L1I$), Level 2 cache (L2$), Level 3 cache (L3$), etc.) to improve computing performance. For example, cache consistency can be achieved between multiple processor cores through a bus.

[0041] A processor core may also be referred to as a computing core, a core, or a kernel. A processor core may be an important component of a processor. All computing operations, receiving / storing command operations, and processing data operations performed by a processor may be performed by a processor core.

[0042] The processor's memory can be used to store the calculation data in the processor and the data exchanged with the external memory such as the hard disk. The storage subsystem can include a storage controller and a corresponding physical layer (PHY). The physical layer (PHY) can realize the long-distance propagation of signals on the physical medium. The storage subsystem can be used to access external storage particles. Generally, in order to increase the system storage capacity and memory access bandwidth, multiple storage subsystems can be integrated into the processor.

[0043] The IO subsystem can be used to implement management and access control of external devices. The IO subsystem may include an IO controller, a corresponding physical coding sublayer (PCS), and a corresponding physical layer (PHY). The physical coding sublayer may be located between the physical layer (PHY) and the media access control (MAC) sublayer, and is responsible for encoding and decoding data for transmission on the physical layer. The physical layer (PHY) enables long-distance propagation of signals on physical media. The IO subsystem can generally implement general IO protocols such as PCIe, USB, and SATA. Multiple IO subsystems are generally configured in the processor according to the requirements for IO types and bandwidth.

[0044] like Figure 1As shown, in normal use, the bus can achieve cache consistency between multiple processor cores and can achieve a global unified physical address for storage and IO access. The entire processor can be used as a complete system. When a processor fails, such as a hardware failure, the processor can be reset. Reset can reset the processor to the default state. Reset can include cold reset and hot reset.

[0045] Figure 2 Figure 2 is a schematic diagram of cold reset and warm reset.

[0046] like Figure 2 As shown, during the cold reset process, the processor can first enable the reset signal (for example, lower the reset signal to a low level), and then complete the power-off process of the power supply. After a predetermined delay, the power supply can be powered on. After the power supply is stable, the reset signal is released (for example, the reset signal is raised to a high level), and the processor initialization begins; during the hot reset process, the processor can enable the reset signal (for example, lower the reset signal to a low level), release the reset signal after a predetermined delay (for example, raise the reset signal to a high level), and start the processor initialization, while the power supply always remains in the powered-on state.

[0047] exist Figure 1 In the processor shown in , the hardware in the entire processor must be powered on or off at the same time, or a unified reset signal is used to perform a cold reset or a warm reset at the same time. When a problem occurs in the processor hardware, all virtual machine systems running on the processor will be affected. Therefore, Figure 1 The processor shown in has a larger blast radius.

[0048] At least one embodiment of the present disclosure provides a processor, which includes: multiple processor cores and a control unit, wherein the multiple processor cores are configured in multiple regions; the control unit is configured to control the processor to operate in a first operating mode or a second operating mode among multiple operating modes, and, in response to the processor operating in the first operating mode, the multiple regions each perform an independent processing task, and the multiple regions achieve communication isolation and power supply isolation from each other, and, in response to the processor operating in the second operating mode, the multiple regions collaboratively perform common processing tasks, and the multiple regions achieve power supply isolation and release communication isolation from each other.

[0049] The processor according to the embodiment of the present disclosure can solve or alleviate the problem of increasing explosion radius in cloud computing.

[0050] According to at least one embodiment of the present disclosure, the processor can switch between different operating modes. For example, the processor according to the present disclosure can operate in a first operating mode corresponding to a high-performance mode to provide high-performance computing services. In addition, the processor according to the present disclosure can operate in a second operating mode corresponding to a cloud computing mode to provide cloud computing services. When the processor operates in the cloud computing mode, since the multiple regions each perform independent processing tasks, and the multiple regions are isolated from each other in communication and power supply, the processor has a reduced blast radius, thereby reducing cloud computing costs.

[0051] Figure 3 is a schematic diagram of a processor according to at least one embodiment of the present disclosure.

[0052] Figure 3 The processor 1000 is shown, and the processor 1000 may be a central processing unit, a graphics processing unit, a digital signal processing unit, an artificial intelligence processing unit, etc. Figure 3 As shown, processor 1000 includes multiple processor cores, for example, processor cores 1111-1113, processor cores 1121-1123, ..., processor cores 11N1-11N3. Each processor core in the multiple processor cores can independently execute program code and process different tasks or threads at the same time. Multiple processor cores can improve the parallel processing capability of the processor, so that the computer can perform multiple tasks or more complex calculations more quickly. Each processor core in the multiple processor cores can execute instructions, including but not limited to arithmetic logic instructions (such as addition, subtraction, multiplication, division, and, or, non, XOR, etc.), data transfer instructions (such as load, store, input, output, etc.), control flow instructions (such as, unconditional jump, subroutine call and return, etc.), string processing instructions (such as comparison, movement, search string, etc.), floating point operation instructions (such as arithmetic operations for floating point numbers, such as addition, subtraction, multiplication, division, square root, etc.), privileged instructions (such as tasks for operating system level, such as interrupt control, virtual memory management, etc.), etc. The embodiments of the present disclosure do not impose any restrictions on the instruction set applicable to the processor core (such as the x86 instruction set, the ARM instruction set, and the RISC-V instruction set), and do not impose any restrictions on the adopted microarchitecture and its composition.

[0053] The processor 1000 may be divided into a plurality of regions, for example, region 1, region 2, . . . , region N.

[0054] The processor 1000 includes a plurality of processor cores that can be configured in a plurality of regions. For example, the processor cores 1111-1113 can be configured in region 1, the processor cores 1121-1123 can be configured in region 2, ..., the processor cores 11N1-11N3 can be configured in region N. Although Figure 3 In the example, three processor cores are configured in each of the multiple regions, but those skilled in the art will appreciate that such a configuration is merely exemplary, and more or fewer processor cores may be configured in each region depending on usage requirements.

[0055] Physical isolation can be achieved between the multiple regions into which the processor 1000 is divided. Physical isolation may include power supply isolation and communication isolation. For example, a cross-power design may be provided at the boundary of each region to achieve power supply isolation. For example, the multiple processor cores included in the processor 1000 may be interconnected through interconnection structures such as a bus (e.g., bus protocols such as Advanced Extensible Interface (AXI), Advanced Microcontroller Bus Architecture (AMBA)), a cross switch, a ring network, a mesh network, an on-chip network, etc. The interconnection structure may be provided with a connection switch at the cross-region. Such a connection switch can realize two states of connection and disconnection of the interconnection structure across regions.

[0056] In response to the connection of the cross-region connection switch, all processor cores of processor 1000 can be communicatively connected, thereby achieving cache consistency between multiple processor cores, and a global unified physical address for storage and IO access can be achieved; in response to the disconnection of the cross-region connection switch, all processor cores of processor 1000 can be communicatively disconnected at the cross-region, and each region can operate as an independent system.

[0057] The processor 1000 may include a control unit 1200. Figure 3 The control unit 1200 is shown as a whole, but in at least one embodiment, the control unit 1200 may be distributed in the processor 1000. For example, the control unit 1200 may include a system control unit (refer to Figure 4 and Figure 5A-Figure 5B Detailed description), for example, can be implemented by hard wiring, microprogram, state machine or programmable logic. The processor 1000 can have multiple operation modes. The control unit 1200 can be configured to control the processor 1000 to operate in one of the multiple operation modes.

[0058] For example, the control unit 1200 may control the processor 1000 to operate in a first operation mode corresponding to a cloud computing mode. In response to the processor 1000 operating in the first operation mode, the multiple regions may each perform independent processing tasks, and the multiple regions may achieve communication isolation and power supply isolation from each other.

[0059] For example, the control unit 1200 may control the processor 1000 to operate in a second operating mode corresponding to a high performance computing mode. In response to the processor 1000 operating in the second operating mode, multiple regions may collaborate to perform common processing tasks, and multiple regions may isolate power supplies from each other and release communication isolation. Depending on usage requirements, more or fewer regions may be connected or disconnected, so the processor 1000 may have more operating modes, which will not be described in detail here.

[0060] Figure 4 is another schematic diagram of a processor according to at least one embodiment of the present disclosure.

[0061] like Figure 4 As shown, processor 1000 includes multiple processor cores, for example, processor cores 1111-1113, processor cores 1121-1123, ..., processor cores 11N1-11N3. Processor 1000 can be divided into multiple regions, for example, region 1, region 2, ..., region N.

[0062] Processor 1000 includes storage subsystems 1310, 1320, ..., 13N0. Processor 1000 may include IO subsystems 1410, 1420, ..., 14N0. Storage subsystems 1310, 1320, ..., 13N0 may include a storage controller and a corresponding physical layer. Storage subsystems 1310, 1320, ..., 13N0 may be used to access external storage particles. IO subsystems 1410, 1420, ..., 14N0 may be used to manage and access control external devices. IO subsystems 1410, 1420, ..., 14N0 may include an IO controller and a corresponding physical layer.

[0063] like Figure 4 As shown, each of the regions 1-N may include 3 processor cores, 1 storage subsystem, and 1 IO subsystem. Those skilled in the art will appreciate that such a configuration is merely exemplary, and each region may be configured with more or fewer processor cores, more storage subsystems, and more IO subsystems depending on usage requirements.

[0064] like Figure 4As shown, each of the regions 1-N may have an independent power supply (e.g., power supply 1-power supply N) for power supply, a reset signal (e.g., reset signals 1-N), a mode selection signal (e.g., mode selection signals 1-N), and a system management logic (e.g., implemented by system control units 1210-12N0).

[0065] The system control unit 1210-12N0 can perform power management, reset management, configuration initialization and continuous system management operations on the corresponding processor core, the corresponding storage subsystem, the IO subsystem and other hardware structures based on the system management logic. Figure 5A and Figure 5B The system control units 1210 - 12N0 are described in detail.

[0066] When the processor 1000 adopts the first operation mode, each area of ​​the processor 1000 can use multiple independent power supplies from the computer motherboard to independently power each area. The reset signal of each area can be independently provided by the computer motherboard, and the system management unit of each area is enabled and can manage the power-on and power-off process management, reset process management, state initialization and continuous system management work of each area.

[0067] For example, the system control unit 1210-12N0 of each area in area 1-N can be enabled. That is, the system control units 1210-12N0 of areas 1-N can each be responsible for operations such as power management, reset management, configuration initialization, and continuous system management of multiple areas of the processor 1000. Multiple areas can independently perform one or more of connection or disconnection operations with the power supply, reset operations, and initialization operations. For example, multiple system control units 1210-12N0 can each perform a reset operation through independent power status signals and reset signals. The connection switches of the interconnect structure in each area are set to a disconnected state. Since power supply isolation and communication isolation have been achieved across areas, each of the multiple areas of the processor 1000 can operate as an independent system, thereby providing cloud computing services with a reduced blast radius. The specific operation process of the processor 1000 in the first mode will be referred to below. Fig. 7A Specific description.

[0068] When the processor 1000 adopts the second operation mode, each area of ​​the processor 1000 can use a common power supply from the motherboard of the computer to power each area. The reset signals 1-N of each area of ​​the processor 1000 can also be provided by the motherboard of the computer. When the processor 1000 operates in the second operation mode, only the system control unit of one area of ​​the multiple areas can be enabled, and the system control units of other areas can be disabled.

[0069] For example, only the system control unit 1210 of area 1 may be enabled, and the system control units 1220-12N0 of areas 2-N may be disabled. That is, the system control unit 1210 of area 1 may be responsible for operations such as power management, reset management, configuration initialization, and continuous system management of multiple areas of the processor 1000. Multiple areas may jointly perform one or more of connection or disconnection operations with the power supply, reset operations, and initialization operations. For example, the system control unit 1210 may use a common power status signal and a reset signal to reset multiple areas of the processor 1000 as a whole. The connection switches of the interconnect structure in each area are set to a connected state, and multiple areas of the processor 1000 may operate as a whole, thereby providing high-performance computing services. The specific operation process of the processor 1000 in the second mode will be referred to below. Figure 7B Specific description.

[0070] Figure 5A is a schematic diagram of a system control unit according to at least one embodiment of the present disclosure.

[0071] like Figure 5A As shown, in this embodiment, the system control unit 5000 includes a reset generation module 5100 , a clock generation module 5200 , a configuration register 5300 , and a process management module 5400 . Figure 5A The system control unit 5000 shown in FIG. 1000 may be one of the system control units 1220 - 12N0 . The system control unit 5000 may be configured in each of the plurality of regions 1 -N of the processor 1000 .

[0072] The reset generation module 5100 may receive a power state signal 5010 and a reset signal 5020 corresponding to a region from the main board. The reset generation module 5100 may be configured to generate a reset signal for components included in the corresponding region based on the configuration information stored in the configuration register 5300, the power state signal 5010, and the reset signal 5020. For example, the reset generation module 5100 releases the reset signal for the components inside the corresponding region only after the power state is valid and the reset signal is released.

[0073] The clock generation module 5200 may receive a reference clock signal 5030 corresponding to a region from the main board. The clock generation module 5200 may be configured to generate a clock signal for components included in a corresponding region based on configuration information stored in the configuration register 5300 and the reference clock signal.

[0074] The configuration register 5300 may receive configuration information 5040 corresponding to the region from the mainboard. The configuration register 5300 may be configured to store configuration information of the corresponding region. The processor may implement corresponding functions according to the configuration information, and may modify the configuration information through the configuration interface. The configuration information may include information indicating the operating mode in which the processor is to operate. For example, the configuration information may indicate one of multiple operating modes. In addition, the processor may operate in one of multiple operating modes based on one or more of the general-purpose input / output ports (GPIO) and one-time programmable memory (eFuse) identifiers. That is, the processor may select from multiple operating modes through GPIO, configuration registers, or eFuse identifiers.

[0075] The process management module 5400 can be configured to perform power management functions, reset management functions, configuration initialization management functions, and continuous system management functions. For example, the process management module 5400 can control the power on and off operations, reset operations, initialization configuration operations, and continuous system management operations of the power supply. Figure 5B The process management module 5400 is further described.

[0076] Figure 5B is a schematic diagram of a process management module 5400 according to at least one embodiment of the present disclosure.

[0077] like Figure 5B As shown, in this embodiment, the process management module 5400 can perform power management function 5410, reset management function 5420, configuration initialization management function 5430, and continuous system management function 5440. Those skilled in the art can understand that the process management module 5400 can include corresponding submodules to perform the above functions.

[0078] The power management function 5410 may include monitoring and managing the power on and off of the power supply during the reset operation of the processor. For example, the power management function 5410 may perform power on and off monitoring and management of the power supply during the cold reset process, thereby ensuring that all module components in the corresponding area are in a closed state during the power on and off process of the power supply.

[0079] The reset management function 5420 may include controlling the orderly release of reset operations of components included in the corresponding area. For example, upon receiving an external reset signal (e.g., Figure 4 After the reset signal 1-N in the control area is released, the reset of the components inside the corresponding area is released in an orderly manner.

[0080] Configuration initialization management function 5430 may include performing initialization configuration on components according to configuration information after orderly release of reset operations of components included in the corresponding area. Continuous system management function 5440 may include performing power consumption monitoring and temperature monitoring and other monitoring operations on the processor during processor operation.

[0081] Figure 6 is a schematic diagram of an implementation of a processor according to at least one embodiment of the present disclosure.

[0082] Figure 6 The processor 6000 is shown, and the processor 6000 may be implemented by a system on chip (System on Chip, SOC) or a chiplet group (chiplet), for example, may be implemented by 2D, 2.5D or 3D packaging, etc. Figure 6 As shown, the processor 6000 may be divided into area 1 and area 2. Those skilled in the art may appreciate that the number of divided areas is exemplary and not limiting.

[0083] Area 1 may receive corresponding reset signal 1 and power state signal 1. Area 1 may be configured with an IO subsystem, a storage subsystem, a processor core, a system control unit, and a connection switch. For example, the IO subsystem may include IO subsystems 1-1 to IO subsystems 1-4, the storage subsystem may include storage subsystems 1-1 to storage subsystems 1-4, the processor core may include processor cores 1-1 to processor cores 1-8, the system control unit may include system control unit 1, and the connection switch may include connection switch 1-1 to connection switch 1-8. Connection switches 1-1 to connection switches 1-6 among connection switches 1-1 to connection switches 1-8 may be referred to as first connection switches, and connection switches 1-7 to connection switches 1-8 among connection switches 1-1 to connection switches 1-8 may be referred to as second connection switches.

[0084] Area 2 may receive corresponding reset signal 2 and power state signal 2. Area 2 may be configured with an IO subsystem, a storage subsystem, a processor core, a system control unit, and a connection switch. For example, the IO subsystem may include IO subsystems 2-1 to IO subsystems 2-4, the storage subsystem may include storage subsystems 2-1 to storage subsystems 2-4, the processor core may include processor cores 2-1 to processor cores 2-8, the system control unit may include system control unit 2, and the connection switch may include connection switch 2-1 to connection switch 2-8. Connection switches 2-1 to connection switches 2-6 among connection switches 2-1 to connection switches 2-8 may be referred to as first connection switches, and connection switches 2-7 to connection switches 2-8 among connection switches 2-1 to connection switches 2-8 may be referred to as second connection switches.

[0085] The processor 6000 may include multiple cores, for example, an IO core 1-1, computing cores 1-1 to computing cores 1-2 located in area 1, and an IO core 2-1, computing cores 2-1 to computing cores 2-2 located in area 2. The system control unit 1 may be arranged in the IO core 1-1, and the system control unit 2 may be arranged in the IO core 2-1. As described above, the system control unit may manage processes such as power on and off, reset, initialization configuration, and continuous system management of the corresponding area. Those skilled in the art may understand that the configuration method of the cores and the configuration location of the system control unit are exemplary. For example, there may be more cores, such as a storage core for setting a storage subsystem, but the disclosure is not limited thereto. For example, the system control unit may be configured in a computing core instead of an IO core, but the disclosure is not limited thereto.

[0086] The various components in the core (e.g., IO subsystem, storage subsystem, connection switch, processor core, etc.) can be interconnected through an internal interconnect structure. The connection switch can be used as the connection switch described above. The connection switch can be implemented through core-to-core (Die-to-Die, D2D) communication.

[0087] The first connection switch in the connection switch can perform intra-region communication. Intra-region communication can be performed within the region. According to an embodiment of the present disclosure, intra-region communication may include communication between core particles located in the same region. For example, for region 1, intra-region communication can be performed between connection switch 1-1 and connection switch 1-3, between connection switch 1-2 and connection switch 1-4, and between connection switch 1-5 and connection switch 1-6. For example, for region 2, intra-region communication can be performed between connection switch 2-1 and connection switch 2-3, between connection switch 2-2 and connection switch 2-4, and between connection switch 2-5 and connection switch 2-6.

[0088] In addition, the second connection switch in the connection switch can perform cross-region communication. According to an embodiment of the present disclosure, cross-region communication may include communication between core particles located in different regions. For example, cross-region communication can be performed between connection switch 1-7 and connection switch 2-7, and between connection switch 1-8 and connection switch 2-8. The connection switch can be configured to achieve communication isolation by disabling cross-region communication. For example, by disabling the second connection switch, thereby disabling cross-region communication between connection switch 1-7 and connection switch 2-7, and between connection switch 1-8 and connection switch 2-8, communication isolation between region 1 and region 2 can be achieved. In this way, region 1 and region 2 can each be operated as an independent system to reduce the blast radius. The connection switch can be configured to release communication isolation by enabling cross-region communication. For example, by enabling the second connection switch, thereby enabling cross-region communication between connection switch 1-7 and connection switch 2-7, and between connection switch 1-8 and connection switch 2-8, communication isolation between region 1 and region 2 can be released. In this way, region 1 and region 2 can be operated as a whole to provide high-performance computing services.

[0089] Fig. 7A is a schematic diagram of a processor operating in a first operation mode according to at least one embodiment of the present disclosure.

[0090] like Fig. 7A As shown, the processor 6000 can be configured to operate in a first operating mode. Area 1 and area 2 can be powered by independent power supplies from the mainboard. A reset signal and a power supply status signal of the power supply can be provided to area 1 and area 2 respectively. The power supply status signal can indicate the power-on or power-off state of the power supply. Reset signal 1 and power supply status signal 1 can be provided to area 1, and reset signal 2 and power supply status signal 2 can be provided to area 2.

[0091] The processor 6000 can be divided into two independent systems. The area 1 including the IO subsystem 1-1 to the IO subsystem 1-4, the storage subsystem 1-1 to the storage subsystem 1-4, the processor core 1-1 to the processor core 1-8, the system control unit 1, and the connection switch 1-1 to the connection switch 1-8 can be operated as an independent system. The system control unit 1 can control the power on and off, reset, initialization configuration, continuous system management and other processes of the area 1.

[0092] The area 2 including the IO subsystem 2-1 to IO subsystem 2-4, the storage subsystem 2-1 to storage subsystem 2-4, the processor core 2-1 to the processor core 2-8, the system control unit 2, and the connection switch 2-1 to the connection switch 2-8 can be operated as an independent system. The system control unit 2 can control the power on and off, reset, initialization configuration, continuous system management and other processes of the area 2.

[0093] The second connection switch may include a disabling logic that is independent of the first connection switch in the connection switch. With such a disabling logic, when the second connection switch is disabled, the first connection switch is enabled without being affected, for example, the normal operation or normal communication of the first connection switch is not affected. According to an embodiment of the present disclosure, the second connection switch may be disabled based on the disabling logic while the first connection switch is enabled. For example, by disabling Fig. 7A The second connection switch shown as filled with diagonal lines in the figure is used to disable the cross-region communication between connection switch 1-7 and connection switch 2-7, and between connection switch 1-8 and connection switch 2-8, so that the communication isolation between area 1 and area 2 can be achieved. At the same time, the first connection switch can be enabled, for example, between connection switch 1-1 and connection switch 1-3, between connection switch 1-2 and connection switch 1-4, between connection switch 1-5 and connection switch 1-6, and between connection switch 2-1 and connection switch 2-3, between connection switch 2-2 and connection switch 2-4, and between connection switch 2-5 and connection switch 2-6 can be performed without being affected. In this way, area 1 and area 2 can each operate as an independent system. Area 1 and area 2 can each perform power on and off or reset operations based on the instructions of the motherboard without affecting the other area, thereby effectively reducing the explosion radius.

[0094] Figure 7B is a schematic diagram of a processor operating in a second operation mode according to at least one embodiment of the present disclosure.

[0095] like Figure 7B As shown, the processor 6000 can be configured to operate in the second operation mode. Area 1 and area 2 can be powered by a common power supply from the mainboard. A reset signal and a power state signal of the power supply can be provided to one of area 1 and area 2, while the reset signal and the power state signal of the other area can be disabled. For example, a reset signal 1 and a power state signal 1 can be provided to area 1, and a reset signal 2 and a power state signal 2 of area 2 can be disabled (e.g., grounded).

[0096] The processor 6000 can operate as a whole system. For example, the area 1 including the IO subsystems 1-1 to 1-4, the storage subsystems 1-1 to 1-4, the processor cores 1-1 to 1-8, the system control unit 1, and the connection switches 1-1 to 1-8 and the area 2 including the IO subsystems 2-1 to 2-4, the storage subsystems 2-1 to 2-4, the processor cores 2-1 to 2-8, the system control unit 2, and the connection switches 2-1 to 2-8 can operate as a whole system.

[0097] One of the system control unit 1 and the system control unit 2 can be enabled, and the other system control unit can be disabled. For example, the system control unit 1 can be enabled, the system control unit 2 can be disabled ( Figure 7B The system control unit 1 can control the power-on and power-off, reset, initialization configuration, continuous system management and other processes of the entire system represented by area 1 and area 2.

[0098] The second connection switch can be enabled to enable cross-region communication between connection switch 1-7 and connection switch 2-7, and between connection switch 1-8 and connection switch 2-8, so as to remove the communication isolation between region 1 and region 2. In this way, region 1 and region 2 can operate as a whole system. Region 1 and region 2 can jointly perform processing tasks and power on / off or reset operations based on the instructions of the mainboard, thereby providing high-performance computing services.

[0099] Figure 8 A configuration method for a processor according to at least one embodiment of the present disclosure includes steps S802 and S804.

[0100] In step S802 , a plurality of processor cores of a processor may be configured in a plurality of regions.

[0101] In step S804, the processor is operated in a first operation mode or a second operation mode among a plurality of operation modes, wherein in the first operation mode, the plurality of regions are used to perform independent processing tasks respectively, and the plurality of regions are isolated from each other in terms of communication and power supply, and in the second operation mode, the plurality of regions are used to perform common processing tasks in cooperation, and the plurality of regions are isolated from each other in terms of power supply and communication isolation is released.

[0102] According to at least one embodiment of the present disclosure, a configuration method for a processor may further include, in response to the processor operating in a first operating mode, powering each of the plurality of regions through an independent power supply, and resetting each of the plurality of regions through an independent power state signal and a reset signal.

[0103] According to at least one embodiment of the present disclosure, the configuration method for a processor may further include configuring an input / output subsystem, a storage subsystem, and a portion of processor cores among the plurality of processor cores for each of the plurality of regions.

[0104] According to at least one embodiment of the present disclosure, a configuration method for a processor may further include configuring a connection switch for each of a plurality of regions, and configuring a plurality of core particles for each region, wherein the connection switch includes a first connection switch and a second connection switch, the first connection switch is configured to perform intra-region communication and the second connection switch is configured to perform cross-region communication.

[0105] The configuration method for a processor according to at least one embodiment of the present disclosure may further include causing the intra-region communication to include communication between chiplets located in the same region.

[0106] The configuration method for a processor according to at least one embodiment of the present disclosure may further include enabling cross-region communication to include communication between chiplets located in different regions.

[0107] The configuration method for a processor according to at least one embodiment of the present disclosure may further include implementing communication isolation by disabling cross-zone communication using a connection switch.

[0108] According to at least one embodiment of the present disclosure, the configuration method for a processor may further include, in response to the processor operating in the second operating mode, supplying power to the multiple regions through a common power supply, and resetting the multiple regions through a common power state signal and a reset signal.

[0109] The configuration method for a processor according to at least one embodiment of the present disclosure may further include releasing communication isolation by enabling cross-zone communication using the connection switch.

[0110] According to at least one embodiment of the present disclosure, the configuration method for a processor may further include, in response to the processor operating in the second operation mode, causing multiple areas to jointly perform one or more of connection or disconnection operations with a power supply, a reset operation, and an initialization operation.

[0111] According to at least one embodiment of the present disclosure, the configuration method for a processor may further include, in response to the processor operating in the first operation mode, enabling multiple areas to independently perform one or more of connection or disconnection operations with a power supply, a reset operation, and an initialization operation.

[0112] According to at least one embodiment of the present disclosure, the configuration method for a processor may further include implementing a connection switch through chiplet-to-chiplet communication.

[0113] According to at least one embodiment of the present disclosure, a configuration method for a processor may further include configuring a system control unit in each of a plurality of areas, and the system control unit includes a configuration register configured to store configuration information of the corresponding area, the configuration information including configuration information indicating one of a plurality of operating modes, wherein the processor will operate in one operating mode; a clock generation module configured to generate a clock signal for components included in the corresponding area based on the configuration information and a reference clock signal; a reset generation module configured to generate a reset signal for components included in the corresponding area based on the configuration information, a power status signal and a reset signal; and a process management module configured to perform power management functions, reset management functions, configuration initialization management functions and continuous system management functions.

[0114] According to at least one embodiment of the present disclosure, the configuration method for a processor may further include monitoring and managing the power supply and power failure of the power supply during the processor reset operation by executing a power management function; controlling the orderly release of the reset operation of the components included in the corresponding area by executing a reset management function; performing initialization configuration on the components according to configuration information after the orderly release of the reset operation of the components included in the corresponding area by executing a configuration initialization management function; and performing power consumption monitoring and temperature monitoring on the processor during the processor operation by executing a continuous system management function.

[0115] According to at least one embodiment of the present disclosure, the configuration method for a processor may further include, in response to the processor operating in a first operating mode, enabling a system control unit included in each of the multiple regions, and in response to the processor operating in a second operating mode, enabling a system control unit included in one of the multiple regions and disabling system control units included in the remaining regions of the multiple regions.

[0116] According to at least one embodiment of the present disclosure, a configuration method for a processor may further include operating the processor in one of a plurality of operation modes based on one or more of configuration information stored in a configuration register, a general purpose input / output port, and a one-time programmable memory identifier.

[0117] The configuration method for a processor according to at least one embodiment of the present disclosure may further include implementing the processor through a system on chip or a chiplet group.

[0118] Fig. 9 An electronic device including a processor according to at least one embodiment of the present disclosure.

[0119] like Fig. 9As shown, the electronic device 900 includes a processor 910 and a memory 920. The memory 920 includes one or more computer program modules 921. The one or more computer program modules 921 are stored in the memory 920 and can be configured to be read and executed by the processor 910.

[0120] The memory 920 and the processor 910 may be interconnected via a bus system and / or other forms of connection mechanisms (not shown). For example, the bus may be a peripheral component interconnect standard (PCI) bus or an extended industrial standard architecture (EISA) bus, etc. The communication bus may be divided into an address bus, a data bus, a control bus, etc.

[0121] The processor 910 may include the Figure 1 -The processor described in FIG7 . Exemplarily, the processor may include a central processing unit (CPU), a digital signal processor (DSP), a graphics processing unit (GPU), or other forms of processing units with data processing capabilities and / or program execution capabilities, such as a field programmable gate array (FPGA), etc. The processor 910 may be a general-purpose processor or a dedicated processor, and may control other components in the electronic device 900 to perform desired functions.

[0122] Exemplarily, the memory 920 may include any combination of one or more computer program products, and the computer program product may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache, etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disk read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer program modules 921 may be stored on the computer-readable storage medium, and the processor 910 may run one or more computer program modules 921 to implement various functions of the electronic device 900. Various applications and various data, as well as various data used and / or generated by the application, etc. may also be stored in the computer-readable storage medium.

[0123] For example, the electronic device 900 may also include input devices such as cameras, touch screens, touch pads, keyboards, mice, webcams, microphones, accelerometers, gyroscopes, etc.; output devices such as liquid crystal displays, speakers, vibrators, etc.; storage devices such as magnetic tapes, hard disks (HDD or SDD), etc.; and communication devices such as network interface cards such as LAN cards, modems, etc. The communication device may allow the electronic device 900 to communicate with other devices wirelessly or wired to exchange data, and perform communication processing via a network such as the Internet. The drive is connected to the I / O interface as needed. Removable storage media, such as magnetic disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on the drive as needed so that the computer program read therefrom is installed into the storage device as needed.

[0124] For example, the electronic device 900 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device may communicate with a network and other devices through wireless communication, such as the Internet, an intranet and / or a wireless network such as a cellular phone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communication may use any of a variety of communication standards, protocols, and technologies, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0125] The electronic device 900 may be, for example, a system on a chip (SOC) or a device including the SOC, for example, a mobile phone, a tablet computer, a laptop computer, an e-book, a game console, a television, a digital photo frame, a navigator, a home appliance, a communication base station, an industrial controller, a server, or any other device, or a combination of any data processing device and hardware, which is not limited by the embodiments of the present disclosure. The specific functions and technical effects of the electronic device 900 may refer to the above description of the processor and its additional aspects according to at least one embodiment of the present disclosure, which will not be repeated here.

[0126] According to at least one embodiment of the present disclosure, the processor can switch between different operating modes. For example, the processor according to the present disclosure can operate in a first operating mode corresponding to a high-performance mode to provide high-performance computing services. In addition, the processor according to the present disclosure can operate in a second operating mode corresponding to a cloud computing mode to provide cloud computing services. When the processor operates in the cloud computing mode, since the multiple regions each perform independent processing tasks, and the multiple regions are isolated from each other in communication and power supply, the processor has a reduced blast radius, thereby reducing cloud computing costs.

[0127] The text and drawings in this disclosure are provided as examples only to help understand the present disclosure. They should not be interpreted as limiting the scope of the present disclosure in any way. Although certain embodiments and examples have been provided, based on the contents disclosed herein, it is clear to those skilled in the art that the embodiments and examples shown may be changed without departing from the scope of the present disclosure.

[0128] Although the present disclosure has been described with exemplary embodiments, various changes and modifications may be suggested to one skilled in the art. The present disclosure is intended to encompass such changes and modifications as fall within the scope of the appended claims.

[0129] Any description in this disclosure should not be construed as implying that any particular element, step, or function is an essential element that must be included in the claims scope. The scope of the patented subject matter is limited solely by the claims.

Claims

1. A processor, comprising: a plurality of processor cores, wherein the plurality of processor cores are arranged in a plurality of zones; and A control unit is configured to control the processor to operate in a first operating mode or a second operating mode among multiple operating modes, and, in response to the processor operating in the first operating mode, the multiple regions each perform an independent processing task, and the multiple regions implement communication isolation and power supply isolation from each other, and, in response to the processor operating in the second operating mode, the multiple regions collaboratively perform a common processing task, and the multiple regions implement the power supply isolation and release the communication isolation from each other.

2. The processor of claim 1, wherein: In response to the processor operating in the first operation mode, the plurality of regions are each powered by an independent power supply and each performs a reset operation by an independent power state signal and a reset signal.

3. The processor of claim 1 , wherein: Each of the plurality of regions includes an input / output subsystem, a storage subsystem, and a portion of the plurality of processor cores.

4. The processor of claim 1, wherein: Each of the plurality of regions includes a connection switch, and each of the regions includes a plurality of core particles, The connection switch includes a first connection switch and a second connection switch, the first connection switch is configured to perform intra-region communication and the second connection switch is configured to perform inter-region communication.

5. The processor according to claim 4, wherein: The intra-region communication includes communication between core particles located in the same region.

6. The processor according to claim 4, wherein: The cross-region communication includes communication between core particles located in different regions.

7. The processor according to claim 4, wherein: The second connection switch is configured to achieve the communication isolation by disabling cross-zone communication.

8. The processor of claim 1, wherein: In response to the processor operating in the second operation mode, the plurality of regions are powered by a common power supply and are reset by a common power state signal and a reset signal.

9. The processor of claim 4, wherein: The second connection switch is configured to release the communication isolation by enabling cross-zone communication.

10. The processor of claim 1, wherein: In response to the processor operating in the second operation mode, the plurality of regions jointly perform one or more of a connection or disconnection operation with a power supply, a reset operation, and an initialization operation.

11. The processor of claim 1, wherein: In response to the processor operating in the first operation mode, the plurality of regions independently perform one or more of a connection or disconnection operation with a power supply, a reset operation, and an initialization operation.

12. The processor of claim 1, wherein: The connection switch is configured to be implemented through chiplet-to-chiplet communication.

13. The processor of claim 1, wherein: The control unit includes a system control unit configured in each of the plurality of areas, the system control unit including: a configuration register configured to store configuration information of a corresponding region, the configuration information including configuration information indicating one operation mode among a plurality of operation modes, wherein the processor is to operate in the one operation mode; a clock generation module configured to generate a clock signal for a component included in a corresponding area based on the configuration information and a reference clock signal; a reset generation module configured to generate a reset signal for components included in a corresponding area based on the configuration information, the power state signal and the reset signal; The process management module is configured to perform power management functions, reset management functions, configuration initialization management functions, and continuous system management functions.

14. The processor of claim 13, wherein: The power management function includes monitoring and managing the power on and off of the power supply during the processor reset operation; The reset management function includes controlling the orderly release of reset operations of components included in the corresponding area; The configuration initialization management function includes performing initialization configuration on the components included in the corresponding area according to the configuration information after orderly release of the reset operation of the components included in the corresponding area; The ongoing system management functions include performing power consumption monitoring and temperature monitoring on the processor during operation of the processor.

15. The processor of claim 13, wherein: In response to the processor operating in the first operating mode, the system control unit included in each of the plurality of areas is enabled, and In response to the processor operating in the second operation mode, the system control unit included in one of the plurality of regions is enabled, and the system control units included in the remaining regions of the plurality of regions are disabled.

16. The processor of claim 1, wherein: The processor is configured to operate in one of the plurality of operation modes based on one or more of configuration information stored in a configuration register, a general purpose input / output port, and a one-time programmable memory flag.

17. The processor of claim 1, wherein: The processor is implemented by a system on chip or a chiplet group.

18. An electronic device comprising the processor according to any one of claims 1-17.

19. A configuration method for a processor, comprising: configuring a plurality of processor cores of the processor in a plurality of zones; as well as The processor is operated in a first operating mode or a second operating mode among multiple operating modes, wherein, in the first operating mode, the multiple regions are used to each perform an independent processing task, and the multiple regions are communicationally isolated and power-isolated from each other, and in the second operating mode, the multiple regions are used to collaboratively perform a common processing task, and the multiple regions are power-isolated from each other and communication isolation is released.

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