Processor, configuration method for processor, and electronic device

Abstract

Embodiments of this disclosure provide a processor, a configuration method for the processor, and an electronic device. The processor includes multiple processor cores configured in multiple regions; a control unit configured to control the processor to operate in a first operating mode or a second operating mode among multiple operating modes, wherein, in response to the processor operating in the first operating mode, each of the multiple regions executes an independent processing task, and the multiple regions are communicatively and power-isolated from each other; and, in response to the processor operating in the second operating mode, the multiple regions collaboratively execute a common processing task, and the multiple regions are power-isolated from each other and their communication isolation is de-isolated. The processor can switch between different operating modes, thereby enabling it to provide high-performance computing services and cloud computing services with a reduced blast radius in different modes respectively.

Description

Technical Field

[0001] Embodiments of this disclosure relate to processors, methods for configuring processors, and electronic devices including processors. Background Technology

[0002] Cloud computing refers to highly powerful computing systems formed through computer networks (such as the Internet). Cloud computing can store and aggregate relevant resources and can be configured on demand to provide personalized services to users. Cloud computing is the result of the hybrid evolution and leap forward of computer technologies such as distributed computing, utility computing, load balancing, parallel computing, network storage, hot backup redundancy, and virtualization.

[0003] In cloud computing applications, with the development of cloud computing technology, more and more information services are migrating to the cloud. Cloud computing significantly improves the utilization of hardware facilities such as processors. In cloud computing, tenants can use cloud services on the cloud platform, renting cloud resources to meet their needs. However, this increased hardware utilization also means that multiple tenants share the same hardware. When a hardware device fails, the services of multiple tenants will be affected simultaneously. For example, in cloud computing, a failure of the Central Processing Unit (CPU) or other hardware can impact the cloud computing system. The extent to which a cloud computing system is affected by a CPU or other hardware failure can be called the blast radius. With advancements in chip technology and design, the number of cores, storage subsystems, and input / output (IO) subsystems integrated into a single CPU is constantly increasing, supporting the needs of an growing number of tenants. Therefore, it is crucial to minimize the blast radius in the cloud.

[0004] However, with advancements in chip manufacturing processes and designs, the number of cores, memory subsystems, and I / O subsystems integrated into a single processor continues to increase, which in turn leads to the problem of an increasing processor blast radius. Summary of the Invention

[0005] A processor is provided according to at least one embodiment of the present disclosure, the processor comprising: a plurality of processor cores, wherein the plurality of processor cores are configured in a plurality of regions; a control unit configured to control the processor to operate in a first operating mode or a second operating mode among a plurality of operating modes, wherein, in response to the processor operating in the first operating mode, each of the plurality of regions executes an independent processing task, and the plurality of regions are communicatively and power-isolated from each other; and, in response to the processor operating in the second operating mode, the plurality of regions collaboratively execute a common processing task, and the plurality of regions are power-isolated from each other and the communication isolation is released.

[0006] For example, in a processor according to an embodiment of the present disclosure, in response to the processor operating in the first operating mode, each of the plurality of regions is powered by an independent power supply and each is reset by an independent power status signal and a reset signal.

[0007] For example, in a processor according to an embodiment of the present disclosure, each of the plurality of regions includes an input / output subsystem, a storage subsystem, and a portion of the plurality of processor cores.

[0008] For example, in a processor according to an embodiment of the present disclosure, each of the plurality of regions includes a connection switch, and each region includes a plurality of chips, wherein the connection switch includes a first connection switch and a second connection switch, the first connection switch being configured to perform intra-regional communication and the second connection switch being configured to perform cross-regional communication.

[0009] For example, in a processor according to an embodiment of the present disclosure, the intra-regional communication includes communication between chips located in the same region.

[0010] For example, in a processor according to an embodiment of this disclosure, the cross-regional communication includes communication between chips located in different regions.

[0011] For example, in a processor according to an embodiment of this disclosure, the second connection switch is configured to achieve the communication isolation by disabling cross-regional communication.

[0012] For example, in a processor according to an embodiment of the present disclosure, in response to the processor operating in a second operating mode, the plurality of regions are powered by a common power supply and reset via a common power status signal and a reset signal.

[0013] For example, in a processor according to an embodiment of this disclosure, the second connection switch is configured to release the communication isolation by enabling cross-regional communication.

[0014] For example, in a processor according to an embodiment of the present disclosure, in response to the processor operating in the second operating mode, the plurality of regions jointly perform one or more of a connection or disconnection operation with the power supply, a reset operation, and an initialization operation.

[0015] For example, in a processor according to an embodiment of the present disclosure, in response to the processor operating in the first operating mode, the plurality of regions independently perform one or more of a connection or disconnection operation with a power supply, a reset operation, and an initialization operation.

[0016] For example, in a processor according to an embodiment of the present disclosure, the connection switch is configured to implement chip-to-chip communication.

[0017] For example, in a processor according to an embodiment of the present disclosure, the control unit includes a system control unit configured in each of the plurality of regions. The system control unit includes: a configuration register configured to store configuration information for the corresponding region, the configuration information including configuration information indicating one of a plurality of operating modes, wherein the processor will operate in the one operating mode; a clock generation module configured to generate a clock signal for components included in the corresponding region based on the configuration information and a reference clock signal; a reset generation module configured to generate a reset signal for components included in the corresponding region based on the configuration information, a power status signal, and a reset signal; and a process management module configured to perform power management functions, reset management functions, configuration initialization management functions, and continuous system management functions.

[0018] For example, in a processor according to an embodiment of this disclosure, the power management function includes monitoring and managing the power supply and power-off of the power supply during the processor reset operation; the reset management function includes controlling the orderly release of the reset operation of components included in the corresponding area; the configuration initialization management function includes performing initialization configuration on the components according to the configuration information after the orderly release of the reset operation of the components included in the corresponding area; and the continuous system management function includes performing power consumption monitoring and temperature monitoring on the processor during processor operation.

[0019] For example, in a processor according to an embodiment of the present disclosure, in response to the processor operating in the first operating mode, the system control unit included in each of the plurality of regions is enabled, and in response to the processor operating in the second operating mode, the system control unit included in one of the plurality of regions is enabled, and the system control unit included in the remaining regions of the plurality of regions is disabled.

[0020] For example, in a processor according to an embodiment of the present disclosure, the processor is configured to operate in one of the plurality of operating modes based on configuration information stored in a configuration register, a general-purpose input / output port, and a one-time programmable memory identifier.

[0021] For example, in the processor according to embodiments of the present disclosure, the processor is implemented via a system-on-a-chip or a chip assembly.

[0022] An electronic device is provided according to at least one embodiment of the present disclosure, the electronic device including the processor of any of the above embodiments.

[0023] According to at least one embodiment of the present disclosure, a configuration method for a processor is provided, the configuration method comprising: configuring a plurality of processor cores of the processor in a plurality of regions; operating the processor in a first operating mode or a second operating mode of a plurality of operating modes, wherein, in the first operating mode, each of the plurality of regions performs an independent processing task and the plurality of regions are communicationally and power-isolated from each other; and in the second operating mode, the plurality of regions collaboratively perform a common processing task and the plurality of regions are power-isolated from each other and communication isolation is removed. Attached Figure Description

[0024] The above and other aspects, features, and advantages of specific embodiments of the present disclosure will become clearer from the following description taken in conjunction with the accompanying drawings, in which:

[0025] Figure 1 This is a schematic diagram of a processor;

[0026] Figure 2 This is a schematic diagram of cold reset and hot reset;

[0027] Figure 3 This is a schematic diagram of a processor according to at least one embodiment of the present disclosure;

[0028] Figure 4 This is another schematic diagram of a processor according to at least one embodiment of the present disclosure;

[0029] Figure 5A This is a schematic diagram of a system control unit according to at least one embodiment of the present disclosure;

[0030] Figure 5B This is a schematic diagram of a process management module according to at least one embodiment of the present disclosure;

[0031] Figure 6 This is a schematic diagram illustrating an implementation of a processor according to at least one embodiment of the present disclosure;

[0032] Figure 7AThis is a schematic diagram of a processor operating in a first operating mode according to at least one embodiment of the present disclosure;

[0033] Figure 7B This is a schematic diagram of a processor operating in a second operating mode according to at least one embodiment of the present disclosure;

[0034] Figure 8 This is a method for configuring a processor according to at least one embodiment of the present disclosure; and

[0035] Figure 9 It is an electronic device including a processor according to at least one embodiment of the present disclosure. Detailed Implementation

[0036] Before proceeding with the detailed description below, it may be advantageous to define certain words and phrases used throughout this disclosure. The terms “comprising” and “including” and their derivatives mean including but not limited to. The term “or” is inclusive, meaning and / or. The phrase “associated with” and its derivatives mean including, comprising, interconnecting, containing, contained within, connected or connected to, coupled or coupled to, communicating with, cooperating, intertwining, juxtaposing, proximate, binding or bound to, having, possessing attributes, having a relationship or being related to, etc. The term “controller” means any device, system, or part thereof that controls at least one operation. Such a controller may be implemented in hardware, or a combination of hardware and software and / or firmware. The functionality associated with any particular controller may be centralized or distributed, local or remote. The phrase “at least one,” when used with a list of items, means that different combinations of one or more of the listed items may be used, and that only one item from the list may be required. For example, "at least one of A, B, and C" includes any one of the following combinations: A, B, C, A and B, A and C, B and C, A and B and C.

[0037] Definitions of other specific words and phrases are provided throughout this disclosure. Those skilled in the art will understand that, in many, if not most, cases, such definitions apply to the prior and future use of the words and phrases thus defined.

[0038] The various embodiments of the principles of this disclosure described below with reference to the accompanying drawings are for illustrative purposes only and should not be construed as limiting the scope of this disclosure in any way. Those skilled in the art will understand that the principles of this disclosure can be implemented in any suitably arranged system or device. In some cases, the actions described in the specification may be performed in a different order and the desired result may still be achieved. Furthermore, the processes depicted in the drawings do not necessarily require a specific order or sequential sequence to achieve the desired result. In certain embodiments, multitasking and parallel processing may be advantageous.

[0039] Figure 1 This is a schematic diagram of a processor.

[0040] Figure 1 This illustrates a processor, such as a CPU chip. Figure 1 As shown, the processor includes multiple processor cores, one or more memory subsystems, one or more I / O subsystems, and a bus. Figure 1 In the processor shown, the processor core, memory subsystem, and I / O subsystem are interconnected via a bus. The processor core typically includes multiple levels of cache (e.g., Level 1 data cache (L1D$), Level 1 instruction cache (L1I$), Level 2 cache (L2$), Level 3 cache (L3$), etc.) to improve computing performance. For example, cache coherency can be achieved between multiple processor cores via a bus.

[0041] A processor core, also known as a computing core, core, or kernel, is a crucial component of a processor. All computational operations, command reception / storage operations, and data processing operations performed by the processor core are executed by the processor core.

[0042] The processor's memory stores data processed by the processor as well as data exchanged with external storage devices such as hard drives. The storage subsystem may include a storage controller and a corresponding physical layer (PHY). The physical layer (PHY) enables long-distance signal propagation over a physical medium. The storage subsystem is used to access external storage components. Generally, to increase system storage capacity and memory access bandwidth, multiple storage subsystems can be integrated into the processor.

[0043] The I / O subsystem is used to manage and control access to external devices. It can include an I / O controller, a corresponding Physical Coding Sublayer (PCS), and a corresponding Physical Layer (PHY). The PCS, located between the PHY and Media Access Control (MAC) sublayer, is responsible for encoding and decoding data for transmission over the physical layer. The PHY enables long-distance signal propagation over the physical medium. I / O subsystems typically implement common I / O protocols such as PCIe, USB, and SATA. Processors generally configure multiple I / O subsystems based on their I / O type and bandwidth requirements.

[0044] like Figure 1As shown, under normal use, the bus can achieve cache coherency across multiple processor cores and provide a globally unified physical address for memory and I / O access. The entire processor can be used as a complete system. In the event of a processor failure, such as a hardware malfunction, the processor can be reset. A reset restores the processor to its default state. Resets can include cold resets and warm resets.

[0045] Figure 2 This is a schematic diagram of cold reset and hot reset.

[0046] like Figure 2 As shown, during a cold reset, the processor can first enable the reset signal (e.g., lower the reset signal to a low level) and then power down the power supply. After a predetermined delay, the power supply can be powered on. After the power supply stabilizes, the reset signal is released (e.g., raised to a high level), and processor initialization begins. During a warm reset, the processor can enable the reset signal (e.g., lower the reset signal to a low level), release the reset signal after a predetermined delay (e.g., raise the reset signal to a high level), and begin processor initialization, while the power supply remains powered on throughout.

[0047] exist Figure 1 In the processor shown, all the hardware in the processor must be powered on or off simultaneously, or a unified reset signal must be used to perform a cold reset or a warm reset simultaneously. When the processor hardware malfunctions, all virtual machine systems running on the processor will be affected. Therefore, Figure 1 The processor shown has a large blast radius.

[0048] At least one embodiment of this disclosure provides a processor comprising: a plurality of processor cores and a control unit, wherein the plurality of processor cores are configured in a plurality of regions; the control unit is configured to control the processor to operate in a first operating mode or a second operating mode among a plurality of operating modes, and, in response to the processor operating in the first operating mode, the plurality of regions each execute an independent processing task, and the plurality of regions are mutually isolated in terms of communication and power supply; and, in response to the processor operating in the second operating mode, the plurality of regions cooperate to execute a common processing task, and the plurality of regions are mutually isolated in terms of power supply and deisolated in terms of communication.

[0049] The processor according to embodiments of this disclosure can solve or mitigate the problem of the growing explosion radius in cloud computing.

[0050] The processor according to at least one embodiment of this disclosure can switch between different operating modes. For example, the processor according to this disclosure can operate in a first operating mode corresponding to a high-performance mode to provide high-performance computing services. Furthermore, the processor according to this disclosure can operate in a second operating mode corresponding to a cloud computing mode to provide cloud computing services. When the processor operates in cloud computing mode, because multiple regions execute independent processing tasks and the multiple regions are communicatively and power-isolated from each other, the processor has a reduced blast radius, thereby reducing cloud computing costs.

[0051] Figure 3 This is a schematic diagram of a processor according to at least one embodiment of the present disclosure.

[0052] Figure 3 A processor 1000 is shown, which can be a central processing unit, graphics processing unit, digital signal processing unit, artificial intelligence processing unit, etc. Figure 3 As shown, processor 1000 includes multiple processor cores, such as processor cores 1111-1113, processor cores 1121-1123, ..., processor cores 11N1-11N3. Each of the multiple processor cores can independently execute program code and handle different tasks or threads simultaneously. Multiple processor cores can improve the processor's parallel processing capabilities, enabling the computer to execute multiple tasks or more complex calculations more quickly. Each of the multiple processor cores can execute instructions, including but not limited to arithmetic logic instructions (such as addition, subtraction, multiplication, division, AND, OR, NOT, XOR, etc.), data transfer instructions (such as load, store, input, output, etc.), control flow instructions (such as unconditional jump, subroutine call, and return, etc.), string processing instructions (such as comparison, shift, and search strings, etc.), floating-point arithmetic instructions (such as arithmetic operations for floating-point numbers, such as addition, subtraction, multiplication, division, square root, etc.), privileged instructions (such as those for operating system-level tasks, such as interrupt control, virtual memory management, etc.), and so on. The embodiments disclosed herein do not limit the instruction set (e.g., x86 instruction set, ARM instruction set, RISC-V instruction set) applicable to the processor core, nor do they limit the microarchitecture used or its composition.

[0053] The processor 1000 can be divided into multiple regions, such as region 1, region 2, ..., region N.

[0054] The processor 1000 includes multiple processor cores that can be configured in multiple regions. For example, processor cores 1111-1113 can be configured in region 1, processor cores 1121-1123 can be configured in region 2, ..., and processor cores 11N1-11N3 can be configured in region N. Although Figure 3 In this design, each of the multiple regions is configured with three processor cores, but those skilled in the art will understand that such a configuration is merely exemplary and that each region may be configured with more or fewer processor cores depending on the application requirements.

[0055] The processor 1000 is divided into multiple regions that can be physically isolated. Physical isolation can include power supply isolation and communication isolation. For example, a cross-power supply design can be provided at the boundary of each region to achieve power supply isolation. For example, the multiple processor cores included in the processor 1000 can be interconnected via interconnect structures such as buses (e.g., bus protocols such as Advanced Dextensible Interface (AXI) and Advanced Microcontroller Bus Architecture (AMBA), crossbar switches, ring networks, mesh networks, on-chip networks, etc.). The interconnect structure can have connection switches at the cross-region boundaries. Such connection switches can enable both connected and disconnected states of the interconnect structure across regions.

[0056] In response to the connection switch being connected across regions, all processor cores of processor 1000 can be communicatively connected, thereby achieving cache consistency among multiple processor cores and enabling a globally unified physical address for storage and I / O access; in response to the connection switch being disconnected across regions, all processor cores of processor 1000 can be communicatively disconnected at the cross-region, and each region can operate as an independent system.

[0057] Processor 1000 may include control unit 1200. Although in Figure 3 The control unit 1200 is shown as a whole, but in at least one embodiment, the control unit 1200 may be distributed within the processor 1000. For example, the control unit 1200 may include a system control unit that can be configured on a substrate (see reference 1000). Figure 4 and Figures 5A-5B (Detailed description), for example, it can be implemented through hardwiring, microprogramming, state machines, or programmable logic. The processor 1000 can have multiple operating modes. The control unit 1200 can be configured to control the processor 1000 to operate in one of these multiple operating modes.

[0058] For example, the control unit 1200 can control the processor 1000 to operate in a first operating mode corresponding to a cloud computing mode. In response to the processor 1000 operating in the first operating mode, multiple regions can each execute independent processing tasks, and the multiple regions can achieve communication isolation and power isolation from each other.

[0059] For example, the control unit 1200 can control the processor 1000 to operate in a second operating mode corresponding to a high-performance computing mode. In response to the processor 1000 operating in the second operating mode, multiple regions can collaboratively execute common processing tasks, and these regions are electrically isolated from each other and their communication isolation is disabled. Depending on usage requirements, more or fewer regions can be connected or disconnected; therefore, the processor 1000 can have more operating modes, which will not be described in detail here.

[0060] Figure 4 This is another schematic diagram of a processor according to at least one embodiment of the present disclosure.

[0061] like Figure 4 As shown, processor 1000 includes multiple processor cores, such as processor cores 1111-1113, processor cores 1121-1123, ..., processor cores 11N1-11N3. Processor 1000 can be divided into multiple regions, such as region 1, region 2, ..., region N.

[0062] Processor 1000 includes storage subsystems 1310, 1320, ..., 13N0. Processor 1000 may include I / O subsystems 1410, 1420, ..., 14N0. Storage subsystems 1310, 1320, ..., 13N0 may include a storage controller and a corresponding physical layer. Storage subsystems 1310, 1320, ..., 13N0 can be used to access external storage components. I / O subsystems 1410, 1420, ..., 14N0 can be used to manage and control access to external devices. I / O subsystems 1410, 1420, ..., 14N0 may include an I / O controller and a corresponding physical layer.

[0063] like Figure 4 As shown, each of regions 1-N may include 3 processor cores, 1 storage subsystem, and 1 I / O subsystem. Those skilled in the art will understand that such configuration is merely exemplary, and depending on usage requirements, each region may be configured with more or fewer processor cores, more storage subsystems, and more I / O subsystems.

[0064] like Figure 4As shown, each of regions 1-N can have an independent power supply (e.g., power supply 1-power supply N) for power supply, a reset signal (e.g., reset signal 1-N), a mode selection signal (e.g., mode selection signal 1-N), and system management logic (e.g., implemented through system control units 1210-12N0).

[0065] The system control unit 1210-12N0 can perform operations such as power management, reset management, configuration initialization, and continuous system management on the corresponding processor core, corresponding storage subsystem, I / O subsystem, and other hardware structures based on system management logic. The following will refer to... Figure 5A and Figure 5B Detailed description of system control unit 1210-12N0.

[0066] When the processor 1000 is in the first operating mode, each region of the processor 1000 can be independently powered by multiple independent power supplies from the computer's motherboard. The reset signal for each region can be provided independently by the computer's motherboard, and the system management unit of each region is enabled and can manage the power-on and power-off process management, reset process management, state initialization, and continuous system management of its respective region.

[0067] For example, system control units 1210-12N0 in each of regions 1-N can be enabled. That is, each system control unit 1210-12N0 in regions 1-N can be responsible for power management, reset management, configuration initialization, and continuous system management operations for multiple regions of the processor 1000. Multiple regions can independently perform one or more of the following operations: connection or disconnection with power supply, reset operation, and initialization operation. For example, multiple system control units 1210-12N0 can each perform a reset operation via independent power status signals and reset signals. The interconnection structure's connection switches in each region are set to the off state. Because power and communication isolation are achieved across regions, each region of the processor 1000 can operate as an independent system, thereby providing cloud computing services with a reduced blast radius. The specific operation process of the processor 1000 in the first mode will be described below with reference to... Figure 7A Detailed description.

[0068] When the processor 1000 operates in the second operating mode, each region of the processor 1000 can be powered by a common power supply from the computer's motherboard. The reset signals 1-N for each region of the processor 1000 can also be provided by the computer's motherboard. When the processor 1000 operates in the second operating mode, the system control unit of only one of the multiple regions can be enabled, while the system control units of the other regions can be disabled.

[0069] For example, only the system control unit 1210 in region 1 can be enabled, while the system control units 1220-12N0 in regions 2-N can be disabled. That is, the system control unit 1210 in region 1 can be responsible for power management, reset management, configuration initialization, and continuous system management operations for multiple regions of the processor 1000. Multiple regions can jointly perform one or more of the following operations: connection or disconnection with the power supply, reset operation, and initialization operation. For example, the system control unit 1210 can use a common power status signal and reset signal to perform a reset operation on all multiple regions of the processor 1000 as a whole. With the interconnect switches in each region set to the connected state, the multiple regions of the processor 1000 can operate as a whole, thereby providing high-performance computing services. The specific operation process of the processor 1000 in the second mode will be described below with reference to... Figure 7B Detailed description.

[0070] Figure 5A This is a schematic diagram of a system control unit according to at least one embodiment of the present disclosure.

[0071] like Figure 5A As shown, in this embodiment, the system control unit 5000 includes a reset generation module 5100, a clock generation module 5200, a configuration register 5300, and a process management module 5400. Figure 5A The system control unit 5000 shown can be one of the system control units 1220-12N0. The system control unit 5000 can be configured in each of the multiple regions 1-N of the processor 1000.

[0072] The reset generation module 5100 can receive a power status signal 5010 and a reset signal 5020 corresponding to a region from the motherboard. The reset generation module 5100 can be configured to generate reset signals for components included in the corresponding region based on configuration information stored in the configuration register 5300, the power status signal 5010, and the reset signal 5020. For example, the reset generation module 5100 only releases the reset signal for components within the corresponding region after the power status is valid and the reset signal is released.

[0073] The clock generation module 5200 can receive a reference clock signal 5030 corresponding to a region from the motherboard. The clock generation module 5200 can be configured to generate clock signals for the components included in the corresponding region based on the configuration information stored in the configuration register 5300 and the reference clock signal.

[0074] Configuration register 5300 can receive configuration information 5040 corresponding to a region from the motherboard. Configuration register 5300 can be configured to store configuration information for the corresponding region. The processor can implement corresponding functions based on the configuration information and can modify the configuration information through a configuration interface. The configuration information may include information indicating the operating mode to be performed by the processor. For example, the configuration information may indicate one of multiple operating modes. Furthermore, the processor can operate in one of multiple operating modes based on one or more of the following: General-Purpose Input / Output (GPIO), Electronic Fuse (eFuse) identifiers. That is, the processor can select between multiple operating modes through GPIO, the configuration register, or the eFuse identifier.

[0075] The process management module 5400 can be configured to perform power management functions, reset management functions, configuration initialization management functions, and continuous system management functions. For example, the process management module 5400 can control the flow of power supply operation (power-on / off), reset operation, initialization configuration operation, and continuous system management operation. See below for reference. Figure 5B Further description of the process management module 5400.

[0076] Figure 5B This is a schematic diagram of a process management module 5400 according to at least one embodiment of the present disclosure.

[0077] like Figure 5B As shown, in this embodiment, the process management module 5400 can perform power management function 5410, reset management function 5420, configuration initialization management function 5430, and continuous system management function 5440. Those skilled in the art will understand that the process management module 5400 may include corresponding sub-modules to perform the above functions.

[0078] The power management function 5410 may include monitoring and managing the power supply and de-energization during the processor's reset operation. For example, the power management function 5410 may perform power supply monitoring and management during a cold reset, thereby ensuring that all module components in the relevant area are in a powered-off state during the power supply power-on and power-off processes.

[0079] The reset management function 5420 may include the orderly release of reset operations for components included in a corresponding area. For example, upon receiving an external reset signal from the host (e.g., ...). Figure 4 After the reset signals 1-N in the control area are released, the reset of the components in the corresponding area is released in an orderly manner.

[0080] Configuration initialization management function 5430 may include performing initialization configuration on components according to configuration information after the orderly release of reset operations of components included in the corresponding area. Continuous system management function 5440 may include performing power consumption monitoring, temperature monitoring, and other monitoring operations on the processor during processor operation.

[0081] Figure 6 This is a schematic diagram illustrating an implementation of a processor according to at least one embodiment of the present disclosure.

[0082] Figure 6 The processor 6000 is shown. The processor 6000 can be implemented as a system-on-a-chip (SOC) or a chiplet, for example, through 2D, 2.5D, or 3D packaging. Figure 6 As shown, the processor 6000 can be divided into region 1 and region 2. Those skilled in the art will understand that the number of regions is exemplary and not limiting.

[0083] Region 1 can receive corresponding reset signal 1 and power status signal 1. Region 1 can be configured with an I / O subsystem, a storage subsystem, a processor core, a system control unit, and connection switches. For example, the I / O subsystem may include I / O subsystems 1-1 to 1-4, the storage subsystem may include storage subsystems 1-1 to 1-4, the processor core may include processor cores 1-1 to 1-8, the system control unit may include system control unit 1, and the connection switches may include connection switches 1-1 to 1-8. Connection switches 1-1 to 1-6 of connection switches 1-1 to 1-8 can be referred to as the first connection switch, and connection switches 1-7 to 1-8 of connection switches 1-1 to 1-8 can be referred to as the second connection switch.

[0084] Region 2 can receive corresponding reset signal 2 and power status signal 2. Region 2 can be configured with an I / O subsystem, a storage subsystem, a processor core, a system control unit, and connection switches. For example, the I / O subsystem may include I / O subsystems 2-1 to 2-4, the storage subsystem may include storage subsystems 2-1 to 2-4, the processor core may include processor cores 2-1 to 2-8, the system control unit may include system control unit 2, and the connection switches may include connection switches 2-1 to 2-8. Connection switches 2-1 to 2-6 among connection switches 2-1 to 2-8 can be referred to as the first connection switch, and connection switches 2-7 to 2-8 among connection switches 2-1 to 2-8 can be referred to as the second connection switch.

[0085] The processor 6000 may include multiple cores, such as IO core 1-1, computing cores 1-1 to 1-2 located in region 1, and IO core 2-1, computing cores 2-1 to 2-2 located in region 2. System control unit 1 may be arranged in IO core 1-1, and system control unit 2 may be arranged in IO core 2-1. As described above, the system control unit can manage processes such as power-on / off, reset, initialization configuration, and continuous system management in the corresponding region. Those skilled in the art will understand that the configuration method of the cores and the configuration location of the system control unit are exemplary. For example, more cores may exist, such as storage cores for setting up the storage subsystem, but the disclosure is not limited thereto. For example, the system control unit may be configured in a computing core instead of an IO core, but the disclosure is not limited thereto.

[0086] The various components within a die (e.g., I / O subsystem, storage subsystem, connection switches, processor core, etc.) can be interconnected via an internal interconnect structure. Connection switches can function as described above. These connection switches can be implemented via die-to-die (D2D) communication.

[0087] The first connecting switch in the connecting switches can perform intra-region communication. Intra-region communication can be performed within the region. According to one embodiment of this disclosure, intra-region communication can include communication between cores located in the same region. For example, for region 1, intra-region communication can be performed between connecting switches 1-1 and 1-3, between connecting switches 1-2 and 1-4, and between connecting switches 1-5 and 1-6. For example, for region 2, intra-region communication can be performed between connecting switches 2-1 and 2-3, between connecting switches 2-2 and 2-4, and between connecting switches 2-5 and 2-6.

[0088] Furthermore, the second connection switch in the connection switch can perform cross-region communication. According to one embodiment of this disclosure, cross-region communication can include communication between cores located in different regions. For example, cross-region communication can be performed between connection switches 1-7 and connection switches 2-7, and between connection switches 1-8 and connection switches 2-8. The connection switches can be configured to achieve communication isolation by disabling cross-region communication. For example, by disabling the second connection switch, thereby disabling cross-region communication between connection switches 1-7 and connection switches 2-7, and between connection switches 1-8 and connection switches 2-8, communication isolation between region 1 and region 2 can be achieved. In this way, region 1 and region 2 can each operate as independent systems to reduce the blast radius. The connection switches can be configured to remove communication isolation by enabling cross-region communication. For example, by enabling the second connection switch, thereby enabling cross-region communication between connection switches 1-7 and connection switches 2-7, and between connection switches 1-8 and connection switches 2-8, communication isolation between region 1 and region 2 can be removed. In this way, region 1 and region 2 can operate as a whole to provide high-performance computing services.

[0089] Figure 7A This is a schematic diagram of a processor operating in a first operating mode according to at least one embodiment of the present disclosure.

[0090] like Figure 7A As shown, the processor 6000 can be configured to operate in a first operating mode. Region 1 and Region 2 can be powered separately by independent power supplies from the motherboard. Reset signals and power status signals can be provided to Region 1 and Region 2 respectively. The power status signals can indicate the power-on or power-off state. Reset signal 1 and power status signal 1 can be provided to Region 1, and reset signal 2 and power status signal 2 can be provided to Region 2.

[0091] The processor 6000 can be divided into two independent systems. Area 1, comprising I / O subsystems 1-1 to 1-4, storage subsystems 1-1 to 1-4, processor cores 1-1 to 1-8, system control unit 1, and connection switches 1-1 to 1-8, can operate as an independent system. System control unit 1 can control the power-on / off, reset, initialization configuration, and continuous system management processes of area 1.

[0092] Region 2, comprising I / O subsystems 2-1 to 2-4, storage subsystems 2-1 to 2-4, processor cores 2-1 to 2-8, system control unit 2, and connection switches 2-1 to 2-8, can operate as an independent system. System control unit 2 can control the power-on / off, reset, initialization configuration, and continuous system management processes of region 2.

[0093] The second connection switch may include disable logic independent of the first connection switch. This disable logic allows disabling the second connection switch without affecting the activation of the first connection switch; for example, it does not affect the normal operation or communication of the first connection switch. According to one embodiment of this disclosure, the second connection switch can be disabled based on disable logic while the first connection switch is enabled. For example, by disabling… Figure 7A The second connection switch, shown in the diagram filled with diagonal lines, disables cross-region communication between connection switches 1-7 and 2-7, and between connection switches 1-8 and 2-8, thus achieving communication isolation between region 1 and region 2. Simultaneously, the first connection switch can be enabled, for example, allowing uninterrupted intra-regional communication between connection switches 1-1 and 1-3, 1-2 and 1-4, 1-5 and 1-6, 2-1 and 2-3, 2-2 and 2-4, and 2-5 and 2-6. In this way, region 1 and region 2 can operate as independent systems. Region 1 and region 2 can each perform power-on / off or reset operations based on motherboard instructions without affecting the other region, thereby effectively reducing the blast radius.

[0094] Figure 7B This is a schematic diagram of a processor operating in a second operating mode according to at least one embodiment of the present disclosure.

[0095] like Figure 7B As shown, the processor 6000 can be configured to operate in a second operating mode. Region 1 and Region 2 can be powered by a common power supply from the motherboard. A reset signal and a power status signal for the power supply can be provided to one of Region 1 and Region 2, while the reset signal and power status signal for the other region can be disabled. For example, a reset signal 1 and a power status signal 1 can be provided to Region 1, and a reset signal 2 and a power status signal 2 can be disabled (e.g., grounded) for Region 2.

[0096] Processor 6000 can operate as a whole system. For example, area 1, which includes IO subsystems 1-1 to IO subsystems 1-4, storage subsystems 1-1 to storage subsystems 1-4, processor cores 1-1 to processor cores 1-8, system control unit 1, and connection switches 1-1 to connection switches 1-8, and area 2, which includes IO subsystems 2-1 to IO subsystems 2-4, storage subsystems 2-1 to storage subsystems 2-4, processor cores 2-1 to processor cores 2-8, system control unit 2, and connection switches 2-1 to connection switches 2-8, can operate as a whole system.

[0097] You can enable one of system control units 1 and system control unit 2, and disable the other system control units. For example, you can enable system control unit 1 and disable system control unit 2. Figure 7B (This is shown as a dashed fill). The system control unit 1 can control the power-on / off, reset, initialization configuration, and continuous system management processes of the entire system represented by area 1 and area 2.

[0098] A second connection switch can be enabled to facilitate cross-region communication between connection switches 1-7 and 2-7, and between connection switches 1-8 and 2-8, thereby removing communication isolation between region 1 and region 2. In this way, region 1 and region 2 can operate as a single system. Region 1 and region 2 can jointly perform processing tasks and power-on / off or reset operations based on instructions from the motherboard, thus providing high-performance computing services.

[0099] Figure 8 This is a configuration method for a processor according to at least one embodiment of the present disclosure. The method includes steps S802 and S804.

[0100] In step S802, multiple processor cores of the processor can be configured in multiple regions.

[0101] In step S804, the processor is operated in either a first operating mode or a second operating mode among multiple operating modes. In the first operating mode, multiple regions each execute independent processing tasks, and the multiple regions are isolated from each other in terms of communication and power supply. In the second operating mode, multiple regions collaboratively execute a common processing task, and the multiple regions are isolated from each other in terms of power supply and communication.

[0102] The configuration method for a processor according to at least one embodiment of the present disclosure may further include, in response to the processor operating in a first operating mode, supplying power to multiple regions respectively through independent power supplies, and causing each of the multiple regions to perform a reset operation through independent power status signals and reset signals.

[0103] The configuration method for a processor according to at least one embodiment of the present disclosure may further include configuring an input / output subsystem, a storage subsystem, and a portion of a plurality of processor cores for each of a plurality of regions.

[0104] The configuration method for a processor according to at least one embodiment of the present disclosure may further include configuring a connection switch for each of a plurality of regions and configuring a plurality of chips for each region, wherein the connection switch includes a first connection switch and a second connection switch, the first connection switch being configured to perform intra-regional communication and the second connection switch being configured to perform cross-regional communication.

[0105] The configuration method for a processor according to at least one embodiment of the present disclosure may further include enabling intra-regional communication to include communication between chips located in the same region.

[0106] The processor configuration method according to at least one embodiment of the present disclosure may further include enabling cross-region communication, including communication between chips located in different regions.

[0107] The configuration method for a processor according to at least one embodiment of the present disclosure may further include using a connection switch to achieve communication isolation by disabling cross-region communication.

[0108] The configuration method for a processor according to at least one embodiment of the present disclosure may further include, in response to the processor operating in a second operating mode, supplying power to multiple regions via a common power supply, and causing the multiple regions to perform a reset operation via a common power status signal and a reset signal.

[0109] The configuration method for a processor according to at least one embodiment of the present disclosure may further include using a connection switch to de-isolate communication by enabling cross-regional communication.

[0110] The configuration method for a processor according to at least one embodiment of the present disclosure may further include, in response to the processor operating in a second operating mode, causing multiple regions to jointly perform one or more of a connection or disconnection operation with a power supply, a reset operation, and an initialization operation.

[0111] The configuration method for a processor according to at least one embodiment of the present disclosure may further include, in response to the processor operating in a first operating mode, causing multiple regions to independently perform one or more of a connection or disconnection operation with a power supply, a reset operation, and an initialization operation.

[0112] The configuration method for a processor according to at least one embodiment of the present disclosure may further include implementing a connection switch via chip-to-chip communication.

[0113] The configuration method for a processor according to at least one embodiment of the present disclosure may further include configuring a system control unit in each of a plurality of regions, wherein the system control unit includes a configuration register configured to store configuration information for the corresponding region, the configuration information including configuration information indicating one of a plurality of operating modes, wherein the processor will operate in an operating mode; a clock generation module configured to generate a clock signal for components included in the corresponding region based on the configuration information and a reference clock signal; a reset generation module configured to generate a reset signal for components included in the corresponding region based on the configuration information, a power status signal, and a reset signal; and a process management module configured to perform power management functions, reset management functions, configuration initialization management functions, and continuous system management functions.

[0114] The configuration method for a processor according to at least one embodiment of the present disclosure may further include monitoring and managing the power supply and power-off of the power supply during a processor reset operation by performing a power management function; controlling the orderly release of reset operations of components included in a corresponding region by performing a reset management function; performing initialization configuration on the components according to configuration information after the orderly release of reset operations of the components included in the corresponding region by performing a configuration initialization management function; and performing power consumption monitoring and temperature monitoring of the processor during processor operation by performing a continuous system management function.

[0115] The configuration method for a processor according to at least one embodiment of the present disclosure may further include enabling a system control unit included in each of a plurality of regions in response to the processor operating in a first operating mode, and enabling a system control unit included in one of the plurality of regions in response to the processor operating in a second operating mode, while disabling system control units included in the remaining regions of the plurality of regions.

[0116] The configuration method for a processor according to at least one embodiment of the present disclosure may further include operating the processor in one of a plurality of operating modes based on one or more of configuration information stored in a configuration register, general-purpose input / output ports, and one-time programmable memory identifiers.

[0117] The configuration method for a processor according to at least one embodiment of the present disclosure may further include implementing the processor via a system-on-a-chip or a chip assembly.

[0118] Figure 9 It is an electronic device including a processor according to at least one embodiment of the present disclosure.

[0119] like Figure 9As shown, the electronic device 900 includes a processor 910 and a memory 920. The memory 920 includes one or more computer program modules 921. The one or more computer program modules 921 are stored in the memory 920 and can be configured to be read and executed by the processor 910.

[0120] The memory 920 and the processor 910 can be interconnected via a bus system and / or other forms of connection mechanism (not shown). For example, the bus can be a Peripheral Component Interconnect Standard (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc.

[0121] Processor 910 may include the above reference Figure 1 - The processor depicted in Figure 7. Exemplarily, the processor may include a central processing unit (CPU), a digital signal processor (DSP), a graphics processing unit (GPU), or other forms of processing unit with data processing capabilities and / or program execution capabilities, such as a field-programmable gate array (FPGA). The processor 910 may be a general-purpose processor or a special-purpose processor, capable of controlling other components in the electronic device 900 to perform desired functions.

[0122] Exemplarily, memory 920 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB storage, flash memory, etc. One or more computer program modules 921 may be stored on the computer-readable storage medium, and processor 910 may run one or more computer program modules 921 to implement various functions of electronic device 900. Various application programs and various data, as well as various data used and / or generated by the application programs, may also be stored in the computer-readable storage medium.

[0123] For example, electronic device 900 may also include input devices such as cameras, touchscreens, touchpads, keyboards, mice, webcams, microphones, accelerometers, and gyroscopes; output devices such as liquid crystal displays, speakers, and vibrators; storage devices such as magnetic tapes and hard disks (HDDs or SDDs); and communication devices such as network interface cards like LAN cards and modems. The communication devices allow electronic device 900 to communicate wirelessly or wiredly with other devices to exchange data and perform communication processing via networks such as the Internet. A drive is connected to the I / O interface as needed. Removable storage media, such as disks, optical disks, magneto-optical disks, and semiconductor memories, are installed on the drive as needed so that computer programs read from them can be installed into the storage device as required.

[0124] For example, the electronic device 900 may further include a peripheral interface (not shown in the figure). This peripheral interface can be various types of interfaces, such as a USB interface, a Lightning interface, etc. The communication device can communicate wirelessly with networks and other devices, such as the Internet, intranets and / or wireless networks such as cellular telephone networks, wireless local area networks (LANs) and / or metropolitan area networks (MANs). Wireless communication can use any of a variety of communication standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0125] The electronic device 900 may be, for example, a system-on-a-chip (SOC) or a device including the SOC. For instance, it can be any device such as a mobile phone, tablet computer, laptop computer, e-reader, game console, television, digital photo frame, navigator, home appliance, communication base station, industrial controller, server, etc., or any combination of data processing devices and hardware. The embodiments of this disclosure do not limit this. The specific functions and technical effects of the electronic device 900 can be found in the foregoing description of the processor and its additional aspects according to at least one embodiment of this disclosure, and will not be repeated here.

[0126] The processor according to at least one embodiment of this disclosure can switch between different operating modes. For example, the processor according to this disclosure can operate in a first operating mode corresponding to a high-performance mode to provide high-performance computing services. Furthermore, the processor according to this disclosure can operate in a second operating mode corresponding to a cloud computing mode to provide cloud computing services. When the processor operates in cloud computing mode, because multiple regions execute independent processing tasks and the multiple regions are communicatively and power-isolated from each other, the processor has a reduced blast radius, thereby reducing cloud computing costs.

[0127] The text and accompanying drawings in this disclosure are provided by way of example only to aid in understanding this disclosure. They should not be construed as limiting the scope of this disclosure in any way. Although certain embodiments and examples have been provided, it will be apparent to those skilled in the art, based on the content disclosed herein, that changes can be made to the illustrated embodiments and examples without departing from the scope of this disclosure.

[0128] Although this disclosure has been described with reference to exemplary embodiments, various changes and modifications may be suggested to those skilled in the art. This disclosure is intended to cover such changes and modifications that fall within the scope of the appended claims.

[0129] Nothing described in this disclosure should be construed as implying that any particular element, step, or function is an essential element that must be included within the scope of the claims. The scope of the patent subject matter is defined only by the claims.

Claims

1. A processor, comprising: Multiple processor cores, wherein the multiple processor cores are configured in multiple regions; and The control unit is configured to control the processor to operate in a first or second operating mode among a plurality of operating modes, according to information indicating the operating mode to be operated by the processor based on configuration information. In response to the processor operating in the first operating mode, each of the plurality of regions executes an independent processing task, and the plurality of regions are communicatively and power-isolated from each other, and are powered independently by a plurality of independent power supplies. In response to the processor operating in the second operating mode, the plurality of regions collaboratively execute a common processing task, and the plurality of regions are power-isolated from each other and the communication isolation is released, and are powered by a common power supply. The power supply isolation means that each of the multiple regions has an independent power supply.

2. The processor according to claim 1, wherein: In response to the processor operating in the first operating mode, each of the plurality of regions performs a reset operation via an independent power status signal and a reset signal.

3. The processor according to claim 1, wherein: Each of the plurality of regions includes an input / output subsystem, a storage subsystem, and a portion of the plurality of processor cores.

4. The processor according to claim 1, wherein: Each of the plurality of regions includes a connection switch, and each region includes a plurality of cores. The connection switch includes a first connection switch and a second connection switch, wherein the first connection switch is configured to perform intra-regional communication and the second connection switch is configured to perform cross-regional communication.

5. The processor according to claim 4, wherein, Communication within the region includes communication between cores located in the same region.

6. The processor of claim 4, wherein, The cross-regional communication includes communication between cores located in different regions.

7. The processor according to claim 4, wherein, The second connection switch is configured to achieve the communication isolation by disabling cross-regional communication.

8. The processor according to claim 1, wherein: In response to the processor operating in a second operating mode, the plurality of regions are reset via a common power status signal and a reset signal.

9. The processor of claim 4, wherein, The second connection switch is configured to release the communication isolation by enabling cross-regional communication.

10. The processor of claim 1, wherein, In response to the processor operating in the second operating mode, the plurality of regions jointly perform one or more of the following operations: connection or disconnection with the power supply, reset, and initialization.

11. The processor of claim 1, wherein, In response to the processor operating in the first operating mode, the plurality of regions independently perform one or more of the following operations: connection or disconnection with the power supply, reset, and initialization.

12. The processor of claim 4, wherein, The connection switch is configured to enable chip-to-chip communication.

13. The processor of claim 1, wherein, The control unit includes a system control unit configured in each of the plurality of regions, the system control unit comprising: A configuration register is configured to store configuration information for a corresponding region, the configuration information including configuration information indicating one of a plurality of operating modes, wherein the processor will operate in said operating mode; The clock generation module is configured to generate clock signals for the components included in the corresponding region based on the configuration information and a reference clock signal; The reset generation module is configured to generate a reset signal for the components included in the corresponding area based on the configuration information, power status signal, and reset signal. The process management module is configured to perform power management, reset management, configuration initialization management, and continuous system management functions.

14. The processor according to claim 13, wherein: The power management function includes monitoring and managing the power supply and power outage during the processor reset operation. The reset management function includes controlling the orderly release of reset operations for components included in the corresponding area; The configuration initialization management function includes performing initialization configuration on the components according to the configuration information after the orderly release of the reset operation of the components included in the corresponding area. The continuous system management functions include performing power consumption monitoring and temperature monitoring on the processor during processor operation.

15. The processor according to claim 13, wherein, In response to the processor operating in the first operating mode, the system control unit included in each of the plurality of regions is enabled, and In response to the processor operating in the second operating mode, the system control unit included in one of the plurality of regions is enabled, and the system control unit included in the remaining regions of the plurality of regions is disabled.

16. The processor of claim 1, wherein, The processor is configured to operate in one of the plurality of operating modes based on one or more of the configuration information stored in the configuration register, general-purpose input / output ports, and one-time programmable memory identifiers.

17. The processor of claim 1, wherein, The processor is implemented through a system-on-a-chip or a chip assembly.

18. An electronic device comprising a processor according to any one of claims 1-17.

19. A method for configuring a processor, comprising: The processor's multiple processor cores are configured in multiple regions; as well as According to the configuration information indicating the operating mode to be performed by the processor, the processor is operated in either a first operating mode or a second operating mode among a plurality of operating modes. In the first operating mode, each of the plurality of regions performs an independent processing task, and the plurality of regions are isolated from each other in terms of communication and power supply, and are powered independently by a plurality of independent power supplies. In the second operating mode, the plurality of regions cooperate to perform a common processing task, and the plurality of regions are isolated from each other in terms of power supply and communication, and are powered by a common power supply. The power supply isolation means that each of the multiple regions has an independent power supply.

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