Data reading and writing method of key value database

Abstract

The invention relates to the field of databases, and discloses a data reading and writing method for a key value database. Concepts of entity nodes and virtual nodes are introduced into a binary hash tree, for a father node, if any child node of the father node is the virtual node, the father node is the virtual node, and the value of the father node is equal to the value of a non-null child node of the father node, namely, the hash value of the father node serving as the virtual node is not calculated or stored. According to the invention, a three-level memory architecture is adopted to store different hierarchical nodes of the binary hash tree, and a plurality of hardware acceleration structures are designed. According to the method, the number of Hash calculation times and the verification data volume are remarkably reduced, the data writing and reading efficiency is improved, and meanwhile the data integrity is guaranteed.

Description

Technical Field

[0001] The present application relates to the field of databases, and in particular to the reading and writing technology of key-value databases. Background Art

[0002] This section is intended to provide a background or context for understanding the embodiments of the present application and is for reference only. The applicant should not be considered to admit that this section belongs to the prior art that has been disclosed before the filing date of the present application.

[0003] As the scale of data continues to expand, key-value databases have been widely used in large-scale distributed systems due to their simple and efficient data model and excellent performance. Key-value databases are a type of non-relational database (NoSQL) in which data is stored and accessed in the form of key-value pairs.

[0004] In key-value database systems, data integrity verification is an important issue. Traditional data integrity verification methods usually use hash technology, that is, hashing the data content to generate a hash value of fixed length. By comparing the hash value of the data, it is possible to detect whether the data has been tampered with. However, when a large amount of data needs to be verified, calculating and storing the hash value of each piece of data one by one will bring a large storage overhead and computing burden.

[0005] In order to optimize the efficiency of data integrity verification, the industry generally adopts data structures such as binary hash tree or Merkle tree. Binary hash tree is a tree data structure, whose leaf nodes store the hash value of data blocks, and non-leaf nodes store the combined hash value of their child nodes' hash values. This hierarchical structure enables the system to quickly verify the integrity of large amounts of data.

[0006] However, the existing data verification scheme based on binary hash tree has the following technical problems: when data is continuously written, the entire hash tree needs to be updated frequently, resulting in high computational overhead.

[0007] Therefore, how to reduce the maintenance cost of hash trees and optimize verification efficiency while ensuring the reliability of data integrity verification is a technical problem that needs to be urgently solved in current key-value database systems. Summary of the invention

[0008] The purpose of this application is to provide a data reading and writing method for a key-value database, which can reduce the maintenance cost of the hash tree and optimize the verification efficiency while ensuring the reliability of data integrity verification.

[0009] The present application discloses a method for writing data into a key-value database, comprising:

[0010] The processor receives a write request, wherein the write request includes key-value pair data;

[0011] The processor writes the key-value pair data into the first memory as a data payload;

[0012] The processor calculates the hash value of the data payload, and writes the hash value as the highest leaf node with the largest current sequence number into a binary hash tree stored in the fourth memory; in the binary hash tree, the sequence numbers of the leaf nodes are increased in sequence, and the leaf nodes with sequence numbers not greater than the highest leaf node are physical nodes, whose values ​​are the hash values ​​of the corresponding data payload, and the leaf nodes with sequence numbers greater than the highest leaf node are virtual nodes, whose values ​​are preset values;

[0013] The processor determines whether parent nodes of all levels corresponding to the highest leaf node are located in a complete entity subtree from the leaf node to the root node, wherein the complete entity subtree is a subtree that does not contain a virtual node;

[0014] In response to determining that the parent node is located in the complete entity subtree, the parent node is used as an entity node, a hash value of the parent node is calculated according to hash values ​​of two child nodes of the parent node, and the hash value of the parent node is stored in the fourth memory;

[0015] In response to determining that the parent node is not located in the complete entity subtree, the parent node is used as a virtual node. When the hash value of the parent node needs to be obtained, the value of the child node of the parent node without the preset value is directly used as the hash value of the parent node.

[0016] In a preferred embodiment, it also includes:

[0017] A plurality of complete entity subtrees are formed from left to right in the binary hash tree, and the processor adds the root node of each complete entity subtree to the root set;

[0018] The processor obtains a global root hash value by calculating hash values ​​for nodes in the root set from right to left level by level;

[0019] The processor calculates the verification hash set, specifically including: starting from the leaf node, in order from low layer to high layer, if the current node is on the left, then searching for the hash value of the paired node on the right side of the node in each layer; if the current node is on the right side, then searching for the hash value of the paired node on the left side of the node, and adding the hash value of the found paired node to the verification hash set;

[0020] The processor returns data for verifying the write operation to the requesting device, the data including: the global root hash value, the root hash set, and the verification hash set.

[0021] In a preferred embodiment, the requesting device verifies the correctness of the writing in the following manner:

[0022] A verification target node is calculated based on the verification hash set and the hash value of the leaf node, and the verification target node should be an element in the root set; and

[0023] The global root hash value can be obtained by calculating the hash value of each element in the root set step by step.

[0024] In a preferred example, the fourth memory includes a second memory and a third memory; the first memory and the second memory are non-volatile memories; the access speeds of the first memory, the second memory, and the third memory increase in sequence;

[0025] The nodes from the 0th to the Nth layers of the binary hash tree are stored in the second memory, wherein the nodes from the 0th to the Nth layers form at least one complete subtree, and each of the complete subtrees is stored in a page of the second memory, and the storage space size of the complete subtree is the same as the size of the page; the nodes from the N+1th layer and higher layers of the binary hash tree are stored in the third memory; wherein N is a preset positive integer.

[0026] In a preferred embodiment, in each page of the second memory, from the 0th layer to the Nth layer, the nodes of each layer of a complete subtree are stored layer by layer; the serial number of the leaf node is directly used as its storage position in the 0th layer; and the one-to-one correspondence between the node serial number and the storage position is maintained in each layer.

[0027] The processor includes multiple parallel long SHA256 calculation circuits and multiple parallel short SHA256 calculation circuits, wherein the long SHA256 calculation circuit is used to parallelly calculate the hash value of each leaf node in a page according to the data load, and the short SHA256 calculation circuit is used to perform pairwise combination calculations on each leaf node in a page to obtain the parent node of the first layer, and then perform multi-path parallel calculations layer by layer from bottom to top in sequence, and finally converge into a single-path calculation to obtain the root node hash value of the complete subtree.

[0028] In a preferred embodiment, it also includes:

[0029] For a complete subtree from empty to half full, use the virtual node to calculate the virtual root hash value of the complete subtree;

[0030] For a complete subtree from half full to full, after it is supplemented into a full tree, the original virtual node is discarded and the hash value of the entire complete subtree to the root is recalculated.

[0031] In a preferred example, when writing key-value pair data in batches, the following pipeline method is used for processing:

[0032] In the first pipeline stage, 64 key-value pairs are read to form a complete subtree;

[0033] In the second pipeline stage, 64 parallel SHA256 calculation circuits are used to calculate the hash values ​​of the 64 key-value pair data as leaf nodes;

[0034] In the third pipeline stage, 32 parallel SHA256 computing circuits are used to perform pairwise calculations on the leaf nodes, and the hash values ​​of the nodes at each layer of the complete subtree are obtained through 16-way parallel calculation, 8-way parallel calculation, 4-way parallel calculation, 2-way parallel calculation and single-way calculation in sequence;

[0035] In the fourth pipeline stage, the node hash value of the complete subtree is written into a 4KB page of the second memory.

[0036] The present application also discloses a data reading method for a key-value database, wherein key-value pair data is stored in a first memory as a data load with increasing serial numbers, and a binary hash tree is stored in a fourth memory; in the binary hash tree, each leaf position corresponds to a serial number, and a leaf node with a serial number not greater than the maximum serial number of the data load in the first memory is a physical node, and its value is the hash value of the corresponding data load, and a leaf node with a larger serial number is a virtual node, and its value is a preset value; for a parent node, if any of its child nodes is a virtual node, then the parent node is a virtual node, and its value is equal to the value of its child node with a non-preset value, otherwise the parent node is a physical node, and its value is the hash operation result of its two child nodes; the method comprises:

[0037] The processor receives a read request from a requesting device, and reads the requested data payload from the first memory, wherein the leaf node corresponding to the data payload is a target leaf node;

[0038] The processor generates a verification hash set of the target leaf node, wherein the elements in the verification hash set are paired nodes at each layer on the path from the target leaf node to the verification target node in the binary hash tree; the verification target node is the root node of the smallest complete entity subtree containing the target leaf node; the complete entity subtree is a subtree that does not contain a virtual node;

[0039] The processor returns the requested data payload and verification hash set to the requesting device.

[0040] In a preferred embodiment, the requesting device verifies the correctness of the read data in the following manner:

[0041] Obtain a global root hash value and a root set, wherein the global root hash value is the hash value of the root node of the binary hash tree, and the root set includes the root nodes of a plurality of complete entity subtrees from left to right in the binary hash tree;

[0042] A verification target node is calculated according to the verification hash set and the hash value of the target leaf node, and the verification target node should be an element in the root set;

[0043] The global root hash value can be obtained by calculating the hash value of each element in the root set step by step.

[0044] In a preferred example, the processor determines the verification target node through the following steps:

[0045] Starting from the most significant bit of the sequence number of the current highest leaf node of the binary hash tree, check the corresponding complete entity subtree;

[0046] If the sequence number of the target leaf node is less than or equal to the total number of nodes in the current complete entity subtree, the root node of the current complete entity subtree is used as the verification target node;

[0047] If the sequence number of the target leaf node is greater than the total number of nodes in the current complete entity subtree, subtract the total number of nodes in the current complete entity subtree from the sequence number of the target leaf node, and continue to check the complete entity subtree corresponding to the next valid bit until the complete entity subtree containing the target leaf node is found.

[0048] In a preferred example, the step of the processor generating the verification hash set includes:

[0049] Convert the sequence number of the target leaf node into binary;

[0050] Establish a hierarchical mapping, with the lowest bit corresponding to layer 0;

[0051] Start processing layer by layer from the target leaf node: detect whether the current node is an odd left subtree or an even right subtree, if it is an odd left subtree, calculate the corresponding even right subtree sequence number and add it to the verification hash set; if it is an even right subtree, calculate the corresponding odd left subtree sequence number and add it to the verification hash set, until the layer where the verification target node is located is reached.

[0052] In a preferred example, the fourth memory includes a second memory and a third memory; the first memory and the second memory are non-volatile memories; the access speeds of the first memory, the second memory and the third memory increase in sequence;

[0053] The nodes from the 0th to the Nth layers of the binary hash tree are stored in the second memory, wherein the nodes from the 0th to the Nth layers form at least one complete subtree, and each of the complete subtrees is stored in a page of the second memory, and the storage space size of the complete subtree is the same as the size of the page; the nodes from the N+1th layer and higher layers of the binary hash tree are stored in the third memory; wherein N is a preset positive integer.

[0054] In a preferred example, the processor determines the path from the target leaf node to the verification target node by the following index-based hardware calculation method:

[0055] Convert the target leaf number into binary as the index of layer 0;

[0056] In each layer of processing:

[0057] Determine the node type by checking the least significant bit. If the least significant bit is 0, it is a left node, and if it is 1, it is a right node.

[0058] For a left node, add 1 to find its right paired node; for a right node, subtract 1 to find its left paired node;

[0059] Get the corresponding index of the previous layer by right shifting 1 bit;

[0060] Repeat the above process until the layer where the verification target node is located is reached.

[0061] In a preferred embodiment, the processor uses a hardware pipeline structure to process read requests of multiple leaf nodes in parallel, including:

[0062] The first processing resource calculates the indexes of each layer of multiple target leaf nodes in parallel through bit operations;

[0063] The second processing resource is used to read the nodes of level 0 to level 6 in multiple 4KB pages from the second memory in parallel and extract the nodes in the verification hash set;

[0064] The third processing resource is used to read in parallel from the third memory the nodes in the verification hash set from the 7th layer to the root node corresponding to the plurality of target leaf nodes;

[0065] The fourth processing resource includes a plurality of parallel SHA256 calculation circuits for calculating hash values ​​of a plurality of verification paths in parallel and returning a complete verification hash set.

[0066] In a preferred embodiment, the processor includes:

[0067] Hardware acceleration circuit for calculating SHA256 hash value, including:

[0068] Multiple parallel long SHA256 calculation circuits for calculating the hash value of the data payload;

[0069] Multiple parallel short SHA256 calculation circuits are used to calculate the node hash values ​​on the verification path;

[0070] The processor supports the use of multiple SHA256 computing circuits for parallel processing during the verification process.

[0071] The present application also discloses a non-transitory computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, the steps in the method described above are implemented.

[0072] The present application also discloses a computer program product, comprising computer executable instructions, which can implement the steps in the method described above when executed by a processor.

[0073] In the implementation of the present application, by introducing the concepts of physical nodes and virtual nodes in a binary hash tree, nodes with serial numbers not greater than the highest leaf node serial number are set as physical nodes, and nodes with larger serial numbers are set as virtual nodes, and the hash values ​​of the parent nodes of the virtual nodes are neither calculated nor stored, which can significantly reduce the number of hash calculations. This innovation avoids the problem that the traditional Merkle tree needs to perform hash calculations on all nodes, improves data writing efficiency, and ensures the reliability of data verification.

[0074] Furthermore, by identifying multiple complete entity subtrees from left to right and adding their root nodes to the root set, and then calculating the hash values ​​of the nodes in the root set from right to left to obtain the global root hash value, and generating a verification hash set based on paired nodes, the data writing process is quickly verified. This hierarchical verification mechanism not only reduces the computational complexity of verification, but also provides fine-grained data integrity assurance.

[0075] Furthermore, by designing a double verification mechanism (the verification target node must exist in the root set, and the global root hash value can be calculated through the root set), a strict correctness guarantee is provided for the data writing operation. This verification method can effectively prevent data tampering, and the verification process has a small amount of calculation and high verification efficiency.

[0076] Furthermore, by adopting a hierarchical storage strategy, the nodes from the 0th to the Nth level of the binary hash tree are stored in the second memory, the higher-level nodes are stored in the faster third memory, and the complete subtree is matched with the storage page size in the second memory, thus achieving a reasonable allocation of storage resources. This hierarchical storage architecture fully considers the access characteristics of nodes at different levels, optimizes storage space utilization, and improves data access performance.

[0077] Furthermore, by designing a processor architecture that includes multiple parallel long SHA256 calculation circuits (for calculating leaf node hash values) and short SHA256 calculation circuits (for calculating parent node hash values), combined with a layered node storage structure, efficient parallel calculation of hash values ​​is achieved. This design significantly improves hash calculation performance and reduces data write latency.

[0078] Furthermore, by adopting differentiated processing strategies for complete subtrees with different filling levels (using virtual nodes to calculate virtual root hash values ​​when empty to half full, and recalculating the hash value of the entire subtree when half full to full), a good balance is achieved between computational overhead and storage efficiency. This dynamic adjustment strategy avoids frequent hash recalculations while ensuring data integrity.

[0079] Furthermore, by designing a four-stage pipeline and using different degrees of parallel processing in each stage, efficient processing of batch read and write operations is achieved. This pipeline architecture fully utilizes hardware parallel computing resources and significantly improves system throughput.

[0080] Furthermore, by optimizing the verification data generation strategy, only the verification hash set on the path from the target leaf node to the root node of the smallest complete entity subtree is returned, which greatly reduces the amount of data required for verification. This solution reduces network transmission overhead, improves data reading efficiency, and ensures the reliability of verification.

[0081] Each technical feature disclosed in the above invention content, each technical feature disclosed in each implementation mode and example below, and each technical feature disclosed in the accompanying drawings can be freely combined with each other to form various new technical solutions (these technical solutions should be deemed to have been recorded in this specification), unless such combination of technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed, and features C and D are equivalent technical means that play the same role. Technically, only one of them can be used, and it is impossible to use them at the same time. Feature E can be combined with feature C technically. Then, the solution of A+B+C+D should not be deemed to have been recorded because it is technically infeasible, while the solution of A+B+C+E should be deemed to have been recorded. BRIEF DESCRIPTION OF THE DRAWINGS

[0082] Figure 1 is an example of an improved hash tree according to an embodiment of the present application;

[0083] Figure 2 This is an example of adding an H13 node to a hash tree that already has 12 elements according to an embodiment of the present application;

[0084] Figure 3This is an example of adding an H14 node to a hash tree that already has 13 elements according to an embodiment of the present application;

[0085] Figure 4 This is an example of reading H7 and H12 nodes in a hash tree that already has 13 elements according to an embodiment of the present application;

[0086] Figure 5 This is an example of reading H7 and H10 nodes in a hash tree that already has 16 elements according to an embodiment of the present application;

[0087] Figure 6 is a schematic diagram of parallel processing of a hardware pipeline according to an embodiment of the present application;

[0088] Figure 7 This is an example table of correspondence between different leaf nodes and each level of the full reality tree according to an embodiment of the present application;

[0089] Figure 8 is an example of parallelized insertion of multiple leaves according to one embodiment of the present application;

[0090] Fig. 9 It is a schematic diagram of parallel calculation of two 64-bit full trees in one PE (processing unit) in a pipeline manner according to one embodiment of the present application;

[0091] Fig.10 It is a schematic diagram of the overall design of a database according to an embodiment of the present application. DETAILED DESCRIPTION

[0092] In the following description, many technical details are provided to help readers better understand the present application. However, those skilled in the art can understand that the technical solution claimed in the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0093] Description of some concepts:

[0094] DDR (Double Data Rate) is a memory technology that can transmit data on both the rising and falling edges of the clock signal. Therefore, double the data transmission rate can be achieved at the same clock frequency. This technology is widely used in the memory and graphics cards of computer systems.

[0095] QLC (Quad-Level Cell) is a flash memory technology. Each storage cell can store 4 bits of data (i.e. 16 different voltage states). Compared with traditional SLC, MLC and TLC storage technologies, it has higher storage density and lower cost, but it also faces problems of low durability and write speed.

[0096] SCM (Storage Class Memory) is a new storage technology that has both memory and storage characteristics. It combines the high-speed access characteristics of DRAM and the non-volatility of flash memory. It can retain data during power failure and provide access speeds close to the memory level, filling the performance gap between traditional memory and storage devices.

[0097] LSB (Least Significant Bit) refers to the rightmost bit in a binary number, which represents the smallest numerical unit.

[0098] TPS (Transactions Per Second) is a performance indicator to measure the system's processing capabilities. It indicates the number of transactions that the system can process per second. It is often used to evaluate the performance of transaction-intensive applications such as databases and payment systems.

[0099] The following is a brief description of some innovative aspects of the implementation methods of the present application.

[0100] The embodiment of the present invention introduces the concepts of physical nodes and virtual nodes in a binary hash tree. In the binary hash tree, each leaf position corresponds to a serial number. The leaf node with a serial number not greater than the maximum serial number of the data load in the key-value database is a physical node, and its value is the hash value of the corresponding data load. The leaf node with a larger serial number is a virtual node, and its value is a preset value. The preset value can generally be empty or other specific values, as long as it can be distinguished from a normal hash value. For a parent node, if any of its child nodes is a virtual node, then the parent node is a virtual node, and its value is equal to the value of its non-empty child node. Otherwise, the parent node is a physical node, and its value is the hash operation result of its two child nodes. The hash value of the parent node that is a virtual node is not calculated or stored. In other words, only the parent node in the complete entity subtree needs to calculate a new hash value, and the parent node in the incomplete entity subtree can directly copy the value of its non-empty child node. This mechanism significantly reduces the number of hash calculations and improves write efficiency.

[0101] The embodiment of the present invention also proposes an efficient data verification scheme: design a mechanism to form multiple complete entity subtrees from left to right and establish a root set; reduce the amount of verification data by generating a minimum verification path (only including the path from the target leaf node to the root node of the minimum complete entity subtree); adopt a double verification mechanism (the verification target node must be an element of the root set and the global root hash value can be calculated through the root set). These designs reduce the verification overhead while ensuring data integrity.

[0102] The embodiment of the present invention also proposes an optimized storage architecture: a three-level memory architecture is adopted to allocate nodes of different levels to memories of different speeds according to access characteristics; the complete subtree is matched with the storage page size of the solid-state drive to optimize storage space utilization; this hierarchical storage strategy improves data access efficiency.

[0103] The embodiment of the present invention also proposes a high-performance hardware acceleration design, including: designing multiple parallel long and short SHA256 calculation circuits; using a four-stage pipeline architecture to process batch reading and writing; implementing hardware-based fast index calculation, etc. These hardware optimizations significantly improve system performance.

[0104] In order to make the objectives, technical solutions and advantages of the present application more clear, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

[0105] In one embodiment, a method for implementing a verifiable key-value database includes:

[0106] An improved Merkle Shrubs hash tree structure is implemented in hardware, which achieves maximum storage bandwidth and storage life based on sequential writes and random reads. The data payload storage is written to the first memory in a journaled (Journal / Log) manner, and the transaction is written to the second memory in a serialized (transaction with ordinal) manner. Part of the MerkleShrubs is written to the second memory and the other part is written to the third memory. Optionally, the first memory can use QLC flash memory, the second memory can use SCM, and the third memory can use DDR. The first, second, and third memories can also use other types of memories. As long as the following conditions are met:

[0107] The first memory is a nonvolatile memory, the second memory is a nonvolatile memory, and the third memory may be a volatile memory (or may be a nonvolatile memory).

[0108] In terms of access speed, the first memory < the second memory < the third memory.

[0109] The design of the above memory types mainly considers the best compromise between performance and cost.

[0110] Real-time verification of write transactions is achieved in the following way: after writing key-value data, the database returns a root hash value and a string of verification hash values. The verification method is to concatenate the hash value of the written data with the verification hash value, and calculate the root hash value through a public fixed algorithm. After that, when performing any read operation, the root hash value returned by the database remains unchanged, and is still the root hash value when the write transaction is completed. All read operations can be verified using this root hash value.

[0111] With the support of a trusted execution environment (TEE) and authenticated firmware, verification of write transactions can be simplified as follows: TEE returns its signed verification data packet, which contains a verified timestamp, a monotonically increasing sequence number, a transaction hash value, and a verification hash value of the transaction.

[0112] Real-time verification of read transactions is achieved in the following way: Before the read operation, the client first obtains the latest root hash value pushed by the database. If there is no write operation, the root hash value remains unchanged. After reading the data, the database returns the data content and a string of verification hash values. The verification method is: concatenate the hash value of the data with the verification hash value, and calculate the root hash value through a public fixed algorithm.

[0113] This solution solves the core problem of traditional solutions: when the database performs read and write transactions, the search and calculation speed of the verification hash value is much slower than the read and write speed of the data payload. This solution provides a parallel computing solution so that the database's transaction processing per second (TPS) is no longer limited by the storage bandwidth, but can be linearly improved with the increase of SHA256 parallel computing units.

[0114] At the same time, this solution provides a cost-effective TEE solution: a TEE computing core containing authenticated firmware, protected DDR memory, and protected non-volatile memory (NVM). Large amounts of data payload are stored in low-cost NVM outside the TEE.

[0115] This implementation is mathematically extremely secure: it is difficult for a malicious attacker to forge a set of verification hash values ​​and root hash values ​​to pass the verification of the public fixed algorithm without actually writing the transaction. Similarly, in a read operation, it is also difficult to forge a string of verification hash values ​​for specific return data to obtain the correct root hash value through the public fixed algorithm.

[0116] This embodiment adopts an improved Merkle Shrubs hash tree structure, which calculates and stores fewer intermediate nodes than the traditional Merkle Tree, thereby improving calculation efficiency. Figure 1 , the specific implementation is as follows:

[0117] In this hash tree structure, the leaf node Hx represents the SHA256 hash value of the data payload of the transaction with serial number x. Among them, the Insert transaction and Update transaction correspond to the hash value Hx of the standard key-value pair {K:V} payload, while the Delete transaction and Hide transaction correspond to the hash value of the special {K:empty} payload. This structural design ensures that the entire improved Merkle Shrubs tree only supports two basic operations: append and read.

[0118] The transaction number is monotonically increasing, and the transactions in the database are continuously accumulated. The x in Hx represents the transaction number. The intermediate node is represented by H1-2, which represents the hash value obtained by calculating SHA256 after concatenating H1 and H2.

[0119] For the convenience of expression, the following two basic operators are defined in this application:

[0120] The "→" operator represents the fixed algorithm of calculating SHA256 level by level after sequentially concatenating the elements in the SHA256 set on the left, and the result is the value on the right;

[0121] The "+{}" operator means adding the elements on the left to the ordered set on the right in order.

[0122] When writing a transaction with sequence number x, the user writes data Data(x), and the database returns the global root hash value GlobalRoot(x), the root hash set RootSet(x), and the verification hash set ProofSet(x). The user verifies Hx+{ProofSet(x)}→W by calculation, and W should be an element in RootSet(x). To improve security, it is also necessary to verify RootSet(x)→GlobalRoot(x), especially when x is an odd number, because Hx itself is an element of RootSet(x). In an embodiment of the present application, the user is the requesting device. The requesting device is generally a computer device, including a processor (connected to the memory, hard disk, and communication interface through a bus), which is used to issue requests, obtain feedback results from the processor, and verify the correctness of the feedback results.

[0123] When reading a transaction with serial number y (y < x), the user holds GlobalRoot(x) and RootSet(x), and the database returns Data(y) and ProofSet(y). The user verifies Hy + {ProofSet(y)} → Z through calculation, and Z should be an element in RootSet(x). It is also necessary to verify the calculation process of RootSet(x) → GlobalRoot(x), especially when y is relatively close to x (such as log2(y - x) < 10), because the anti-interference ability is relatively low at this time. The global root hash value GlobalRoot(x) and the root set RootSet(x) for data reading verification can be obtained from reliable sources. For example, the global root hash value and the root set feedback during the previous write (it is necessary to ensure that the data read this time has been in the key-value database during this write), or from other reliable third parties, or provided by the key-value database during reading.

[0124] This embodiment adopts a full-tree design from left to right. For the convenience of hardware acceleration implementation, it is required to maintain an independent one-dimensional array ArrayIndex (array index) for each layer. In specific implementation, the 64-node full tree from layer L0 to L6 uses SCM storage units with a size of 4KB. This storage method facilitates the direct transfer of data to DDR without displacement operations.

[0125] The following further describes the implementation of the write operation of the improved Merkle Shrubs hash tree. The following is illustrated by specific examples:

[0126] As Figure 2 shown, when appending and writing H13:

[0127] The system generates a virtual global root hash GlobalRoot(13), that is, the virtual H1-16. The corresponding RootSet(13) contains three elements: H1-8, H9-12, and H13. ProofSet(13in13) is its own RootSet. (a in b) in the embodiments of this application represents the a-th node in the hash tree with a total of b nodes. During quick verification, it is only necessary to confirm that H13 exists in RootSet(13); during complete verification, it is necessary to calculate SHA256(H1-8, SHA256(H9-12, H13)) and verify that it is equal to GlobalRoot(13). Since 13 is an odd serial number, its RootSet is composed of a series of the highest Concrete tree roots from left to right and the node itself.

[0128] As Figure 3 shown, when appending and writing H14:

[0129] The system generates a virtual global root hash GlobalRoot(14), which is a virtual H1-16. The corresponding RootSet(14) contains: H1-8, H9-12, and H13-14. Its ProofSet(14in14) only contains H13. During quick verification, SHA256(H13,H14) is calculated and verified to be equal to H13-14; during full verification, SHA256(H1-8,SHA256(H9-12,SHA256(H13,H14))) is calculated and verified to be equal to GlobalRoot(14). Since 14 is an even number, its RootSet consists of a series of the highest entity tree roots from left to right, and its ProofSet is the RootSet corresponding to the number minus one.

[0130] This embodiment introduces the concept of virtual nodes and replaces the SHA256 calculation for virtual nodes with a simple copy operation. This is essentially different from the traditional Merkle Tree implementation: in the traditional implementation, each upper node is a concrete node. For example, when writing H13, H13-14 needs to exist as a concrete node and complete the actual copy storage, and the value of H13-14 needs to be rewritten when writing H14. After the introduction of virtual nodes, the overwriting operation of the tail node of each layer can be avoided.

[0131] After the append write operation is completed, several power-of-two entity trees are formed from left to right. The root nodes of these entity trees are combined in order from right to left to finally form a virtual total tree root. This design significantly reduces storage and computing overhead.

[0132] The following further describes the read operation implementation of the improved Merkle Shrubs hash tree:

[0133] refer to Figure 4 (The light-colored nodes (such as H14 to H18, H13-14, H15-16, H17-18, H13-16, H9-16) are virtual nodes, and H1-16 are virtual total tree roots). When the highest node is H13, the process of reading H7 is as follows:

[0134] GlobalRoot(13) is obtained by calculating SHA256(H1-8,SHA256(H9-12,H13)), and the corresponding RootSet(13) contains H1-8, H9-12, and H13. The system determines that ProofTarget(7in13) is H1-8, and generates ProofSet(7in13) containing H1-4, H5-6, H7, and H8. During quick verification, SHA256(H1-4,SHA256(H5-6,SHA256(H7,H8))) is calculated and verified to be equal to H1-8. During full verification, based on the quick verification, it is further verified whether GlobalRoot(13) can be calculated from RootSet(13).

[0135] refer to Figure 4 , when the highest node is H13, the process of reading H12 is as follows:

[0136] GlobalRoot(13) is obtained by calculating SHA256(H1-8,SHA256(H9-12,H13)), and the corresponding RootSet(13) contains H1-8, H9-12, and H13. The system determines that ProofTarget(12in13) is H9-12, and generates ProofSet(12in13) containing H9-10, H11, and H12. During fast verification, SHA256(H9-10,SHA256(H11,H12)) is calculated and verified to be equal to H9-12. During full verification, based on the fast verification, it is further verified whether GlobalRoot(13) can be calculated from RootSet(13).

[0137] The generation rule of the proof set is: starting from the target leaf node, search for paired nodes in each layer in order from low to high layers. If the current node is on the left, search for its paired node on the right; if it is on the right, search for its paired node on the left.

[0138] The ProofTarget is defined as: the root node of the complete entity tree that directly contains the target read leaf in the RootSet of the highest appended leaf.

[0139] The verification process (Proof) is: starting from the leaf node read, build up layer by layer. In each layer, find the paired node according to the node position (the left side finds the right side or the right side finds the left side), splice the paired nodes in order and calculate SHA256 to get the node of the previous layer. Repeat this process until the root node of a complete entity tree is reached.

[0140] The following further explains the verification mechanism of virtual nodes:

[0141] Take the case where the tree has accumulated to H13 and H7 needs to be verified as an example: when the tree accumulates to H13, the GlobalRoot of the entire tree is the virtual H1-16. It should be noted that the real H1-16 will only appear when H16 is also written into the tree. Since H14 to H16 have not been written yet, the RootSet corresponding to H13 contains three elements: H1-8, H9-12 and H13.

[0142] The calculation process of virtual root node H1-16 adopts a hierarchical virtual node processing method:

[0143] First, the virtual H1-16 is calculated as SHA256(H1-8+virtual H9-16); among them, the virtual H9-16 is calculated by SHA256(H9-12+virtual H13-16); the virtual H13-16 is calculated by SHA256(virtual H13-14+virtual H15-16); the virtual H13-14 is equal to SHA256(H13+virtual H14), because H14 is empty, H13-14 is directly equal to H13; the virtual H15-16 is calculated by SHA256(virtual H15+virtual H16), because H15 and H16 are both empty, so H15-16 is also empty.

[0144] In summary, the final calculation of the virtual H1-16 is simplified to: SHA256(H1-8+SHA256(H9-12+H13)). This calculation process actually reflects the SHA256 calculation of the path from the rightmost node H13 to the virtual root. Compared with the original Merkle Tree structure, this design significantly reduces the number of SHA256 calculations and improves the calculation efficiency.

[0145] The calculation process of the proof set (ProofSet) is further described below. Take two examples of reading H7 and H10 when the highest node is H16 as an example:

[0146] refer to Figure 5 , when reading H7: At this time, GlobalRoot(16) is the entity's H1-16, RootSet(16) only contains H1-16, and ProofTarget(7in16) is H1-16. The system-generated ProofSet(7in16) contains H1-4, H5-6, H7, H8, and H9-16.

[0147] refer to Figure 5, when reading H10: GlobalRoot(16) and RootSet(16) remain unchanged, ProofTarget(10in16) is H1-16. The ProofSet(10in16) generated by the system contains H9, H10, H11-12, H13-16, and H1-8.

[0148] To facilitate hardware implementation, this embodiment adopts a node representation method based on each layer index. Taking the calculation of the ProofSet of the target leaf H7 as an example, the Index calculation process from left to right is described in detail:

[0149] The target leaf number x=7 (binary 111b) has an index of 111b in the L0 layer. The specific calculation steps are as follows:

[0150] Step 1: In the L0 layer, 111b is the left-left node, and the right node needs to be found. 111b+1=1000b=8. So the right node found is H8. Push H8 into ProofSet. (The way to determine whether a node is left is when the LSB is 0, and the way to determine whether a node is right is when the LSB is 1. The left-to-right operation is +1, and the right-to-left operation is -1. H8 is represented by its Index=8 in the L0 layer. This design is for the convenience of hardware.).

[0151] Step 2: At the L0 layer, concatenate the left and right nodes to calculate SHA256, and then find the position of this calculation result at the L1 layer (using the right node for calculation). 1000b is shifted right by one position to get 100b=4. (The calculation method for calculating the index of the corresponding intermediate node at the previous layer from the index of the right node of this pair of leaf nodes at the L0 layer is simply to shift right by one position. This design is also for the convenience of hardware. The calculation result is H7-8, represented by its index=4 at the L1 layer)

[0152] Step 3: In the L1 layer, 100b is the right node, and the left node needs to be found. 100b-1=11b. So the left node H5-6 is found. H5-6 is pushed into the ProofSet. (Similarly, H5-6 is represented by its index=11b=3 in the L1 layer.)

[0153] Step 4: At the L1 layer, concatenate the left and right nodes to calculate SHA256, and then find the position of this calculation result at the L2 layer (using the right node). 100b is shifted right by one position to get 10b

[0154] Step 5: In the L2 layer, 10b is the right node, and the left node needs to be found, 10b-1=1b. Push H1-4 into the ProofSet (H1-4 is represented by its Index=1b=1 in the L2 layer).

[0155] Step 6: At the L2 layer, concatenate the left and right nodes to calculate SHA256, and then find the position of this calculation result at the L3 layer (using the right node). Shift 10b right by one position to get 1b.

[0156] Step 7: In the L3 layer, 1b is the left node, and the right node needs to be found, 1b+1=10b. Push H9-16 into the ProofSet (H9-16 is represented by its index=10b=2 in the L3 layer)

[0157] Step 8: At L3, concatenate the left and right nodes to calculate SHA256, and then find the position of this calculation result at L4 (using the right node). Shift 10b right by one position to get 1b.

[0158] Step 9: Reaching the L4 layer. This is a real root of the highest leaf H16, that is, reaching an element in the RootSet of the highest leaf, and successfully completing the push of the element in the ProofSet.

[0159] This index-based design significantly simplifies the hardware implementation, and all operations can be completed through simple bit operations: if the LSB (least significant bit) is 0, it can be determined as the left node (left sub-leaf) of the bottom-level binary tree; if the LSB is 1, it can be determined as the right node (right sub-leaf) of the bottom-level binary tree. The left node uses the plus 1 operation to search for the right node, the right node uses the minus 1 operation to search for the left node, and the level conversion uses the right shift operation.

[0160] The performance characteristics of the above embodiment are analyzed as follows:

[0161] Read transaction performance characteristics:

[0162] The complete hash tree from L0 to the root node is calculated and stored in the SCM and DDR when the data is written. Therefore, the ProofSet returned by the read transaction is directly read from the existing tree structure without recalculation. The number of processing operations per second (IOPS) of the read transaction is mainly limited by the speed of obtaining the L0 layer leaf hash value and its corresponding ProofSet from the SCM and DDR. After analysis and verification, the processing volume per second (TPS) of reading the ProofSet of a transaction is approximately equal to the IOPS of random reading of a 4KB SCM page.

[0163] Write transaction performance characteristics:

[0164] The write process requires calculating the L0 leaf hash value corresponding to the data, as well as the entire tree up to the virtual (or physical) root hash. Specifically: for 10 9 The height of the tree with leaf nodes ranges from L0 to L30; for 10 7The tree has leaf nodes, and its height ranges from L0 to L24; in the best case, only one hash value needs to be calculated (the rest are virtual copies of virtual nodes); in the worst case, 30 / 24 hash values ​​need to be calculated from leaf to root; the best to worst cases are evenly distributed, and on average half the number of hash values ​​of the tree height needs to be calculated.

[0165] The constraints on write transaction TPS (transactions per second) include:

[0166] 1. Parallel processing capability of long SHA256 calculation: Calculate 1KB data to obtain the hash value of a 32-byte leaf node.

[0167] 2. Parallel processing capability of short SHA256 calculations with an average half height in the tree structure from leaf nodes to root nodes (reducing the amount of calculation by 50% compared to traditional Merkle Tree).

[0168] 3. Data is written using the sequential APPEND method of NAND flash memory.

[0169] 4. Each 64-node full tree of the hash tree L0 to L6 layers is written using the sequential APPEND of the SCM 4KB page.

[0170] 5. Hash tree L7 to the root node is temporarily stored in DDR (the bandwidth is significantly higher than the above factors and does not constitute a bottleneck for the time being). The overall write performance is determined by the minimum bandwidth among the above factors. To achieve K TPS write performance, the system needs:

[0171] -K TPS long SHA256 computing power

[0172] -15*K TPS short SHA256 computing power

[0173] It can be seen that the TPS of write transactions is linearly related to the processing power of the SHA256 parallel computing engine.

[0174] In one embodiment, a hardware pipeline structure that supports parallel reading of multiple leaf nodes is used to simultaneously process ProofSet acquisition operations of multiple leaf nodes.

[0175] The verification process of each leaf node follows a unified pattern:

[0176] -First get the node hash value;

[0177] -Read the hash value of the peer partner;

[0178] -Concatenate the two hash values ​​and calculate the hash value of the upper node;

[0179] - Repeat the above "read-compute" dependency graph (DependGraph) until reaching the predefined root node.

[0180] Based on the storage hierarchy characteristics, the system divides the read operation into two parallel execution parts: the full tree of 64 nodes from L0 to L6 is stored in the 4KB page of SCM; the nodes at L7 and above are stored in DDR.

[0181] The parallel processing structure of the hardware pipeline is as follows Figure 6 As shown, Figure 6 Each column of is a time slice.

[0182] The processing of each leaf node is divided into four processing steps, and each processing step is processed in one processing resource. That is:

[0183] Processing resource 1: quickly calculate the index of each layer (step 1);

[0184] Processing resource 2: Read the relevant pages of L0-L6 layers from SCM and extract the ProofSet node (step 2);

[0185] Processing resource 3: reads L7 from DDR to the ProofSet node of the root node at the same time (step 3);

[0186] Processing resource 4: Returns the L0 value and complete ProofSet of the leaf node (step 4).

[0187] Different leaf nodes (such as Figure 6 Leaf 1 to Leaf 3 in the diagram are all processed by processing resources 1-4 in sequence, but at different times. For example, when processing resource 3 is processing step 3 of Leaf 1, resource 2 is processing step 2 of Leaf 2, and resource 1 is processing step 1 of Leaf 1.

[0188] Preferably, because the data is read from different memories (SCM and DDR), processing resource 2 and processing resource 3 can be further processed in parallel, that is, step 2 and step 3 can be processed simultaneously.

[0189] The performance of this pipeline design is mainly limited by the random read IOPS of 4KB pages in SCM, without the need for additional SHA256 calculation overhead. Through the parallel processing mechanism, the system can process ProofSet acquisition requests for multiple leaf nodes at the same time, significantly improving the overall read performance.

[0190] The following is an explanation of a hardware calculation acceleration solution for the RootSet of the highest leaf node in an embodiment. The main points of the solution are as follows:

[0191] Node addressing scheme: Nodes at each layer are numbered starting from 1; the serial number of the leaf node directly corresponds to its storage position in the L0 layer; each layer maintains a one-to-one correspondence between the serial number and the storage position.

[0192] Take the node with serial number 11 (H11) as an example. Since serial number 11 is less than 16, the 16-node tree is not filled; since the serial number is greater than 8, H1 to H8 have filled the 8-node full tree; H9 to H10 have filled the 2-node full tree; H11 alone has filled the 1-node full tree; and finally, from left to right, an 8-full tree, a 2-full tree, and a 1-full tree structure are formed.

[0193] This structure corresponds to the bit pattern of decimal 11 (binary 1011b). The bits from high to low correspond to full trees of different sizes; the root node of each full tree is located at the odd number position of the corresponding layer; L3, L1, and L0 are valued bit layers (layers corresponding to 1 in binary 1011b).

[0194] 8 The root of the whole tree is located at L3@1 (the first unit of the L3 layer); 2 The root of the whole tree is located at L1@5 (the fifth unit of the L1 layer); 1 The root of the whole tree is located at L0@11 (the eleventh unit of the L0 layer). The sequence number of each layer is just a truncated one-squared increment starting from the highest value bit.

[0195] The L2 layer is the valueless bit layer (the layer corresponding to 0 in binary 1011b), and the result after truncation is (10)b. This is not the root of a full tree.

[0196] For the highest leaf node with sequence number x, the calculation method of its RootSet is as follows:

[0197] 1. Convert the target sequence number x to binary representation.

[0198] 2. Start processing from the most significant bit (MSB):

[0199] - Determine the corresponding number of layers according to the position (see the one-to-one correspondence method for details) Figure 7 );

[0200] - check the value of the bit (1 or 0);

[0201] -If it is 1, the unit with index=1 in this layer is a RootSet element; if it is 0, there is no RootSet element in this layer.

[0202] 3. Processing the second highest position:

[0203] - Take MSB-1 and MSB;

[0204] -Determine the number of layers according to the MSB-1 position (see the one-to-one correspondence method for details) Figure 7 );

[0205] -If the MSB-1 bit is 1, the unit with index equal to the value of these two bits in this layer is a RootSet element; if the MSB-1 bit is 0, there is no RootSet element in this layer.

[0206] 4. Repeat the above process until all bits are processed.

[0207] The above calculation method can be processed in parallel, that is, all bits from MSB to LSB can be processed at the same time, thereby improving calculation efficiency.

[0208] The following describes a calculation method of ProofTarget in an embodiment, which is intended to determine the ProofTarget of a target leaf node from the RootSet of the highest leaf node.

[0209] Calculation principle:

[0210] -Check the full entity tree set (RootSet) of the highest leaf node from left to right (high to low)

[0211] - Start the search from the most significant bit of the highest leaf node number

[0212] The calculation process is divided into two cases:

[0213] Case 1: The target leaf node is located in the current full entity tree

[0214] -Judgment condition: The target leaf node number is less than or equal to the total number of nodes in the current full entity tree.

[0215] -Handling method: directly use the root node of the current full entity tree as ProofTarget.

[0216] - Example (13in 16): The target leaf node number is 13, and the highest leaf node number is 16 (binary 10000b); the 4th bit is 1, corresponding to a 16-node full tree; 13 is less than 16, so the root node (L4@1) of the 16-node full tree is ProofTarget.

[0217] Case 2: The target leaf node number exceeds the current full entity tree range

[0218] -Judgment condition: The target leaf node number is greater than the total number of nodes in the current full entity tree.

[0219] -Processing method:

[0220] - Subtract the total number of nodes in the current full entity tree from the target leaf node sequence number;

[0221] -Continue to check the full entity tree corresponding to the next valid bit

[0222] - Example (13in 14):

[0223] 1. First check the most significant bit L3 of the highest leaf node 14 (8-node full tree);

[0224] -13 is greater than 8, so execute 13-8=5.

[0225] 2. Check the next valid bit L2 (4-node full tree);

[0226] -5 is greater than 4, so 5-4=1 is executed.

[0227] 3. Check the next valid bit L1 (2-node full tree);

[0228] -1 is less than 2, so the 2-node full tree with ProofTarget 14 is determined;

[0229] -The index value of the root in L1 layer is 111b;

[0230] -Index value calculation method: take the position of the 2-node full tree corresponding to the layer (L1) of the highest leaf node 14 and the binary value composed of all the bits above it.

[0231] This design method supports efficient hardware implementation and can quickly determine the ProofTarget of any target leaf node through layer-by-layer comparison and calculation.

[0232] In one embodiment, when ProofTarget is known, the instruction sequence for calculating ProofSet is generated as follows. Take ProofTarget (13in 16) as an example:

[0233] Initialization process:

[0234] -Convert the leaf number to binary (13=1011b);

[0235] -Confirm that the target ProofTarget is located at L4@1;

[0236] -Establish hierarchical mapping: the lowest bit corresponds to L0, and so on up to L4.

[0237] ProofSet construction steps:

[0238] 1. Initialization: Insert the target leaf node {L0@13}.

[0239] 2.L0 layer processing:

[0240] - 1101b is detected as an odd left subtree;

[0241] - Calculate the corresponding even right subtree number 1110b (14);

[0242] -Insert the right node to form {L0@13,L0@14};

[0243] -Right shift 1110b to obtain 111b as the L1 layer sequence number.

[0244] 3.L1 layer processing:

[0245] - 111b is detected as an odd left subtree;

[0246] - Calculate the corresponding even right subtree number 1000b (8);

[0247] -Insert the right node to form {{L0@13,L0@14},L1@8};

[0248] - Shift right by 1000b to get 100b as the L2 layer sequence number.

[0249] 4.L2 layer processing:

[0250] - 100b is detected as an even right subtree;

[0251] - Calculate the corresponding odd left subtree number 11b(3);

[0252] -Insert the left node to form {L2@3,{{L0@13,L0@14},L1@8}};

[0253] - Shift right by 100b to get 10b as the L3 layer sequence number.

[0254] 5.L3 layer processing:

[0255] - 10b is detected as an even right subtree;

[0256] -Calculate the corresponding odd left subtree number 1b;

[0257] -Insert the left node to form {L3@1,L2@3,{{L0@13,L0@14},L1@8}}}; -Shift right by 1b to get 0b.

[0258] 6. Arrive at the L4 layer (the layer where ProofTarget is located) and complete the calculation.

[0259] Instruction sequence optimization:

[0260] 1. Basic instruction sequence:

[0261] {L0@13 is pushed into the stack,

[0262] L0@14 is pushed onto the stack and then right-combined.

[0263] L1@8 is pushed into the stack and then right-combined.

[0264] L2@3 is pushed onto the stack and then left combined.

[0265] L3@1 is pushed into the stack and then left combined.

[0266] Compare the top of the stack with ProofTarget}

[0267] 2. Simplified instruction sequence:

[0268] {Start:Data(L0@13),

[0269] Right:Data(L0@14),

[0270] Right:Data(L1@8),

[0271] Left:Data(L2@3),

[0272] Left:Data(L3@1),

[0273] Compare:Data(L4@1)}

[0274] Optimization features:

[0275] - Supports performing SHA256 value reads only, deferring merge calculations to the client.

[0276] -Use the parity of node index to directly correspond to left-join and right-join operations.

[0277] -Applicable to 64 full-tree hierarchical design, hierarchical scheduling during instruction execution follows the established scheme.

[0278] -Supports flexible instruction sequence generation, such as ProofSet (14in16) can generate corresponding optimized instruction sequences.

[0279] This design method achieves efficient hardware acceleration and instruction optimization while ensuring correctness.

[0280] In one embodiment, ProofSet is calculated by short calculation when ProofTarget is known. Take the calculation of ProofSet(13) when ProofTarget(13in 14) is known as an example:

[0281] The target leaf number is converted to binary (13=1011b), confirming that ProofTarget is located at L1@7, and establishing a hierarchical mapping: the lowest bit corresponds to L0, up to L1 (the layer where ProofTarget is located).

[0282] ProofSet construction steps:

[0283] 1. Insert the target leaf node {L0@13}

[0284] 2.L0 layer processing:

[0285] - Detected that 1101b is an odd left subtree

[0286] - Calculate the corresponding even right subtree number 1110b (14)

[0287] -Insert the right node to form {L0@13,L0@14}

[0288] - Shift right by 1110b to get 111b as the L1 layer number

[0289] 3.L1 layer processing:

[0290] - Detected that the ProofTarget layer has been reached

[0291] - Verify that 111b(7) is equal to the ProofTarget sequence number

[0292] -Complete calculation

[0293] Simplified instruction sequence:

[0294] {Start:Data(L0@13),

[0295] Right:Data(L0@14),

[0296] Compare:Data(L1@7)}

[0297] In one embodiment, the virtual GlobalRoot is calculated level by level from right to left. Specifically, starting from the two rightmost elements in the RootSet, the SHA256 hash values ​​are calculated level by level until all elements are processed.

[0298] The reverse processing order can match the previous algorithm design because the construction process of RootSet is gradually pushed from the highest level of the tree to the lowest level (for example, using a stack). This order maintains the continuity of calculations and the locality of data, ensuring the correct combination order of virtual nodes. This design method is coordinated with the data flow of the entire system, effectively supports the processing mechanism of virtual nodes, and maintains computational efficiency.

[0299] In one embodiment, the parallel insertion of multiple leaf nodes is further optimized. Parallel insertion can omit unnecessary calculation of VirtualGlobalRoot.

[0300] Figure 8 An example is shown in which H12 is ready and H13 to H18 are written.

[0301] Corresponding to the 64 full tree layers in SCM, the design is as follows:

[0302] From L0 to L6:

[0303] ·64 When the full tree goes directly from empty to full, the calculation of the entire tree is first completed in DDR and then stored in SCM.

[0304] When the 64-bit tree goes from empty to half full, the virtual node design is still used in DDR to calculate the virtual root of the tree. It will not be written to the disk unless there is an emergency such as a power outage.

[0305] When the 64-tree is half full and then fully filled, after the DDR is filled with the full tree, the original virtual nodes are discarded and the entire 64-tree to the root is recalculated.

[0306] From L7 layer to Lroot layer: Calculate GlobalRoot according to virtual nodes.

[0307] Compared with inserting only one leaf node, inserting multiple leaf nodes means that multiple upper-level nodes are changed from virtual nodes (copy type) to nodes that need to be actually calculated.

[0308] Generally speaking, the length of the data payload is greater than the length of the SHA256 value. Therefore, the calculation of the L0 layer is slower than that of the L1 and upper layers. Therefore, an intuitive scheduling is to read the tail of L0 first and then calculate the entire L0 layer (calculate in pairs from left to right, and then append and write). Then read the tail of L1 and then calculate the entire L1 layer. Then go up. The calculation and throughput mode of each layer in the L1 layer is (optional) tail reading, pair calculation, and the result is appended to the previous layer. The next pair is calculated in pairs, and the result is appended to the previous layer until there are no new units in this layer. Compared with the above rules, the calculation and throughput mode of the L0 layer is to first calculate each new unit of this layer (L0) from the data payload, and then process it in the same way as in the previous L1 layer. This embodiment can write multiple back-to-back results in a layer at one time, and because multiple SHA256 results can be pieced together to form a NAND page, this solution can better play the write advantage of NAND.

[0309] The following example analyzes the hardware bottleneck problem when writing transactions to the database.

[0310] According to an embodiment of the present application, L0 to L6 are in the 4KB page of SCM and L7 to Lroot (the layer where the tree root is located) are in DDR, and the storage bandwidth is no longer a bottleneck.

[0311] The computational effort required to calculate a 64-bit full tree includes 64, serial 32, 16, 8, 4, 2, and 1 short SHA256. Here, long SHA256 refers to calculating SHA256 from the usually longer original data, and short SHA256 refers to calculating the SHA256 of a higher-level node from the SHA256 of a lower-level node. Theoretically, if the computational resources for 64 parallel long SHA256 and 63 short SHA256 are prepared, two 64-bit full trees can be calculated in parallel (pipeline).

[0312] Several processing units can be set in the system, and each processing unit has 64 parallel long SHA256 calculation circuits and 32 parallel short SHA256 calculation circuits. The calculation circuit here can be a hardware circuit for implementing SHA256 calculation. There are many types of such hardware circuits in the prior art, which will not be described in detail in this application. The 64 parallel long SHA256 calculation circuits calculate 64 SHA256 as L0 leaf nodes based on the 64 records input, starting from the 32 parallel short SHA256 calculation circuits, and the calculation results are combined in pairs, and then through 16-way parallel calculation, 8-way parallel calculation, 4-way parallel calculation, and 2-way parallel calculation, they are finally converged into a single-way calculation to obtain the final calculation result.

[0313] like Fig. 9 As shown in the figure, there are four steps in the pipeline processing, namely: read Data until a 64-bit full tree is full; calculate 64 parallel long SHA256s of the LO layer of this 64-bit full tree; serial 32, 16, 8, 42, and 1 short SHA256s; write this tree to SCM. In one processing unit, two 64-bit full trees are calculated in parallel, and finally L7~Lroot is calculated from the roots of these 64-bit full trees, and L7~Lroot is lazily committed (Lazy Commit). The horizontal axis in the figure is time, which is just a schematic and does not accurately represent the actual duration of each step.

[0314] Taking 1 million records as an example, there are 14 layers to be calculated from L7 to L24. The widest layer requires 2 14 =16K short SHA256.

[0315] Through the above design, the present application basically moves the bottleneck of the database's TPS from the storage bandwidth to the bandwidth of the PE (processing unit) of SHA256.

[0316] The following is an analysis of the performance bottleneck of database read transactions: parallel reading of ProofSets of multiple leaves.

[0317] System parameter settings: database capacity is 1 billion transactions; single transaction data load is 1KB; total data load space is 1TB; total hash tree space is 64GB; parallel reading scale is 128 leaf nodes.

[0318] Storage level design:

[0319] 1.SCM storage (about 63.5GB):

[0320] - Each 4KB page stores a 64-node full tree from L0 to L6;

[0321] -Page structure:

[0322] (L0-1,...,L0-64,

[0323] L1-1,...,L1-32,

[0324] L2-1,...,L2-16,

[0325] L3-1,...,L3-8,

[0326] L4-1,...,L4-4,

[0327] L5-1,L5-2,

[0328] L6-1)

[0329] -SCM page structure is the same as in DDR, supporting direct data migration;

[0330] -The conversion from layer number and sequence number within the layer to address within the page uses a fixed formula and supports hardware implementation.

[0331] 2.DDR storage (512MB): stores L7 and higher-level nodes.

[0332] Parallel read optimization: Reading 128 randomly distributed leaf ProofSets in parallel is equivalent to reading a 64-node full tree from 128 4KB pages at random addresses; then extracting the corresponding 7 elements from L0 to L6 from each full tree. Because it is a completely random 32-byte read, the read amplification is reduced from 128 times to 128 / 7 times.

[0333] When writing, it is necessary to handle the situation where the 64 full trees on the far right are incomplete (in memory, ensure that they are flushed into SCM before power failure).

[0334] Special case handling: When writing, the situation where the full tree of the rightmost 64 nodes is incomplete must be handled. The incomplete tree is kept in the DDR, and it is necessary to ensure that it is written to the SCM before the DDR is powered off.

[0335] Key points for performance optimization: Utilize the NAND page size feature; Give full play to data locality; Hardwareize address conversion calculation to increase speed; Minimize random read overhead.

[0336] This design significantly reduces the read amplification effect and improves the overall read performance of the system through optimized storage structure and parallel read strategy.

[0337] In one embodiment, the system of the verifiable key-value database includes: a visible layer in the host computer main memory, a middle layer on the device side, and an innermost layer. The overall design of the database is as follows Fig.10 shown.

[0338] Multiple visual windows are set in the visual layer of the host computer's main memory. Each window presents the mapping relationship between primary key and data payload to the outside, and implements the mapping relationship between primary key and transaction handle internally. Each window corresponds to a snapshot of a specific version of the database. The visual layer uses the computing and storage resources of the host computer to provide flexible multi-primary key construction and query functions, and can be rebuilt from the middle layer and the innermost layer. To optimize performance, the visual layer supports multi-level caching strategies, including a non-cached security mode, a first-level acceleration mode that caches the data payload addressing handle after obfuscated hashing, and a second-level acceleration mode that directly caches the data payload.

[0339] The middle layer on the device side implements serialized transaction log management, assigning a unique serial number and external handle to each transaction. The log records the serial number, data payload index, data payload hash value, and related signature information. The middle layer uses an improved log hash tree structure, which is designed based on the transaction serialization mechanism. The transaction handle is more secure through device-specific obfuscated hashing, which remains unchanged during the life cycle of the device.

[0340] The innermost layer of the device side maintains the data payload log to achieve a one-to-one correspondence between transaction actions and payload units. Each payload unit contains a complete key-value pair or data record. The middle layer uses SCM storage media, while the data payload log uses QLC storage media to balance performance and cost. The system supports the parallel use of storage bandwidth, can obtain data payload and hash proof at the same time, and simplifies the design structure through a strict sequential write random read mode. Although the transaction action log must be obtained before the data payload can be accessed, the performance loss can be effectively alleviated by storing the middle layer through SCM.

[0341] The system builds a version chain through the leading transaction sequence number, supports data version control, facilitates external review, and reserves expansion space to support future business needs. The host computer CPU is responsible for performing operations such as primary key search and transaction type judgment. This layered architecture ensures data verifiability while achieving a balance between performance and security through multi-level caching and optimized storage strategies.

[0342] In summary, the embodiments of the present application provide a verifiable key-value database system for data centers, which is used to support secure hosting services for multi-party data cooperation. The system provides real-time verifiability protection for data hosting through the trusted computing circuit built into the disk or array, ensuring the confidentiality, consistency, integrity and non-repudiation of the data. The system can provide customers with proof in real time to verify that the hosted data has not been destroyed by the custodian or malicious third party. At the same time, the system can prove that the full database obtained by the customer after payment is identical to the database selected (CherryPick) before payment.

[0343] The technical advantage of the embodiment of the present application is that the system cost is significantly reduced by optimizing the storage and memory bandwidth utilization and the parallel calculation of SHA256. Compared with the same performance system using the server trusted computing solution, the embodiment of the present application has a significant cost advantage.

[0344] At present, the field of data cooperation and transaction matching is in the exploration stage of legal authority and value assessment. Large Internet companies and authorized innovative companies are exploring verifiable database products based on data centers. As products based on server trusted computing solutions gradually form a performance and price competition pattern, the system described in the embodiment of this application will have a broad market application space.

[0345] Accordingly, the embodiments of the present application also provide a computer-readable storage medium, in which computer executable instructions are stored, and when the computer executable instructions are executed by the processor, the various method embodiments of the present application are implemented. Computer-readable storage media include permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be a computer-readable instruction, a data structure, a module of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. According to the definition herein, computer-readable storage media do not include transient computer-readable media (transitory media), such as modulated data signals and carriers.

[0346] In addition, the embodiment of the present application also provides a data reading and writing system for a key-value database, which includes a memory for storing computer executable instructions, and a processor; the processor is used to implement the steps in the above-mentioned method implementation when executing the computer executable instructions in the memory. Among them, the processor can be a central processing unit (Central Processing Unit, referred to as "CPU"), a graphic processor (Graphic Processing Unit, referred to as "GPU"), a digital signal processor (Digital Signal Processor, referred to as "DSP"), a microcontroller unit (Microcontroller Unit, referred to as "MCU"), a neural network processor (referred to as "NPU"), an application-specific integrated circuit (Application Specific Integrated Circuit, referred to as "ASIC"), a field programmable gate array (Field Programmable Gate Array, referred to as "FPGA") or other programmable logic devices, etc. The aforementioned memory can be a read-only memory (read-only memory, referred to as "ROM"), a random access memory (random access memory, referred to as "RAM"), a flash memory (Flash), a hard disk or a solid-state hard disk, etc. The steps of the method disclosed in each embodiment of the present invention can be directly embodied as a hardware processor to be executed, or a combination of hardware and software modules in the processor can be executed.

[0347] In addition, an embodiment of the present application further provides a computer program product, which includes computer executable instructions, and when the computer executable instructions are executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0348] It should be noted that, in the present application, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the sentence "include one" do not exclude the existence of other identical elements in the process, method, article or equipment including the elements. In the present application, if it is mentioned that a certain action is performed according to a certain element, it means at least the meaning of performing the action according to the element, which includes two situations: performing the action only according to the element and performing the action according to the element and other elements. Multiple, multiple, multiple, etc. expressions include 2, 2 times, 2 kinds and more than 2, more than 2 times, more than 2 kinds.

[0349] The serial numbers used in describing the steps of a method do not themselves constitute any limitation on the order of these steps. For example, the step with a larger serial number does not necessarily have to be executed after the step with a smaller serial number. The step with a larger serial number may be executed first and then the step with a smaller serial number, or they may be executed in parallel, as long as the execution order is reasonable to those skilled in the art.

[0350] This specification includes combinations of the various embodiments described herein. Individual references to embodiments (e.g., "one embodiment" or "some embodiments" or "preferred embodiments"); however, these embodiments are not mutually exclusive unless indicated as mutually exclusive or it is clear to a person skilled in the art that they are mutually exclusive. It should be noted that the word "or" is used in this specification in a non-exclusive sense unless the context clearly indicates or requires otherwise.

[0351] All documents mentioned in this specification are considered to be included in the disclosure of this application as a whole, so that they can be used as a basis for modification when necessary. In addition, it should be understood that the above is only a preferred embodiment of this specification and is not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of one or more embodiments of this specification should be included in the scope of protection of one or more embodiments of this specification.

[0352] In some cases, the actions or steps described in the claims may be performed in a different order than in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

Claims

1. A method for writing data into a key-value database, characterized in that: include: The processor receives a write request, wherein the write request includes key-value pair data; The processor writes the key-value pair data into the first memory as a data payload; The processor calculates a hash value of the data payload, and writes the hash value into a binary hash tree stored in a fourth memory as the highest leaf node with the largest current sequence number; In the binary hash tree, the sequence number of each leaf node increases in sequence. The leaf node with a sequence number not greater than the highest leaf node is a physical node, and its value is the hash value of the corresponding data load. The leaf node with a sequence number greater than the highest leaf node is a virtual node, and its value is a preset value. The processor determines whether parent nodes of all levels corresponding to the highest leaf node are located in a complete entity subtree from the leaf node to the root node, wherein the complete entity subtree is a subtree that does not contain a virtual node; In response to determining that the parent node is located in the complete entity subtree, the parent node is used as an entity node, a hash value of the parent node is calculated according to hash values ​​of two child nodes of the parent node, and the hash value of the parent node is stored in the fourth memory; In response to determining that the parent node is not located in the complete entity subtree, the parent node is used as a virtual node. When the hash value of the parent node needs to be obtained, the value of the child node of the parent node without the preset value is directly used as the hash value of the parent node.

2. The method for writing data into a key-value database according to claim 1, characterized in that: Also includes: A plurality of complete entity subtrees are formed from left to right in the binary hash tree, and the processor adds the root node of each complete entity subtree to the root set; The processor obtains a global root hash value by calculating hash values ​​for nodes in the root set from right to left level by level; The processor calculates the verification hash set, specifically including: starting from the leaf node, in order from low layer to high layer, if the current node is on the left, then searching for the hash value of the paired node on the right side of the node in each layer; if the current node is on the right side, then searching for the hash value of the paired node on the left side of the node, and adding the hash value of the found paired node to the verification hash set; The processor returns data for verifying the write operation to the requesting device, the data including: the global root hash value, the root hash set, and the verification hash set.

3. The method for writing data into a key-value database according to claim 2, characterized in that: The requesting device verifies the correctness of the write in the following manner: A verification target node is calculated based on the verification hash set and the hash value of the leaf node, and the verification target node should be an element in the root set; and The global root hash value can be obtained by calculating the hash value of each element in the root set step by step.

4. The method for writing data into a key-value database according to claim 1, characterized in that: The fourth memory includes a second memory and a third memory; the first memory and the second memory are non-volatile memories; the access speeds of the first memory, the second memory, and the third memory increase in sequence; The nodes from the 0th to the Nth layers of the binary hash tree are stored in the second memory, wherein the nodes from the 0th to the Nth layers form at least one complete subtree, and each of the complete subtrees is stored in a page of the second memory, and the storage space size of the complete subtree is the same as the size of the page; the nodes from the N+1th layer and higher layers of the binary hash tree are stored in the third memory; wherein N is a preset positive integer.

5. The method for writing data into a key-value database according to claim 4, characterized in that: In each page of the second memory, the nodes of each layer of a complete subtree are stored layer by layer from layer 0 to layer N; the sequence number of the leaf node is directly used as its storage position in layer 0; and a one-to-one correspondence between the node sequence number and the storage position is maintained in each layer. The processor includes multiple parallel long SHA256 calculation circuits and multiple parallel short SHA256 calculation circuits, wherein the long SHA256 calculation circuit is used to parallelly calculate the hash value of each leaf node in a page according to the data load, and the short SHA256 calculation circuit is used to perform pairwise combination calculations on each leaf node in a page to obtain the parent node of the first layer, and then perform multi-path parallel calculations layer by layer from bottom to top in sequence, and finally converge into a single-path calculation to obtain the root node hash value of the complete subtree.

6. The method for writing data into a key-value database according to claim 5, characterized in that: Also includes: For a complete subtree from empty to half full, use the virtual node to calculate the virtual root hash value of the complete subtree; For a complete subtree from half full to full, after it is supplemented into a full tree, the original virtual node is discarded and the hash value of the entire complete subtree to the root is recalculated.

7. The method for writing data into a key-value database according to claim 5, characterized in that: When writing key-value pairs in batches, the following pipeline is used for processing: In the first pipeline stage, 64 key-value pairs are read to form a complete subtree; In the second pipeline stage, 64 parallel SHA256 calculation circuits are used to calculate the hash values ​​of the 64 key-value pair data as leaf nodes; In the third pipeline stage, 32 parallel SHA256 computing circuits are used to perform pairwise calculations on the leaf nodes, and the hash values ​​of the nodes at each layer of the complete subtree are obtained through 16-way parallel calculation, 8-way parallel calculation, 4-way parallel calculation, 2-way parallel calculation and single-way calculation in sequence; In the fourth pipeline stage, the node hash value of the complete subtree is written into a 4KB page of the second memory.

8. A method for reading data from a key-value database, characterized in that: The key-value pair data is stored in a first memory as a data load with increasing serial numbers, and a binary hash tree is stored in a fourth memory; in the binary hash tree, each leaf position corresponds to a serial number, and a leaf node with a serial number not greater than the maximum serial number of the data load in the first memory is a physical node, and its value is the hash value of the corresponding data load, and a leaf node with a larger serial number is a virtual node, and its value is a preset value; for a parent node, if any of its child nodes is a virtual node, then the parent node is a virtual node, and its value is equal to the value of its child node with a non-preset value, otherwise the parent node is a physical node, and its value is the hash operation result of its two child nodes; the method includes: The processor receives a read request from a requesting device, and reads the requested data payload from the first memory, wherein the leaf node corresponding to the data payload is a target leaf node; The processor generates a verification hash set of the target leaf node, wherein the elements in the verification hash set are paired nodes at each layer on the path from the target leaf node to the verification target node in the binary hash tree; the verification target node is the root node of the smallest complete entity subtree containing the target leaf node; the complete entity subtree is a subtree that does not contain a virtual node; The processor returns the requested data payload and verification hash set to the requesting device.

9. The method for reading data from a key-value database according to claim 8, wherein: The requesting device verifies the correctness of the read data by: Obtain a global root hash value and a root set, wherein the global root hash value is the hash value of the root node of the binary hash tree, and the root set includes the root nodes of a plurality of complete entity subtrees from left to right in the binary hash tree; A verification target node is calculated according to the verification hash set and the hash value of the target leaf node, and the verification target node should be an element in the root set; The global root hash value can be obtained by calculating the hash value of each element in the root set step by step.

10. The method for reading data from a key-value database according to claim 8, wherein: The processor determines the verification target node by the following steps: Starting from the most significant bit of the sequence number of the current highest leaf node of the binary hash tree, check the corresponding complete entity subtree; If the sequence number of the target leaf node is less than or equal to the total number of nodes in the current complete entity subtree, the root node of the current complete entity subtree is used as the verification target node; If the sequence number of the target leaf node is greater than the total number of nodes in the current complete entity subtree, subtract the total number of nodes in the current complete entity subtree from the sequence number of the target leaf node, and continue to check the complete entity subtree corresponding to the next valid bit until the complete entity subtree containing the target leaf node is found.

11. The method for reading data from a key-value database according to claim 8, wherein: The step of the processor generating the verification hash set comprises: Convert the sequence number of the target leaf node into binary; Establish a hierarchical mapping, with the lowest bit corresponding to layer 0; Start processing layer by layer from the target leaf node: detect whether the current node is an odd left subtree or an even right subtree, if it is an odd left subtree, calculate the corresponding even right subtree sequence number and add it to the verification hash set; if it is an even right subtree, calculate the corresponding odd left subtree sequence number and add it to the verification hash set, until the layer where the verification target node is located is reached.

12. The method for reading data from a key-value database according to claim 8, wherein: The fourth memory includes a second memory and a third memory; the first memory and the second memory are non-volatile memories; the access speeds of the first memory, the second memory and the third memory increase in sequence; The nodes from the 0th to the Nth layers of the binary hash tree are stored in the second memory, wherein the nodes from the 0th to the Nth layers form at least one complete subtree, and each of the complete subtrees is stored in a page of the second memory, and the storage space size of the complete subtree is the same as the size of the page; the nodes from the N+1th layer and higher layers of the binary hash tree are stored in the third memory; wherein N is a preset positive integer.

13. The method for reading data from a key-value database according to claim 11, wherein: The processor determines the path from the target leaf node to the verification target node by the following index-based hardware calculation method: Convert the target leaf number into binary as the index of layer 0; In each layer of processing: Determine the node type by checking the least significant bit. If the least significant bit is 0, it is a left node, and if it is 1, it is a right node. For a left node, add 1 to find its right paired node; for a right node, subtract 1 to find its left paired node; Get the corresponding index of the previous layer by right shifting 1 bit; Repeat the above process until the layer where the verification target node is located is reached.

14. The method for reading data from a key-value database according to claim 12, wherein: The processor uses a hardware pipeline structure to process read requests of multiple leaf nodes in parallel, including: The first processing resource calculates the indexes of each layer of multiple target leaf nodes in parallel through bit operations; The second processing resource is used to read the nodes of level 0 to level 6 in multiple 4KB pages from the second memory in parallel and extract the nodes in the verification hash set; The third processing resource is used to read in parallel from the third memory the nodes in the verification hash set from the 7th layer to the root node corresponding to the plurality of target leaf nodes; The fourth processing resource includes a plurality of parallel SHA256 calculation circuits for calculating hash values ​​of a plurality of verification paths in parallel and returning a complete verification hash set.

15. The method for reading data from a key-value database according to claim 14, wherein: The processor comprises: Hardware acceleration circuit for calculating SHA256 hash value, including: Multiple parallel long SHA256 calculation circuits for calculating the hash value of the data payload; Multiple parallel short SHA256 calculation circuits are used to calculate the node hash values ​​on the verification path; The processor supports the use of multiple SHA256 computing circuits for parallel processing during the verification process.

16. A non-transitory computer-readable storage medium, characterized in that: The non-transitory computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the steps in the method according to any one of claims 1 to 15 are implemented.

17. A computer program product comprising computer executable instructions, characterized in that: When the computer executable instructions are executed by a processor, the steps in the method described in any one of claims 1 to 15 are implemented.

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