Compensation method for optimizing conductance drift of phase change memory
By fitting the conductance drift model of the phase change memory and calculating the compensated conductance value, the problem of conductance drift of the phase change memory in Bayesian neural network is solved, reducing the difficulty of implementing the hardware neural network and improving network performance.
Patent Information
- Application Number
- CN202411820068.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-11
- Publication Date
- 2025-04-04
AI Technical Summary
Phase change memory has conductance drift problems in Bayesian neural networks, resulting in weight matrix offset and affecting network performance.
By fitting the conductance drift model of the phase change memory, the device conductance drift coefficient is obtained, the conductance drift curve and the average conductance value are calculated, the conductance measured value after subtracting the conductance drift curve, and adding the average conductance value to obtain the compensated conductance value.
Effectively compensates for the conductance drift of phase change memory, reduces the difficulty of implementing hardware neural networks, and improves the performance of Bayesian deep neural networks.
Smart Images
Figure CN119760329A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of deep neural networks, and in particular to a compensation method for optimizing conductance drift of a phase change memory. Background Art
[0002] Over the past half century, the improvement of chip computing performance has mainly relied on the reduction of CMOS transistor size. As the feature size decreases, the device preparation cost and manufacturing process difficulty continue to increase, and the device size is approaching the physical limit. The era of Moore's Law is about to face the "end".
[0003] The rapid development of artificial intelligence, big data, and deep neural networks has put forward higher requirements on the computing power of traditional hardware platforms. The von Neumann architecture is the mainstream architecture of computers in the world. Hardware platforms based on the von Neumann computing architecture will be restricted by the "storage wall" when processing related tasks. A large amount of data will flow between the computing unit and the storage unit, and the computing speed of the computing unit is much higher than the reading speed of the storage unit. The operation process of accessing the memory accounts for the vast majority of the overall energy consumption and delay, which limits the data processing speed. In computing tasks that require processing large amounts of data, the problems brought by "memory" are more prominent.
[0004] Unlike the von Neumann architecture, in the human brain, which is characterized by massive parallelism, self-adaptation, and self-learning, there is no clear dividing line between information storage and computation, and both are accomplished using neurons and synapses. The characteristics of memristors are very similar to those of synapses. Synapses can change their weights according to the stimulation of previous and subsequent neurons, while memristors can change their conductance values by adjusting the applied voltage. The use of new memristors such as phase change memory can achieve data storage while also enabling in-situ computing, thereby realizing storage-computing integration and neural networks, fundamentally eliminating the limitations of the "storage wall".
[0005] Phase change memory has some non-ideal characteristics, which limit its application in Bayesian neural networks. Among them, the conductance drift causes the weight matrix of the Bayesian neural network to shift as a whole, which ultimately affects the performance of the network. In recent years, several solutions have been proposed to address the conductance drift problem, such as (i) multiplying the activation function by a compensation factor that varies with time; (ii) multiplying the input voltage by a compensation factor that varies with time. These solutions greatly increase the complexity of the system and are difficult to implement. Therefore, it is necessary to design a compensation method for optimizing the conductance drift of phase change memory to solve the above technical problems. Summary of the invention
[0006] The technical problem to be solved by the present invention is to provide a compensation method for optimizing the conductivity drift of a phase change memory, which can effectively compensate for the conductivity drift of the phase change memory.
[0007] The technical solution adopted by the present invention to solve the technical problem is: to provide a compensation method for optimizing the conductivity drift of a phase change memory, comprising the following steps:
[0008] According to the conductance drift model of the phase change memory, the conductance drift data of the actual phase change memory device is used for fitting to obtain the conductance drift coefficient of the device;
[0009] Substituting the device conductivity drift coefficient into the conductivity drift model to obtain a conductivity drift curve and an average conductivity value of the phase change memory;
[0010] Subtracting the conductance of the phase change memory obtained according to the conductance drift curve from the conductance measurement value of the phase change memory to obtain conductance random noise;
[0011] The conductance random noise is added to the average conductance value to obtain a compensated conductance value of the phase change memory device.
[0012] The conductivity drift model of the phase change memory is expressed as: Among them, G t is the conductance of the phase change memory at time t, G0 is the initial conductance of the phase change memory, t0 is the initial time, and v is the device conductance drift coefficient.
[0013] The calculation formula of the average conductance value is: Among them, G avg is the average conductivity value, G t is the conductance of the phase change memory at time t, and t0 is the initial time.
[0014] The calculation formula of the conductance random noise is: , where G rand is the conductance random noise, G meas is the conductivity measurement value of the phase change memory, is the conductance of the phase change memory obtained according to the conductance drift curve.
[0015] The calculation formula of the conductance value after compensation of the phase change memory device is: fnl =G rand +G avg , where G fnl is the compensated conductance value of the phase change memory device, G rand is the conductance random noise, G avg is the average conductivity value.
[0016] The technical solution adopted by the present invention to solve its technical problem is: providing a phase change memory array, each row of storage cells includes a plurality of phase change memory groups, the phase change memory group is composed of three phase change memories that adopt the above-mentioned compensation method for optimizing the conductivity drift of the phase change memory, and the plurality of phase change memory groups in each row of storage cells are used to realize a plurality of Gaussian weights in a Bayesian deep neural network.
[0017] The three phase change memories in each phase change memory group act as a Gaussian weight distribution in the Bayesian neural network.
[0018] When implementing the Bayesian neural network, according to the central limit theorem, the total currents of the three phase change memories are accumulated to make the total output current class close to the Gaussian distribution, and the Gaussian weight w = N (μ, σ 2 ), where μ is the mean value in the Gaussian weight, expressed as: I n is the output current of the nth phase change memory from the source line end of the phase change memory array, expressed as: I n =V in,m ×G fnl , V in,m is the read voltage pulse applied to the bit line terminal, G fnl is the compensated conductance value of the phase change memory device, σ is the standard deviation in the Gaussian weight, expressed as: Where σ( ) is the standard deviation calculation.
[0019] The technical solution adopted by the present invention to solve its technical problem is: to provide a Bayesian deep neural network, and the Gaussian weights of the Bayesian deep neural network are realized by the phase change memory array as mentioned above.
[0020] Beneficial Effects
[0021] Due to the adoption of the above-mentioned technical solution, the present invention has the following advantages and positive effects compared with the prior art: the present invention compensates for the conductivity drift of the phase change memory by subtracting the current drift curve from the output current and then adding the average value of the output current, thereby solving the conductivity drift problem of the phase change memory device in the Bayesian deep neural network and reducing the difficulty of implementing the hardware neural network. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figure 1 is a flow chart of a method for compensating for conductance drift of a phase change memory according to a first embodiment of the present invention;
[0023] Figure 2 is a conductivity drift model curve and an actual conductivity curve diagram of the phase change memory device in the first embodiment of the present invention;
[0024] Figure 31 is a diagram of the compensated conductance and average conductance of the phase change memory device in the first embodiment of the present invention;
[0025] Figure 4 is a schematic diagram of a phase change memory array according to a second embodiment of the present invention;
[0026] Figure 5 It is a weight hardware mapping diagram of a Bayesian neural network based on a phase change memory array according to the third embodiment of the present invention. DETAILED DESCRIPTION
[0027] The present invention will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall within the scope limited by the appended claims of the application equally.
[0028] The first embodiment of the present invention relates to a method for compensating for conductance drift of a phase change memory, such as Figure 1 As shown, the following steps are included:
[0029] Step 1: According to the conductance drift model of the phase change memory, the conductance drift data of the actual phase change memory device is fitted to obtain the device conductance drift coefficient.
[0030] The conductivity drift model of the phase change memory used in this step is expressed as:
[0031]
[0032] Among them, G t is the conductance of the phase change memory at time t, G0 is the initial conductance of the phase change memory, t0 is the initial time, and v is the device conductance drift coefficient.
[0033] Step 2: Substitute the device conductivity drift coefficient into the conductivity drift model to obtain the conductivity drift curve and average conductivity value of the phase change memory.
[0034] The conductivity drift curve of the phase change memory obtained in this step can be expressed as:
[0035]
[0036] Among them, v i is the device conductivity drift coefficient obtained by fitting the conductivity drift data of the actual phase change memory device, is the actual conductance of the phase change memory device at time t.
[0037] The calculation formula for the average conductance value in this step is:
[0038]
[0039] Among them, G avg is the average conductivity value.
[0040] Step 3: subtract the conductance of the phase change memory obtained according to the conductance drift curve from the conductance measurement value of the phase change memory to obtain conductance random noise.
[0041] The calculation formula of the conductivity random noise in this step is:
[0042]
[0043] Among them, G rand is the conductance random noise, G meas is the conductivity measurement value of the phase change memory. Figure 2 1 is a diagram of the conductance drift model curve and the actual conductance curve of the phase change memory device. It can be understood that the random noise of the conductance can be obtained by subtracting the conductance drift curve from the actual measured value of the conductance.
[0044] Step 4: Add the conductance random noise to the average conductance value to obtain a compensated conductance value of the phase change memory device.
[0045] The calculation formula of the compensated conductance value of the phase change memory device in this step is:
[0046] G fnl =G rand +G avg ;
[0047] Among them, G fnl is the compensated conductance value of the phase change memory device. Figure 3 ] is a diagram of the final conductance and average conductance of the phase change memory device. It can be understood that by adding the random conductance of the phase change memory device to the average conductance, the final conductance of the device (ie, the compensated conductance) can be obtained.
[0048] It is not difficult to find that the present invention compensates for the conductivity drift of the phase change memory by subtracting the current drift curve from the output current and then adding the average value of the output current, thereby solving the conductivity drift problem of the phase change memory device in the Bayesian deep neural network and reducing the difficulty of implementing the hardware neural network.
[0049] A second embodiment of the present invention relates to a phase change memory array, such as Figure 4As shown, in the phase change memory array, the source line terminal SL is perpendicular to the bit line terminal BL and parallel to the word line terminal WL, thereby forming a cross array structure. Each row of memory cells includes a plurality of phase change memory groups, and the phase change memory groups are composed of three phase change memories using the first embodiment of the method for compensating the conductivity drift of the optimized phase change memory. The plurality of phase change memory groups in each row of memory cells are used to implement a plurality of Gaussian weights in the Bayesian deep neural network.
[0050] In this embodiment, the three phase change memories in each phase change memory group act as a Gaussian weight distribution in the Bayesian neural network. When implementing the Bayesian neural network, according to the central limit theorem, the total current of the three phase change memories is accumulated to make the total output current close to the Gaussian distribution, and the Gaussian weight w=N(μ,σ 2 ). Where μ is the mean value in the Gaussian weight, expressed as: σ is the standard deviation in Gaussian weights, expressed as:
[0051] I n is the output current of the nth phase change memory flowing from the source line end of the phase change memory array, which can be expressed as: I n =V in,m ×G fnl , V in,m is the read voltage pulse applied to the bit line terminal, G fnl is the compensated conductance value of the phase change memory device, and σ() is the standard deviation calculation.
[0052] The third embodiment of the present invention relates to a Bayesian deep neural network, wherein the Gaussian weights of the Bayesian deep neural network are implemented by the phase change memory array as in the second embodiment. Figure 5 is a weight hardware mapping diagram of the Bayesian neural network based on the phase change memory array in this embodiment. The phase change memory cross structure array has two orthogonal interconnections of rows and columns. A phase change memory device is sandwiched at each node of the interconnection line. Assume that the voltage value applied to each column is V in,m According to Ohm's law and Kirchhoff's current law, the total current value of a row can be obtained. The total current value is the product of the conductivity matrix and the voltage vector. The calculation formula is:
[0053] I0=ΣG 0,m V in,m ;
[0054] Where I0 is the total current value of the first row of the array, G 0,m is the conductance value of the phase change memory device in the first row and the mth column, V in,m is the input voltage of the 1st row and the mth column.
[0055] In a neural network, the conductance value of the phase change memory represents the size of the synaptic weight, the voltage applied to the column is the output value of the previous neuron, the accumulated total current is the input value of the neurons in this layer, the column lines and row lines represent the input neurons and output neurons in the neural network respectively, and the phase change memory array can simulate neurons and synapses, naturally realizing hardware acceleration of deep neural networks.
Claims
1. A method for optimizing the compensation of conductance drift of a phase change memory, characterized in that: The following steps are involved: According to the conductance drift model of the phase change memory, the conductance drift data of the actual phase change memory device is used for fitting to obtain the conductance drift coefficient of the device; Substituting the device conductivity drift coefficient into the conductivity drift model to obtain a conductivity drift curve and an average conductivity value of the phase change memory; Subtracting the conductance of the phase change memory obtained according to the conductance drift curve from the conductance measurement value of the phase change memory to obtain conductance random noise; The conductance random noise is added to the average conductance value to obtain a compensated conductance value of the phase change memory device.
2. The method for compensating for conductivity drift of a phase change memory according to claim 1, characterized in that: The conductivity drift model of the phase change memory is expressed as: Among them, G t is the conductance of the phase change memory at time t, G0 is the initial conductance of the phase change memory, t0 is the initial time, and v is the device conductance drift coefficient.
3. The method for optimizing the compensation of conductance drift of phase change memory according to claim 1, characterized in that: The calculation formula of the average conductance value is: Among them, G avg is the average conductivity value, G t is the conductance of the phase change memory at time t, and t0 is the initial time.
4. The method for optimizing the compensation of conductance drift of phase change memory according to claim 1, characterized in that: The calculation formula of the conductance random noise is: Among them, G rand is the conductance random noise, G meas is the conductivity measurement value of the phase change memory, is the conductance of the phase change memory obtained according to the conductance drift curve.
5. The method for compensating for conductivity drift of a phase change memory according to claim 1, characterized in that: The calculation formula of the conductance value after compensation of the phase change memory device is: fnl =G rand +G avg , where G fnl is the compensated conductance value of the phase change memory device, G rand is the conductance random noise, G avg is the average conductivity value.
6. A phase change memory array, characterized in that: Each row of storage cells includes several phase change memory groups, which are composed of three phase change memories that adopt the compensation method for optimizing phase change memory conductivity drift as described in any one of claims 1-5. The several phase change memory groups in each row of storage cells are used to implement several Gaussian weights in a Bayesian deep neural network.
7. The phase change memory array according to claim 6, characterized in that: The three phase change memories in each phase change memory group act as a Gaussian weight distribution in the Bayesian neural network.
8. The phase change memory array according to claim 7, characterized in that: When implementing the Bayesian neural network, according to the central limit theorem, the total currents of the three phase change memories are accumulated to make the total output current class close to the Gaussian distribution, and the Gaussian weight w = N (μ, σ 2 ), where μ is the mean value in the Gaussian weight, expressed as: I n is the output current of the nth phase change memory from the source line end of the phase change memory array, expressed as: I n =V in,m ×G fnl , V in,m is the read voltage pulse applied to the bit line terminal, G fnl is the compensated conductance value of the phase change memory device, σ is the standard deviation in the Gaussian weight, expressed as: Among them, σ() is the standard deviation calculation.
9. A Bayesian deep neural network, characterized in that The Gaussian weights of the Bayesian deep neural network are implemented by the phase change memory array as described in any one of claims 6-8.