Signal-level model operation method, device, equipment and medium based on CPU+GPU architecture

Abstract

The embodiment of the present invention provides a signal-level model operation method, device, equipment and medium based on the CPU+GPU architecture, which relates to the field of signal-level simulation technology, including loading the signal-level model through the CPU main thread, dividing it into a serially executable part and a parallel executable part according to the computational complexity and data dependency of the model simulation task; allocating the serially executable part to the CPU for processing to obtain a first simulation result; transferring the calculation data of the parallel executable part from the CPU main memory to the GPU video memory, and the GPU starting thread executes the parallel executable part in parallel and allows multiple parallel threads to access and modify shared resources at the same time to obtain a second simulation result; transmitting the second simulation result to the CPU and integrating it with the first simulation result to obtain the final simulation output of the signal-level model. This solution realizes efficient, stable and transparent simulation experiments, improves the stability and transparency of the system, and avoids waste of resources.

Description

Technical Field

[0001] The present invention relates to the technical field of signal level simulation, and in particular to a signal level model operation based on a CPU+GPU architecture. Background Art

[0002] Signal-level simulation technology is an important means widely used in the design, verification and evaluation of electronic information systems. It is difficult to meet the needs of complex systems for high-performance computing. As the scale of chips continues to expand, the simulation execution time is getting longer and longer, and improving simulation efficiency and shortening simulation time have become urgent issues to be solved.

[0003] The existing software simulation acceleration solutions have limited efficiency and cannot effectively realize the segmentation of "verification code". At the same time, the number of thread tasks is far greater than the number of CPU cores that can be used, which offsets part of the acceleration effect. In addition, the traditional single-mode simulation platform has problems such as poor system stability, low transparency and waste of resources. It is difficult to achieve efficient, stable and transparent simulation experiments under the requirements of high distribution, interoperability, high real-time and scalability. Therefore, it is necessary to find a new acceleration solution that combines hardware and software. Summary of the invention

[0004] In view of this, an embodiment of the present invention provides a signal-level model operation method based on a CPU+GPU architecture to solve the technical problem that the prior art cannot fully utilize the computing power of the CPU and GPU working together and cannot achieve efficient, stable, and transparent simulation experiments. The method includes: Loading the signal-level model through the main thread of the CPU, and dividing the simulation task into a serially executable part and a parallel executable part according to the computational complexity and data dependency of the simulation task of the signal-level model; Allocating the serially executable part to a CPU for processing to obtain a first simulation result; The calculation data corresponding to the parallel executable part is transferred from the main memory of the CPU to the video memory of the GPU, and the GPU starts the thread to execute the simulation task of the parallel executable part in parallel and allows multiple parallel threads to access and modify the shared resource at the same time to obtain a second simulation result; The second simulation result is transmitted to the main memory of the CPU and integrated with the first simulation result to obtain the final simulation output of the signal level model.

[0005] The embodiment of the present invention also provides a signal-level model operation device based on a CPU+GPU architecture to solve the technical problem that the prior art cannot fully utilize the computing power of the CPU and GPU working together and cannot achieve efficient, stable and transparent simulation experiments. The device includes: A partitioning module, used for loading a signal-level model through a main thread of a CPU, and partitioning the simulation task into a serially executable part and a parallel executable part according to the computational complexity and data dependency of the simulation task of the signal-level model; A first simulation module, used for allocating the serially executable part to a CPU for processing to obtain a first simulation result; A second simulation module is used to transfer the calculation data corresponding to the parallel executable part from the main memory of the CPU to the video memory of the GPU, and the GPU starts the thread to execute the simulation task of the parallel executable part in parallel and allows multiple parallel threads to access and modify the shared resources at the same time to obtain a second simulation result; An integration module is used to transmit the second simulation result to the main memory of the CPU and integrate it with the first simulation result to obtain the final simulation output of the signal level model.

[0006] An embodiment of the present invention also provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements any of the above-mentioned signal-level model operation methods based on the CPU+GPU architecture when executing the computer program, so as to solve the technical problems in the prior art that the computing power of the CPU and GPU working together cannot be fully utilized and efficient, stable and transparent simulation experiments cannot be realized.

[0007] An embodiment of the present invention also provides a computer-readable storage medium, which stores a computer program for executing any of the above-mentioned signal-level model operation methods based on the CPU+GPU architecture, so as to solve the technical problems in the prior art that the computing power of the CPU and GPU working together cannot be fully utilized and efficient, stable and transparent simulation experiments cannot be achieved.

[0008] Compared with the prior art, the beneficial effects that can be achieved by at least one of the above-mentioned technical solutions adopted in the embodiments of this specification include at least: loading the signal-level model through the CPU main thread, and dividing it into a serially executable part and a parallel executable part according to the computational complexity and data dependency of the model simulation task; allocating the serially executable part to the CPU for processing to obtain a first simulation result; transferring the calculation data of the parallel executable part from the CPU main memory to the GPU video memory, and the GPU startup thread executes the parallel executable part in parallel and allows multiple parallel threads to access and modify shared resources at the same time to obtain a second simulation result; transmitting the second simulation result to the CPU for integration with the first simulation result to obtain the final simulation output of the signal-level model. This application makes full use of the computing power of the CPU and GPU to achieve efficient parallel execution of signal-level model simulation tasks, greatly improves simulation efficiency, shortens simulation time, and meets the needs of complex systems for high-performance computing; by dividing the simulation tasks of the signal-level model into a serially executable part and a parallel executable part, the "verification code" is effectively segmented, and the number of thread tasks is not limited by the number of CPU cores, giving full play to the advantages of parallel acceleration; the CPU and GPU work together, the CPU is responsible for the serial execution part and integrating the final results, and the GPU is responsible for the parallel execution part, achieving efficient, stable, and transparent simulation experiments, improving the stability and transparency of the system, and avoiding waste of resources; the method of this application has good scalability, and the task allocation ratio of the CPU and GPU can be flexibly adjusted according to actual needs, meeting complex needs such as high distribution, interoperability, high real-time, and scalability. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0010] Figure 1 is a flow chart of a signal level model operation method based on CPU+GPU architecture provided by an embodiment of the present invention; Figure 2 is a structural block diagram of a computer device provided by an embodiment of the present invention; Figure 3 It is a structural block diagram of a signal-level model running device based on CPU+GPU architecture provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0011] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0012] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0013] In an embodiment of the present invention, a signal level model operation method based on a CPU+GPU architecture is provided, such as Figure 1 As shown, the method includes: Step S101, loading a signal-level model through a main thread of a CPU, and dividing the simulation task into a serially executable part and a parallel executable part according to the computational complexity and data dependency of the simulation task of the signal-level model; Step S102, allocating the serially executable part to a CPU for processing to obtain a first simulation result; Step S103, transferring the calculation data corresponding to the parallel executable part from the main memory of the CPU to the video memory of the GPU, and the GPU starting the thread to execute the simulation task of the parallel executable part in parallel and allowing multiple parallel threads to access and modify the shared resources at the same time to obtain a second simulation result; Step S104: transmitting the second simulation result to the main memory of the CPU, and integrating it with the first simulation result to obtain a final simulation output of the signal level model.

[0014] In this embodiment, the computing power of the CPU and GPU is fully utilized to realize the efficient parallel execution of the signal-level model simulation task, which greatly improves the simulation efficiency, shortens the simulation time, and meets the needs of complex systems for high-performance computing; by dividing the simulation task of the signal-level model into a serially executable part and a parallelly executable part, the "verification code" is effectively segmented, and the number of thread tasks is not limited by the number of CPU cores, giving full play to the advantages of parallel acceleration; the CPU and GPU are used in a collaborative manner, with the CPU being responsible for the serial execution part and integrating the final results, and the GPU being responsible for the parallel execution part, to achieve efficient, stable, and transparent simulation experiments, improve the stability and transparency of the system, and avoid waste of resources; the method of the present application has good scalability, and the task allocation ratio of the CPU and GPU can be flexibly adjusted according to actual needs, meeting complex needs such as high distribution, interoperability, high real-time, and scalability.

[0015] In one embodiment, the simulation task is divided into a serially executable part and a parallel executable part according to the computational complexity and data dependency of the simulation task of the signal level model, including: Obtain all simulation tasks of the signal level model, and analyze the function and computational characteristics of each simulation task; Based on the functions and computing characteristics of each simulation task, primary parallel executable tasks and primary serial executable tasks are obtained; The data dependency judgment is performed on the primary parallel executable tasks, including: listing the input-output relationship of all primary parallel executable tasks, determining the predecessor task and the successor task of each primary parallel executable task; representing the dependency relationship between each primary parallel executable task and its corresponding predecessor task and successor task through a directed graph; based on the directed graph, screening out the primary parallel executable tasks with zero predecessor tasks; Calculating the computational complexity of each primary parallel executable task whose predecessor task is zero, and dividing the primary parallel executable tasks whose computational complexity is greater than a preset threshold and whose predecessor task is zero into parallel executable parts; The remaining tasks in the primary parallel executable tasks and the primary serial executable tasks are divided into serial executable parts.

[0016] In this embodiment, the functions of the simulation task generally include signal generation, signal processing, data transmission, parameter adjustment, result analysis and status update, etc. The calculation characteristics of the simulation task generally include memory usage, whether the task involves a large number of input and output operations, whether the task is computationally intensive or I / O intensive, whether the task has strict real-time requirements, etc. By analyzing the functions and calculation characteristics of each simulation task, it is possible to accurately identify which tasks are suitable for parallel execution and which tasks require serial processing. This method ensures that the computing resources CPU and GPU are used most effectively. Through the analysis of data dependency and computational complexity, for tasks with high computational complexity and low data dependency, they can be assigned to high-performance parallel computing devices such as GPU, thereby greatly improving the computing speed. By evaluating the computational complexity and data dependency of primary parallel executable tasks, it is possible to avoid forcibly parallelizing tasks that are not suitable for parallelization, thereby reducing potential performance bottlenecks.

[0017] In practice, computational complexity refers to the number of basic operations required to complete a task. For simulation tasks, the computational complexity can be estimated in the following ways: (1) Theoretical analysis Algorithm complexity: Based on the algorithm used, its time complexity can be derived; Operation count: By analyzing the main operations involved in the task (such as addition, multiplication, function call, etc.), and estimating the number of these operations. For example, if a task needs to process n elements one by one, and each element needs m operations, the total number of operations is n*m.

[0018] (2) Actual measurement Profiling Tools: Use performance profiling tools (such as NVIDIA Nsight, Intel VTune, etc.) to measure the task execution time and number of operations at actual runtime. These tools can help identify hot code segments and provide specific performance indicators; Sampling and statistics: During the execution of a task, the number of key operations, such as the number of floating-point operations and the number of memory accesses, is recorded, and then the overall complexity is estimated based on these statistics.

[0019] Data dependency describes the degree of data interaction between different parts of the simulation task. High data dependency means that some parts of the task must wait for other parts to complete before continuing, which limits the potential for parallelization. Data dependency can also be estimated in the following ways: (1) Static analysis Control Flow Graph (CFG): Draw a control flow graph for the task and identify all possible data flow paths. By analyzing the edges and nodes in the CFG, identify which parts have data dependencies.

[0020] Data Flow Graph (DFG): Build a data flow graph that shows how data flows between different parts of a task. Loops or feedback paths in a DFG usually indicate the presence of data dependencies.

[0021] (2) Dynamic analysis Runtime monitoring: During task execution, data access patterns are monitored in real time. For example, timestamps of memory read and write operations are recorded to analyze whether there are overlapping or conflicting accesses.

[0022] Synchronization point detection: Identify synchronization points in tasks, i.e. those parts that need to wait for other tasks to complete before continuing. The presence of synchronization points usually indicates a high degree of data dependency.

[0023] In one embodiment, the transferring of the computing data corresponding to the parallel executable part from the main memory of the CPU to the video memory of the GPU includes: Determining data blocks that need to be pre-fetched according to the calculation data corresponding to the parallel executable part; Add a prefetch instruction to prefetch the data block from the main memory of the CPU and cache the data block into the high-speed cache of the CPU; The data block cached in the CPU's cache is transferred to the GPU's video memory through asynchronous transmission.

[0024] In the specific implementation, by analyzing the needs of the simulation task, it is clear which data blocks are about to be used, and the transmission of these data blocks is prioritized, thereby avoiding unnecessary data transmission and reducing bandwidth waste. By explicitly adding prefetch instructions in the code, the CPU can load the required data into the cache (L1 / L2 Cache) in advance. This active data management method can significantly reduce waiting time and improve overall performance. By caching the data blocks in the CPU's cache first and then transmitting them, the low latency characteristics of the cache can be used to accelerate the data transmission process from the main memory to the video memory; using asynchronous transmission technology, data transmission can be performed while the CPU continues to process other tasks, that is, data transmission and computing tasks can be executed in an overlapping manner, thereby hiding the transmission delay and further improving the system throughput.

[0025] Traditional synchronous data transmission methods cause the communication between the CPU and GPU to become a performance bottleneck, but asynchronous transmission and prefetching mechanisms can effectively reduce this bottleneck effect and shorten the response time of the entire system. In addition, the combination of prefetching and asynchronous transmission ensures the continuity and smoothness of the data flow, reduces the task stagnation caused by unprepared data, and improves the stability and reliability of the system.

[0026] In one embodiment, the adding of the prefetch instruction to prefetch the data block from the main memory of the CPU includes: The data block is prefetched from the main memory of the CPU by calling the prefetch instruction __builtin_prefetch of the GCC or Clang compiler.

[0027] Specifically, __builtin_prefetch is a built-in function provided by the GCC and Clang compilers to prompt the compiler to load the specified memory address into the CPU cache (usually L1 or L2 cache) in advance. __builtin_prefetch allows parameters (such as read / write flags and cache locality) to be adjusted according to specific needs to adapt to different hardware characteristics and application scenarios. For example, higher locality parameters can be set in high locality scenarios to extend the retention time of data in the cache. Since __builtin_prefetch is a built-in function of the compiler, the same code logic can be used on different platforms, and only the parameters need to be fine-tuned for specific platforms.

[0028] In one embodiment, the step of transmitting the data block cached in the CPU cache to the GPU memory through asynchronous transmission includes: Use CUDA's cudaMemGetInfo function to query the size of the GPU's current free memory; The size of the data blocks that can be transferred to the GPU video memory is determined based on the size of the GPU's current free memory and the total size of the data blocks cached in the CPU's cache. When the total size of the data blocks cached in the CPU's cache exceeds the size of the GPU's current free memory, the data blocks cached in the CPU's cache are asynchronously transferred in blocks to the GPU's video memory. The asynchronous transmission is implemented through CUDA's cudaMemcpyAsync function.

[0029] In specific implementation, the size of the data block that can be currently transferred to the GPU video memory is evaluated based on the queried GPU free memory size (free); if the total size of the data blocks cached in the CPU cache is less than or equal to the size of the GPU's current free memory, all data blocks can be directly transferred; if the total size of the data blocks cached in the CPU cache exceeds the size of the GPU's current free memory, the data blocks need to be transferred in blocks. When block transmission is required, the data block can be divided into several small blocks based on the GPU's free memory size, and one block is transmitted at a time, using CUDA's cudaMemcpyAsync function for asynchronous transmission, which allows data transmission without blocking the CPU, thereby improving overall efficiency.

[0030] This embodiment can effectively avoid the problem of GPU memory overflow caused by transmitting too much data at one time by querying the current free memory size of the GPU and adjusting the size of the data block to be transmitted accordingly. This method helps to balance the load between the CPU and the GPU, prevent one end from being overloaded or idle, and thus improve the resource utilization of the entire system. By controlling the size of the data block transmitted each time, the system instability caused by memory competition can be avoided and the reliability of the system can be improved; the combination of block transmission and asynchronous processing ensures the continuity and smoothness of the data flow, reduces the task stagnation caused by unprepared data, and further improves the stability and reliability of the system.

[0031] In one embodiment, the GPU starts the thread to execute the simulation task of the parallel executable part in parallel and allows multiple parallel threads to access and modify shared resources at the same time, including: Building a global task queue based on the simulation tasks of the parallel executable part; For each thread, simulation tasks are dynamically allocated from the global task queue through atomic operations, allowing multiple parallel threads to access and modify shared resources at the same time.

[0032] In one embodiment, for each thread, dynamically allocating simulation tasks from the global task queue through atomic operations and allowing multiple threads in parallel to access and modify shared resources at the same time include: Define a CUDA kernel function executed on the GPU, wherein the CUDA kernel function includes a pointer to the global task queue, a pointer to a task index, a pointer to input data, a pointer to output data, and a total number of tasks, and the pointer to the task index is used to dynamically allocate tasks; Define a first variable, where the first variable is used to represent the global index of the current thread, and the definition of the first variable includes the index of the current thread in the thread block, the index of the current thread block in the grid, and the number of threads in the thread block; For each thread, use the atomic operation function atomicAdd to obtain the current task ID from the task index, and add 1 to the value of the task index; Define a second variable, and assign the acquired current task ID to the second variable; Obtain data corresponding to the current task ID from the global task queue; Call the process_task function to perform simulation calculations on the acquired data; Through the second variable, it is determined whether the current task ID exceeds the total number of tasks. If it does not exceed the total number of tasks, the simulation calculation is performed in a loop until all simulation tasks in the global task queue are completed.

[0033] Specifically, the global task queue is a data structure used to dynamically allocate and manage simulation tasks in parallel computing. A global task queue is constructed, and all tasks to be executed are placed in this queue, so that tasks can be centrally managed to ensure that each thread can obtain tasks fairly. Atomic operations are used to dynamically allocate tasks to each thread from the global task queue. The combination of atomic operations and the first and second variables ensures that there will be no competition conditions when multiple threads can access and modify shared resources at the same time, thereby ensuring the correctness and consistency of task allocation. At the same time, due to the use of atomic operations for task allocation, the performance bottleneck caused by the traditional lock mechanism is avoided, which allows threads to quickly obtain tasks without waiting, thereby improving the overall parallelism.

[0034] The dynamic allocation mechanism of this embodiment can flexibly allocate tasks according to the working status of each thread, avoid the situation where some threads are overloaded while other threads are idle, and achieve a more balanced load distribution.

[0035] In this embodiment, a computer device is provided, such as Figure 2 As shown, it includes a memory 201, a processor 202, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, any of the above-mentioned signal-level model operation methods based on the CPU+GPU architecture is implemented.

[0036] Specifically, the computer device may be a computer terminal, a server or a similar computing device.

[0037] In this embodiment, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores a computer program for executing any of the above-mentioned signal-level model operation methods based on the CPU+GPU architecture.

[0038] Specifically, computer-readable storage media include permanent and non-permanent, removable and non-removable media that can be used to store information by any method or technology. Information can be computer-readable instructions, data structures, program modules or other data. Examples of computer-readable storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, tape disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable storage media does not include temporary computer-readable media (transitory media), such as modulated data signals and carrier waves.

[0039] Based on the same inventive concept, a signal-level model operation device based on a CPU+GPU architecture is also provided in an embodiment of the present invention, as described in the following embodiments. Since the principle of solving the problem by the signal-level model operation device based on the CPU+GPU architecture is similar to that of the signal-level model operation method based on the CPU+GPU architecture, the implementation of the signal-level model operation device based on the CPU+GPU architecture can refer to the implementation of the signal-level model operation method based on the CPU+GPU architecture, and the repeated parts will not be repeated. As used below, the term "unit" or "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceived.

[0040] Figure 3 is a structural block diagram of a signal level model running device based on CPU+GPU architecture according to an embodiment of the present invention. Figure 3 As shown, it includes: a division module 301, a first simulation module 302, a second simulation module 303 and an integration module 304. The structure is described below.

[0041] A partitioning module 301 is used to load a signal-level model through a main thread of a CPU, and to partition the simulation task of the signal-level model into a serially executable part and a parallel executable part according to the computational complexity and data dependency of the simulation task; A first simulation module 302, used for allocating the serially executable part to a CPU for processing to obtain a first simulation result; The second simulation module 303 is used to transfer the calculation data corresponding to the parallel executable part from the main memory of the CPU to the video memory of the GPU, and the GPU starts the thread to execute the simulation task of the parallel executable part in parallel and allows multiple parallel threads to access and modify the shared resources at the same time to obtain a second simulation result; The integration module 304 is used to transmit the second simulation result to the main memory of the CPU and integrate it with the first simulation result to obtain the final simulation output of the signal level model.

[0042] In one embodiment, the division module 301 is further used to: Obtain all simulation tasks of the signal level model, and analyze the function and computational characteristics of each simulation task; Based on the functions and computing characteristics of each simulation task, primary parallel executable tasks and primary serial executable tasks are obtained; The data dependency judgment is performed on the primary parallel executable tasks, including: listing the input-output relationship of all primary parallel executable tasks, determining the predecessor task and the successor task of each primary parallel executable task; representing the dependency relationship between each primary parallel executable task and its corresponding predecessor task and successor task through a directed graph; based on the directed graph, screening out the primary parallel executable tasks with zero predecessor tasks; Calculating the computational complexity of each primary parallel executable task whose predecessor task is zero, and dividing the primary parallel executable tasks whose computational complexity is greater than a preset threshold and whose predecessor task is zero into parallel executable parts; The remaining tasks in the primary parallel executable tasks and the primary serial executable tasks are divided into serial executable parts.

[0043] In one embodiment, the second simulation module 303 is further used to: Determining data blocks that need to be pre-fetched according to the calculation data corresponding to the parallel executable part; Add a prefetch instruction to prefetch the data block from the main memory of the CPU and cache the data block into the high-speed cache of the CPU; The data block cached in the CPU's cache is transferred to the GPU's video memory through asynchronous transmission.

[0044] In one embodiment, the second simulation module 303 is further used to: The data block is prefetched from the main memory of the CPU by calling the prefetch instruction __builtin_prefetch of the GCC or Clang compiler.

[0045] In one embodiment, the second simulation module 303 is further used to: Use CUDA's cudaMemGetInfo function to query the size of the GPU's current free memory; The size of the data blocks that can be transferred to the GPU video memory is determined based on the size of the GPU's current free memory and the total size of the data blocks cached in the CPU's cache. When the total size of the data blocks cached in the CPU's cache exceeds the size of the GPU's current free memory, the data blocks cached in the CPU's cache are asynchronously transferred in blocks to the GPU's video memory. The asynchronous transmission is implemented through CUDA's cudaMemcpyAsync function.

[0046] In one embodiment, the second simulation module 303 is further used to: Building a global task queue based on the simulation tasks of the parallel executable part; For each thread, simulation tasks are dynamically allocated from the global task queue through atomic operations, allowing multiple parallel threads to access and modify shared resources at the same time.

[0047] In one embodiment, the second simulation module 303 is further used to: Define a CUDA kernel function executed on the GPU, wherein the CUDA kernel function includes a pointer to the global task queue, a pointer to a task index, a pointer to input data, a pointer to output data, and a total number of tasks, and the pointer to the task index is used to dynamically allocate tasks; Define a first variable, where the first variable is used to represent the global index of the current thread, and the definition of the first variable includes the index of the current thread in the thread block, the index of the current thread block in the grid, and the number of threads in the thread block; For each thread, use the atomic operation function atomicAdd to obtain the current task ID from the task index, and add 1 to the value of the task index; Define a second variable, and assign the acquired current task ID to the second variable; Obtain data corresponding to the current task ID from the global task queue; Call the process_task function to perform simulation calculations on the acquired data; Through the second variable, it is determined whether the current task ID exceeds the total number of tasks. If it does not exceed the total number of tasks, the simulation calculation is performed in a loop until all simulation tasks in the global task queue are completed.

[0048] The embodiment of the present invention achieves the following technical effects: a signal-level model is loaded through a CPU main thread, and is divided into a serially executable part and a parallel executable part according to the computational complexity and data dependency of the model simulation task; the serially executable part is allocated to the CPU for processing to obtain a first simulation result; the calculation data of the parallel executable part is transferred from the CPU main memory to the GPU video memory, and the GPU starts a thread to execute the parallel executable part in parallel and allows multiple parallel threads to access and modify shared resources at the same time to obtain a second simulation result; the second simulation result is transmitted to the CPU for integration with the first simulation result to obtain the final simulation output of the signal-level model. This application makes full use of the computing power of the CPU and GPU to achieve efficient parallel execution of signal-level model simulation tasks, greatly improves simulation efficiency, shortens simulation time, and meets the needs of complex systems for high-performance computing; by dividing the simulation tasks of the signal-level model into a serially executable part and a parallel executable part, the "verification code" is effectively segmented, and the number of thread tasks is not limited by the number of CPU cores, giving full play to the advantages of parallel acceleration; the CPU and GPU work together, the CPU is responsible for the serial execution part and integrating the final results, and the GPU is responsible for the parallel execution part, achieving efficient, stable, and transparent simulation experiments, improving the stability and transparency of the system, and avoiding waste of resources; the method of this application has good scalability, and the task allocation ratio of the CPU and GPU can be flexibly adjusted according to actual needs, meeting complex needs such as high distribution, interoperability, high real-time, and scalability.

[0049] Obviously, those skilled in the art should understand that the modules or steps of the above-mentioned embodiments of the present invention can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, and optionally, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that here, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. In this way, the embodiments of the present invention are not limited to any specific combination of hardware and software.

[0050] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the embodiments of the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A signal-level model operation method based on CPU+GPU architecture, characterized in that: include: Loading the signal-level model through the main thread of the CPU, and dividing the simulation task into a serially executable part and a parallel executable part according to the computational complexity and data dependency of the simulation task of the signal-level model; Allocating the serially executable part to a CPU for processing to obtain a first simulation result; The calculation data corresponding to the parallel executable part is transferred from the main memory of the CPU to the video memory of the GPU, and the GPU starts the thread to execute the simulation task of the parallel executable part in parallel and allows multiple parallel threads to access and modify the shared resource at the same time to obtain a second simulation result; The second simulation result is transmitted to the main memory of the CPU and integrated with the first simulation result to obtain the final simulation output of the signal level model.

2. The signal level model operation method based on CPU+GPU architecture as claimed in claim 1, characterized in that: The step of dividing the simulation task into a serially executable part and a parallel executable part according to the computational complexity and data dependency of the simulation task of the signal level model comprises: Obtain all simulation tasks of the signal level model, and analyze the function and computational characteristics of each simulation task; Based on the functions and computing characteristics of each simulation task, primary parallel executable tasks and primary serial executable tasks are obtained; The data dependency judgment is performed on the primary parallel executable tasks, including: listing the input-output relationship of all primary parallel executable tasks, determining the predecessor task and the successor task of each primary parallel executable task; representing the dependency relationship between each primary parallel executable task and its corresponding predecessor task and successor task through a directed graph; based on the directed graph, screening out the primary parallel executable tasks with zero predecessor tasks; Calculating the computational complexity of each primary parallel executable task whose predecessor task is zero, and dividing the primary parallel executable tasks whose computational complexity is greater than a preset threshold and whose predecessor task is zero into parallel executable parts; The remaining tasks in the primary parallel executable tasks and the primary serial executable tasks are divided into serial executable parts.

3. The signal level model operation method based on CPU+GPU architecture as claimed in claim 1, characterized in that: The transferring the computing data corresponding to the parallel executable part from the main memory of the CPU to the video memory of the GPU includes: Determining data blocks that need to be pre-fetched according to the calculation data corresponding to the parallel executable part; Add a prefetch instruction to prefetch the data block from the main memory of the CPU and cache the data block into the high-speed cache of the CPU; The data block cached in the CPU's cache is transferred to the GPU's video memory through asynchronous transmission.

4. The signal level model operation method based on CPU+GPU architecture as claimed in claim 3, characterized in that: The adding of the prefetch instruction to prefetch the data block from the main memory of the CPU comprises: The data block is prefetched from the main memory of the CPU by calling the prefetch instruction __builtin_prefetch of the GCC or Clang compiler.

5. The signal level model operation method based on CPU+GPU architecture as claimed in claim 3, characterized in that: The step of transmitting the data block cached in the CPU's cache to the GPU's video memory through asynchronous transmission includes: Use CUDA's cudaMemGetInfo function to query the size of the GPU's current free memory; The size of the data blocks that can be transferred to the GPU video memory is determined based on the size of the GPU's current free memory and the total size of the data blocks cached in the CPU's cache. When the total size of the data blocks cached in the CPU's cache exceeds the size of the GPU's current free memory, the data blocks cached in the CPU's cache are asynchronously transferred in blocks to the GPU's video memory. The asynchronous transmission is implemented through CUDA's cudaMemcpyAsync function.

6. The signal level model operation method based on CPU+GPU architecture as claimed in claim 1, characterized in that: The GPU starts the thread to execute the simulation task of the parallel executable part in parallel and allows multiple parallel threads to access and modify shared resources at the same time, including: Building a global task queue based on the simulation tasks of the parallel executable part; For each thread, simulation tasks are dynamically allocated from the global task queue through atomic operations, allowing multiple parallel threads to access and modify shared resources at the same time.

7. The signal level model operation method based on CPU+GPU architecture as claimed in claim 6, characterized in that: The method dynamically allocates simulation tasks from the global task queue through atomic operations for each thread and allows multiple parallel threads to access and modify shared resources at the same time, including: Define a CUDA kernel function executed on the GPU, wherein the CUDA kernel function includes a pointer to the global task queue, a pointer to a task index, a pointer to input data, a pointer to output data, and a total number of tasks, and the pointer to the task index is used to dynamically allocate tasks; Define a first variable, where the first variable is used to represent the global index of the current thread, and the definition of the first variable includes the index of the current thread in the thread block, the index of the current thread block in the grid, and the number of threads in the thread block; For each thread, use the atomic operation function atomicAdd to obtain the current task ID from the task index, and add 1 to the value of the task index; Define a second variable, and assign the acquired current task ID to the second variable; Obtain data corresponding to the current task ID from the global task queue; Call the process_task function to perform simulation calculations on the acquired data; Through the second variable, it is determined whether the current task ID exceeds the total number of tasks. If it does not exceed the total number of tasks, the simulation calculation is performed in a loop until all simulation tasks in the global task queue are completed.

8. A signal-level model running device based on CPU+GPU architecture, characterized in that: include: A partitioning module, used for loading a signal-level model through a main thread of a CPU, and partitioning the simulation task into a serially executable part and a parallel executable part according to the computational complexity and data dependency of the simulation task of the signal-level model; A first simulation module, used for allocating the serially executable part to a CPU for processing to obtain a first simulation result; A second simulation module is used to transfer the calculation data corresponding to the parallel executable part from the main memory of the CPU to the video memory of the GPU, and the GPU starts the thread to execute the simulation task of the parallel executable part in parallel and allows multiple parallel threads to access and modify the shared resources at the same time to obtain a second simulation result; An integration module is used to transmit the second simulation result to the main memory of the CPU and integrate it with the first simulation result to obtain the final simulation output of the signal level model.

9. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the signal-level model operation method based on the CPU+GPU architecture described in any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program for executing the signal-level model running method based on CPU+GPU architecture according to any one of claims 1 to 7.

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