Substrate material zero alignment mark etching method and semiconductor device
By using a combined mask of photoresist + TEOS and PECVD to deposit TEOS layers in semiconductor wafer manufacturing, the problem of insufficient angle and depth of the sidewall of zero-aligned marks is solved, achieving higher process stability and recognition, while controlling production costs.
Patent Information
- Application Number
- CN202411856437.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-17
- Publication Date
- 2025-04-04
AI Technical Summary
During the semiconductor wafer manufacturing process, the sidewall angle and depth of the zero-position alignment mark are insufficient, resulting in abnormal alignment of the lithography machine, affecting the recognition and stability of subsequent processing processes.
By changing the type of mask layer, the pure photoresist is replaced with a combined mask of photoresist + TEOS, the growing TEOS layer is deposited by PECVD, and a zero-position alignment mark is formed through a dry etching process to achieve a deeper and steeper sidewall angle.
Without changing the sidewall angle, the etching depth and contrast of the zero alignment mark are improved, which solves the problem of alignment abnormalities in subsequent processes, improves process stability, and controls production costs.
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Figure CN119764171A_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the field of semiconductor manufacturing, and in particular relates to a substrate material zero-position alignment mark etching method and a semiconductor device. Background Art
[0002] Semiconductor wafer manufacturing is a typical precision manufacturing industry, which has very high requirements on materials, processes, equipment, etc. Wafers, as high-precision products, are widely used in various electronic devices, such as computers, mobile phones, computers, televisions, etc.
[0003] In wafer manufacturing technology, photolithography is the most critical step, which is used to transfer the pattern on the mask to the substrate or dielectric material. The alignment error in the photolithography process is an important influencing parameter, which directly affects the transfer quality of the photolithography pattern. If this alignment error exceeds the set allowable range, it will cause errors in chip production, and in severe cases, it may cause the equipment to fail to work properly. Therefore, for the photolithography process, how to reduce the alignment error is very critical.
[0004] In the current SIC power device manufacturing process, the transfer of multi-layer patterns relies on the zero alignment mark (Zeromark) for alignment, so the side wall angle (Profile angle) of the zero alignment mark is required to be high. A shallow depth or a side wall angle that is too low will cause abnormal alignment of the lithography machine when the wafer is transferred to the metal and passivation process.
[0005] However, as the processes are added, the clarity of the mark will gradually change. Especially when the product is deposited with metal or passivation medium, the outline of the mark will become more difficult to identify, often causing the lithography machine to report an error and stop the wafer flow.
[0006] Therefore, how to improve the side wall angle of the absolute zero mark (Zero Mark Profile) to make it develop in a deeper and steeper direction and improve the recognition of the zero alignment mark in subsequent processing steps has become a goal pursued by various wafer fabs. Summary of the invention
[0007] In order to address the deficiencies of the prior art, the present application provides a method for etching a zero-position alignment mark of a substrate material and a semiconductor device. By changing the type of the mask layer and replacing the mask material (Mask) from pure photoresist to photoresist + TEOS, the zero-position alignment mark can obtain a steep sidewall angle while keeping the production cost almost unchanged. At the same time, the etching depth of the zero-position alignment mark can be deepened, thereby solving the problem of abnormal alignment of silicon carbide wafers in the metal or passivation process.
[0008] The technical effects to be achieved by this application are achieved through the following solutions:
[0009] According to a first aspect of the present application, a method for etching a zero alignment mark of a substrate material is provided, comprising the following steps:
[0010] Step 1: Prepare a silicon carbide wafer substrate and deposit and grow a TEOS layer on the epitaxial surface of the substrate;
[0011] Step 2: coating photoresist on the surface of the TEOS layer, and forming a zero alignment mark pattern through exposure and development processes;
[0012] Step 3: etching the TEOS layer in the zero alignment mark pattern to expose the silicon carbide epitaxial layer;
[0013] Step 4: etching the silicon carbide epitaxial layer in the zero alignment mark pattern to a required depth of the zero alignment mark;
[0014] Step 5: After removing the remaining photoresist, a barrier layer and a damage barrier layer are prepared on the TEOS layer to complete the production of the zero alignment mark.
[0015] Preferably, in step 1, a 500 angstrom TEOS layer is deposited and grown on the epitaxial portion of the substrate by PECVD.
[0016] Preferably, the process parameters for depositing and growing the TEOS layer are: chamber pressure 5-10 Torr; power 400-600 W; temperature 300-400° C.; TEOS flow 500-600 sccm; He flow 600-800 sccm; O2 flow 500-600 sccm; and deposition time 10-20 s.
[0017] Preferably, in step 2, the photoresist is AR80 photoresist, and the photoresist coating thickness is 2.0 um.
[0018] Preferably, in step 2, the zero position alignment mark pattern formed by exposure and development process has a side wall angle greater than 85°.
[0019] Preferably, in step 3, a 500 angstrom TEOS layer is etched away using a dry etching process, and the specific method is:
[0020] A CCP type etcher is used, and the process parameters are: chamber pressure 40-80mT; upper electrode power 400-800W; lower electrode power 200-400W; CF4 gas flow 20-70sccm; CHF3 flow 35-50sccm; Ar gas flow 200-400sccm; etching time 10-20s.
[0021] Preferably, in step 4, the silicon carbide epitaxial layer is etched using a dry etching process, and the specific method is:
[0022] The silicon carbide epitaxial layer is etched by an ICP type etcher in By Time mode, and the process parameters are: chamber pressure 10-20mT; upper electrode power 1000-2000W; lower electrode power 500-1000W; SF6 gas flow 10-20sccm; Ar gas flow 100-200sccm; O2 gas flow 10-30sccm; etching time 150-250s.
[0023] Preferably, in step 5, the residual photoresist on the surface is removed by a dry-wetting method.
[0024] Preferably, the method for preparing a barrier layer on a TEOS layer and damaging the barrier layer is specifically as follows:
[0025] Poly deposition and TEOS deposition are performed on the TEOS layer to form an OPO structure with the TEOS layer, and the OPO structure serves as a barrier layer for Poly etching and a damage barrier layer for subsequent high-energy implantation processes.
[0026] According to a second aspect of the present application, a semiconductor device is provided, which is produced by a wafer substrate manufactured by the above-mentioned substrate material zero alignment mark etching method.
[0027] According to an embodiment of the present application, the beneficial effect of using the substrate material zero alignment mark etching method is that by changing the mask type, a combined mask of photoresist (photoresist) plus TEOS is used to replace a single photoresist mask, so as to achieve a deeper etching depth without changing the side wall angle, thereby improving the contrast of the zero alignment mark, solving the problem of abnormal alignment in subsequent processes, and improving process stability;
[0028] The addition of TEOS in the mask can play a better role in protecting the mask corners, so that the photoresist can be used as a mask to perform etching blocking to the maximum extent;
[0029] The TEOS layer thickness is 500Å and can also be used as a Poly etch stop layer for the subsequent PBD process. There is no need to perform an additional TEOS Remove process after etching the zero alignment mark, thus achieving the purpose of controlling costs. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] In order to more clearly illustrate the embodiments of the present application or the existing technical solutions, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.
[0031] Figure 1 This is a flow chart of a method for etching a zero alignment mark of a substrate material in one embodiment of the present application;
[0032] Figure 2 for Figure 1 Schematic diagram of the structure of the mask on the substrate. DETAILED DESCRIPTION
[0033] In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.
[0034] like Figure 1 As shown, a method for etching a zero alignment mark of a substrate material in an embodiment of the present application includes the following steps:
[0035] Step 1: Prepare a silicon carbide wafer substrate and deposit and grow a TEOS layer on the epitaxial layer of the substrate;
[0036] In this step, a 500 angstrom TEOS layer is deposited and grown on the epitaxial surface of the wafer substrate by using PECVD. The specific method is as follows: the wafer substrate is cleaned and pre-treated to remove surface impurities and contaminants, and the substrate is placed in the reaction chamber of the PECVD equipment, and its position is ensured to be correct and stable;
[0037] According to the required TEOS layer thickness (500 angstroms), calculate and prepare the appropriate amount of TEOS precursor gas and other necessary reaction gases (such as oxygen, nitrogen, etc.); use a mass flow meter to accurately control the flow of each reaction gas to ensure the stability and uniformity of the reaction;
[0038] Set the temperature and pressure of the reaction chamber. The specific parameters are: chamber pressure 5-10 Torr; power 400-600 W; temperature 300-400 ° C; TEOS flow 500-600 sccm; He flow 600-800 sccm; O2 flow 500-600 sccm; deposition time 10-20 s;
[0039] Start the RF power supply to generate plasma. The plasma excites the reaction gas through glow discharge and other methods, decomposing it into active particles. These active particles undergo chemical reactions on the substrate surface and gradually form a TEOS film.
[0040] During the film growth process, real-time monitoring technology (such as ellipsometer, reflectometer, etc.) is used to monitor the thickness and growth rate of the film; when the TEOS film reaches the required thickness of 500 angstroms, the supply of the reaction gas is stopped and the RF power is turned off;
[0041] The reaction chamber is cooled and the substrate is taken out of the chamber; necessary post-processing, such as annealing and cleaning, is performed on the substrate on which the TEOS film is grown to improve the quality and stability of the film.
[0042] The TEOS layer is an organic silicon compound layer formed by chemical vapor deposition of tetraethoxysilane. In other embodiments, APCVD and LPCVD processes may be used instead.
[0043] Step 2: coating photoresist on the surface of the TEOS layer, and forming a zero alignment mark pattern through exposure and development processes;
[0044] In this step, a layer of photoresist is coated on the surface of the TEOS layer, and the thickness of the coated photoresist is 2.0 um; then, a zero alignment mark pattern is formed by exposure and development process, so that the side wall angle of the zero alignment mark pattern is greater than 85°. The specific method is as follows:
[0045] Spin coating is used to coat the TEOS layer with photoresist. The photoresist is evenly covered on the wafer surface by the high-speed rotation of the coating machine. After a certain drying process, the solvent in the photoresist is removed to ensure its stability in subsequent processes.
[0046] After the photoresist is coated, pre-baking is performed to soften the photoresist and improve its adhesion, while further removing the solvent in the photoresist;
[0047] The wafer coated with photoresist is placed in the photolithography machine. Through precise alignment and positioning, the pattern on the mask is precisely matched with the photoresist on the wafer. The photoresist is irradiated with a light source of a specific wavelength (such as ultraviolet light), so that the photoresist undergoes a chemical reaction under the action of light, forming a latent image corresponding to the mask pattern.
[0048] After exposure, the wafer is placed in a constant temperature oven again to control the temperature and time to make the chemical reaction in the photoresist more stable, thus ensuring that the latent image will not change during the subsequent development process.
[0049] Use a specific chemical solution (developer) to remove the parts of the photoresist that have not reacted chemically (or the parts that have undergone a specific chemical reaction), leaving a pattern corresponding to the mask pattern. Finally, use deionized water or dry air to clean and dry the wafer to remove residual developer and moisture, and complete the etching of the zero alignment mark pattern.
[0050] In this step, since the selection of photoresist determines the applicable profile angle of the photoresist, in order to ensure that the side wall angle is greater than 85°, AR80 photoresist is selected in this step, and the post-baking conditions after development are controlled to bake it on a hot plate at 90-100°C for 60s to achieve this angle. Too high a temperature or too long a time will cause the angle of the photoresist to be lower than 85°.
[0051] Step 3: etching the TEOS layer in the zero alignment mark pattern to expose the silicon carbide epitaxial layer;
[0052] In this step, a 500 angstrom TEOS layer is etched away using a dry etching process, and the specific method is as follows:
[0053] After cleaning and pre-treating the wafer, place the substrate in the reaction chamber of the dry etching equipment and ensure that it is positioned correctly and stably;
[0054] According to the required TEOS layer thickness (500 angstroms), calculate and prepare the appropriate amount of etching gas. In this step, select CF4 and CHF3;
[0055] The temperature and pressure of the reaction chamber are set to be within a range suitable for the dry etching process. In this step, a CCP type etcher is used, and the process parameters are: chamber pressure 40-80mT; upper electrode power 400-800W; lower electrode power 200-400W; CF4 gas flow 20-70sccm; CHF3 flow 35-50sccm; Ar gas flow 200-400sccm; etching time 10-20s;
[0056] Start the RF power supply to generate plasma. The plasma excites the etching gas through glow discharge and other methods, causing it to decompose into active particles; these active particles undergo chemical reactions on the substrate surface, gradually forming the etching area of the TEOS film;
[0057] Use real-time monitoring technology (such as ellipsometer, reflectometer, etc.) to monitor the thickness and etching rate of the film. According to the monitoring results, adjust the parameters such as the flow rate, temperature or plasma power of the etching gas in a timely manner to ensure the uniformity of the film and the realization of the target thickness;
[0058] When the TEOS film reaches the required thickness of 500 angstroms, the supply of etching gas is stopped and the RF power is turned off; the reaction chamber is cooled, and the substrate is taken out of the chamber, and necessary post-processing is performed on the etched substrate, such as cleaning and drying, to improve the quality and stability of the film.
[0059] In this step, a large flow of Ar is introduced to give the Rec ipe Body a stronger physical bombardment ability. At the same time, the low-pressure environment reduces the probability of plasma collision and increases the energy obtained by ion acceleration, which is conducive to forming a highly vertical silicon oxide morphology and realizing the vertical morphology transfer from photoresist to TEOS, so that the side wall angle of the zero-position alignment mark pattern on the TEOS layer is greater than 88°.
[0060] In this step, CF4, CHF3 and Ar are used as etching gases, and the selectivity of the photoresist to the TEOS layer can reach 3:1. After the TEOS layer is etched, the residual film thickness of the photoresist can still reach more than 1.3um.
[0061] Step 4: etching the silicon carbide epitaxial layer in the zero alignment mark pattern to a required depth of the zero alignment mark;
[0062] In this step, an ICP type etcher is used in a By Time mode to etch the silicon carbide epitaxial layer using a dry etching process. The specific method is as follows:
[0063] After the wafer is cleaned and pre-treated, it is placed in the reaction chamber of the ICP etching equipment and its position is ensured to be correct and stable;
[0064] According to the required etching effect, select the appropriate etching gas. In this step, select SF6 gas, and use a mass flow meter to accurately control the flow of each etching gas to ensure the stability and uniformity of the reaction;
[0065] Set the temperature and pressure of the reaction chamber. The process parameters selected in this step are: chamber pressure 10-20mT; upper electrode power 1000-2000W; lower electrode power 500-1000W; SF6 gas flow 10-20sccm; Ar gas flow 100-200sccm; O2 gas flow 10-30sccm; etching time 150-250s;
[0066] Start the RF power supply, the generated electrons and Ar ions are accelerated in the high-frequency electromagnetic field, collide with neutral atoms, ionize more working gas, and form plasma gas. The strong induced current induced by the conductive plasma gas under the action of the magnetic field generates a large amount of heat energy, which heats the plasma again, making its temperature reach 1×10^4K, forming ICP discharge;
[0067] During the etching process, real-time monitoring technology (such as ellipsometer, reflectometer, etc.) is used to monitor the thickness and etching rate of the film;
[0068] When the silicon carbide epitaxial layer reaches the required etching depth, the supply of etching gas is stopped and the RF power is turned off; the reaction chamber is cooled, and the substrate is taken out of the chamber, and necessary post-processing is performed on the etched substrate, such as cleaning and drying, to improve the quality and stability of the film.
[0069] In the above steps, as the etching process proceeds, the photoresist around the zero alignment mark will be gradually consumed, especially at the corners where the photoresist is consumed faster, thus gradually exposing the TEOS layer at the bottom of the photoresist. A large flow of O2 gas is added in this step, and the higher upper electrode power provides a large amount of plasma to increase the etching rate. The higher lower electrode power gives the ions a stronger directionality, so that the entire reaction obtains a stronger anisotropy. The introduction of a large flow of O2 makes it in an oxygen-rich state during the equilibrium reaction of Si and O2 to form SiO2, and the consumption of SiO2 is greatly reduced, thereby obtaining a higher SIC:SiO2 selectivity.
[0070] The high selectivity of SiC to oxide (usually >6:1) is used to protect the photoresist corner, so that the photoresist can be used as much as possible for etching blocking. Finally, the maximum etching depth of the zero alignment mark can be increased from 5000A to 6500A, and the side wall angle of the zero alignment mark can still reach 88° to 90°.
[0071] Step 5: After removing the remaining photoresist, a barrier layer and a damage barrier layer are prepared on the TEOS layer to complete the production of the zero alignment mark.
[0072] In this step, the remaining photoresist on the surface is removed by a dry-wet method. The specific method is as follows:
[0073] The substrate after film formation is initially debonded by immersing it in a debonding liquid for 1-2 hours. The substrate after initial debonding is placed in a dry etching machine and high-purity oxygen and argon are introduced for dry etching for 3-10 minutes to quickly remove the residual glue of the remaining photosensitive adhesive.
[0074] After removing the photoresist, the method of preparing a barrier layer on the TEOS layer and damaging the barrier layer is specifically as follows:
[0075] Poly deposition and TEOS deposition are performed on the TEOS layer to form an OPO structure with the TEOS layer, and the OPO structure serves as a barrier layer for Poly etching and a damage barrier layer for subsequent high-energy implantation processes. In this embodiment, the thicknesses of the TEOS layer, the Poly layer, and the upper TEOS layer from bottom to top are 500A, 4000A, and 20000A, respectively. This thickness mainly depends on the implantation requirements, product performance design, etc., and needs to be optimized and matched with the capabilities of the subsequent etching process.
[0076] In this step, the TEOS layer is directly combined with the photoresist as a mask. When the optimized zero-position alignment mark is achieved, the subsequent OPO structure does not need to re-deposit Teos. Compared with the traditional method of directly etching the zero-position alignment mark with photoresist, it not only optimizes the depth of the mark, but also does not need to add a cleaning process and a bottom TEOS deposition process, which greatly reduces the process cost and improves efficiency.
[0077] According to a second aspect of the present application, a semiconductor device is provided, which is produced by a wafer substrate manufactured by the above-mentioned substrate material zero alignment mark etching method.
[0078] According to an embodiment of the present application, the beneficial effect of using the substrate material zero alignment mark etching method is that by changing the mask type, a combined mask of photoresist + TEOS is used to replace a single photoresist mask, so as to achieve a deeper etching depth without changing the side wall angle, thereby improving the contrast of the zero alignment mark, solving the problem of abnormal alignment in subsequent processes, and improving process stability;
[0079] The addition of TEOS in the mask can provide better protection for the mask corners, allowing PR to function as a mask for etching blocking to the maximum extent;
[0080] The TEOS layer thickness is 500Å and can also be used as a Poly etch stop layer for the subsequent PBD process. There is no need to perform an additional TEOS Remove process after etching the zero alignment mark, thus achieving the purpose of controlling costs.
[0081] It should be noted that the above detailed descriptions are exemplary and are intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present application belongs.
[0082] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should also be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.
[0083] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein.
[0084] In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or inherent to these processes, methods, products, or apparatuses.
[0085] For ease of description, spatially relative terms, such as "above", "above", "on the upper surface of", "above", etc., may be used herein to describe the spatial positional relationship between a device or feature and other devices or features as shown in the figure. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" may include both "above" and "below". The device may also be positioned in other different ways, such as rotated 90 degrees or in other orientations, and the spatially relative descriptions used herein are interpreted accordingly.
[0086] In the above detailed description, reference is made to the accompanying drawings, which form a part of this document. In the accompanying drawings, similar symbols typically identify similar components unless the context indicates otherwise. The illustrated embodiments described in the detailed description, drawings, and claims are not meant to be limiting. Other embodiments may be used, and other changes may be made, without departing from the spirit or scope of the subject matter presented herein.
[0087] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.
Claims
1. A method for etching a zero alignment mark of a substrate material, characterized in that: The steps include: Step 1: Prepare a silicon carbide wafer substrate and deposit and grow a TEOS layer on the epitaxial layer of the substrate; Step 2: coating photoresist on the surface of the TEOS layer, and forming a zero alignment mark pattern through exposure and development processes; Step 3: etching the TEOS layer in the zero alignment mark pattern to expose the silicon carbide epitaxial layer; Step 4: etching the silicon carbide epitaxial layer in the zero alignment mark pattern to a required depth of the zero alignment mark; Step 5: After removing the remaining photoresist, a barrier layer and a damage barrier layer are prepared on the TEOS layer to complete the production of the zero alignment mark.
2. The method for etching a zero alignment mark of a substrate material according to claim 1, characterized in that: In step 1, a 500 angstrom TEOS layer is deposited and grown on the epitaxial surface of the substrate by using PECVD.
3. The method for etching a zero alignment mark of a substrate material according to claim 2, characterized in that: The process parameters for depositing and growing the TEOS layer are: chamber pressure 5-10 Torr; power 400-600 W; temperature 300-400° C.; TEOS flow 500-600 sccm; He flow 600-800 sccm; O2 flow 500-600 sccm; deposition time 10-20 s.
4. The method for etching a zero alignment mark of a substrate material according to claim 2, characterized in that: In step 2, the photoresist is AR80 photoresist, and the photoresist coating thickness is 2.0 um.
5. The method for etching a zero alignment mark of a substrate material according to claim 4, characterized in that: In step 2, the zero position alignment mark pattern formed by exposure and development process has a side wall angle greater than 85°.
6. The method for etching a zero alignment mark of a substrate material according to claim 5, characterized in that: In step 3, a 500 angstrom TEOS layer is etched away using a dry etching process, and the specific method is as follows: A CCP type etcher is used, and the process parameters are: chamber pressure 40-80mT; upper electrode power 400-800W; lower electrode power 200-400W; CF4 gas flow 20-70sccm; CHF3 flow 35-50sccm; Ar gas flow 200-400sccm; etching time 10-20s.
7. The method for etching a zero alignment mark of a substrate material according to claim 5, characterized in that: In step 4, the silicon carbide epitaxial layer is etched using a dry etching process, and the specific method is as follows: The silicon carbide epitaxial layer is etched by an ICP type etcher in By Time mode, and the process parameters are: chamber pressure 10-20mT; upper electrode power 1000-2000W; lower electrode power 500-1000W; SF6 gas flow 10-20sccm; Ar gas flow 100-200sccm; O2 gas flow 10-30sccm; etching time 150-250s.
8. The method for etching a zero alignment mark of a substrate material according to claim 1, characterized in that: In step 5, the remaining photoresist on the surface is removed by using a dry-wet method.
9. The method for etching a zero alignment mark of a substrate material according to claim 1, characterized in that: The method for preparing a barrier layer on a TEOS layer and damaging the barrier layer is specifically as follows: Poly deposition and TEOS deposition are performed on the TEOS layer to form an OPO structure with the TEOS layer, and the OPO structure serves as a barrier layer for Poly etching and a damage barrier layer for subsequent high-energy implantation processes.
10. A semiconductor device, characterized in that: The wafer substrate is produced by using the substrate material zero alignment mark etching method as described in any one of claims 1 to 9.