3D chip packaging method and packaging device

Abstract

The embodiment of the invention provides a 3D chip packaging method and packaging device, and the method comprises the steps: enabling a plurality of middle-layer chips to be stacked in sequence, and enabling the middle-layer chips to be arranged in a bottom-layer chip, so as to form a plurality of chip stacking modules which are distributed at intervals in the transverse direction of the bottom-layer chip; stacking the top-layer chip on the uppermost-layer and middle-layer chip of each chip stacking module; forming a plastic package layer wrapping the bottom layer chip, the plurality of chip stacking modules and the plurality of top layer chips respectively; cutting is carried out in the direction from the top layer chip to the bottom layer chip and along the plastic packaging layer between the two adjacent chip stacking modules, and a first cutting channel is formed; and cutting the bottom-layer chip from the bottom-layer chip to the top-layer chip to form a second cutting channel connected with the first cutting channel. According to the method, the stress of the 3D chip is released in a double-sided cutting mode, the influence of overlarge warping is reduced, packaging of the 3D chip is not damaged, and the reliability of a packaging device is improved.

Description

Technical Field

[0001] The embodiments of the present disclosure belong to the field of semiconductor packaging technology, and specifically relate to a 3D chip packaging method and a packaging device. Background Art

[0002] In the preparation process of existing 3D packaging, the chip has a large warping (>2mm) due to the presence of plastic packaging materials and Si materials, and different thermal expansion coefficients, which leads to stress concentration. Direct cutting will cause microcracks and hidden cracks. The heat-sensitive characteristics of 3D chips cannot reduce stress and avoid surface microcracks by laser grooving. Figure 1 As shown, current technology directly performs mechanical cutting on the surface of the silicon adapter board. Because the silicon adapter board is thin and contains a large proportion of epoxy resin (the higher the stack, the more EMC content), stress is released instantly during the cutting process, which will cause hidden cracks, such as Figure 2 The micro crack a shown affects the reliability of the packaged device.

[0003] In view of the above problems, it is necessary to propose a 3D chip packaging method and packaging device that are reasonably designed and effectively solve the above problems. Summary of the invention

[0004] The embodiments of the present disclosure aim to solve at least one of the technical problems existing in the prior art and provide a 3D chip packaging method and a packaging device.

[0005] An aspect of an embodiment of the present disclosure provides a 3D chip packaging method.

[0006] The law includes:

[0007] Providing a bottom chip, a top chip and a plurality of middle chips, wherein the bottom chip and the middle chip are each provided with a plurality of through silicon vias penetrating the thickness thereof;

[0008] Stacking a plurality of the intermediate layer chips in sequence to arrange the bottom layer chip, so as to form a plurality of chip stacking modules spaced apart and distributed in a lateral direction of the bottom layer chip;

[0009] Stacking the top layer chip on the topmost middle layer chip of each chip stacking module;

[0010] Forming plastic packaging layers respectively wrapping the bottom chip, the plurality of chip stacking modules and the plurality of top chips;

[0011] Cutting from the top chip toward the bottom chip and along the plastic packaging layer between two adjacent chip stacking modules to form a first cutting path;

[0012] The bottom chip is cut from the bottom chip to the top chip to form a second cutting street connected to the first cutting street.

[0013] Optionally, the width of the second cutting street is greater than the width of the first cutting street.

[0014] Optionally, the depth of the first cutting road is greater than 1 / 2 of the total stacking thickness of the chips.

[0015] Optionally, a plurality of grooves are formed in an edge region of the top chip on a side facing away from the bottom chip;

[0016] When the plastic sealing layer is formed, the groove is filled with a plastic sealing material;

[0017] After forming the plastic encapsulation layer, the method further includes:

[0018] The side of the top chip facing away from the bottom chip is thinned, and then the groove filled with plastic packaging material is thinned to form a cutting mark; wherein the depth of the groove is greater than the thinned thickness of the top chip.

[0019] Optionally, the cutting from the top chip to the bottom chip and along the plastic packaging layer between two adjacent chip stacking modules to form a first cutting path includes:

[0020] According to the cutting mark of the top chip, cutting is performed along the plastic packaging layer between two adjacent chip stacking modules to form the first cutting path.

[0021] Optionally, stacking a plurality of the intermediate layer chips in sequence to arrange the bottom layer chip includes:

[0022] Bonding the conductive bumps of the bottommost intermediate layer chip to the pads of the bottom layer chip;

[0023] The conductive bumps of the upper intermediate layer chip are bonded to the pads of the adjacent lower intermediate layer chip.

[0024] Optionally, stacking the top layer chip on the topmost middle layer chip of each chip stacking module includes:

[0025] The conductive bumps of the top layer chip are bonded to the pads of the uppermost middle layer chip in the chip stacking module.

[0026] Optionally, before stacking the plurality of intermediate layer chips in sequence to form the bottom layer chip, the method includes:

[0027] The side of the bottom chip facing away from the top chip is fixed to the first temporary carrier through a bonding adhesive layer.

[0028] Optionally, before cutting the bottom chip, the method further includes:

[0029] Fixing a side of the top chip facing away from the bottom chip to a second temporary carrier;

[0030] Removing the bonding adhesive layer and the first temporary carrier to expose the conductive bumps of the bottom chip;

[0031] After forming the second cutting street, the method further includes:

[0032] The second temporary carrier is removed to form a plurality of 3D chip packaging devices.

[0033] Another aspect of the embodiments of the present disclosure provides a 3D chip packaging device, which is packaged using the 3D chip packaging method described above.

[0034] The 3D chip packaging method and packaging device of the disclosed embodiment include: stacking each layer of chips in sequence to form a plastic layer that wraps each chip, cutting from the top chip to the bottom chip and along the plastic layer between two adjacent chip stacking modules to form a first cutting path, complete stress release, and balance warping; then cut the bottom chip from the bottom chip to the top chip to form a second cutting path connected to the first cutting path. The double-sided secondary cutting method is used to release the stress of the 3D chip, reduce warping, accurately cut and package without damage, avoid hidden cracks, achieve damage-free 3D chip packaging, and improve the reliability of the packaged device. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a schematic diagram of a cut cross section of a 3D chip package in the prior art;

[0036] Figure 2 A schematic diagram of a cross section of hidden cracks and micro cracks generated by cutting a 3D chip package in the prior art;

[0037] Figure 3 A schematic diagram of a 3D chip packaging method according to an embodiment of the present disclosure;

[0038] Figures 4 to 12 This is a packaging process schematic diagram of a 3D chip packaging method according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] In order to enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, the embodiments of the present disclosure are further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0040] like Figure 3 As shown, one aspect of an embodiment of the present disclosure provides a 3D chip packaging method S100, the 3D chip packaging method S100 comprising:

[0041] S110, providing a bottom chip, a top chip and a plurality of middle chips, wherein the bottom chip and the middle chip are both provided with a plurality of through silicon vias penetrating the thickness thereof.

[0042] like Figures 4 to 12 As shown, a bottom chip 110, a top chip 120 and a plurality of middle chips 130 are provided, wherein Figure 4 and Figure 5 As shown, the bottom chip 110 and the top chip 120 are both provided with a plurality of through silicon vias (TSVs) b that penetrate through their thicknesses, and vertical interconnection between the stacked chips can be achieved through the TSVs b. No TSVs are provided in the top chip 120.

[0043] S120, stacking the plurality of intermediate layer chips in sequence on the bottom layer chip to form a plurality of chip stacking modules that are spaced apart and distributed laterally on the bottom layer chip.

[0044] First, if Figure 4 As shown, the side of the bottom chip 110 facing away from the top chip 120 is fixed to the first temporary carrier 142 through the bonding layer 141. The conductive protrusion 111 of the bottom chip 110 is wrapped in the bonding layer 141 to protect the conductive protrusion 111 of the bottom chip 110.

[0045] Secondly, if Figure 5 As shown, the conductive bumps 131 of the bottom intermediate layer chip 130 are bonded to the pads 112 of the bottom chip 110 to stack the bottom intermediate layer chip 130 on the bottom chip 110. In other words, the bottom intermediate layer chip 130 is flip-chip mounted on the bottom chip 110.

[0046] Again, if Figure 5 As shown, the conductive bumps 131 of the upper intermediate layer chip 130 are bonded to the pads 132 of the adjacent lower intermediate layer chip 130 to achieve sequential stacking of multiple intermediate layer chips 130, thereby forming multiple chip stacking modules A spaced apart along the lateral direction of the bottom chip 110. In other words, each chip stacking module A includes multiple sequentially stacked intermediate layer chips 130, and the multiple intermediate layer chips 130 are sequentially flip-chip connected.

[0047] S130, stacking the top layer chip on the topmost middle layer chip of each chip stacking module.

[0048] Specifically, Figure 6 As shown, the conductive bumps 121 of the top chip 120 are bonded to the pads 132 of the top middle chip 130 in the chip stacking module A, and the top chip is stacked on the top middle chip 130 in each chip stacking module A. In other words, the top chip 120 is flipped on the top middle chip 130.

[0049] Among them, Figure 6 As shown, a plurality of grooves 122 are formed in advance in the edge region of the top chip 120 facing away from the bottom chip 110 by dry etching process.

[0050] S140, forming a plastic packaging layer to respectively wrap the bottom chip, the plurality of chip stacking modules and the plurality of top chips.

[0051] like Figure 7 As shown, a plastic encapsulation layer 150 is formed on the side of the bottom chip 110 facing the top chip 120, and the plastic encapsulation layer 150 respectively wraps the bottom chip 110, multiple chip stacking modules A and multiple top chips 120, thereby protecting the bottom chip 110, multiple chip stacking modules A and multiple top chips 120.

[0052] At the same time, when the plastic packaging layer 150 is formed, the groove 122 of the top chip 120 is also filled with plastic packaging material accordingly.

[0053] Exemplarily, after forming the plastic encapsulation layer 150, the packaging method further includes:

[0054] like Figure 8 As shown, the side of the top chip 120 facing away from the bottom chip 110 is ground and thinned, and then the groove 122 filled with plastic packaging material is thinned to form a cutting mark B; wherein the depth of the groove 122 is greater than the thinned thickness of the top chip 120 to ensure that the cutting mark B is retained after grinding and thinning.

[0055] S150, cutting from the top chip toward the bottom chip and along the plastic packaging layer between two adjacent chip stacking modules to form a first cutting path.

[0056] Specifically, Fig. 9 As shown, according to the cutting mark B of the top chip 120, cutting is performed along the plastic packaging layer 150 between two adjacent chip stacking modules A to form a first cutting line C, thus completing the first cutting.

[0057] In this embodiment, the top chip itself forms a "natural cutting path" because the plastic encapsulation material and Si are different media, but there are no characteristic patterns and identification points on the plastic encapsulation material surface and the top chip surface, which will result in the inability to start the slicing, and the operation path is set to operate automatically. Therefore, a cutting mark B is formed at the edge area of ​​the top chip, and the cutting mark B can play a good role in cutting alignment marks when cutting the plastic encapsulation layer 150 from the top chip to the bottom chip, so as to better complete the first cutting of the chip.

[0058] It should be noted that the depth of the first cutting line C is greater than 1 / 2 of the total stacking thickness of the chips, which is more conducive to warpage control and damage-free chip packaging. In other words, the first cutting depth should be greater than 1 / 2 of the total stacking thickness of the chips.

[0059] Specifically, in the preparation of 3D chip stacking, the thickness of each layer of chips is generally the same, about 50um to 100um. The number of stacked chip layers is mostly 3 to 8 layers, and the stacking thickness is greater than the thickness of the bottom chip, so the thickness of the plastic layer is much greater than the thickness of the bottom chip. In order to achieve the stress release effect, the depth of the first cutting path C is set to be greater than 1 / 2 of the total stacking thickness of each chip, excluding most of the connection of the plastic material, reducing the stress effect to a minimum, and facilitating subsequent transfer and cutting.

[0060] In this embodiment, cutting is performed from the top chip to the bottom chip and along the plastic layer between two adjacent chip stacking modules to form a first cutting path, complete stress release, balance warping, reduce warping stress requirements, and achieve damage-free chip packaging.

[0061] S160 , cutting the bottom chip from the bottom chip toward the top chip to form a second cutting street connected to the first cutting street.

[0062] First, if Fig.10 As shown, the side of the top chip 120 facing away from the bottom chip 110 is fixed to the second temporary carrier 160 to achieve chip transfer.

[0063] Secondly, if Fig.11 As shown, the bonding glue layer 141 and the first temporary carrier 142 are removed to expose the conductive bumps 111 of the bottom chip 110 .

[0064] Again, if Fig.12 As shown, the second temporary carrier 160 is used as a carrier, and the bottom chip 110 is cut from the bottom chip 110 to the top chip 120 to form a second cutting line D connected to the first cutting line C. In other words, the bottom chip 110 is cut at a position corresponding to the first cutting line C, and the second cutting of the chip is completed to obtain multiple 3D chip packaged devices, meeting the chip packaging requirements.

[0065] It should be noted that if Fig.12 As shown, the width of the second cutting street D is greater than the width of the first cutting street C, which prevents cutting deviation and improves the reliability of the chip packaging device after cutting.

[0066] Exemplarily, after forming the second cutting street, the method further includes:

[0067] The second temporary carrier 160 is removed to form a plurality of 3D chip packaging devices.

[0068] The 3D chip packaging method of the disclosed embodiment stacks each layer of chips in sequence to form a plastic layer that wraps each chip, then cuts from the top chip to the bottom chip and along the plastic layer between two adjacent chip stacking modules to form a first cutting path, complete stress release, and balance warpage; then cuts the bottom chip from the bottom chip to the top chip to form a second cutting path connected to the first cutting path. The double-sided secondary cutting method is used to release the stress of the 3D chip, reduce warpage, avoid hidden cracks, achieve damage-free 3D chip packaging, and improve the reliability of the packaged device.

[0069] Another aspect of the present disclosure provides a 3D chip packaging device, which is formed by packaging using the 3D chip packaging method S100 described above. The specific process of the 3D chip packaging method S100 has been described in detail above and will not be repeated here.

[0070] The 3D chip packaging device of the embodiment of the present disclosure is formed by packaging using the 3D chip packaging method described above. The formed 3D chip packaging device can avoid the generation of micro cracks, thereby improving the reliability of the 3D chip packaging device.

[0071] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the embodiments of the present disclosure, but the embodiments of the present disclosure are not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the embodiments of the present disclosure, and these modifications and improvements are also considered to be within the protection scope of the embodiments of the present disclosure.

Claims

1. A 3D chip packaging method, characterized in that: The method comprises: Providing a bottom chip, a top chip and a plurality of middle chips, wherein the bottom chip and the middle chip are each provided with a plurality of through silicon vias penetrating the thickness thereof; Stacking a plurality of the intermediate layer chips in sequence to arrange the bottom layer chip, so as to form a plurality of chip stacking modules spaced apart and distributed in a lateral direction of the bottom layer chip; Stacking the top layer chip on the topmost middle layer chip of each chip stacking module; Forming plastic packaging layers respectively wrapping the bottom chip, the plurality of chip stacking modules and the plurality of top chips; Cutting from the top chip toward the bottom chip and along the plastic packaging layer between two adjacent chip stacking modules to form a first cutting path; The bottom chip is cut from the bottom chip to the top chip to form a second cutting street connected to the first cutting street.

2. The method according to claim 1, characterized in that The width of the second scribe line is greater than the width of the first scribe line.

3. The method according to claim 1, characterized in that The depth of the first scribe line is greater than 1 / 2 of the total stacking thickness of the chips.

4. The method according to any one of claims 1 to 3, characterized in that: A plurality of grooves are formed on the edge area of ​​the top chip facing away from the bottom chip; When the plastic sealing layer is formed, the groove is filled with a plastic sealing material; After forming the plastic encapsulation layer, the method further includes: The side of the top chip facing away from the bottom chip is thinned, and then the groove filled with plastic packaging material is thinned to form a cutting mark; wherein the depth of the groove is greater than the thinned thickness of the top chip.

5. The method according to claim 4, characterized in that The cutting is performed in a direction from the top chip to the bottom chip and along the plastic packaging layer between two adjacent chip stacking modules to form a first cutting path, including: According to the cutting mark of the top chip, cutting is performed along the plastic packaging layer between two adjacent chip stacking modules to form the first cutting path.

6. The method according to any one of claims 1 to 3, characterized in that: The step of stacking a plurality of the intermediate layer chips in sequence to arrange the bottom layer chip comprises: Bonding the conductive bumps of the bottommost intermediate layer chip to the pads of the bottom layer chip; The conductive bumps of the upper intermediate layer chip are bonded to the pads of the adjacent lower intermediate layer chip.

7. The method according to any one of claims 1 to 3, characterized in that: The step of stacking the top layer chip on the topmost middle layer chip of each chip stacking module comprises: The conductive bumps of the top layer chip are bonded to the pads of the uppermost middle layer chip in the chip stacking module.

8. The method according to any one of claims 1 to 3, characterized in that: Before stacking a plurality of the intermediate layer chips in sequence to arrange the bottom layer chip, the method comprises: The side of the bottom chip facing away from the top chip is fixed to the first temporary carrier through a bonding adhesive layer.

9. The method according to claim 8, characterized in that Before cutting the bottom chip, the method further includes: Fixing a side of the top chip facing away from the bottom chip to a second temporary carrier; Removing the bonding adhesive layer and the first temporary carrier to expose the conductive bumps of the bottom chip; After forming the second cutting street, the method further includes: The second temporary carrier is removed to form a plurality of 3D chip packaging devices.

10. A 3D chip packaging device, characterized in that: The 3D chip packaging method according to any one of claims 1 to 9 is used for packaging.

Images