Packaging structure and forming method thereof

Abstract

According to the packaging structure and the forming method thereof provided by the invention, the top of the internal rewiring layer of the bridging chip is not provided with a conductive column, so that the overall thickness of the bridging chip is reduced, the defects caused by over-thickness of the bridging chip in a manufacturing process are further reduced, the thickness of a wiring insertion layer formed by the first plastic packaging layer and the bridging chip assembly is reduced, and the reliability of the packaging structure is improved. Therefore, the warping problem and the quality risk of each working procedure in the whole manufacturing process are reduced. In the forming method, the silicon through hole of the bridging chip is exposed in a mode of firstly depositing the protective layer and then thinning the silicon through hole, so that the problem of reliability failure of the packaging structure caused by migration and diffusion of metal ions is avoided. The first plastic package layer is directly formed by adopting a film-assisted plastic package process, so that warping caused by over-thick pre-coated plastic package layer in the manufacturing process is avoided, and the influence of the warping on the manufacturing operation is further avoided; and moreover, the height of other components is reduced, higher connection density is formed, and miniaturization of products is facilitated.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging, and in particular to a packaging structure and a forming method thereof. Background Art

[0002] Advanced Packaging is a new type of electronic packaging technology that aims to integrate multiple chips or other electronic components with higher integration, smaller size, lower power consumption and higher reliability through innovative technical means.

[0003] Wafer Level Package (WLP) is a packaging process in which most of the process steps are performed on wafers. The demand for wafer level packaging is not only limited by the requirements of smaller package size and height, but also must meet the requirements of simplifying the supply chain, reducing overall costs, and improving overall performance.

[0004] Fan-out wafer-level packaging can be divided into die first and die last according to the process. The die first process simply means putting the chip on first and then doing the wiring (Redistribution layer, referred to as RDL). The die last process means doing the wiring first and then putting the chip on after the unit has passed the test. In the advanced packaging structure using the die last, a bridge chip (Si Bridge Die) needs to be buried in the wiring insertion layer (interposer). The bridge chip is a structure with TSV and DTC functions. Among them, one side of the bridge chip needs to be connected to the corresponding redistribution layer through a conductive column (Stud), and the other side needs to be connected to the corresponding redistribution layer through a bump. The thickness of the bridge chip, the thickness of the conductive column, and the thickness of the bump are superimposed, which makes the thickness of the initial pre-coated structure and the thickness of the wiring insertion layer formed in the end thicker, and the warping is larger, which affects the process operation.

[0005] Therefore, how to reduce the thickness of the wiring insertion layer and thus reduce the warping problem has become the focus of current research. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a packaging structure and a method for forming the same, which can reduce the thickness of the wiring insertion layer, thereby reducing the warping problem and quality risk of each process in the overall manufacturing process.

[0007] In order to solve the above problems, an embodiment of the present invention provides a method for forming a packaging structure, including: forming a bridge chip component, the bridge chip component including: a bridge chip, a protective layer, an adhesion layer and a thin film layer; the bridge chip includes a substrate, a silicon through hole penetrating the substrate and an internal redistribution layer covering the top surface of the substrate, the internal redistribution layer is electrically connected to the silicon through hole; the protective layer is arranged on the bottom surface of the substrate and exposes the bottom surface of the silicon through hole, wherein the bottom surface of the silicon through hole is flush with the bottom surface of the protective layer by first depositing the protective layer and then thinning the silicon through hole; the adhesion layer covers the bottom surface of the protective layer and the bottom surface of the silicon through hole; the thin film layer covers the top surface of the internal redistribution layer; the bridge chip component is flipped or mounted on the top surface of a carrier; a film-assisted plastic sealing process is used for plastic sealing to form a first plastic sealing layer, the first plastic sealing layer covers the side surface of the bridge chip component with and the top surface of the carrier, the adhesive layer or the film layer is exposed to the first plastic sealing layer; remove the exposed adhesive layer or the film layer; remove part of the first plastic sealing layer, so that the surface of the first plastic sealing layer facing away from the carrier is flush with the surface of the bridge chip component facing away from the carrier; form a chip packaging component on the surface of the first plastic sealing layer facing away from the carrier and the surface of the bridge chip component facing away from the carrier, and the bridge chip component is electrically connected to the chip packaging component; remove the adhesive layer or the film layer of the carrier and the bridge chip component, and remove part of the first plastic sealing layer, so that the surface of the first plastic sealing layer facing away from the chip packaging component is flush with the surface of the bridge chip component facing away from the chip packaging component; form a bottom interconnection structure on the surface of the first plastic sealing layer facing away from the chip packaging component and the surface of the bridge chip component facing away from the chip packaging component.

[0008] In order to solve the above problems, an embodiment of the present invention further provides a packaging structure, which includes: a bridge chip component, the bridge chip component includes a bridge chip and a protective layer; the bridge chip includes a substrate, a silicon through hole penetrating the substrate, and an internal redistribution layer covering the top surface of the substrate, the protective layer is arranged on the bottom surface of the substrate and exposes the bottom surface of the silicon through hole, and the bottom surface of the silicon through hole is flush with the bottom surface of the protective layer; a first plastic sealing layer, the first plastic sealing layer covers the side surface of the bridge chip component, and the bottom surface of the first plastic sealing layer is flush with the bottom surface of the protective layer, and the top surface of the first plastic sealing layer is flush with the top surface of the internal redistribution layer; a chip packaging component, which is arranged on one surface of the first plastic sealing layer and the bridge chip component, and the bridge chip component is electrically connected to the chip packaging component; a bottom interconnection structure, which is arranged on the other surface of the first plastic sealing layer and the bridge chip component, and the bridge chip component is electrically connected to the bottom interconnection structure; wherein the internal redistribution layer is directly electrically connected to the chip packaging component or the bottom interconnection structure.

[0009] No conductive column is provided on the top of the internal redistribution layer of the bridge chip, which reduces the overall thickness of the bridge chip, thereby reducing the defects caused by the bridge chip being too thick in the process technology, such as reducing the coating thickness when the bridge chip is plastic-sealed, and reducing the thickness of the wiring insertion layer composed of the first plastic sealing layer and the bridge chip component, thereby reducing the warping problem and quality risk of each process in the overall process. The formation method provides a thin film layer on the top of the bridge chip component and an adhesive layer on the bottom of the bridge chip component, which is conducive to the embedding of an ultra-thin bridge chip.

[0010] In the formation method, a bridge chip assembly is first formed, wherein the through silicon vias of the bridge chip are exposed by first depositing a protective layer and then thinning the through silicon vias. During the thinning process, the protective layer can protect the substrate, thereby preventing metal ions (such as copper ions) generated by the thinning of the through silicon vias from migrating and diffusing into the substrate, thereby avoiding reliability failure problems of the packaging structure caused by the migration and diffusion of metal ions.

[0011] In the formation method, a film assistant molding (FAM) process is used to directly form the first plastic encapsulation layer. There is no need to first form a thick pre-coating plastic encapsulation layer and then thin it to form the first plastic encapsulation layer, thereby avoiding warping caused by an overly thick pre-coating plastic encapsulation layer in the process technology, thereby avoiding the warping from affecting the process operation. In addition, directly forming the first plastic encapsulation layer is beneficial to reducing the height of other components (such as the height of metal columns), shortening their spacing and critical dimensions, thereby forming a higher connection density, which is beneficial to the miniaturization of products.

[0012] In the packaging structure formed by the formation method, the bridge chip is directly connected to the chip packaging component or the bottom interconnection structure through the internal redistribution layer fan-out, without the need to fan out through the internal redistribution layer, and then connected to the chip packaging component or the bottom interconnection structure through the conductive column, which better meets the product application requirements of high-frequency and high-speed signals. The top surface of the first plastic encapsulation layer is flush with the top surface of the internal redistribution layer, and the bottom surface of the first plastic encapsulation layer is flush with the bottom surface of the bridge chip component, that is, the upper and lower surfaces of the bridge chip component are at the same height as the surface of the first plastic encapsulation layer, which can further improve the interconnection density between the bridge chip and the top chip packaging component (for example, the top redistribution layer in the chip packaging component) and the bottom interconnection structure (for example, the bottom redistribution layer in the bottom interconnection structure). BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 is a schematic diagram of steps of a method for forming a packaging structure provided by an embodiment of the present invention;

[0015] Figure 2 to Figure 17 is a process flow chart of a method for forming a packaging structure provided by an embodiment of the present invention;

[0016] Fig.18 It is a schematic diagram of a packaging structure formed by a forming method provided in another embodiment of the present invention. DETAILED DESCRIPTION

[0017] The specific implementation manner of the packaging structure and the method for forming the same provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0018] Figure 1 is a schematic diagram of the steps of a method for forming a packaging structure provided by an embodiment of the present invention. Figure 1The formation method comprises: step S10, forming a bridge chip component, the bridge chip component comprises: a bridge chip, a protective layer, an adhesive layer and a thin film layer; the bridge chip comprises a substrate, a silicon through hole penetrating the substrate and an internal redistribution layer covering the top surface of the substrate, the internal redistribution layer is electrically connected to the silicon through hole; the protective layer is arranged on the bottom surface of the substrate and exposes the bottom surface of the silicon through hole, wherein the bottom surface of the silicon through hole is flush with the bottom surface of the protective layer by first depositing the protective layer and then thinning the silicon through hole; the adhesive layer covers the bottom surface of the protective layer and the bottom surface of the silicon through hole; the thin film layer covers the top surface of the internal redistribution layer; step S11, flip-chip or face-up the bridge chip component on the top surface of a carrier; step S12, use a thin film assisted plastic sealing process to perform plastic sealing to form a first plastic sealing layer, the first plastic sealing layer covers the side surface of the bridge chip component and the top surface of the carrier, the adhesive layer or the The film layer is exposed to the first plastic sealing layer; step S13, removing the exposed adhesive layer or the film layer; step S14, removing part of the first plastic sealing layer, so that the surface of the first plastic sealing layer facing away from the carrier is flush with the surface of the bridge chip component facing away from the carrier; step S15, forming a chip packaging component on the surface of the first plastic sealing layer facing away from the carrier and the surface of the bridge chip component facing away from the carrier, and the bridge chip component is electrically connected to the chip packaging component; step S16, removing the adhesive layer or the film layer of the carrier and the bridge chip component, and removing part of the first plastic sealing layer, so that the surface of the first plastic sealing layer facing away from the chip packaging component is flush with the surface of the bridge chip component facing away from the chip packaging component; step S17, forming a bottom interconnection structure on the surface of the first plastic sealing layer facing away from the chip packaging component and the surface of the bridge chip component facing away from the chip packaging component.

[0019] No conductive column is provided on the top of the internal redistribution layer of the bridge chip, which reduces the overall thickness of the bridge chip, thereby reducing the defects caused by the bridge chip being too thick in the process technology, such as reducing the coating thickness when the bridge chip is plastic-sealed, and reducing the thickness of the wiring insertion layer composed of the first plastic sealing layer and the bridge chip component, thereby reducing the warping problem and quality risk of each process in the overall process. The formation method provides a thin film layer on the top of the bridge chip component and an adhesive layer on the bottom of the bridge chip component, which is conducive to the embedding of an ultra-thin bridge chip.

[0020] In the formation method, a bridge chip assembly is first formed, wherein the through silicon vias of the bridge chip are exposed by first depositing a protective layer and then thinning the through silicon vias. During the thinning process, the protective layer can protect the substrate, thereby preventing metal ions (such as copper ions) generated by the thinning of the through silicon vias from migrating and diffusing into the substrate, thereby avoiding reliability failure problems of the packaging structure caused by the migration and diffusion of metal ions.

[0021] In the formation method, a film assistant molding (FAM) process is used to directly form the first plastic encapsulation layer. There is no need to first form a thick pre-coating plastic encapsulation layer and then thin it to form the first plastic encapsulation layer, thereby avoiding warping caused by an overly thick pre-coating plastic encapsulation layer in the process technology, thereby avoiding the warping from affecting the process operation. In addition, directly forming the first plastic encapsulation layer is beneficial to reducing the height of other components (such as the height of metal columns), shortening their spacing and critical dimensions, thereby forming a higher connection density, which is beneficial to the miniaturization of products.

[0022] In the packaging structure formed by the formation method, the bridge chip is directly connected to the chip packaging component or the bottom interconnection structure through the internal redistribution layer fan-out, without the need to fan out through the internal redistribution layer, and then connected to the chip packaging component or the bottom interconnection structure through the conductive column, which better meets the product application requirements of high-frequency and high-speed signals. The top surface of the first plastic encapsulation layer is flush with the top surface of the internal redistribution layer, and the bottom surface of the first plastic encapsulation layer is flush with the bottom surface of the bridge chip component, that is, the upper and lower surfaces of the bridge chip component are at the same height as the first plastic encapsulation layer, which can further improve the interconnection density between the bridge chip and the top chip packaging component (for example, the top redistribution layer in the chip packaging component) and the bottom interconnection structure (for example, the bottom redistribution layer in the bottom interconnection structure).

[0023] Figure 2 to Figure 17 It is a process flow chart of a method for forming a packaging structure provided by an embodiment of the present invention.

[0024] See also Figure 1 and Fig.10, step S10, forming a bridge chip component 100, the bridge chip component 100 includes: a bridge chip 110, a protective layer 120, an adhesive layer 130 and a thin film layer 140; the bridge chip 110 includes a substrate 111, a silicon through hole 112 penetrating the substrate 111 and an internal redistribution layer 114 covering the top surface of the substrate 111, the internal redistribution layer 114 is electrically connected to the silicon through hole 112; the protective layer 120 is arranged on the bottom surface of the substrate 111 and exposes the bottom surface of the silicon through hole 112, wherein the bottom surface of the silicon through hole 112 is flush with the bottom surface of the protective layer 120 by first depositing the protective layer 120 and then thinning the silicon through hole 112; the adhesive layer 130 covers the bottom surface of the protective layer 120 and the bottom surface of the silicon through hole 112; the thin film layer 140 covers the top surface of the internal redistribution layer 114.

[0025] In the bridge chip assembly 100 provided in the embodiment of the present invention, the bottom surface of the silicon through via 112 is flush with the bottom surface of the protective layer 120. When manufacturing the bridge chip assembly 100, the protective layer 120 is first deposited, and then the bottom surface of the silicon through via 112 is ground. During the grinding process, the protective layer 120 can protect the substrate 111, and can prevent the metal ions (such as copper ions) generated by grinding the silicon through via 112 from migrating and diffusing into the substrate 111, thereby avoiding the reliability failure problem of the packaging structure caused by the migration and diffusion of metal ions.

[0026] In one embodiment, the substrate 111 is a silicon substrate, the through silicon via 112 is a copper column, the internal redistribution layer 114 covers the top surface of the silicon substrate and is electrically connected to the top surface of the through silicon via 112, and the internal redistribution layer 114 includes a dielectric layer and a conductive circuit located in the dielectric layer, one side of the conductive circuit is electrically connected to the top surface of the through silicon via 112, and the other side is used to electrically connect to the chip packaging component 170 or the bottom interconnect structure 180. The dielectric layer can be a silicon dioxide layer or a silicon nitride layer. In one embodiment, a passivation layer 113 (marked at Figure 2 ), the passivation layer 113 is used to isolate the silicon through hole 112 from the substrate 111 to prevent the metal ions in the silicon through hole 112 from diffusing into the substrate 111, and the passivation layer 113 includes but is not limited to silicon oxide, silicon nitride and a combination thereof.

[0027] In one embodiment, the protective layer 120 is a single layer structure or a composite layer structure, and its material includes but is not limited to silicon nitride, silicon dioxide or nitrogen silicon dioxide. The adhesion layer 130 is composed of a material with a certain viscosity, such as an acrylic resin series (acrylic). In some embodiments, the adhesion layer 130 is a die attachment film (DAF), which has excellent thermal conductivity and adhesion. The film layer 140 is composed of a material with a certain viscosity and can be removed, for example, a UV-type PI film, which has good viscosity and can be removed by ultraviolet irradiation or wet etching.

[0028] The embodiment of the present invention further provides a method for forming a bridge chip assembly 100. Specifically, the steps of forming the bridge chip assembly 100 include:

[0029] See also Figure 2 , providing a device wafer, the device wafer comprising a bridge chip 110, the bridge chip 110 comprising an initial substrate 200, an initial silicon through-hole 210 extending from the top surface of the initial substrate 200 to the inside of the initial substrate 200, and the internal redistribution layer 114 arranged on the top surface of the initial substrate 200, the side and bottom surfaces of the initial silicon through-hole 210 are covered with a passivation layer 113, and the top surface of the initial silicon through-hole 210 is in contact with the bottom surface of the internal redistribution layer 114.

[0030] In some embodiments, the bridge chip 110 further includes a deep trench capacitor (DTC) 180, which is disposed in the initial substrate 200. In some embodiments, the deep trench capacitor 180 extends from the top surface of the initial substrate 200 to the inside of the initial substrate 200, and the deep trench capacitor 180 is electrically connected to the bottom surface of the internal redistribution layer 114.

[0031] In some embodiments, the step of providing a device wafer specifically includes: providing an initial wafer, the initial wafer including an initial substrate 200, an initial silicon through-via 210 extending from the top surface of the initial substrate 200 to the inside of the initial substrate 200, and a deep trench capacitor 180 extending from the top surface of the initial substrate 200 to the inside of the initial substrate 200; forming an internal redistribution layer 114 on the top surface of the initial substrate 200, the internal redistribution layer 114 being electrically connected to the top surface of the initial silicon through-via 210. In some embodiments, the top surfaces of the initial silicon through-via 210 and the deep trench capacitor 180 are flush with the top surface of the initial substrate 200.

[0032] Optionally, in some embodiments, in order to support the device wafer in the subsequent step of processing the bottom surface of the device wafer (for example, thinning the initial substrate 200), the step of providing the device wafer further includes: Figure 3 , bonding the support substrate 300 to the front side of the device wafer. The support substrate 300 includes but is not limited to a glass substrate. Further, the step of bonding the support substrate 300 to the front side of the device wafer includes: bonding the support substrate 300 to a side of the device wafer having the internal redistribution layer 114. Specifically, this step includes: forming a bonding layer 310 on the top surface of the internal redistribution layer 114, and bonding the support substrate 300 to the device wafer using the surface of the support substrate 300 and the surface of the bonding layer 310 as bonding surfaces.

[0033] See also Figure 4 and Figure 5 , a portion of the initial substrate 200 is removed from the bottom surface of the initial substrate 200 to form the substrate 111 , and the initial silicon through vias 210 protrude from the bottom surface of the substrate 111 .

[0034] In some embodiments, this step may include the following two steps:

[0035] See also Figure 4 , a thinning and flattening process is used to remove a portion of the initial substrate 200 from the bottom surface of the initial substrate 200 to a set distance from the passivation layer 113 of the bottom surface of the initial silicon via 210. Specifically, the initial substrate 200 is processed by a thinning and flattening process from the bottom surface of the initial substrate 200 to a position close to the initial silicon via 210, the initial silicon via 210 is covered by the passivation layer 113, the passivation layer 113 is covered by the initial substrate 200, and the initial silicon via 210 is still not exposed, which can prevent the initial silicon via 210 from exposing copper ions to contaminate the substrate 111. During the thinning process, the supporting substrate 300 supports the device wafer. Figure 4 As shown, in this step, the support substrate 300 is facing downward, and the device wafer is located above the support substrate 300 .

[0036] See also Figure 5 , a portion of the initial substrate 200 is removed from the bottom surface of the initial substrate 200 by dry etching process to form the substrate 111, and the initial silicon through-holes 210 protrude from the bottom surface of the substrate 111. Figure 5As shown, when performing this step, the support substrate 300 is facing downward, and the device wafer is located above the support substrate 300. In this step, the initial silicon through hole 210 is not removed, so that the initial silicon through hole 210 protrudes from the bottom surface of the substrate 111, and the deep trench capacitor 180 is not exposed from the bottom surface of the substrate 111. A dry etching process is used to remove part of the initial substrate 200. The dry etching material can etch the initial substrate 200 without etching the passivation layer 113 on the surface of the initial silicon through hole 210, thereby avoiding copper ion contamination of the substrate 111 and the cavity of the subsequent process.

[0037] See also Figure 6 , forming a protective layer 120 on the bottom surface of the substrate 111. In this embodiment, the protective layer 120 also covers the surface of the passivation layer 113. In this step, the protective layer 120 can be formed by a chemical vapor deposition process (CVD), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD) or other processes. In other embodiments, the protective layer 120 may also only cover the bottom surface of the substrate 111.

[0038] See also Figure 7 , the passivation layer 113 and the initial silicon through hole 210 are thinned from the bottom surface of the initial silicon through hole 210 to form the silicon through hole 112, so that the bottom surface of the silicon through hole 112 is flush with the bottom surface of the protective layer 120, and the side of the silicon through hole 112 is covered with the passivation layer 113. In this step, the surface of the passivation layer 113 is also covered with the protective layer 120, then the protective layer 120 on the top surface of the passivation layer 113, the passivation layer 113 and the initial silicon through hole 210 are thinned in sequence, and when the initial silicon through hole 210 is further thinned, the passivation layer 113 on the side of the initial silicon through hole 210 and the protective layer 120 covering the surface of the passivation layer 113 are also removed synchronously. In this step, the initial silicon through hole 210 can be polished by a chemical mechanical polishing process until the formed silicon through hole 112 meets the preset height requirement. In some embodiments, the bottom surface of the protective layer 120 is simultaneously ground to provide a flat surface for subsequent processes. When the initial through silicon via 210 is ground, the surface of the substrate 111 is covered by the protective layer 120, and the metal ions generated during the grinding cannot diffuse into the substrate 111, thereby avoiding the reliability failure problem of the packaging structure caused by the migration and diffusion of metal ions.

[0039] See also Figure 8, forming the adhesive layer 130, the adhesive layer 130 covers the bottom surface of the protective layer 120 and the bottom surface of the through silicon via 112. The bridge chip assembly 100 is fixed on the wafer ring 350 (Waferring) 350 through the adhesive layer 130. In some embodiments, the bottom surface of the device wafer is fixed on the wafer ring 350 through the adhesive layer 130, and the support substrate 300 faces upward.

[0040] In some embodiments, after the step of forming the adhesion layer 130, the step further includes: Fig. 9 , debonding the support substrate 300. In this step, after debonding the support substrate 300, the bonding layer 310 on the front side of the device wafer is also removed, and the internal redistribution layer 114 is exposed. In some embodiments, a suitable debonding process can be selected according to the characteristics of the temporary bonding adhesive, such as laser debonding, thermal debonding, etc.

[0041] See also Fig.10 , forming the thin film layer 140. The thin film layer 140 covers the top surface of the internal redistribution layer 114. In some embodiments, the thin film layer 140 can be formed by a process such as spin coating or by covering and laminating a dry film of a certain thickness. After forming the thin film layer 140, the device wafer is singulated to form the bridge chip assembly 100.

[0042] The above is an embodiment of forming the bridge chip assembly 100 .

[0043] See also Figure 1 as well as Fig.11 , step S11, the bridge chip assembly 100 is placed on the top surface of a carrier 400 by flipping or mounting. In this embodiment, the bridge chip assembly 100 is mounted on the top surface of the carrier 400, and the adhesive layer 130 is in contact with the top surface of the carrier 400. In another embodiment, the bridge chip assembly 100 is placed on the top surface of the carrier 400 by flipping or mounting, and the film layer 140 is in contact with the top surface of the carrier 400.

[0044] In some embodiments, the carrier 400 is a glass substrate, and a temporary bonding layer 401 and a buffer metal layer 402 are provided on its surface. The bridge chip assembly 100 is disposed on the buffer metal layer 402 by a die attach or die bonding (DA) process. In some embodiments, this step further disposes a metal column 160 on the surface of the carrier 400. The metal column 160 can be formed by an electroplating process, which can better meet the product application requirements of high-frequency and high-speed signals.

[0045] See also Figure 1 as well as Fig.12, step S12, using film assistant molding (FAM) process to perform plastic encapsulation to form a first plastic encapsulation layer 150, the first plastic encapsulation layer 150 covers the side of the bridge chip assembly 100 and the top surface of the carrier 400, and the adhesive layer 130 or the film layer 140 is exposed to the first plastic encapsulation layer 150. In this embodiment, the bridge chip assembly 100 is arranged on the top surface of the carrier 400, and in this step, the film layer 140 is exposed to the first plastic encapsulation layer 150; in another embodiment, the bridge chip assembly 100 is arranged on the top surface of the carrier 400, and the adhesive layer 130 is exposed to the first plastic encapsulation layer 150. When the film assistant molding process is used for plastic encapsulation, the covering film directly covers the surface of the adhesive layer 130 or the film layer 140, and after the covering film is removed, the adhesive layer 130 or the film layer 140 is exposed.

[0046] The film-assisted molding process can directly form a first molding layer 150 with a set height, without the need to first form a thick pre-molding molding layer and then thin it to form the first molding layer 150, thereby avoiding warping caused by too thick a pre-molding molding layer in the process, thereby avoiding the warping affecting the process operation; and directly forming the first molding layer 150 is beneficial to reducing the height of other components, such as reducing the height of the metal column 160, which can shorten the spacing between the metal columns 160 and the critical dimensions, thereby forming a higher connection density, which is beneficial to the miniaturization of the product. Specifically, the spacing and critical dimensions of the metal pillars 160 are related to the height of the metal pillars 160. The higher the height of the metal pillars 160, the larger the spacing and critical dimensions of the metal pillars 160. Since the formation method provided in the embodiment of the present invention does not need to first form a thick pre-coating plastic encapsulation layer and then thin it to form the first plastic encapsulation layer 150, when the metal pillars 160 are set on the surface of the carrier 400, it is not necessary to form the metal pillars 160 with the same height as the pre-coating plastic encapsulation layer. It is only necessary to form the metal pillars 160 with the same height as the first plastic encapsulation layer 150. The height of the metal pillars 160 is reduced, and the spacing and critical dimensions of the metal pillars 160 can be shortened, thereby forming a higher connection density, which is conducive to the miniaturization of the product.

[0047] In some embodiments, after the first plastic encapsulation layer 150 is formed, the surface of the first plastic encapsulation layer 150 facing away from the carrier 400 is flush with the surface of the bridge chip assembly 100 facing away from the carrier 400. Specifically, in this embodiment, the bridge chip assembly 100 is disposed upright on the top surface of the carrier 400. Fig.12As shown, the surface of the first plastic encapsulation layer 150 facing away from the carrier 400 is flush with the top surface of the film layer 140; further, in this embodiment, the surface of the metal pillar 160 facing away from the carrier 400 is flush with the surface of the first plastic encapsulation layer 150 facing away from the carrier 400. In another embodiment, the bridge chip assembly 100 is flip-chip mounted on the top surface of the carrier 400, and the surface of the first plastic encapsulation layer 150 facing away from the carrier 400 is flush with the bottom surface of the adhesive layer 130.

[0048] In other embodiments, after the first plastic encapsulation layer 150 is formed, the surface of the first plastic encapsulation layer 150 facing away from the carrier 400 is lower than the surface of the bridge chip assembly 100 facing away from the carrier 400. Specifically, in one embodiment, the bridge chip assembly 100 is disposed upright on the top surface of the carrier 400, and the surface of the first plastic encapsulation layer 150 facing away from the carrier 400 is lower than the top surface of the film layer 140. In another embodiment, the bridge chip assembly 100 is disposed flip-chip on the top surface of the carrier 400, and the surface of the first plastic encapsulation layer 150 facing away from the carrier 400 is lower than the bottom surface of the adhesive layer 130.

[0049] See also Figure 1 as well as Fig.13 , step S13, removing the exposed adhesive layer 130 or the film layer 140. In this embodiment, the bridge chip assembly 100 is disposed upright on the top surface of the carrier 400, and the film layer 140 is removed in this step; in another embodiment, the bridge chip assembly 100 is disposed flip-down on the top surface of the carrier 400, and the adhesive layer 130 is removed in this step.

[0050] In this step, the exposed adhesive layer 130 or the thin film layer 140 may be removed by ultraviolet irradiation, wet etching, dry etching, or the like, or by using a high-viscosity material film layer adhesion method. After removing the adhesive layer 130 or the thin film layer 140, the top surface of the internal redistribution layer 114 is lower than the top surface of the first plastic encapsulation layer 150, forming a groove.

[0051] See also Figure 1 as well as Fig.14, step S14, removing part of the first plastic encapsulation layer 150, so that the surface of the first plastic encapsulation layer 150 away from the carrier 400 is flush with the surface of the bridge chip assembly 100 away from the carrier 400. In this embodiment, the bridge chip assembly 100 is arranged upright on the top surface of the carrier 400, and after removing part of the first plastic encapsulation layer 150, the surface of the first plastic encapsulation layer 150 away from the carrier 400 is flush with the top surface of the internal redistribution layer 114; in another embodiment, the bridge chip assembly 100 is arranged flip-chip on the top surface of the carrier 400, and after removing part of the first plastic encapsulation layer 150, the surface of the first plastic encapsulation layer 150 away from the carrier 400 is flush with the bottom surface of the protective layer 120. In some embodiments, the surface of the first plastic sealing layer 150 facing away from the carrier 400 is flush with the surface of the bridge chip component 100 facing away from the carrier 400, including that the surface of the first plastic sealing layer 150 facing away from the carrier 400 and the surface of the bridge chip component 100 facing away from the carrier 400 are in the same plane, or the surface of the first plastic sealing layer 150 facing away from the carrier 400 is slightly higher than the surface of the bridge chip component 100 facing away from the carrier 400 by a set distance, and the set distance can be 2 to 5 microns.

[0052] In some embodiments, a grinding and planarization process is used to remove part of the first plastic encapsulation layer 150. The metal pillar 160 is also provided in the first plastic encapsulation layer 150. In the step of removing part of the first plastic encapsulation layer 150 by grinding and planarization process, the metal pillar 160 is etched so that the surface of the metal pillar 160 away from the carrier 400 is flush with the surface of the first plastic encapsulation layer 150 away from the carrier 400.

[0053] See also Figure 1 as well as Fig.15 , step S15, forming a chip packaging component 170 on the surface of the first plastic packaging layer 150 away from the carrier 400 and the surface of the bridge chip component 100 away from the carrier 400, and the bridge chip component 100 is electrically connected to the chip packaging component 170. In this embodiment, the bridge chip component 100 is disposed upright on the top surface of the carrier 400, and the chip packaging component 170 is electrically connected to the internal redistribution layer 114; in another embodiment, the bridge chip component 100 is disposed flip-chip on the top surface of the carrier 400, and the chip packaging component 170 is electrically connected to the bottom surface of the through silicon via 112.

[0054] In one embodiment, the chip package assembly 170 includes a top redistribution layer 171, a top pad 172, and a top device 173. The steps of forming the chip package assembly 170 on the surface of the first plastic packaging layer 150 away from the carrier 400 and the surface of the bridge chip assembly 100 away from the carrier 400 include:

[0055] A top redistribution layer 171 is formed on the surface of the first plastic encapsulation layer 150 away from the carrier 400 and the surface of the bridge chip assembly 100 away from the carrier 400. The top redistribution layer 171 includes a dielectric layer and a conductive circuit located in the dielectric layer. The conductive circuit is electrically connected to the bridge chip assembly 100, wherein the conductive circuit is formed by an electroplating process. In one embodiment, the top redistribution layer 171 can be formed by a photolithography process and an electroplating process, for example, by adding layers and stacking them through processes such as coating, exposure, development, electroplating, and degumming to form the top redistribution layer 171.

[0056] A top pad 172 is formed on the top surface of the top redistribution layer 171 , and the top pad 172 is electrically connected to the top redistribution layer 171 .

[0057] A top device 173 is disposed on the top redistribution layer 171, and the top device 173 is soldered to the top pad 172. In some embodiments, the top device 173 is flip-chip mounted on the top redistribution layer 171. The top device 173 is soldered to the top pad 172 via a conductive bump.

[0058] The second plastic encapsulation layer 174 is formed by plastic encapsulation, and the second plastic encapsulation layer 174 covers the top device 173. In some embodiments, before the top device 173 is plastic encapsulated, the process further includes filling a filling layer 175 between the bottom of the top device 173 and the top redistribution layer 171, and the second plastic encapsulation layer 174 also covers the filling layer 175.

[0059] See also Figure 1 and Fig.16, step S16, removing the adhesive layer 130 or the film layer 140 of the carrier 400 and the bridge chip assembly 100, and removing part of the first plastic sealing layer 150, so that the surface of the first plastic sealing layer 150 away from the chip packaging assembly 170 is flush with the surface of the bridge chip assembly 100 away from the chip packaging assembly 170. In this embodiment, the bridge chip assembly 100 is arranged upright on the top surface of the carrier 400, so in this step, the carrier 400 and the adhesive layer 130 of the bridge chip assembly 100 are removed, and the surface of the first plastic sealing layer 150 away from the chip packaging assembly 170 is flush with the bottom surface of the protective layer 120 of the bridge chip assembly 100, and the bottom surface of the first plastic sealing layer 150, the bottom surface of the metal column 160, the bottom surface of the protective layer 120, and the bottom surface of the through silicon via 112 are flush with each other. is exposed; in another embodiment, the bridge chip component 100 is flipped and arranged on the top surface of the carrier 400, then in this step, the carrier 400 and the thin film layer 140 of the bridge chip component 100 are removed, and the surface of the first plastic sealing layer 150 facing away from the chip packaging component 170 is flush with the bottom surface of the thin film layer 140 of the bridge chip component 100, and the top surface of the first plastic sealing layer 150, the top surface of the metal column 160, and the top surface of the internal redistribution layer 114 are exposed.

[0060] In this step, a suitable debonding process is selected according to the characteristics of the temporary bonding adhesive, such as laser debonding, thermal debonding, etc., to remove the carrier 400. After removing the carrier 400, the temporary bonding layer 401 and the buffer metal layer 402 are also removed. In this step, a suitable process is selected according to the material characteristics and molecular system of the adhesion layer 130 or the film layer 140 to remove the adhesion layer 130 or the film layer 140.

[0061] In some embodiments, a grinding and planarization process is used to remove part of the first plastic encapsulation layer 150. In the step of removing the adhesion layer 130 or the thin film layer 140, if a dry etching process is used, the bottom surface of the first plastic encapsulation layer 150 will be too rough. Therefore, when a grinding and planarization process is used to remove part of the first plastic encapsulation layer 150, the bottom surface of the first plastic encapsulation layer 150 can be polished to form a surface with a roughness that meets the requirements. In one embodiment, in the step of removing part of the first plastic encapsulation layer 150 by grinding and planarization process, the metal column 160 is etched so that the surface of the metal column 160 away from the carrier 400 is flush with the surface of the first plastic encapsulation layer 150 away from the carrier 400.

[0062] See also Figure 1 and Fig.17, step S17, forming a bottom interconnection structure 180 on the surface of the first plastic encapsulation layer 150 away from the chip package component 170 and the surface of the bridge chip component 100 away from the chip package component 170. In this embodiment, the bridge chip component 100 is disposed upright on the top surface of the carrier 400, and after this step, the bottom interconnection structure 180 is disposed on the bottom surface of the protection layer 120 and is electrically connected to the through silicon via 112; in another embodiment, the bridge chip component 100 is disposed flip-chip on the top surface of the carrier 400, and after this step, the bottom interconnection structure 180 is disposed on the top surface of the internal redistribution layer 114 and is electrically connected to the internal redistribution layer 114.

[0063] In some embodiments, the step of forming a bottom interconnect structure 180 on a surface of the first plastic encapsulation layer 150 facing away from the chip package component 170 and a surface of the bridge chip component 100 facing away from the chip package component 170 further includes:

[0064] A dielectric layer is formed on the surface of the first plastic encapsulation layer 150 away from the chip package component 170 and the surface of the bridge chip component 100 away from the chip package component 170. In this embodiment, the bridge chip component 100 is disposed upright on the top surface of the carrier 400, and the dielectric layer is formed on the surface of the first plastic encapsulation layer 150 away from the chip package component 170 and the bottom surface of the protective layer 120 of the bridge chip component 100 and the bottom surface of the through silicon via 112 in this step; in another embodiment, the bridge chip component 100 is disposed flip-chip on the top surface of the carrier 400, and the dielectric layer is formed on the surface of the first plastic encapsulation layer 150 away from the chip package component 170 and the top surface of the internal redistribution layer 114 of the bridge chip component 100 in this step.

[0065] A through hole is formed on the dielectric layer to expose the bottom surface of the through silicon via 112 or the pad of the internal redistribution layer 114. In this embodiment, the bridge chip assembly 100 is disposed upright on the top surface of the carrier 400, and after this step, the through hole exposes the bottom surface of the through silicon via 112 and the bottom surface of the metal column 160; in another embodiment, the bridge chip assembly 100 is disposed flip-chip on the top surface of the carrier 400, and after this step, the through hole exposes the pad of the internal redistribution and the top surface of the metal column 160.

[0066] The through hole is sputtered and / or electroplated to form a plating circuit, the plating circuit is in contact with the silicon through via 112 or the pad of the internal redistribution layer 114, and the dielectric layer and the plating circuit are used together as the bottom redistribution layer 181. In this embodiment, the bridge chip component 100 is arranged upright on the top surface of the carrier 400, and after this step, the plating circuit is in contact with the silicon through via 112 and the metal column 160; in another embodiment, the bridge chip component 100 is arranged flip-chip on the top surface of the carrier 400, and after this step, the plating circuit is in contact with the pad of the internal redistribution. In this step, the plating circuit is formed by sputtering and electroplating, and tin (Sn) welding is not required, which eliminates the aging problem of tin welding in the process processing, and there is no problem of voids (Void) and cracks (Crack) appearing at the welding point, which improves the reliability of the packaging structure, and the sputtering and electroplating are coordinated to take into account both efficiency and cost.

[0067] A conductive connection structure 182 is formed on the bottom surface of the bottom redistribution layer 181, and the conductive connection structure 182 and the bottom redistribution layer 181 together serve as the bottom interconnect structure 180. In some embodiments, the conductive connection structure 182 includes but is not limited to a controllably collapsed chip connection bump (C4).

[0068] Optionally, after or before forming the conductive connection structure 182, the second plastic encapsulation layer 174 is thinned to expose the top surface of the top device 173, which is useful for device heat dissipation. Optionally, after forming the conductive connection structure 182, singulation is performed to form a plurality of independent package structures, each of which may include a plurality of the bridge chip components 100 and a plurality of the top devices 173.

[0069] In the above embodiment, the bottom surface of the through silicon via 112 is not provided with a bottom pad, but is directly connected to the bottom interconnection structure 180 or the chip packaging component 170. In another embodiment, the bottom surface of the through silicon via 112 is provided with a bottom pad, and the through silicon via 112 is connected to the bottom interconnection structure 180 or the chip packaging component 170 through the bottom pad. In one embodiment, the bottom pad is a micro pad (μPad). The bottom pad is provided on the bottom surface of the through silicon via 112, so that the thickness of the first plastic sealing layer 150 covering the bridge chip component 100 can be reduced in the packaging structure using the bridge chip component 100, thereby reducing the warping of this part of the structure, which is more conducive to production and yield. In this embodiment, the cross-sectional area of ​​the bottom pad is greater than the cross-sectional area of ​​the through silicon via 112, so as to ensure that the through silicon via 112 can be fully in contact with the bottom pad, reduce the contact resistance, and thus make the delay of the electrical signal smaller.

[0070] Specifically, see Fig.18 , which is a schematic diagram of a packaging structure formed by a forming method provided by another embodiment of the present invention. In this embodiment, the passivation layer 113 and the initial silicon via 210 are thinned from the bottom surface of the initial silicon via 210 to form the silicon via 112 (see Figure 7 ) and then further comprising: forming a bottom pad 190, wherein the bottom pad 190 is disposed on the bottom surface of the through silicon via 112 and is electrically connected to the through silicon via 112. Forming the adhesion layer 130 (see Figure 8 ), the adhesive layer 130 covers the surface of the bottom pad 190 and the bottom surface of the protection layer 120. The bottom pad 190 can be formed by photolithography and electroplating.

[0071] When the bridge chip component 100 is uprightly arranged on the top surface of the carrier 400, after the step of removing the adhesion layer 130 of the carrier 400 and the bridge chip component 100, and removing part of the first plastic sealing layer 150, so that the surface of the first plastic sealing layer 150 away from the chip packaging component 170 is flush with the surface of the bridge chip component 100 away from the chip packaging component 170, the bottom pad 190 is exposed, and the surface of the first plastic sealing layer 150 away from the chip packaging component 170 is flush with the bottom surface of the bottom pad 190; after the step of forming a bottom interconnection structure 180 between the surface of the first plastic sealing layer 150 away from the chip packaging component 170 and the surface of the bridge chip component 100 away from the chip packaging component 170, the bottom interconnection structure 180 is connected to the bottom pad 190, that is, the through silicon via 112 is electrically connected to the bottom interconnection structure 180 through the bottom pad 190.

[0072] When the bridge chip component 100 is flipped and arranged on the top surface of the carrier 400, after the step of removing the exposed adhesive layer 130 or the thin film layer 140, the bottom pad 190 is exposed; after the step of removing part of the first plastic sealing layer 150 so that the surface of the first plastic sealing layer 150 facing away from the carrier 400 is flush with the surface of the bridge chip component 100 facing away from the carrier 400, the surface of the first plastic sealing layer 150 facing away from the carrier 400 is flush with the bottom surface of the bottom pad 190; after the step of forming a chip packaging component 170 between the surface of the first plastic sealing layer 150 facing away from the carrier 400 and the surface of the bridge chip component 100 facing away from the carrier 400, the chip packaging component 170 is electrically connected to the bottom surface of the bottom pad 190.

[0073] The method for forming the packaging structure provided by the embodiment of the present invention reduces the coating thickness when the bridge chip 110 is plastic-sealed, and reduces the thickness of the wiring insertion layer composed of the first plastic sealing layer 150 and the bridge chip assembly 100, thereby reducing the warping problem and quality risk of each process in the overall process. In addition, by first depositing the protective layer 120 and then thinning the silicon through-via 112 to expose the silicon through-via 112 of the bridge chip 110, the metal ions (such as copper ions) generated by the thinning of the silicon through-via 112 can be prevented from migrating and diffusing into the substrate 111, thereby avoiding the reliability failure problem of the packaging structure caused by the migration and diffusion of metal ions. At the same time, in the formation method, the film-assisted molding (FAM) process is used to directly form the first plastic layer 150, which avoids the warping caused by the excessive thickness of the pre-coated plastic layer in the process, thereby avoiding the warping from affecting the process operation; and directly forming the first plastic layer 150 is conducive to reducing the height of other components (such as the height of the metal column 160), which can shorten their spacing and key dimensions, thereby forming a higher connection density, which is conducive to the miniaturization of the product. The bridge chip 110 is directly connected to the chip packaging component 170 or the bottom interconnection structure 180 through the internal redistribution layer 114 fan-out, which better meets the product application requirements of high-frequency and high-speed signals. The upper and lower surfaces of the bridge chip component 100 are at the same height as the first plastic layer 150, which can further improve the interconnection density between the bridge chip 110 and the top chip packaging component 170 and the bottom interconnection structure 180.

[0074] Based on the same inventive concept, an embodiment of the present invention also provides a packaging structure formed by the above-mentioned forming method. Figure 2 to Figure 17The packaging structure includes: a bridge chip component 100, the bridge chip component 100 includes a bridge chip 110 and a protective layer 120; the bridge chip 110 includes a substrate 111, a silicon-through hole 112 penetrating the substrate 111, and an internal redistribution layer 114 covering the top surface of the substrate 111, the protective layer 120 is arranged on the bottom surface of the substrate 111, and exposes the bottom surface of the silicon-through hole 112, and the bottom surface of the silicon-through hole 112 is flush with the bottom surface of the protective layer 120; a first plastic sealing layer 150, the first plastic sealing layer 150 covers the side of the bridge chip component 100, and the bottom surface of the first plastic sealing layer 150 is flush with the bottom surface of the protective layer The bottom surface of the first plastic encapsulation layer 120 is flush with the top surface of the internal redistribution layer 114; the chip packaging component 170 is arranged on one surface of the first plastic encapsulation layer 150 and the bridge chip component 100, and the bridge chip component 100 is electrically connected to the chip packaging component 170; the bottom interconnection structure 180 is arranged on the other surface of the first plastic encapsulation layer 150 and the bridge chip component 100, and the bridge chip component 100 is electrically connected to the bottom interconnection structure 180; wherein the internal redistribution layer 114 is directly electrically connected to the chip packaging component 170 or the bottom interconnection structure 180.

[0075] In the packaging structure provided in the embodiment of the present invention, no conductive column is set on the top of the internal redistribution layer 114 of the bridge chip 110, thereby reducing the overall thickness of the bridge chip 110, thereby reducing the defects caused by the bridge chip 110 being too thick in the process technology, for example, reducing the coating thickness when the bridge chip 110 is plastic-sealed, and reducing the thickness of the wiring insertion layer formed by the first plastic sealing layer 150 and the bridge chip assembly 100, thereby reducing the warping problem and quality risk of each process in the overall process.

[0076] In the packaging structure provided in the embodiment of the present invention, the bottom surface of the silicon through via 112 is flush with the bottom surface of the protective layer 120. When manufacturing the bridge chip component 100, the protective layer 120 is first formed, and then the bottom surface of the silicon through via 112 is ground. During the grinding process, the protective layer 120 can protect the substrate 111, and can prevent the metal ions (such as copper ions) generated by grinding the silicon through via 112 from migrating and diffusing into the substrate 111, thereby avoiding the reliability failure problem of the packaging structure caused by the migration and diffusion of metal ions.

[0077] The first plastic encapsulation layer 150 is directly formed by a film assistant molding (FAM) process, without first forming a thick pre-encapsulation plastic encapsulation layer and then thinning it to form the first plastic encapsulation layer 150, thereby avoiding warping caused by an overly thick pre-encapsulation plastic encapsulation layer in the process technology, thereby avoiding the warping from affecting the process operation; and directly forming the first plastic encapsulation layer 150 is beneficial to reducing the height of other components (such as the height of the metal column 160), and can shorten their spacing and critical dimensions, thereby forming a higher connection density, which is beneficial to the miniaturization of the product.

[0078] The bridge chip 110 is directly connected to the chip package component 170 or the bottom interconnection structure 180 by fanning out through the internal redistribution layer 114, without fanning out through the internal redistribution layer 114, and then connected to the chip package component 170 or the bottom interconnection structure 180 through the conductive column, which better meets the product application requirements of high-frequency and high-speed signals. The top surface of the first plastic encapsulation layer 150 is flush with the top surface of the internal redistribution layer 114, and the bottom surface of the first plastic encapsulation layer 150 is flush with the bottom surface of the bridge chip component 100, that is, the upper and lower surfaces of the bridge chip component 100 are at the same height as the first plastic encapsulation layer 150, which can further improve the interconnection density between the bridge chip 110 and the top chip package component 170 (for example, the top redistribution layer 171 in the chip package component 170) and the bottom interconnection structure 180 (for example, the bottom redistribution layer 181 in the bottom interconnection structure 180).

[0079] In one embodiment, the internal redistribution layer 114 includes a dielectric layer and a conductive circuit in the dielectric layer, one side of the conductive circuit is electrically connected to the top surface of the through silicon via 112 , and the other side is electrically connected to the chip package assembly 170 or the bottom interconnect structure 180 .

[0080] In one embodiment, the bridge chip 110 further includes a deep trench capacitor 180 (DTC), which is disposed in the substrate 111. In some embodiments, the deep trench capacitor 180 extends from the top surface of the substrate 111 to the inside of the substrate 111, and the deep trench capacitor 180 is electrically connected to the internal redistribution layer 114.

[0081] In one embodiment, a passivation layer 113 is further disposed on the side of the TSV 112 . The passivation layer 113 is used to isolate the TSV 112 from the substrate 111 to prevent metal ions in the TSV 112 from diffusing into the substrate 111 .

[0082] In one embodiment, the packaging structure further includes a metal column 160, the metal column 160 penetrates the first plastic packaging layer 150, and the bottom surface of the metal column 160 is flush with the bottom surface of the first plastic packaging layer 150, and the top surface of the metal column 160 is flush with the top surface of the first plastic packaging layer 150. The packaging structure may include a plurality of the bridge chip components 100 and a plurality of the metal columns 160, and the metal columns 160 are distributed around the bridge chip components 100 and between two adjacent bridge chip components 100.

[0083] In one embodiment, the chip package component 170 includes: a top redistribution layer 171, which is disposed on a surface of the first plastic packaging layer 150 and the bridge chip component 100, the top redistribution layer 171 includes a dielectric layer and a conductive circuit located in the dielectric layer, and the conductive circuit is electrically connected to the bridge chip component 100; a top solder pad 172, which is disposed on the top redistribution layer 171 and is electrically connected to the top redistribution layer 171; a top device 173, which is disposed on the top redistribution layer 171, and the top device 173 is soldered to the top solder pad 172; and a second plastic packaging layer 174, which covers the top device 173. In one embodiment, the top redistribution layer 171 includes a dielectric layer and a conductive circuit located in the dielectric layer, and the conductive circuit is in contact with and connected to the bridge chip component 100. The material of the dielectric layer can be a polymer material such as polybutylene styrene (PBO) and polyimide (PI). The conductive circuit is formed by an electroplating process, and there is no need to use tin (Sn) welding, which eliminates the aging problem of tin welding during the process, and there is no problem of voids (Void) and cracks (Crack) at the welding points, which improves the reliability of the packaging structure. The top device 173 can be flipped on the top redistribution layer 171 and welded to the top pad 172. The top device 173 can be a SOC device, etc. In some embodiments, the packaging structure also includes a filling layer 175 filled between the bottom of the top device 173 and the top redistribution layer 171, and the filling layer 175 is used to protect the conductive structure of the top device 173 and the top pad 172. The second plastic encapsulation layer 174 covers the top device 173, the surface of the top redistribution layer 171, and the surface of the filling layer 175.

[0084] In one embodiment, the bottom interconnect structure 180 also includes: a bottom redistribution layer 181, the bottom redistribution layer 181 includes a dielectric layer and an electroplating circuit located in the dielectric layer, the electroplating circuit is in contact and connected with the through silicon via 112, or the bottom pad 190 arranged on the bottom surface of the through silicon via 112, or the pad of the internal redistribution layer 114; a conductive connection structure 182, which is arranged on the bottom surface of the bottom redistribution layer 181 and is electrically connected to the bottom redistribution layer 181.

[0085] In some embodiments, the bottom rewiring layer 181 includes a dielectric layer and an electroplating circuit located in the dielectric layer, and the electroplating circuit is in contact with the through silicon via 112 of the bridge chip 110 and the metal column 160. The material of the dielectric layer can be a polymer material such as polystyrene butyrate (PBO) and polyimide (PI) to further relieve stress. In one embodiment, the electroplating circuit is formed on the bottom surface of the through silicon via 112 and the bottom surface of the metal column 160 by an electroplating process, without the need for tin (Sn) welding, eliminating the aging problem of tin welding during process processing, and there is no problem of voids (Void) and cracks (Crack) at the welding point, thereby improving the reliability of the packaging structure. The conductive connection structure 182 is arranged on the bottom surface of the bottom rewiring layer 181. In some embodiments, the conductive connection structure 182 includes but is not limited to a controllable collapse chip connection bump (C4).

[0086] In one embodiment, see Fig.18 , the bridge chip assembly 100 further includes a bottom pad 190, the bottom pad 190 is disposed on the bottom surface of the through silicon via 112 and is electrically connected to the through silicon via 112, the bottom surface of the first plastic encapsulation layer 150 is flush with the bottom surface of the bottom pad 190, and the chip packaging assembly 170 or the bottom interconnect structure 180 is electrically connected to the bottom pad 190. In one embodiment, the bottom pad 190 is a micro pad (μPad). The bottom pad 190 is disposed on the bottom surface of the through silicon via 112, so that in the packaging structure using the bridge chip assembly 100, the thickness of the first plastic encapsulation layer 150 covering the bridge chip assembly 100 can be reduced, thereby reducing the warping of this part of the structure, which is more conducive to production and yield. In this embodiment, the cross-sectional area of ​​the bottom pad 190 is larger than the cross-sectional area of ​​the TSV 112 to ensure that the TSV 112 can all contact the bottom pad 190, thereby reducing contact resistance and further reducing the delay of the electrical signal.

[0087] In the packaging structure provided by the embodiment of the present invention, the overall thickness of the bridge chip 110 is reduced, thereby reducing the defects caused by the bridge chip 110 being too thick in the process. The bottom surface of the silicon through hole 112 is flush with the bottom surface of the protective layer 120. When manufacturing the bridge chip assembly 100, the protective layer 120 is formed first, and then the bottom surface of the silicon through hole 112 is ground, which can avoid the migration and diffusion of metal ions (such as copper ions) generated by grinding the silicon through hole 112 into the substrate 111, thereby avoiding the reliability failure problem of the packaging structure caused by the migration and diffusion of metal ions. The first plastic encapsulation layer 150 is directly formed by a film assistant molding (FAM) process, thereby avoiding the warping caused by the pre-coating plastic encapsulation layer being too thick in the process, thereby avoiding the warping affecting the process operation; and the direct formation of the first plastic encapsulation layer 150 is conducive to reducing the height of other components (such as the height of the metal column 160), which can shorten their spacing and critical dimensions, thereby forming a higher connection density, which is conducive to the miniaturization of the product. The bridge chip 110 is directly connected to the chip package component 170 or the bottom interconnect structure 180 through the fan-out of the internal redistribution layer 114, which better meets the product application requirements of high-frequency and high-speed signals. The upper and lower surfaces of the bridge chip component 100 are at the same height as the first plastic packaging layer 150, which can further improve the interconnection density between the bridge chip 110 and the top chip package component 170 (for example, the top redistribution layer 171 in the chip package component 170) and the bottom interconnect structure 180 (for example, the bottom redistribution layer 181 in the bottom interconnect structure 180).

[0088] It should be noted that the terms "including" and "having" and their variations involved in the document of the present invention are intended to cover non-exclusive inclusions. The terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence, unless the context clearly indicates, and it should be understood that the data used in this way can be interchanged under appropriate circumstances. The term "one or more" depends at least in part on the context, and can be used to describe features, structures or characteristics in a singular sense, or can be used to describe features, structures or combinations of features in a plural sense. The term "based on" can be understood as not necessarily intended to express a set of exclusive factors, but can alternatively, also at least in part depending on the context, allow the presence of other factors that are not necessarily explicitly described. In addition, the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict. In addition, in the above description, the description of well-known components and technologies is omitted to avoid unnecessary confusion of the concept of the present invention. In the above embodiments, each embodiment focuses on the differences from other embodiments, and the same / similar parts between the embodiments can be referred to each other.

[0089] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for forming a packaging structure, characterized in that: include: A bridge chip assembly is formed, the bridge chip assembly comprising: a bridge chip, a protective layer, an adhesive layer and a thin film layer; the bridge chip comprises a substrate, a silicon through hole penetrating the substrate and an internal redistribution layer covering the top surface of the substrate, the internal redistribution layer being electrically connected to the silicon through hole; the protective layer is arranged on the bottom surface of the substrate and exposes the bottom surface of the silicon through hole, wherein the bottom surface of the silicon through hole is flush with the bottom surface of the protective layer by first depositing the protective layer and then thinning the silicon through hole; the adhesive layer covers the bottom surface of the protective layer and the bottom surface of the silicon through hole; The thin film layer covers the top surface of the internal redistribution layer; The bridge chip assembly is placed on the top surface of a carrier board by flipping or mounting it face-up; Performing plastic sealing by using a film-assisted plastic sealing process to form a first plastic sealing layer, wherein the first plastic sealing layer covers the side surface of the bridge chip component and the top surface of the carrier, and the adhesive layer or the film layer is exposed to the first plastic sealing layer; removing the exposed adhesive layer or the film layer; removing a portion of the first plastic sealing layer so that a surface of the first plastic sealing layer facing away from the carrier is flush with a surface of the bridge chip assembly facing away from the carrier; A chip packaging assembly is formed on a surface of the first plastic packaging layer facing away from the carrier board and a surface of the bridge chip assembly facing away from the carrier board, wherein the bridge chip assembly is electrically connected to the chip packaging assembly; Removing the adhesive layer or the film layer of the carrier and the bridge chip assembly, and removing part of the first plastic sealing layer, so that the surface of the first plastic sealing layer facing away from the chip packaging assembly is flush with the surface of the bridge chip assembly facing away from the chip packaging assembly; A bottom interconnection structure is formed between a surface of the first plastic packaging layer facing away from the chip packaging component and a surface of the bridge chip component facing away from the chip packaging component.

2. The method for forming a packaging structure according to claim 1, characterized in that: The steps of forming the bridge chip assembly include: Providing a device wafer, the device wafer comprising a bridge chip, the bridge chip comprising an initial substrate, an initial silicon through-hole extending from the top surface of the initial substrate to the inside of the initial substrate, and the internal redistribution layer arranged on the top surface of the initial substrate, the side surface and the bottom surface of the initial silicon through-hole covered with a passivation layer, and the top surface of the initial silicon through-hole in contact with the bottom surface of the internal redistribution layer; Removing a portion of the initial substrate from the bottom surface of the initial substrate to form the substrate, wherein the initial through silicon vias protrude from the bottom surface of the substrate; forming a protective layer on the bottom surface of the substrate; Thinning the passivation layer and the initial through silicon via from the bottom surface of the initial through silicon via to form the through silicon via, so that the bottom surface of the through silicon via is flush with the bottom surface of the protection layer, and the side surface of the through silicon via is covered with the passivation layer; forming the adhesion layer; The thin film layer is formed.

3. The method for forming a packaging structure according to claim 2, wherein: The step of removing a portion of the initial substrate from the bottom surface of the initial substrate to form the substrate further comprises: Using a thinning and flattening process to remove a portion of the initial substrate from the bottom surface of the initial substrate to a set distance from the passivation layer of the bottom surface of the initial through silicon via; A dry etching process is adopted to remove a portion of the initial substrate from the bottom surface of the initial substrate to form the substrate.

4. The method for forming a packaging structure according to claim 2, wherein: In the step of forming a protective layer on the bottom surface of the substrate, the protective layer also covers the surface of the passivation layer; in the step of thinning the passivation layer and the initial silicon via from the bottom surface of the initial silicon via to form the silicon via, the protective layer is also thinned.

5. The method for forming a packaging structure according to claim 2, wherein: After the step of providing the device wafer, the method further includes: bonding a support substrate to a side of the device wafer having the internal redistribution layer; after the step of forming the adhesion layer, the method further includes: debonding the support substrate; after the step of forming the thin film layer, the method further includes: singulating the device wafer to form the bridge chip assembly.

6. The method for forming a packaging structure according to claim 2, wherein: After the step of thinning the passivation layer and the initial through silicon via from the bottom surface of the initial through silicon via to form the through silicon via, the method further comprises: forming a bottom pad, wherein the bottom pad is disposed on the bottom surface of the through silicon via and is electrically connected to the through silicon via; In the step of forming the adhesion layer, the adhesion layer covers the surface of the bottom pad and the bottom surface of the protection layer.

7. The method for forming a packaging structure according to claim 1, characterized in that: The step of placing the bridge chip component in an inverted or upright manner on the top surface of a carrier also includes: placing a metal column on the top surface of the carrier; in the step of performing plastic sealing using a film-assisted plastic sealing process, the first plastic sealing layer also covers the side surface of the metal column; in the step of removing part of the first plastic sealing layer so that the surface of the first plastic sealing layer facing away from the carrier is flush with the surface of the bridge chip component facing away from the carrier, the metal column is etched so that the surface of the metal column facing away from the carrier is flush with the surface of the first plastic sealing layer facing away from the carrier; in the step of removing part of the first plastic sealing layer so that the surface of the first plastic sealing layer facing away from the chip packaging component is flush with the surface of the bridge chip component facing away from the chip packaging component, the metal column is etched so that the surface of the metal column facing away from the chip packaging component is flush with the surface of the first plastic sealing layer facing away from the chip packaging component.

8. The method for forming a packaging structure according to claim 1, wherein: The film-assisted molding process is used for molding, and in the step of forming a first molding layer, the surface of the first molding layer facing away from the carrier is flush with the surface of the bridge chip component facing away from the carrier, or the surface of the first molding layer facing away from the carrier is lower than the surface of the bridge chip component facing away from the carrier.

9. The method for forming a packaging structure according to claim 1, wherein: A grinding and planarization process is used to remove a portion of the first plastic packaging layer.

10. The method for forming a packaging structure according to claim 1, wherein: The step of forming a chip packaging assembly on the surface of the first plastic packaging layer away from the carrier board and the surface of the bridge chip assembly away from the carrier board comprises: forming a top redistribution layer on the surface of the first plastic packaging layer away from the carrier board and the surface of the bridge chip assembly away from the carrier board, the top redistribution layer comprising a dielectric layer and a conductive circuit located in the dielectric layer, the conductive circuit being electrically connected to the bridge chip assembly, wherein the conductive circuit is formed by an electroplating process; forming a top pad on a top surface of the top redistribution layer, wherein the top pad is electrically connected to the top redistribution layer; Disposing a top device on the top redistribution layer, wherein the top device is welded to the top pad; Plastic encapsulation is performed to form a second plastic encapsulation layer, wherein the second plastic encapsulation layer covers the top device.

11. The method for forming a packaging structure according to claim 1, wherein: The step of forming a bottom interconnection structure on a surface of the first plastic packaging layer facing away from the chip package component and a surface of the bridge chip component facing away from the chip package component further comprises: forming a dielectric layer on a surface of the first plastic packaging layer facing away from the chip packaging component and a surface of the bridge chip component facing away from the chip packaging component; Forming a through hole on the dielectric layer to expose the bottom surface of the through silicon via, or a bottom pad of the bottom surface of the through silicon via, or a pad of the internal redistribution layer; Sputtering and / or electroplating in the through hole to form a plating circuit, the plating circuit is in contact with and connected to the through silicon via, or the bottom pad, or the pad of the internal redistribution layer, and the dielectric layer and the plating circuit together serve as a bottom redistribution layer; A conductive connection structure is formed on the bottom surface of the bottom redistribution layer, and the conductive connection structure and the bottom redistribution layer together serve as the bottom interconnection structure.

12. A packaging structure, characterized in that: include: A bridge chip assembly, the bridge chip assembly comprising a bridge chip and a protective layer; the bridge chip comprises a substrate, a silicon through hole penetrating the substrate, and an internal redistribution layer covering the top surface of the substrate, the protective layer is arranged on the bottom surface of the substrate and exposes the bottom surface of the silicon through hole, and the bottom surface of the silicon through hole is flush with the bottom surface of the protective layer; A first plastic encapsulation layer, wherein the first plastic encapsulation layer covers the side surface of the bridge chip assembly, and the bottom surface of the first plastic encapsulation layer is flush with the bottom surface of the protective layer, and the top surface of the first plastic encapsulation layer is flush with the top surface of the internal redistribution layer; A chip packaging component, disposed on the first plastic packaging layer and a surface of the bridge chip component, the bridge chip component being electrically connected to the chip packaging component; A bottom interconnection structure is provided on the first plastic packaging layer and the other surface of the bridge chip assembly, and the bridge chip assembly is electrically connected to the bottom interconnection structure; Wherein, the internal redistribution layer is directly electrically connected to the chip packaging component or the bottom interconnection structure.

13. The packaging structure according to claim 12, characterized in that: The bridge chip further includes a deep trench capacitor, which is disposed in the substrate.

14. The packaging structure according to claim 12, characterized in that: A passivation layer is also provided on the side of the through silicon via.

15. The packaging structure according to claim 12, characterized in that: The packaging structure further includes a metal column, which penetrates the first plastic packaging layer, and the bottom surface of the metal column is flush with the bottom surface of the first plastic packaging layer, and the top surface of the metal column is flush with the top surface of the first plastic packaging layer.

16. The packaging structure according to claim 12, characterized in that: The bridge chip assembly also includes a bottom pad, which is arranged on the bottom surface of the through silicon via and electrically connected to the through silicon via. The bottom surface of the first plastic packaging layer is flush with the bottom surface of the bottom pad, and the chip packaging assembly or the bottom interconnection structure is electrically connected to the bottom pad.

17. The packaging structure according to claim 12, characterized in that: The chip packaging assembly comprises: A top redistribution layer is disposed on a surface of the first plastic packaging layer and the bridge chip assembly, the top redistribution layer includes a dielectric layer and a conductive circuit located in the dielectric layer, and the conductive circuit is electrically connected to the bridge chip assembly; A top pad, disposed on the top redistribution layer and electrically connected to the top redistribution layer; A top device is disposed on the top redistribution layer, and the top device is welded to the top pad; The second plastic packaging layer covers the top device.

18. The packaging structure according to claim 12, characterized in that: The bottom interconnect structure further comprises: A bottom redistribution layer, the bottom redistribution layer comprising a dielectric layer and an electroplating circuit located in the dielectric layer, the electroplating circuit being in contact and connected with the through silicon via, or a bottom pad disposed on the bottom surface of the through silicon via, or a pad of the internal redistribution layer; The conductive connection structure is arranged on the bottom surface of the bottom redistribution layer and is electrically connected to the bottom redistribution layer.

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