Preparation method of semiconductor element comprising contact structure

Abstract

The invention provides a preparation method of a semiconductor element. The preparation method comprises the following steps: providing a substrate; forming a dielectric layer on the substrate; forming a cell contact opening along the dielectric layer to expose the substrate; conformally forming a sacrificial layer partially filling the cell contact opening to form an intermediate opening exposing the substrate; forming a barrier layer completely filling the middle opening; removing the sacrificial layer; performing an etching process using the barrier layer as a mask to deepen the cell contact opening into the substrate and convert the cell contact opening into an extended cell contact opening surrounding a protrusion of the substrate; removing the barrier layer; and forming a contact structure in the extension unit contact point opening.

Description

[0001] This application is a divisional of Chinese invention patent application No. 202410050224.7, entitled “Contact structure, semiconductor element comprising contact structure and preparation method thereof”, filed on January 12, 2024. Application No. 202410050224.7 claims priority and benefits of U.S. formal application No. 18 / 376,059 filed on October 3, 2023. The contents of the U.S. formal application are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a contact structure, a semiconductor element including the contact structure and a method for preparing the semiconductor element, and more particularly to a contact structure having an extension portion. Background Art

[0003] Semiconductor components are used in various electronic applications, such as personal computers, mobile phones, digital cameras, or other electronic devices. The size of semiconductor components is gradually getting smaller to meet the increasing demand for computing power. However, during the process of size reduction, different problems increase. Therefore, there are still challenges in achieving improved quality, yield, performance and reliability, as well as reducing complexity.

[0004] The above description of “prior art” only provides background technology, does not admit that the above description of “prior art” discloses the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of the present disclosure. Summary of the invention

[0005] One embodiment of the present disclosure provides a method for preparing a semiconductor element, including providing a substrate; forming a dielectric layer on the substrate; forming a unit contact opening along the dielectric layer to expose the substrate; conformally forming a sacrificial layer that partially fills the unit contact opening to form an intermediate opening that exposes the substrate; forming a barrier layer that completely fills the intermediate opening; removing the sacrificial layer; performing an etching process using the barrier layer as a mask to deepen the unit contact opening into the substrate and transform the unit contact opening into an extended unit contact opening that surrounds a protrusion of the substrate; removing the barrier layer; and forming a contact structure in the extended unit contact opening.

[0006] Due to the design of the semiconductor device disclosed herein, the extension portion can increase the contact area of ​​the contact structure, thereby improving the performance of the semiconductor device.

[0007] The above has been a fairly broad overview of the technical features and advantages of the present disclosure, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those skilled in the art to which the present disclosure belongs that the concepts and specific embodiments disclosed below can be used to modify or design other structures or processes to achieve the same purpose as the present disclosure. It should also be understood by those skilled in the art to which the present disclosure belongs that such equivalent constructions cannot depart from the concept and scope of the present disclosure as defined by the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] When with Figure 1 When read together, various aspects of the present disclosure can be best understood from the following detailed description. It should be understood that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the size of various features can be arbitrarily increased or reduced for clarity of discussion.

[0009] Figure 1 1 is a flow chart illustrating a method for preparing a semiconductor device according to an embodiment of the present disclosure.

[0010] Figures 2 to 10 It is a cross-sectional schematic diagram illustrating a process of preparing a semiconductor element according to an embodiment of the present disclosure.

[0011] Fig.11 FIG. 4 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure.

[0012] Fig.12 is along Fig.11 A schematic cross-sectional view of the section line A-A'.

[0013] Fig.13 FIG. 4 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure.

[0014] Fig.14 is along Fig.13 A schematic cross-sectional view of the section line A-A'.

[0015] Fig.15 FIG. 4 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure.

[0016] Fig.16 and Fig.17 is along Fig.15 The cross-sectional schematic diagram along the section line AA' of FIG. 1 illustrates a partial manufacturing process of a semiconductor device according to an embodiment of the present disclosure.

[0017] Fig.18 FIG. 4 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure.

[0018] Fig.19 is along Fig.18 A schematic cross-sectional view of the section line A-A'.

[0019] Fig. 20 FIG. 4 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure.

[0020] Fig.21 is along Fig. 20 A schematic cross-sectional view of the section line A-A'.

[0021] Fig. 22 FIG. 4 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure.

[0022] Figure 23 to Figure 26 is along Fig. 22 The cross-sectional schematic diagram along the section line AA' of FIG. 1 illustrates a partial manufacturing process of a semiconductor device according to an embodiment of the present disclosure.

[0023] Fig. 27 FIG. 4 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure.

[0024] Fig.28 and Fig.29 is a cross-sectional schematic diagram illustrating a main body portion and an extension portion of a semiconductor element according to some embodiments of the present disclosure.

[0025] Fig.30 FIG. 4 is a schematic cross-sectional view illustrating a semiconductor device according to another embodiment of the present disclosure.

[0026] Description of reference numerals:

[0027] 10: Preparation method

[0028] 1A: Semiconductor components

[0029] 1B: Semiconductor components

[0030] 1C: Semiconductor components

[0031] 1D: Semiconductor components

[0032] 101: Base

[0033] 101P: Protrusion

[0034] 101PT: Upper surface

[0035] 101TS: Top surface

[0036] 103: Isolation layer

[0037] 105: Impurity region

[0038] 111: Lower dielectric layer

[0039] 113: Intermediate dielectric layer

[0040] 115: Upper dielectric layer

[0041] 200: Character line structure

[0042] 201: word line dielectric layer

[0043] 203: Character line conductive layer

[0044] 205: Conductive layer on the character line

[0045] 207: Character line cover layer

[0046] 301: Bit line contact

[0047] 301O: Bit line contact opening

[0048] 303: Bit line

[0049] 400: Contact structure

[0050] 401: Ontology Department

[0051] 401O: Unit contact opening

[0052] 403: Extension

[0053] 403BS: Lower surface

[0054] 403E: Extended cell contact opening

[0055] 403R: Grooved

[0056] 403TS: Top surface

[0057] 611: First insulating material layer

[0058] 711: First sacrificial layer

[0059] 711O: First middle opening

[0060] 713: Second Sacrificial Layer

[0061] 713O: Second middle opening

[0062] 811: First mask layer

[0063] 813: Second mask layer

[0064] 815: The third mask layer

[0065] 817: Barrier layer

[0066] AA: Active Area

[0067] CP1: Center Point

[0068] CP2: Center Point

[0069] D1: diameter

[0070] D2: diameter

[0071] H1: Height

[0072] H2: Height

[0073] S11: Steps

[0074] S13: Steps

[0075] S15: Steps

[0076] TR1: Groove

[0077] TR2: Grooves

[0078] Z: Direction DETAILED DESCRIPTION

[0079] Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these embodiments are for illustration only and are not intended to limit the scope of the present disclosure. For example, in the description, the first component is formed on the second component, which may include an embodiment in which the first and second components are in direct contact, and may also include an embodiment in which additional components are formed between the first and second components so that the first and second components are not in direct contact. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in many examples. The purpose of these repetitions is to simplify and clarify, and unless otherwise specified in the text, they do not themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0080] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature shown in the figures to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0081] It should be understood that when forming a component on, connected to, and / or coupled to another component, it may include embodiments in which these components are in direct contact, and may also include embodiments in which additional components are formed between these components so that these components are not in direct contact.

[0082] It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Instead, these terms are only used to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the progressive conception of the present invention, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0083] Unless the context indicates otherwise, as used herein, terms such as "same," "equal," "planar," or "coplanar" when referring to orientation, layout, location, shapes, sizes, amounts, or other measures do not necessarily mean an exactly identical orientation, layout, location, shape, size, amount, or other measure, but rather mean nearly identical orientation, layout, location, shape, size, amount, or other measure within acceptable variances that may occur, for example, due to manufacturing processes. The term "substantially" may be used herein to convey this meaning. For example, substantially the same, substantially equal, or substantially planar, is exactly the same, equal, or planar, or it may be the same, equal, or planar within an acceptable variance, and for example, the acceptable variance may occur due to the manufacturing process.

[0084] In the present disclosure, a semiconductor device generally refers to a device that can operate by utilizing semiconductor characteristics, and an electro-optic device, a light-emitting display device, a semiconductor circuit, and an electronic device are all included in the scope of semiconductor devices.

[0085] It should be understood that in the description of the present disclosure, above (or up) corresponds to the direction of the Z-direction arrow, and below (or down) corresponds to the relative direction of the Z-direction arrow.

[0086] Figure 1 1 is a flow chart illustrating a method 10 for manufacturing a semiconductor device 1A according to an embodiment of the present disclosure. Figures 2 to 10 1 is a cross-sectional schematic diagram illustrating a process of manufacturing a semiconductor device 1A according to an embodiment of the present disclosure. Fig.11 FIG. 4 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure. Fig.12 is along Fig.11 A schematic cross-sectional view of the section line A-A'.

[0087] Please refer to Figures 1 to 10 In step S11, a substrate 101 may be provided, a plurality of word line structures 200 may be formed in the substrate 101, a lower dielectric layer 111 may be formed on the substrate 101, a bit line contact 301 may be formed on the substrate 101, an intermediate dielectric layer 113 and an upper dielectric layer 115 may be sequentially formed on the lower dielectric layer 111, a bit line 303 may be formed on the bit line contact 301, and a plurality of cell contact openings 401O may be formed along the upper dielectric layer 115, the intermediate dielectric layer 113 and the lower dielectric layer 111 to expose the substrate 101.

[0088] Please refer to Figure 2 The substrate 101 may include a bulk semiconductor substrate. For example, the bulk semiconductor substrate may include an elemental semiconductor, such as silicon or germanium; a compound semiconductor, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other III-V compound semiconductors or II-VI compound semiconductors; or a combination thereof.

[0089] Please refer to Figure 2, an isolation layer 103 may be formed in the substrate 101. A series of deposition processes may be performed to deposit a pad oxide layer (not shown) and a pad nitride layer (not shown) on the substrate 101. A photolithography process and a subsequent etching process, such as an anisotropic dry etching process, may be performed to form a plurality of trenches penetrating the pad oxide layer, the pad nitride layer and extending to the substrate 101. An insulating material may be deposited into the trenches, and a planarization process, such as chemical mechanical polishing, may be subsequently performed until the upper surface 101TS of the substrate 101 is exposed to remove excess filling material, provide a substantially flat surface for subsequent processing steps, and form the isolation layer 103 at the same time. For example, the insulating material may be silicon oxide or other applicable insulating materials. In some embodiments, the isolation layer 103 may define an active area AA in the substrate 101.

[0090] Please refer to Figure 2 An impurity region 105 may be formed in the active region AA. In some embodiments, the impurity region 105 may be formed by an implantation process using a p-type dopant or an n-type dopant. The impurity region 105 may be used as a source and a drain of the semiconductor device 1A.

[0091] The term "p-type dopant" refers to an impurity that produces a plurality of valence electron defects when added to an intrinsic semiconductor material. In a silicon-containing semiconductor material, examples of p-type dopants include, but are not limited to, boron, aluminum, gallium, or indium. The term "n-type dopant" refers to an impurity that contributes a plurality of free electrons to an intrinsic semiconductor material when added to the intrinsic semiconductor material. In a silicon-containing material, examples of n-type dopants include, but are not limited to, antimony, arsenic, or phosphorus.

[0092] Please refer to Figure 2 A first mask layer 811 may be formed on the substrate 101 . In some embodiments, the first mask layer 811 may be a photoresist layer and may include patterns of a plurality of word line structures 200 .

[0093] Please refer to Figure 3 , a trench etching process can be performed using the first mask layer 811 as a mask to remove a portion of the isolation layer 103 and a portion of the substrate 101, and simultaneously form a plurality of trenches TR1, TR2. In some embodiments, the plurality of trenches TR1 formed in the substrate 101 can be shallower than the plurality of trenches TR2 formed in the isolation layer 103. After the plurality of trenches TR1, TR2 are formed, the first mask layer 811 can be removed.

[0094] Please refer to Figure 4, a first insulating material layer 611 may be conformally formed on the substrate 101, on the isolation layer 103, and in the plurality of trenches TR1, TR2. The first insulating material layer 611 may have a U-shaped cross-sectional profile in the plurality of trenches TR1, TR2. In some embodiments, the first insulating material layer 611 may have a thickness in a range of about 1 nm to about 7 nm, including about 1 nm, about 2 nm, about 3 nm, about 4 nm, about 5 nm, about 6 nm, or about 7 nm.

[0095] In some embodiments, the manufacturing technology of the first insulating material layer 611 may include a thermal oxidation process. For example, the manufacturing technology of the first insulating material layer 611 may include oxidizing the surfaces of the plurality of trenches TR1, TR2. In some embodiments, the manufacturing technology of the first insulating material layer 611 may include a deposition process, such as chemical vapor deposition or atomic layer deposition. The first insulating material 611 may include a high-k material, an oxide, a nitride, an oxynitride, or a combination thereof. In some embodiments, after depositing a pad polysilicon layer (not shown in the figure for clarity), the manufacturing technology of the first insulating material layer 611 may include free radical oxidation of the pad polysilicon layer. In some embodiments, after forming a pad silicon nitride layer (not shown in the figure for clarity), the manufacturing technology of the first insulating material layer 611 may include free radical oxidation of the pad silicon nitride layer.

[0096] In some embodiments, the high-k dielectric material may include a hafnium-containing material. For example, the hafnium-containing material may be hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. In some embodiments, for example, the high-k dielectric material may be lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, silicon zirconium oxide, zirconium silicon oxynitride, aluminum oxide, or a combination thereof.

[0097] Please refer to Figure 4 , multiple word line under-conductive layers 203 may be formed in the multiple trenches TR1, TR2 respectively. For example, a conductive material (not shown) may be formed to fill the multiple trenches TR1, TR2. Subsequently, an etch-back process may be performed to partially remove the conductive material formed in the multiple trenches TR1, TR2, and simultaneously form multiple word line under-conductive layers 203. In some embodiments, the conductive material may be a work function material, such as titanium, titanium nitride, silicon, silicon germanium, or a combination thereof. It should be noted that the term "work function" refers to the overall chemical potential of a material (such as a metal) relative to a vacuum level. For example, in the present embodiment, the conductive material is titanium nitride, and its manufacturing technology may include chemical vapor deposition.

[0098] Please refer to Figure 4, a plurality of conductive layers 205 on word lines may be formed in a plurality of trenches TR1, TR2. In some embodiments, for example, the conductive layers 205 on the word lines may include polysilicon, polycrystalline germanium, polycrystalline silicon germanium, doped polysilicon, doped polycrystalline germanium, doped polycrystalline silicon germanium, or a combination thereof. In some embodiments, the conductive layers 205 on the word lines may be doped with p-type dopants or n-type dopants. In some embodiments, a conductive material such as polysilicon, polycrystalline germanium, or polycrystalline silicon germanium may be deposited into the plurality of trenches TR1, TR2. Subsequently, an etch-back process may be performed to remove a portion of the conductive layer to form the conductive layers 205 on the word lines. In some embodiments, dopants may be incorporated into the deposition process of the conductive material. In some embodiments, dopants may be doped using an implantation process after the etch-back process.

[0099] Please refer to Figure 4 , a word line capping layer 207 may be formed to completely fill the plurality of trenches TR1, TR2. In some embodiments, for example, the word line capping layer 207 may include silicon nitride, silicon oxynitride, silicon oxynitride or other applicable dielectric materials. In some embodiments, for example, the word line capping layer 207 may be fabricated using chemical vapor deposition, plasma enhanced chemical vapor deposition or other applicable deposition processes.

[0100] It should be understood that the silicon oxynitride of the present disclosure refers to a substance containing silicon, nitrogen and oxygen, wherein the proportion of oxygen is greater than the proportion of nitrogen. Silicon oxynitride refers to a substance containing silicon, oxygen and nitrogen, wherein the proportion of nitrogen is greater than the proportion of oxygen.

[0101] Please refer to Figure 5 , a planarization process, such as chemical mechanical polishing, may be performed until the upper surface 101TS of the substrate 101 is exposed to remove excess material and provide a substantially flat surface for subsequent processing steps. After the planarization process, the first insulating material layer 611 may be converted into a plurality of word line dielectric layers 201 in the plurality of trenches TR1, TR2, respectively. The word line capping layer 207 may be divided into a plurality of segments and may be formed on the plurality of word line conductive layers 205, respectively. The plurality of word line dielectric layers 201, the plurality of word line lower conductive layers 203, the plurality of word line conductive layers 205, and the plurality of word line capping layers 207 are configured together into a plurality of word line structures 200. It should be understood that, although the word line structure 200 in the trench TR1 and the word line structure 200 in the trench TR2 are different in size, their layer compositions remain the same.

[0102] Please refer to Figure 6, a lower dielectric layer 111 may be formed on the substrate 101. In some embodiments, for example, the lower dielectric layer 111 may include silicon oxide, undoped silicate glass, fluorosilicate glass, borophosphosilicate glass, a spin-on low-k dielectric layer, a chemical vapor deposited low-k dielectric layer, or a combination thereof. The term "low-k" as used throughout this disclosure refers to a dielectric material having a dielectric constant less than silicon oxide. In some embodiments, the lower dielectric layer 111 may include a self-planarizing material, such as a spin-on glass or a spin-on low-k dielectric material, such as SiLK TM The use of self-planarizing dielectric materials can avoid the need to perform a subsequent planarization step. In some embodiments, for example, the fabrication technique of the lower dielectric layer 111 may include a deposition process such as chemical vapor deposition, plasma enhanced chemical vapor deposition, evaporation, or spin coating.

[0103] Please refer to Figure 6 , a second mask layer 813 may be formed on the lower dielectric layer 111. In some embodiments, the second mask layer 813 may be a photoresist layer and may include a pattern of the bit line contact 301.

[0104] Please refer to Figure 7 , a bit line contact etching process may be performed using the second mask layer 813 as a mask to remove a portion of the lower dielectric layer 111 and a portion of the impurity region 105, and simultaneously form a bit line contact opening 301O. The bit line contact opening 301O may be formed to extend to the impurity region 105, and may be located between the word line structures 200 formed in the trench TR2. After the bit line contact opening 301O is formed, the second mask layer 813 may be removed.

[0105] Please refer to Figure 8 The bit line contact 301 may be formed in the bit line contact opening 301O by depositing a conductive material and then undergoing a planarization process such as chemical mechanical polishing. In some embodiments, the conductive material may be, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (e.g., titanium nitride), transition metal aluminides, or combinations thereof. The bit line contact 301 may be electrically connected to the impurity region 105.

[0106] Please refer to Fig. 9, the middle dielectric layer 113 may be formed on the lower dielectric layer 111. In some embodiments, the middle dielectric layer 113 may include the same material as the lower dielectric layer 111, but is not limited thereto. In some embodiments, the bit line 303 may be formed in the middle dielectric layer 113 and may be formed on the bit line contact 301. The bit line 303 may be electrically coupled to the impurity region 105 via the bit line contact 301. In some embodiments, for example, the bit line 303 may include tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbide (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitride (e.g., titanium nitride), transition metal aluminide, or a combination thereof.

[0107] Please refer to Fig. 9 , an upper dielectric layer 115 may be formed on the middle dielectric layer 113. In some embodiments, the upper dielectric layer 115 may include the same material as the lower dielectric layer 111, but is not limited thereto. A third mask layer 815 may be formed on the upper dielectric layer 115. In some embodiments, the third mask layer 815 may be a photoresist layer and may include a pattern of a plurality of cell contact openings 401O.

[0108] Please refer to Fig.10 , a cell contact etching process may be performed using the third mask layer 815 as a mask to remove portions of the upper dielectric layer 115, the intermediate dielectric layer 113, and the lower dielectric layer 111. After the cell contact etching process, a plurality of cell contact openings 401O may be formed through the upper dielectric layer 115, the intermediate dielectric layer 113, and the lower dielectric layer 111.

[0109] For the sake of brevity, clarity and convenience of description, only one cell contact opening 401O is described.

[0110] Please refer to Fig.11 and Fig.12 , the third mask layer 815 may be removed by an ashing process or other applicable semiconductor processes. A portion of the impurity region 105 and a portion of the isolation layer 103 may be exposed through the cell contact opening 401O. In some embodiments, in a top view, the cell contact opening 401O may include a square cross-sectional profile. In some embodiments, the cell contact opening 401O may include a rectangular cross-sectional profile (not shown).

[0111] Fig.13 FIG. 4 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure. Fig.14 is along Fig.13 A schematic cross-sectional view of the section line A-A'. Fig.15 FIG. 4 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure. Fig.16 and Fig.17is along Fig.15 The cross-sectional schematic diagram along the section line AA' of FIG. 1 illustrates a partial manufacturing process of a semiconductor device according to an embodiment of the present disclosure. Fig.18 FIG. 4 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure. Fig.19 is along Fig.18 A schematic cross-sectional view of the section line A-A'.

[0112] Please refer to Figure 1 and Figures 13 to 19 In step S13 , a first sacrificial layer 711 and a second sacrificial layer 713 may be sequentially formed to partially fill the plurality of cell contact openings 401O, thereby forming a plurality of first middle openings 711O and a plurality of second middle openings 713O exposing the impurity regions 105 .

[0113] An opening adjustment process may be performed to adjust the exposed portion within the cell contact opening 401O. In some embodiments, the opening adjustment process may include a deposition action and a subsequent etching action. The deposition action and the subsequent etching action may be referred to as a cycle. Multiple cycles may be performed during the opening adjustment process. During the deposition action, the sacrificial material may be completely filled into the cell contact opening 401O. The subsequent etching action may remove a portion of the sacrificial material, thereby leaving an intermediate opening within the cell contact opening 401O. This may effectively reduce the size of the exposed portion within the cell contact opening 401O, causing it to be only partially filled. For a visual representation of the process, refer to Figures 13 to 19 , which shows an exemplary opening adjustment process including two cycles.

[0114] Please refer to Fig.13 and Fig.14 During the deposition action of the first cycle of the opening adjustment process, a first sacrificial layer 711 may be deposited to completely fill the cell contact opening 401O. The first sacrificial layer 711 may include a sacrificial material. In some embodiments, for example, the fabrication technique of the first sacrificial layer 711 may include chemical vapor deposition, plasma enhanced chemical vapor deposition, or other applicable deposition processes. A planarization process may be performed until the upper surface of the upper dielectric layer 115 is exposed to provide a substantially flat surface for subsequent semiconductor processes. In some embodiments, the planarization process may be optional.

[0115] In some embodiments, the sacrificial material may be a material having an etching selectivity to the upper dielectric layer 115 and the impurity region 105 (or the substrate 101). In some embodiments, for example, the sacrificial material may include silicon nitride, boron nitride, silicon boron nitride, boron nitride phosphide, boron carbon nitride silicon, or a combination thereof. In some embodiments, for example, the sacrificial material may include boron nitride, silicon boron nitride, boron nitride phosphide, boron carbon nitride silicon, or a combination thereof.

[0116] Please refer to Fig.15 and Fig.16 During the etching action of the first cycle of the opening adjustment process, an etching process may be performed to remove a portion of the first sacrificial layer 711, thereby generating a first intermediate opening 711O. The remaining first sacrificial layer 711 may be mainly adhered to the sidewalls of the cell contact opening 401O. At the present stage, the exposed portion within the cell contact opening 401O may still include the isolation layer 103 and the impurity region 105. In some embodiments, the first intermediate opening 711O may have a circular cross-sectional profile in a top view, but is not limited thereto. In some embodiments, the first intermediate opening 711O may have a diameter (or size) D1.

[0117] Please refer to Fig.17 During the deposition action of the second cycle of the opening tuning process, additional sacrificial material may be conformally deposited over the upper dielectric layer 115 to transform the first sacrificial layer 711 into the second sacrificial layer 713. At this stage, the base of the first intermediate opening 711O may be filled, thereby leaving no exposed portion within the cell contact opening 401O.

[0118] refer to Fig.18 and Fig.19 During the etching action of the second cycle of the opening adjustment process, an etching process may be performed to remove a portion of the second sacrificial layer 713, thereby generating a second intermediate opening 713O. The remaining second sacrificial layer 713 may be mainly adhered to the sidewalls of the cell contact opening 401O. The remaining second sacrificial layer 713 may be thicker than the remaining first sacrificial layer 711. At the present stage, the exposed portion within the cell contact opening 401O may include only the impurity region 105. In some embodiments, the second intermediate opening 713O may have a circular cross-sectional profile in a top view, but is not limited thereto. In some embodiments, the second intermediate opening 713O may have a diameter (or size) D2. The diameter D2 of the second intermediate opening 713O may be smaller than the diameter D1 of the first intermediate opening 711O.

[0119] Alternatively, in some embodiments, after forming the second middle opening 713O (not shown), the exposed portion within the cell contact opening 401O may further include the impurity region 105 and the isolation layer 103. However, the area of ​​the exposed portion within the cell contact opening 401O after forming the second middle opening 713O may be smaller than the area of ​​the exposed portion within the cell contact opening 401O after forming the first middle opening 711O.

[0120] In some embodiments, a planarization process, such as chemical mechanical polishing, may be performed until the upper surface of the upper dielectric layer 115 is exposed to remove excess material and provide a substantially planar surface for subsequent processing steps. In some embodiments, the planarization process may be optional.

[0121] In some embodiments, more cycles of the opening adjustment process may be performed until the desired diameter (or size) of the intermediate opening is achieved. In some embodiments, only one cycle of the opening adjustment process may be performed to achieve the desired diameter of the intermediate opening.

[0122] Fig. 20 FIG. 4 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure. Fig.21 is along Fig. 20 A schematic cross-sectional view of the section line A-A'. Fig. 22 FIG. 4 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure. Figure 23 to Figure 26 is along Fig. 22 The cross-sectional schematic diagram along the section line AA' of FIG. 1 illustrates a partial manufacturing process of a semiconductor device according to an embodiment of the present disclosure. Fig. 27 FIG. 4 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure.

[0123] Please refer to Figure 1 and Figures 20 to 27 In step S15, a plurality of barrier layers 817 may be formed in the plurality of second intermediate openings 713O, the second sacrificial layer 713 may be removed, the plurality of cell contact openings 401O may be deepened to form a plurality of extended cell contact openings 403E, the plurality of barrier layers 817 may be removed, and a plurality of contact structures 400 may be formed in the plurality of extended cell contact openings 403E.

[0124] For the sake of brevity, clarity and convenience of description, only one barrier layer 817 is described.

[0125] Please refer to Fig. 20 and Fig.21 , the barrier layer 817 may completely fill the second middle opening 713O. In some embodiments, the upper surfaces of the barrier layer 817, the second sacrificial layer 713, and the upper dielectric layer 115 may be substantially coplanar. In some embodiments, the barrier layer 817 may include a material having an etching selectivity to the second sacrificial layer 713 and the upper dielectric layer 115. In some embodiments, the barrier layer 817 may be a photoresist layer.

[0126] Alternatively, in some embodiments, the upper surface of the barrier layer 817 may be lower than the upper surface of the second sacrificial layer 713 or the upper surface of the upper dielectric layer 115 (not shown).

[0127] Please refer to Fig. 22and Fig.23 , the second sacrificial layer 713 may be removed. In some embodiments, the removal of the second sacrificial layer 713 may be achieved by an etching process, such as a wet etching process. In some embodiments, during wet etching, an etching rate ratio of the second sacrificial layer 713 to the barrier layer 817 may be between about 100:1 and about 2:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1. In some embodiments, during wet etching, an etching rate ratio of the second sacrificial layer 713 to the upper dielectric layer 115 may be between about 100:1 and about 2:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1.

[0128] Please refer to Fig.24 , an etching process such as an anisotropic dry etching process may be used to deepen the cell contact opening 401O toward the substrate 101. The anisotropic dry etching process may use the barrier layer 817 as a mask. After the anisotropic etching process, the cell contact opening 401O may be extended to form an extended cell contact opening 403E. The lower section of the extended cell contact opening 403E may surround a protrusion 101P of the impurity region 105, which is shielded by the barrier layer 817.

[0129] Please refer to Fig.25 , the barrier layer 817 may be removed by, for example, an ashing process or an etching process. In some embodiments, the upper surface 101PT of the protrusion 101P and the upper surface 101TS of the substrate 101 may be substantially coplanar. In some embodiments, due to the consumption of the protrusion 101P during the removal of the barrier layer 817 (not shown), the upper surface 101PT of the protrusion 101P may be slightly lower than the upper surface 101PT of the substrate 101.

[0130] Please refer to Fig.26 and Fig. 27 , a conductive material may be deposited to completely fill the extended cell contact opening 403E. A planarization process, such as chemical mechanical polishing, may be performed until the upper surface of the upper dielectric layer 115 is exposed to remove excess material, provide a substantially flat surface for subsequent processing steps, and simultaneously form a plurality of contact structures 400. In some embodiments, for example, the conductive material may be tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbide (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitride (e.g., titanium nitride), transition metal aluminide, or a combination thereof.

[0131] For the sake of brevity, clarity and convenience of description, only one contact structure 400 is described.

[0132] In some embodiments, the contact structure 400 may include a body portion 401 and an extension portion 403. The extension portion 403 may be disposed in the lower section of the extended cell contact point opening 403E and surround the protrusion 101P of the impurity region 105. In some embodiments, the upper surface 403TS of the extension portion 403, the upper surface 101PT of the protrusion 101P, and the upper surface 101TS of the substrate 101 may be substantially coplanar. In some embodiments, the lower surface 403BS of the extension portion 403 may be substantially flat. In some embodiments, in a top view, the extension portion 403 may have a square annular cross-sectional profile.

[0133] The body portion 401 may be formed on the extension portion 403 and the protrusion 101P. In some embodiments, the body portion 401 may have a square cross-sectional profile in a top view. In some embodiments, the body portion 401 may have a rectangular cross-sectional profile in a top view (not shown). In some embodiments, a height ratio of a height H1 of the extension portion 403 to a height H2 of the contact structure 400 may be between about 0.05 and about 0.30, between about 0.10 and about 0.30, or between about 0.15 and about 0.20.

[0134] In other words, the extension portion 403 may extend from the body portion 401 to the base 101. A groove 403R may be recessed from the lower surface 403BS of the extension portion 403 and lead to the body portion 401. The groove 403R may accommodate the protrusion 101P that directly contacts the body portion 401. In some embodiments, in the top view, the center point CP1 (indicated as a cross mark) of the body portion 401 may be aligned with the center point CP2 (indicated as a cross mark) of the groove (or referred to as the center point CP2 of the protrusion 101P).

[0135] In the description of this disclosure, an xyz coordinate system is assumed, where x and y refer to dimensions in a plane parallel to the major surfaces of the structure and z refers to a dimension perpendicular to the plane. A feature is aligned with another feature when it has approximately the same x and y coordinates.

[0136] The contact area of ​​the contact structure 400 can be increased by using the extension 403. As a result, the performance of the semiconductor device 1A can be improved.

[0137] Fig.28 1 is a cross-sectional view illustrating a main body portion 401 and an extension portion 403 of a semiconductor element 1B according to another embodiment of the present disclosure.

[0138] Please refer to Fig.28 , the semiconductor element 1B may have Fig. 27 A structure similar to the structure shown. Fig.28 Zhongyu Fig. 27The same or similar elements have been marked with like element numbers, and repeated descriptions have been omitted.

[0139] In the semiconductor device 1B, the body portion 401 may have a circular cross-sectional profile in the top view. The extension portion 403 may have a ring cross-sectional profile in the top view.

[0140] Fig.29 4 is a cross-sectional view illustrating a main body portion 401 and an extension portion 403 of a semiconductor element 1C according to another embodiment of the present disclosure.

[0141] Please refer to Fig.29 , the semiconductor element 1C may have Fig. 27 A structure similar to the structure shown. Fig.29 Zhongyu Fig. 27 The same or similar elements have been marked with like element numbers, and repeated descriptions have been omitted.

[0142] In the semiconductor element 1C, in the top view, the center point CP1 of the body portion 401 may not be aligned with the center point CP2 of the groove (or the center point CP2 of the protrusion 101P).

[0143] Fig.30 FIG. 1 is a schematic cross-sectional view illustrating a semiconductor device 1D according to another embodiment of the present disclosure.

[0144] Please refer to Fig.30 , the semiconductor element 1D may have Fig. 27 A structure similar to the structure shown. Fig.30 Zhongyu Fig. 27 The same or similar elements have been marked with like element numbers, and repeated descriptions have been omitted.

[0145] In the semiconductor device 1D, the lower surface 403BS of the extension 403 may be inclined relative to the upper surface 101TS of the substrate 101. In some embodiments, the lower surface 403BS near the word line structure 200 disposed in the trench TR2 may be higher than the lower surface 403BS near the word line structure 200 disposed in the trench TR1.

[0146] An embodiment of the present disclosure provides a contact structure, comprising a main body portion and an extension portion extending downward from the main body portion and comprising a groove. The groove is recessed from a lower surface of the extension portion, leading to the main body portion and exposing the main body portion.

[0147] Another embodiment of the present disclosure provides a semiconductor element, including a substrate; an impurity region disposed in the substrate; and a contact structure, including: a body portion disposed on the substrate; and an extension portion extending downward from the body portion toward the substrate and forming a groove. The groove accommodates a protrusion of the impurity region, and the protrusion directly contacts the body portion.

[0148] Another embodiment of the present disclosure provides a method for preparing a semiconductor element, including providing a substrate; forming a dielectric layer on the substrate; forming a unit contact opening along the dielectric layer to expose the substrate; conformally forming a sacrificial layer that partially fills the unit contact opening to form an intermediate opening that exposes the substrate; forming a barrier layer that completely fills the intermediate opening; removing the sacrificial layer; performing an etching process using the barrier layer as a mask to deepen the unit contact opening into the substrate and transform the unit contact opening into an extended unit contact opening that surrounds a protrusion of the substrate; removing the barrier layer; and forming a contact structure in the extended unit contact opening.

[0149] Due to the design of the semiconductor device of the present disclosure, the extension 403 can increase the contact area between the contact structure 400 and the impurity region 105. As a result, the performance of the semiconductor device 1A can be improved.

[0150] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements can be made without departing from the concept and scope of the present disclosure defined by the claims. For example, many of the above processes can be implemented in different ways, and other processes or combinations thereof can be used to replace many of the above processes.

[0151] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art can understand from the disclosure of the present disclosure that existing or future developed processes, machines, manufactures, compositions of matter, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. Accordingly, these processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. A method for preparing a semiconductor element, comprising: providing a substrate; forming a dielectric layer on the substrate; forming a cell contact opening along the dielectric layer to expose the substrate; Conformally forming a sacrificial layer partially filling the cell contact opening to form a middle opening exposing the substrate; forming a barrier layer that completely fills the middle opening; removing the sacrificial layer; performing an etching process with the barrier layer as a mask to deepen the cell contact opening into the substrate and transform the cell contact opening into an extended cell contact opening surrounding a protrusion of the substrate; removing the barrier layer; as well as A contact structure is formed in the extension unit contact point opening. 2 . The method of claim 1 , wherein the sacrificial layer comprises silicon nitride, boron nitride, silicon boron nitride, boron phosphide, silicon boron carbon nitride or a combination thereof. The preparation method as claimed in claim 1 , wherein the blocking layer comprises photoresist. The preparation method according to claim 3 , wherein the barrier layer is removed by an ashing process.

5. The method of claim 1, wherein the contact structure comprises tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbide, metal nitride, transition metal aluminide, or a combination thereof. 6 . The manufacturing method as claimed in claim 1 , wherein the contact structure comprises an extension portion and a main body portion, wherein the extension portion surrounds the protrusion of the substrate and the main body portion formed on the extension portion. 7 . The preparation method as claimed in claim 6 , wherein the main body has a square cross-sectional profile in a top view. 8 . The manufacturing method according to claim 7 , wherein the extension portion has a square annular cross-sectional profile in the top view.

9. The preparation method as claimed in claim 6, wherein the main body has a circular cross-sectional profile in a top view. 10 . The manufacturing method according to claim 9 , wherein the extension portion has a square ring-shaped cross-sectional profile in the top view.

Images