Node interconnection method and device of software defined system on chip and chip

Abstract

The invention provides a node interconnection method, a node interconnection device and a node interconnection chip of a software-defined system on chip, the software-defined system on chip comprises a wafer substrate and a plurality of core particle module groups located on the wafer substrate, and each core particle module group comprises a plurality of mutually connected core particles located on a functional layer. The method comprises the following steps: adding an interconnection layer comprising a plurality of core particles on a plurality of core particles of a functional layer; the plurality of core particles of the interconnection layer are in communication connection with the plurality of core particles of the functional layer; and performing communication connection on the plurality of core particles in the interconnection layer, wherein an interconnection line of the plurality of core particles in the interconnection layer is determined according to the connection relationship among the plurality of core particles in the functional layer. The invention further provides a node interconnection device of the software-defined system-on-chip and a chip.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, in particular to the field of node interconnection of software-defined on-chip systems. Background Art

[0002] With the development of emerging technologies such as artificial intelligence, big data, cloud computing, and machine learning, the performance requirements for processors to process and access data are getting higher and higher. Traditional single processor solutions can no longer provide such high computing power and meet the corresponding data transmission needs. Affected by the slowdown in the growth rate of Moore's Law and the failure of Dennard scaling, current research has gradually shifted to the field of software-defined on-chip systems. Software-defined on-chip systems usually have multiple functional nodes and multiple input and output (IO) nodes, and the interconnection mode between functional nodes and input and output nodes is often many-to-many. Functional nodes and input and output nodes are directly connected to each other using interconnection lines. The number of interconnection lines will increase rapidly with the increase in the number of nodes, and the corresponding design difficulty and manufacturing cost will also increase rapidly. Summary of the invention

[0003] In order to solve the above technical problems, the present invention discloses a node interconnection method of a software-defined on-wafer system, wherein the software-defined on-wafer system comprises a wafer substrate, and a plurality of chiplet module groups located on the wafer substrate, wherein the chiplet module groups further comprise a plurality of interconnected chiplets located at a functional layer, and the method comprises the following steps:

[0004] Adding an interconnection layer including a plurality of core particles on the plurality of core particles of the functional layer;

[0005] communicatively connecting the plurality of core particles of the interconnect layer with the plurality of core particles of the functional layer;

[0006] The plurality of core particles in the interconnection layer are communicatively connected, wherein the interconnection lines of the plurality of core particles in the interconnection layer are determined according to the connection relationship between the plurality of core particles in the functional layer.

[0007] In one embodiment of the above method of the present invention, the step of determining the interconnection lines of the plurality of core particles in the interconnection layer according to the connection relationship between the plurality of core particles in the functional layer further comprises:

[0008] The interconnection lines of the plurality of core particles in the interconnection layer are arranged according to the core particle interconnection performance and the core particle interconnection cost.

[0009] In one embodiment of the above method of the present invention, the step of setting the interconnection lines of the plurality of cores in the interconnection layer according to the core interconnection performance and the core interconnection cost further comprises:

[0010] Setting a circuit in which the plurality of core particles are connected in series, or,

[0011] The plurality of cores are arranged in series and include circuits for cross-core connection.

[0012] In one embodiment of the above method of the present invention, the step of communicatively connecting the plurality of chiplets in the interconnect layer further comprises:

[0013] The interconnection logics of the plurality of core particles are reconfigured by programming the plurality of core particles in the interconnection layer.

[0014] In one embodiment of the above method of the present invention, the step of communicatively connecting the plurality of core particles of the interconnect layer with the plurality of core particles of the functional layer further comprises:

[0015] Connecting the core particles of the functional layer to the core particles of the interconnect layer one-to-one, or

[0016] The core particles of the functional layer are connected to the core particles of the interconnect layer in a one-to-many manner.

[0017] In one embodiment of the above method of the present invention, the method further comprises the steps of:

[0018] One or more of a routing algorithm, a flow control algorithm, and a congestion control algorithm are implemented on the core particles of the interconnect layer.

[0019] In one embodiment of the method of the present invention, the plurality of cores of the interconnect layer are FPGA cores.

[0020] The present invention also provides a node interconnection device of a software-defined on-chip system, which is used to implement the above method, including:

[0021] An interconnection layer setting module, used for adding an interconnection layer including a plurality of core particles on the functional layer;

[0022] A first communication connection module, used for communication connection of a plurality of core particles in the interconnection layer;

[0023] The second communication connection module is used to connect the plurality of core particles of the interconnection layer to the plurality of core particles of the functional layer through communication.

[0024] The present invention also provides a chip for implementing the aforementioned method, comprising a wafer substrate and a plurality of core module groups located on the wafer substrate, wherein the wafer substrate and the plurality of core module groups are encapsulated via a packaging layer, and the core module groups include a plurality of interconnected cores located in a functional layer, a power module, and a plurality of cores located in an interconnect layer; wherein the power module provides power for the plurality of cores in the functional layer, the plurality of cores in the functional layer are communicatively connected to the plurality of cores in the interconnect layer, and the plurality of cores in the interconnect layer are communicatively connected.

[0025] The present invention also provides a storage medium for storing a computer control program, wherein the computer control program is used to execute the steps of the above method.

[0026] The present invention proposes a node interconnection method, device and chip for a software-defined on-wafer system. In a chip module group on a wafer substrate, an interconnection layer including multiple chiplets is added on top of multiple chiplets in a functional layer of the chip module group, and then multiple chiplets in the interconnection layer are communicatively connected, as well as multiple chiplets in the interconnection layer are communicatively connected with multiple chiplets in the functional layer, and interconnection lines of the multiple chiplets in the interconnection layer are determined according to the connection relationship between the multiple chiplets in the functional layer. Compared with directly using interconnection lines to connect functional nodes and input-output nodes in pairs, the total length of the interconnection lines is reduced, and the corresponding design difficulty and manufacturing cost are also reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 The present invention is a flowchart of a method for interconnecting nodes in a software-defined on-chip system according to an embodiment of the present invention.

[0028] Figure 2 FIG. 4 is a schematic diagram of the composition of a wafer substrate and a chip module group in one embodiment of the present invention.

[0029] Figure 3 Schematic diagram of the composition of the functional layer of the core module group in one embodiment of the present invention.

[0030] Figure 4 Schematic diagram of the composition of the interconnection layer of the core module group in one embodiment of the present invention.

[0031] Figure 5a FIG. 1 is a schematic diagram of a chip interconnection circuit in a chip module group interconnection layer according to an embodiment of the present invention.

[0032] Figure 5b FIG. 1 is a schematic diagram of a chip interconnection circuit in a chip module group interconnection layer in another embodiment of the present invention.

[0033] Figure 5c FIG. 1 is a schematic diagram of a chip interconnection circuit in a chip module group interconnection layer in another embodiment of the present invention.

[0034] Figure 5d FIG. 1 is a schematic diagram of a chip interconnection circuit in a chip module group interconnection layer in another embodiment of the present invention.

[0035] Figure 5e FIG. 1 is a schematic diagram of a chip interconnection circuit in a chip module group interconnection layer in another embodiment of the present invention.

[0036] Figure 6 Schematic diagram of the communication connection between the core module group functional layer and the interconnection layer in one embodiment of the present invention.

[0037] Figure 7 The present invention is a block diagram of a node interconnection device of a software-defined on-chip system in one embodiment of the present invention.

[0038] Figure 8 The figure is a block diagram of a chip in one embodiment of the present invention.

[0039] Wherein, the reference numerals are:

[0040] 1: Wafer substrate

[0041] 2: Chip module group

[0042] 20: Functional layer

[0043] 21: Input and output chip

[0044] 22: Functional core particles

[0045] 23, 32: Power module

[0046] 30: Interconnect layer

[0047] 31: Interconnection Chip

[0048] 4: Interconnection lines

[0049] 5: Heat dissipation layer

[0050] 6: Encapsulation layer

[0051] 10: Node interconnection device of software-defined on-chip system

[0052] 11: Interconnect layer setting module

[0053] 12: First communication connection module

[0054] 13: Second communication connection module DETAILED DESCRIPTION

[0055] The technical solution of the present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments to further understand the purpose, solution and beneficial technical effects of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0056] It should be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0057] Certain words are used in the specification and the appended claims to refer to specific components or parts. It should be understood by those skilled in the art that technical users or manufacturers may refer to the same component or part by different nouns or terms. This specification and the appended claims do not distinguish components or parts by differences in names, but by differences in functions.

[0058] In the present invention, the directions or positional relationships indicated by the terms "upper", "lower", "left", "right", "front", "back", "top", "bottom", "inner", "outer", "middle", "vertical", "horizontal", "lateral", "longitudinal" and the like are based on the directions or positional relationships shown in the drawings. These terms are mainly used to better describe the present invention and its embodiments, and are not used to limit the indicated devices, elements or components to have a specific direction, or to be constructed and operated in a specific direction.

[0059] In addition, some of the above terms may be used to express other meanings in addition to indicating orientation or positional relationship. For example, the term "on" may also be used to express a certain dependency or connection relationship in some cases. For those skilled in the art, the specific meanings of these terms in the present invention can be understood according to specific circumstances.

[0060] In addition, the terms "installed", "set", "provided with", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, elements, or components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0061] System on Wafer, i.e. wafer-level system, directly uses the complete wafer substrate 1, without other substrates or PCB boards, as the interconnection base of each module inside the system, and uses the above advantages to support more precise routing to tightly interconnect and package the internal core particles to obtain higher bandwidth, lower latency and lower power consumption. Software-defined System on Wafer further improves the overall performance and flexibility of the system on wafer. Software-defined system on wafer supports software-defined connection mode and can software-define its own functions at the module level. This design idea increases flexibility and scalability while maintaining the high performance and low latency of the original system on wafer, and can meet complex and diverse application requirements. However, in the face of the increasing demand for computing system computing power and memory bandwidth in applications in various fields, it is necessary to design advanced interconnection solutions to further give play to the advantages of software-defined system on wafer, and dense interconnection is required to ensure high performance and low power consumption of data transmission between modules and various types of core particles within modules.

[0062] In the scheme of direct interconnection between functional nodes (core particles that actually provide computing power or storage and other actual task processing functions in software-defined on-chip systems, i.e., functional core particles 22) and input-output nodes (core particles that undertake inter-system communication tasks in software-defined on-chip systems, i.e., input-output core particles 21), each node needs to be physically wired to other nodes. In a software-defined on-chip system, if the number of nodes (functional nodes, input-output nodes) is n, the number of wires required is n(n-1) / 2, and the direct interconnection of distant nodes requires longer wiring distances and more careful wiring design. As the number of nodes increases, the wiring cost and wiring difficulty rise sharply.

[0063] See also Figure 1 and Figure 2 , Figure 1 The present invention is a flowchart of a method for interconnecting nodes in a software-defined on-chip system according to an embodiment of the present invention. Figure 2The present invention is a schematic diagram of the composition of a wafer substrate 1 and a core module group 2 in an embodiment of the present invention. In order to solve the technical problem that the number of interconnection lines 4 will increase rapidly with the increase of the number of nodes, and the corresponding design difficulty and manufacturing cost will also increase rapidly when the functional nodes and input and output nodes in the software-defined on-wafer system are directly connected by interconnection lines 4, the software-defined on-wafer system includes a wafer substrate 1, and a plurality of core module groups 2 located on the wafer substrate 1, and the core module group 2 includes a plurality of cores located in the functional layer 20, and the method includes the following steps: step S1: adding an interconnection layer 30 including a plurality of cores to the plurality of cores in the functional layer 20; step S2: connecting the plurality of cores in the interconnection layer 30 to the plurality of cores in the functional layer 20; step S3: connecting the plurality of cores in the interconnection layer 30 to each other, wherein the interconnection lines of the plurality of cores in the interconnection layer 30 are determined according to the connection relationship between the plurality of cores in the functional layer 20.

[0064] In one embodiment, in step S1, an interconnection layer 30 including multiple core particles is added on the multiple core particles of the functional layer 20. The interconnection layer 30 of the multiple core particles can be physically located above the functional layer 20 of the multiple core particles, or the interconnection layer 30 of the multiple core particles can be directly located on the wafer substrate 1. Hierarchically, the interconnection layer 30 is located above the functional layer 20.

[0065] In one embodiment, the interconnection lines 4 may be connected by metal wiring using RDL (Redistribution layer) technology, but the present invention is not limited thereto.

[0066] In one embodiment, when performing step S3: communicating and connecting multiple core particles in the interconnection layer 30, the interconnection lines of the multiple core particles in the interconnection layer 30 are determined according to the connection relationship between the multiple core particles in the functional layer 20. The topological network of the interconnection between the multiple core particles in the interconnection layer 30 determines the interconnection performance between the functional nodes and the input and output nodes to a certain extent. In actual design and operation, it is also necessary to weigh the interconnection performance requirements and the interconnection design and manufacturing complexity.

[0067] See also Figure 3 , Figure 3 The figure is a schematic diagram of the composition of the functional layer 20 of the core module group 2 in one embodiment of the present invention. In one embodiment, the multiple cores of the functional layer 20 include functional cores 22 (cores that actually provide computing power or storage and other actual task processing functions in the software-defined on-chip system, specifically deep learning cores with deep learning computing functions, privacy computing cores with privacy computing processing functions, storage cores that provide on-chip storage functions, etc.) and input-output cores 21, and may also include other types of cores. The power module 23 supplies power to the functional cores 22, the general node cores, and the input-output cores 21.

[0068] See also Figure 4 , Figure 4 Schematic diagram of the composition of the interconnection layer 30 of the core module group 2 in one embodiment of the present invention. In one embodiment, the interconnection layer 30 includes a plurality of cores, including an interconnection core 31, and the power module 32 in the interconnection layer 30 supplies power to the plurality of interconnection cores 31. The plurality of interconnection cores 31 in the interconnection layer 30 can also obtain power through the power module 23 of the functional layer 20. The plurality of interconnection cores 31 in the interconnection layer 30 provide routing functions between functional nodes and input and output nodes.

[0069] In one embodiment, the step of determining the interconnection lines of the plurality of core particles in the interconnection layer 30 according to the connection relationship between the plurality of core particles in the functional layer 20 further includes:

[0070] The interconnection lines of more than 30 core particles in the interconnection layer are set according to the core particle interconnection performance and core particle interconnection cost. The beneficial effect of this embodiment is that by taking all-round considerations when determining the interconnection lines of more than 30 core particles in the interconnection layer, the design difficulty and manufacturing cost of the interconnection between the functional nodes and the input and output nodes in the software-defined on-chip system can be reduced under the premise of ensuring functional integrity and performance requirements.

[0071] See also Figure 5a to Figure 5e In one embodiment, the step of setting interconnection lines of more than 30 core particles of the interconnection layer according to the core particle interconnection performance and the core particle interconnection cost further includes:

[0072] Set up multiple chips in series connection circuit, or,

[0073] A plurality of die are provided to be connected in series and include circuits for cross-die connections.

[0074] Figure 5a to Figure 5d The interconnection between the interconnection layer 30 core particles is shown. When the interconnection lines of the interconnection layer 30 core particles are set according to the core particle interconnection performance and the core particle interconnection cost, the interconnection lines of the core particles can be set according to the length of the interconnection line 4 and the degree of core particle interconnection. In one embodiment, Figure 5a As shown, the interconnection layer 30 core particles are connected in series (except the first and last core particles). This interconnection method uses the least connection wires and has the lowest cost. Figure 5b As shown, more than 30 core particles in the interconnection layer are connected in series. This interconnection method is Figure 5a In the connection mode, a communication line is added, but the communication delay is lower. In one embodiment, Figure 5c As shown, in Figure 5c Two cross-chip connection lines are added on the basis of the interconnection lines. Figure 5bThe connection mode increases the cost of the connection line, while the communication delay between the chips is lower and the load is more balanced. Figure 5d As shown, in Figure 5c Two more cross-chip connection lines are added on top of the interconnection lines. Figure 5c The connection mode has lower communication delay and more balanced load. In one embodiment, Figure 5e As shown, more than 30 core particles of the interconnection layer are connected in series, and the arrows pointing from the core particles to the outside represent the interconnection lines 4 between the core particle module groups 2, that is, the core particles in the current core particle module group 2 communicate with the core particles in other core particle module groups 2. In this embodiment, all the core particles can communicate with the core particles in other core particle module groups 2, and the connection lines between the core particle module groups 2 can be increased or decreased according to specific needs, core particle interconnection performance, and core particle interconnection cost.

[0075] The beneficial effect of this embodiment is that when determining the interconnection lines of more than 30 core particles in the interconnection layer, facing the requirements of reducing the design difficulty of interconnection between functional nodes and input-output nodes, ensuring the interconnection performance between functional nodes and input-output nodes, and the manufacturing cost of interconnection between functional nodes and input-output nodes, a suitable communication connection scheme between more than 30 core particles in the interconnection layer is selected. The interconnection lines of more than 30 core particles in the interconnection layer are shorter than the direct connection between the functional core particle 22 and the input-output core particle 21, and the manufacturing cost of interconnection between functional nodes and input-output nodes is also reduced.

[0076] In one embodiment, the plurality of interconnection chips 31 of the interconnection layer 30 are field programmable gate array (FPGA) chips. It should be noted that the interconnection chip may also be other types of programmable chips, but is not limited thereto.

[0077] In one embodiment, the step of communicatively connecting the plurality of cores in the interconnect layer 30 further includes:

[0078] The interconnection logic of multiple core particles in the interconnection layer 30 is reconstructed by programming. In one embodiment, different core particle module groups 2 (such as privacy computing, deep learning, graph computing, etc.) correspond to different task loads, and different task loads have different traffic characteristics. The beneficial effect of this embodiment is that the interconnection logic of the interconnected core particles 31 (such as FPGA core particles) is dynamically programmed and configured, so that different traffic characteristics of different load tasks can be personalized and flexibly adapted, and finally the load balancing ability, deadlock avoidance ability, and congestion control ability of the core particle module group 2 and the communication between the core particle module groups 2 are improved. In one embodiment, when programming the interconnected core particles 31 (i.e., dynamically programming and configuring), the electronic design automation EDA tool can be used to program and burn the interconnected core particles 31. The beneficial effect of this embodiment is that by dynamically programming and configuring the interconnected core particles 31 to reconstruct the interconnection logic of multiple core particles, the problem that the interconnection line 4 between the functional node and the input and output node is fixed and cannot be dynamically adjusted is solved;

[0079] See also Figure 6 In one embodiment, the step of communicatively connecting the plurality of core particles of the interconnect layer 30 with the plurality of core particles of the functional layer 20 further includes:

[0080] Connect the core particles of the functional layer 20 to the core particles of the interconnect layer 30 one-to-one, or

[0081] The core particles of the functional layer 20 are connected one-to-many with the core particles of the interconnection layer 30. Conventionally, the core particles of the functional layer 20 are connected one-to-one with the core particles of the interconnection layer 30. In the broadcast communication scenario, one core particle of the functional layer 20 corresponds to multiple core particles of the interconnection layer 30, which can improve the performance of point-to-multipoint communication requirements.

[0082] In one embodiment, the node interconnection method of the software-defined on-chip system further includes the steps of:

[0083] One or more of the routing algorithm, flow control algorithm, and congestion control algorithm are implemented for the core particles of the interconnection layer 30. In this embodiment, the routing algorithm, flow control algorithm, and congestion control algorithm implemented for the core particles of the interconnection layer 30 are algorithms in the prior art, which will not be described in detail here, and the load balancing capability, deadlock avoidance capability, and congestion control capability of the core particle module group 2 and the communication between the core particle module groups 2 can be improved by implementing the aforementioned algorithms for the core particles of the interconnection layer 30.

[0084] See also Figure 7 The present invention also provides a node interconnection device 10 of a software-defined on-chip system, which is used to implement the aforementioned method, including:

[0085] An interconnection layer setting module 11 is used to add an interconnection layer 30 including a plurality of core particles on the functional layer 20;

[0086] A first communication connection module 12, used for communication connection of multiple core particles in the interconnection layer 30;

[0087] The second communication connection module 13 is used for communication connection between the plurality of core particles of the interconnection layer 30 and the plurality of core particles of the functional layer 20 .

[0088] See also Figure 8 The present invention also provides a chip for implementing the aforementioned method, including a wafer substrate 1, a plurality of core module groups 2 located on the wafer substrate 1, and a heat dissipation layer 5 connected to the wafer substrate, the wafer substrate 1 and the plurality of core module groups 2 are encapsulated via an encapsulation layer 6, the core module group 2 includes a plurality of cores located in a functional layer 20, a power module 23, and a plurality of cores located in an interconnection layer 30; wherein the power module provides power for the plurality of cores in the functional layer 20, the plurality of cores in the functional layer 20 are communicatively connected to the plurality of cores in the interconnection layer 30, and the plurality of cores in the interconnection layer 30 are communicatively connected.

[0089] The present invention also provides a storage medium for storing a computer control program, and the computer control program is used to execute the steps of the above method.

[0090] It should be understood that the storage medium in the embodiment of the present invention may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0091] The present invention proposes a node interconnection method, device and chip for a software-defined on-wafer system. In a chip module group on a wafer substrate, an interconnection layer including multiple chiplets is added on top of multiple chiplets in a functional layer of the chip module group, and then multiple chiplets in the interconnection layer are communicatively connected, as well as multiple chiplets in the interconnection layer are communicatively connected with multiple chiplets in the functional layer, and interconnection lines of multiple chiplets in the interconnection layer are determined according to the connection relationship between the multiple chiplets in the functional layer. Compared with directly using interconnection lines to connect functional nodes and input-output nodes in pairs, the total length of the interconnection lines is reduced, and the corresponding design difficulty and manufacturing cost are also reduced.

[0092] In summary, the present invention may have many other embodiments. Without departing from the spirit and essence of the present invention, technicians familiar with the field can evolve various corresponding changes and deformations based on the present invention, but these corresponding changes and deformations should all fall within the scope of protection of the patent applied for the present invention.

Claims

1. A node interconnection method for a software-defined on-wafer system, the software-defined on-wafer system comprising a wafer substrate, and a plurality of chiplet module groups located on the wafer substrate, the chiplet module groups further comprising a plurality of interconnected chiplets located at a functional layer, characterized in that: The method comprises the following steps: Adding an interconnection layer including a plurality of core particles on the plurality of core particles of the functional layer; communicatively connecting the plurality of core particles of the interconnect layer with the plurality of core particles of the functional layer; The plurality of core particles in the interconnection layer are communicatively connected, wherein the interconnection lines of the plurality of core particles in the interconnection layer are determined according to the connection relationship between the plurality of core particles in the functional layer.

2. The method according to claim 1, characterized in that The step of determining the interconnection lines of the plurality of core particles in the interconnection layer according to the connection relationship between the plurality of core particles in the functional layer further comprises: The interconnection lines of the plurality of core particles in the interconnection layer are arranged according to the core particle interconnection performance and the core particle interconnection cost.

3. The method according to claim 2, characterized in that The step of setting interconnection lines of the plurality of core particles in the interconnection layer according to the core particle interconnection performance and the core particle interconnection cost further comprises: Setting a circuit in which the plurality of core particles are connected in series, or, The plurality of cores are arranged in series and include circuits for cross-core connection.

4. The method according to claim 1, 2 or 3, characterized in that: The step of communicatively connecting the plurality of core particles in the interconnect layer further comprises: The interconnection logics of the plurality of core particles are reconfigured by programming the plurality of core particles in the interconnection layer.

5. The method according to claim 1, 2 or 3, characterized in that: The step of communicatively connecting the plurality of core particles of the interconnect layer with the plurality of core particles of the functional layer further comprises: Connecting the core particles of the functional layer to the core particles of the interconnect layer one-to-one, or The core particles of the functional layer are connected to the core particles of the interconnect layer in a one-to-many manner.

6. The method according to claim 4, characterized in that Also includes the steps: One or more of a routing algorithm, a flow control algorithm, and a congestion control algorithm are implemented on the core particles of the interconnect layer.

7. The method according to any one of claims 1, 2, 3 and 6, characterized in that: The plurality of core particles of the interconnect layer are FPGA core particles.

8. A node interconnection device of a software-defined on-chip system, used to implement the method according to any one of claims 1 to 7, characterized in that: include: An interconnection layer setting module, used for adding an interconnection layer including a plurality of core particles on the functional layer; A first communication connection module, used for communication connection of a plurality of core particles in the interconnection layer; The second communication connection module is used to connect the plurality of core particles of the interconnection layer to the plurality of core particles of the functional layer through communication.

9. A chip for implementing the method according to any one of claims 1 to 7, characterized in that: It includes a wafer substrate and a plurality of chip module groups located on the wafer substrate, the wafer substrate and the plurality of chip module groups are encapsulated via a packaging layer, the chip module group includes a plurality of interconnected chiplets located in a functional layer, a power module, and a plurality of chiplets located in an interconnect layer; wherein the power module provides power for the plurality of chiplets in the functional layer, the plurality of chiplets in the functional layer are communicatively connected with the plurality of chiplets in the interconnect layer, and the plurality of chiplets in the interconnect layer are communicatively connected.

10. A storage medium for storing a computer control program, characterized in that: The computer control program is used to execute the steps of the method according to any one of claims 1 to 7.

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