Packaging structure and manufacturing method thereof

Abstract

The invention discloses a packaging structure and a manufacturing method thereof, and the packaging structure comprises a first substrate, a plurality of chip structures which are distributed on the first substrate at intervals, and a gap which surrounds the plurality of chip structures. The second substrate is correspondingly connected with one side, far away from the first substrate, of each chip structure in a bonding manner; the side, opposite to the first substrate, of the second substrate is provided with a plurality of first groove patterns distributed at intervals, and the first groove patterns are arranged above the chip structures in a one-to-one correspondence mode.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing, and in particular to a packaging structure and a manufacturing method thereof. Background Art

[0002] Three Dimension (3D) integrated circuits are a new type of packaging in which multiple layers of chips are stacked in sequence and electrically connected through conductive vias. They can effectively reduce the interconnection power consumption and interconnection delay between chips. Compared with traditional two-dimensional chips, 3D integrated circuits have high integration and performance advantages such as high storage and high bandwidth. They can better realize the miniaturization and diversification of devices, and are of great significance to the development of high-tech fields such as mobile communications and artificial intelligence.

[0003] As the chip line width shrinks and the number of 3D integrated circuit stacking layers increases, the performance of the chip gradually increases, while the heat generation increases, which will increase the chip temperature and affect its lifespan, performance, and signal input and output. Therefore, improving the chip's heat dissipation performance has become an important research direction in the development of 3D integrated circuits. Summary of the invention

[0004] The present disclosure provides a packaging structure, comprising:

[0005] A first substrate, a plurality of chip structures spaced apart from each other on the first substrate, and gaps surrounding the plurality of chip structures;

[0006] The second substrate is bonded to the side of the plurality of chip structures away from the first substrate. The second substrate has a plurality of first groove patterns spaced apart on the side opposite to the first substrate. The plurality of first groove patterns are arranged one by one above the plurality of chip structures.

[0007] In some embodiments, at least one of the first groove patterns is in communication with the gap.

[0008] In some embodiments, the chip structure includes at least one heat spot, which is an area in the chip structure where the operating temperature is greater than or equal to a predetermined reference temperature; the density of the portion of the first groove pattern located above the heat spot is greater than the density of the portion of the first groove pattern located above other areas of the chip structure except the heat spot.

[0009] In some embodiments, the cross-sectional shapes of the first groove patterns above at least two of the plurality of chip structures along a direction parallel to the plane of the second substrate are different.

[0010] In some embodiments, the packaging structure further includes: a second groove pattern located on a side of the second substrate opposite to the first substrate, the second groove pattern being located above the gap and communicating with the gap.

[0011] In some embodiments, the packaging structure further includes:

[0012] A first dielectric layer, covering the sidewalls of the chip structure and the bottom surface of the gap;

[0013] The second dielectric layer covers the upper surface of the chip structure and the first dielectric layer.

[0014] The present disclosure also provides a method for manufacturing a packaging structure, comprising:

[0015] Providing a first substrate, and forming a plurality of spaced-apart chip structures and gaps surrounding the chip structures on the first substrate;

[0016] Providing a second substrate, and forming a plurality of first groove patterns on a side surface of the second substrate;

[0017] The side of the second substrate formed with the first groove pattern is bonded and connected to the side of the plurality of chip structures away from the first substrate, and the plurality of first groove patterns are arranged above the plurality of chip structures in a one-to-one correspondence.

[0018] In some embodiments, the method further includes: forming a second groove pattern on the same side surface of the second substrate as that on which the first groove pattern is formed;

[0019] After the second substrate is bonded and connected to the plurality of chip structures in correspondence, the second groove pattern is located above the gap and communicated with the gap.

[0020] In some embodiments, before forming a plurality of first groove patterns on one side surface of the second substrate, the method further includes:

[0021] respectively obtaining heat dissipation requirements of the plurality of chip structures;

[0022] Densities of the plurality of first groove patterns corresponding to the plurality of chip structures are determined according to heat dissipation requirements of the plurality of chip structures.

[0023] In some embodiments, after forming a plurality of spaced chip structures on the first substrate and before bonding the second substrate to the plurality of chip structures, the method further includes:

[0024] forming a first dielectric layer, wherein the first dielectric layer covers surfaces of the plurality of chip structures and the bottom of the gap;

[0025] Performing a thinning process on a side of the chip structure away from the first substrate to remove a predetermined thickness of the chip structure and a first dielectric layer located on an upper surface and a portion of a side wall of the chip structure;

[0026] A second dielectric layer is formed, wherein the second dielectric layer covers the thinned upper surface of the chip structure and the first dielectric layer.

[0027] The packaging structure and manufacturing method thereof provided by the embodiment of the present disclosure, wherein the packaging structure includes: a first substrate, a plurality of chip structures spaced apart on the first substrate, and a gap surrounding the plurality of chip structures; a second substrate, correspondingly bonded to the side of the plurality of chip structures away from the first substrate; the second substrate has a plurality of first groove patterns spaced apart on the side opposite to the first substrate, and the plurality of first groove patterns are arranged one by one above the plurality of chip structures. In the embodiment of the present disclosure, the plurality of chip structures are surrounded by gaps, and the gaps surround the chip structures. If the gaps constitute microfluidic channels for the side heat dissipation of the plurality of chip structures, the side heat dissipation efficiency of the chip structures can be improved; at the same time, the plurality of chip structures are bonded to the second substrate, and the side opposite to the chip structure of the second substrate is provided with a first groove pattern, and the first groove pattern is located above the chip structure, which enhances the heat dissipation efficiency of the upper surface of the chip structure; in addition, in the embodiment of the present disclosure, the gaps can also be connected with the first groove pattern to form an integrated circulation microfluidic channel to further improve the heat dissipation effect of the chip structure.

[0028] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features and advantages of the present disclosure will become apparent from the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0030] Figure 1 A schematic diagram of a packaging structure provided by an embodiment of the present disclosure;

[0031] Figure 2 and Figure 3 Different examples of bottom view schematic diagrams of the second substrate provided in the embodiments of the present disclosure; Figure 4 , Figure 5 and Figure 6 Different examples of bottom view schematic diagrams of the partial structure of the second substrate provided in the embodiments of the present disclosure;

[0032] Figure 7 A flowchart of a method for manufacturing a packaging structure provided by an embodiment of the present disclosure;

[0033] Figures 8 to 14 A process flow chart of a method for manufacturing a packaging structure provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0035] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0036] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0037] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0038] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0039] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0040] Three Dimension (3D) integrated circuits are a new type of packaging in which multiple layers of chips are stacked in sequence and electrically connected through conductive vias. They can effectively reduce the interconnection power consumption and interconnection delay between chips. Compared with traditional two-dimensional chips, 3D integrated circuits have high integration and performance advantages such as high storage and high bandwidth. They can better realize the miniaturization and diversification of devices, and are of great significance to the development of high-tech fields such as mobile communications and artificial intelligence.

[0041] As the chip line width shrinks and the number of 3D integrated circuit stacking layers increases, the performance of the chip gradually increases, while the heat generation increases, which will increase the chip temperature and affect its lifespan, performance, and signal input and output. Therefore, improving the chip's heat dissipation performance has become an important research direction in the development of 3D integrated circuits.

[0042] Based on this, the following technical solutions of the embodiments of the present disclosure are proposed.

[0043] In the embodiment of the present disclosure, there are gaps around the multiple chip structures, and the gaps surround the chip structures. If the gaps constitute microfluidic channels for side heat dissipation of the multiple chip structures, the side heat dissipation efficiency of the chip structures can be improved; at the same time, the multiple chip structures are bonded to the second substrate, and a first groove pattern is provided on the side of the second substrate opposite to the chip structure. The first groove pattern is located above the chip structure, thereby enhancing the heat dissipation efficiency of the upper surface of the chip structure; in addition, in the embodiment of the present disclosure, the gaps can also be connected with the first groove pattern to form an integrated circulating microfluidic channel to further improve the heat dissipation effect of the chip structure.

[0044] The specific implementation of the present disclosure is described in detail below in conjunction with the accompanying drawings. When describing the embodiments of the present disclosure in detail, for the sake of convenience, the schematic diagram will not be partially enlarged according to the general scale, and the schematic diagram is only an example, which should not limit the scope of protection of the present disclosure.

[0045] Figure 1 A schematic diagram of a packaging structure provided by an embodiment of the present disclosure; Figure 2 and Figure 3 Different examples of bottom view schematic diagrams of the second substrate provided in the embodiments of the present disclosure; Figure 4 , Figure 5 and Figure 6 Different examples of bottom view schematic diagrams of the partial structure of the second substrate provided in the embodiments of the present disclosure; wherein, Figures 2 to 6 The dotted boxes in the figure represent the distribution positions of the multiple chip structures located below the second substrate. Figures 1 to 6 The packaging structure provided by the embodiment of the present disclosure is further described.

[0046] like Figures 1 to 6 As shown, the packaging structure includes: a first substrate 10, a plurality of chip structures 12 spaced apart on the first substrate 10, and gaps 14 surrounding the plurality of chip structures 12; a second substrate 17, bonded to and connected to a side of the plurality of chip structures 12 away from the first substrate 10; a side of the second substrate 17 opposite to the first substrate 10 has a plurality of first groove patterns T1 spaced apart, and the plurality of first groove patterns T1 are arranged one by one above the plurality of chip structures 12.

[0047] It should be noted that "upper" here and below refers to the upward direction or upper side in the drawings, and "lower" refers to the downward direction or lower side in the drawings. It should be understood that the descriptions of "upper" and "lower" in this application are not to be construed as limiting the placement position of the packaging structure during manufacturing and use.

[0048] Here, the material of the first substrate 10 may be a semiconductor material, such as silicon. More specifically, the first substrate 10 may be a silicon wafer, and the plurality of chip structures 12 are fixed on the first substrate 10 by a chip-to-wafer bonding (D2W) process. However, the present invention is not limited thereto, and the first substrate 10 may also be a substrate formed of ceramic, glass, inorganic material or any other appropriate material.

[0049] like Figure 1 As shown, in one embodiment, a first bump 111 and a first interlayer dielectric layer 11 formed around the first bump 111 are disposed on a side of the first substrate 10 opposite to the chip structure 12, and a surface of the first bump 111 is exposed outside the first interlayer dielectric layer 11. In some embodiments, a first interconnect structure 112 is further formed in the first interlayer dielectric layer 11, and the first interconnect structure 112 and the first bump 111 are electrically connected.

[0050] Figure 1 The first interconnect structure 112 shown in the figure is 2 layers, but not limited thereto, the number of the first interconnect structure 112 can be 1 layer or more layers, for example, 3 layers, 4 layers, 5 layers or more, and two adjacent first interconnect structures 112 can be electrically connected by a conductive plug.

[0051] There are multiple chip structures 12, and multiple chip structures 12 are discretely arranged on the first substrate 10. Multiple chip structures 12 may include the same or different electronic components and have the same or different functions. At least some of the chip structures 12 are functional chips with corresponding circuits, and the functional chips include non-volatile memory (such as NOR flash memory or NAND flash memory, etc.), random access memory, etc., or other types of active devices or passive devices. Exemplarily, at least one chip structure 12 is a high bandwidth memory (HBM) chip or an image signal processor (ISP) chip. Optionally, some chip structures 12 can be filler chips, which are used to adjust the size mismatch and uneven spacing between functional chips. The number and arrangement of the chip structures 12 can be set according to the function of the three-dimensional integrated device.

[0052] In actual operation, the chip structure 12 can be manufactured by a wafer-level semiconductor process and obtained by cutting the wafer. For example, the chip structure 12 can be a single-layer chip obtained by making a single wafer, or it can be a chip stack obtained by a three-dimensional integration process. For example, the chip structure 12 can be a chip stack composed of 2, 3, 4, 5, 10, a dozen, or dozens of chips stacked in sequence in a direction perpendicular to the first substrate 10, and two adjacent chips among the multiple chips are bonded to each other.

[0053] In actual operation, the plurality of chip structures 12 and the first substrate 10 may be bonded together by hybrid bonding. Figure 1As shown, in some embodiments, a second bump 131 and a second interlayer dielectric layer 13 formed around the second bump 131 are formed on one side of the chip structure 12 adjacent to the first substrate 10, a second interconnect structure 132 is further provided in the second interlayer dielectric layer 13, and the second bump 131 is electrically connected to the second interconnect structure 132; the surface of the second bump 131 is exposed outside the second interlayer dielectric layer 13, and the electrical connection between the first substrate 10 and the chip structure 12 is achieved by respectively bonding the second bump 131 and the second interlayer dielectric layer 13 of the chip structure 12 to the first bump 111 and the first interlayer dielectric layer 11 of the first substrate 10.

[0054] However, it is not limited to this. In some embodiments, other bonding methods that can achieve electrical connection between the first substrate 10 and the chip structure 12 can be applied in the embodiments of the present disclosure. The specific method can be selected according to actual conditions and is not specifically limited here.

[0055] In some embodiments, the material of the first interlayer dielectric layer 11 and the second interlayer dielectric layer 13 includes one or a combination of oxides, nitrides, oxynitrides, etc.; the material of the first bump 111 and the second bump 131 includes a conductive material, and the conductive material includes but is not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide or any combination thereof.

[0056] like Figure 1 As shown, multiple chip structures 12 are separately arranged on the first substrate 10, the gap 14 is an open area outside the multiple chip structures 12, and the second substrate 17 is located above the multiple chip structures 12 and does not occupy the area where the gap 14 is located. Therefore, the gap 14 constitutes a cavity that surrounds the multiple chip structures 12 and dissipates heat from the side thereof, so that the heat generated by the chip structure 12 when working can be quickly dissipated, so that the side heat dissipation efficiency of the chip structure 12 can be improved. In some embodiments, the gap 14 can be filled with a circulating heat-conducting gas or heat-conducting liquid to further improve the heat dissipation efficiency of the chip structure 12.

[0057] At the same time, in the embodiment of the present disclosure, multiple first groove patterns T1 are arranged one by one above the multiple chip structures 12. The first groove pattern T1 enhances the heat dissipation efficiency of the upper surface of the chip structure 12. Subsequently, the first groove pattern T1 can be filled with circulating heat-conducting gas or heat-conducting liquid to further improve the heat dissipation efficiency of the chip structure 12.

[0058] In some embodiments, the material of the second substrate 17 includes but is not limited to silicon, for example, the second substrate 17 may be a silicon wafer. However, the second substrate 17 may also be made of other known materials with good thermal conductivity.

[0059] Figure 2and Figure 3 The arrangement of the four chip structures 12 and the cross-sectional shapes of the four first groove patterns T1 respectively corresponding to the four chip structures 12 are shown, wherein the four chip structures 12 respectively include a first chip structure 121, a second chip structure 122, a third chip structure 123 and a fourth chip structure 124. Here, the first groove pattern T1 corresponding to the chip structure 12 refers to the first groove pattern T1 disposed above the chip structure 12.

[0060] It should be noted that Figure 2 and Figure 3 The number and arrangement of the chip structures 12 and the cross-sectional shape of the first groove pattern T1 are only examples and are not intended to limit the present disclosure. In fact, the number of the chip structures 12 may be more or less, and the chip structures 12 may have any other arrangement.

[0061] like Figure 2 As shown, in some embodiments, the first groove pattern T1 may include a plurality of sub-grooves T11, the plurality of sub-grooves T11 may extend in a straight line, and the plurality of sub-grooves T11 may be arranged side by side along the first direction and / or the second direction, and the plurality of sub-grooves T11 in any first groove pattern T1 may be spaced apart from each other, or may be interconnected, or may be partially spaced apart and partially interconnected. For example:

[0062] Referring to the first groove pattern T1 corresponding to the first chip structure 121 and the fourth chip structure 124, the first groove pattern T1 may include a plurality of sub-grooves T11 extending along the first direction and arranged along the second direction; referring to the first groove pattern T1 corresponding to the third chip structure 123, the first groove pattern T1 may also include a plurality of sub-grooves T11 arranged along the first direction and a plurality of sub-grooves T11 arranged along the second direction, and the plurality of sub-grooves T11 arranged along the first direction and the plurality of sub-grooves T11 arranged along the second direction are cross-connected to form a grid-like first groove pattern T1, which can achieve a better heat dissipation effect than a plurality of sub-grooves T11 arranged at intervals. Here, the first direction and the second direction are parallel to the plane of the second substrate 17 and are perpendicular or oblique to each other.

[0063] However, the first groove pattern T1 may further include a sub-groove T11, and the sub-groove T11 may extend in a straight line and / or a curve along any direction on the second substrate 17. Figure 2 In the first groove pattern T1 corresponding to the second chip structure 122, in some embodiments, the cross-sectional shape of the first groove pattern T1 along the direction parallel to the second substrate 17 can be a zigzag shape. However, it is not limited thereto, and the cross-sectional shape of the first groove pattern T1 along the direction parallel to the second substrate 17 can also be a wave shape, a U-shaped shape, a ring shape, etc.

[0064] Figure 2 The cross-sectional shapes of the first groove pattern T1 shown in the figure along the direction parallel to the second substrate 17 are all composed of regular rectangles. However, the cross-sectional shapes of the first groove pattern T1 along the direction parallel to the second substrate 17 can also be polygons such as triangles, pentagons, hexagons, as well as circles, ellipses, and irregular shapes, or a combination thereof.

[0065] In actual operation, first, the heat dissipation requirements of the multiple chip structures 12 can be obtained respectively, and the densities of the multiple first groove patterns T1 corresponding to the multiple chip structures 12 can be determined respectively according to the heat dissipation requirements of the multiple chip structures 12; then, after determining the density of the multiple first groove patterns T1, the cross-sectional shapes of the multiple first groove patterns T1 along the direction parallel to the second substrate 17 can be determined respectively according to the density of the multiple first groove patterns T1; then, the corresponding first groove pattern T1 can be formed on the second substrate 17 according to the cross-sectional shape.

[0066] In some embodiments, determining the density of the first groove pattern T1 corresponding to the chip structure 12 may include determining an average density of the first groove pattern T1 , where the average density of the first groove pattern T1 refers to a ratio of an area of ​​the first groove pattern T1 located above the chip structure 12 to an area of ​​the chip structure 12 .

[0067] It can be understood that the larger the total area of ​​the first groove pattern T1 in the second substrate 17, the better the heat dissipation effect on the chip structure 12; however, the total area of ​​the first groove pattern T1 cannot be too large, which will affect the mechanical strength of the second substrate 17 and its bonding strength with the chip structure 12, thereby affecting the stability of the packaging structure. In the embodiment of the present disclosure, before forming the first groove pattern T1, the density of the first groove pattern T1 corresponding to the multiple chip structures 12 is determined in advance according to the heat dissipation requirements of the multiple chip structures 12. For example, when the chip structure 12 generates a large amount of heat during operation and has a high heat dissipation requirement, the density of the first groove pattern T1 located above the chip structure 12 can be set to be larger. When the chip structure 12 generates a small amount of heat during operation and has a low heat dissipation requirement, the density of the first groove pattern T1 located above the chip structure 12 can be set to be smaller. Then, the shape of the first groove pattern T1 is designed according to the density. In this way, the total area occupied by the first groove pattern T1 on the second substrate 17 can be reasonably allocated. On the one hand, the heat dissipation requirements of the chip structure 12 can be met. On the other hand, the area ratio of the first groove pattern T1 can be controlled, thereby improving the heat dissipation efficiency of the chip structure 12 while improving the mechanical strength of the second substrate 17 and the bonding strength with the chip structure 12.

[0068] In some embodiments, at least two chip structures 12 among the plurality of chip structures 12 have different heat dissipation requirements, and the cross-sectional shapes of the first groove patterns T1 above at least two chip structures 12 among the plurality of chip structures 12 along the direction parallel to the second substrate 17 are different. For example, Figure 2 The first chip structure 121 generates a large amount of heat when working and has a high heat dissipation requirement, while the fourth chip structure 124 generates a small amount of heat when working and has a low heat dissipation requirement. The arrangement of the multiple sub-grooves T1 of the first groove pattern T1 corresponding to the first chip structure 121 can be set to be denser, and the arrangement of the multiple sub-grooves T1 of the first groove pattern T1 corresponding to the fourth chip structure 124 can be set to be sparser. In addition, this can also be achieved by adjusting the width of each sub-groove T11.

[0069] like Figure 4 As shown, the chip structure 12 includes at least one heat spot 120, and the heat spot 120 is an area in the chip structure where the operating temperature is greater than or equal to a predetermined reference temperature; the density of the portion of the first groove pattern T1 located above the heat spot 120 is greater than the density of the portion of the first groove pattern T1 located above other areas of the chip structure 12 except the heat spot 120.

[0070] Here, the density of the portion of the first groove pattern T1 located above the heat point 120 refers to the ratio of the area of ​​the portion of the first groove pattern T1 located above the heat point 120 to the area of ​​the heat point 120; the density of the portion of the first groove pattern T1 located above other regions of the chip structure 12 except the heat point 120 refers to the ratio of the area of ​​the first groove pattern T1 located above other regions to the area of ​​other regions of the chip structure 12. It can be understood that when the chip structure 12 is working, the heat point 120 generates more heat and has a higher heat dissipation requirement than other regions. Arranging a first groove pattern T1 with a higher density above the heat point 120 helps to improve the overall heat dissipation effect of the chip structure 12.

[0071] In actual operation, respectively obtaining the heat dissipation requirements of the multiple chip structures 12 may include obtaining the overall heat dissipation requirement of each chip structure 12 in the multiple chip structures 12 and the heat dissipation requirement of the heat spot 120; in the case where the chip structure 12 has a heat spot 120, respectively determining the density of the multiple first groove patterns T1 corresponding to the multiple chip structures 12 may include determining the density of the portion of the first groove pattern T1 located above the heat spot 120 in each first groove pattern T1, and the density of the portion of the first groove pattern T1 located above other areas except the heat spot 120.

[0072] like Figure 1 and Figure 3As shown, in some embodiments, the packaging structure further includes: a second groove pattern T2, located on a side of the second substrate 17 opposite to the first substrate 10, and the second groove pattern T2 is located above the gap 14 and communicates with the gap 14. In this way, the gap 14 and the second groove pattern T2 jointly dissipate heat from the side of the chip structure 12, increasing the volume of the cavity between the first substrate 10 and the second substrate 17, thereby further improving the heat dissipation efficiency of the chip structure 12.

[0073] like Figure 2 and Figure 3 As shown, in some embodiments, the first groove pattern T1 and the gap 14 are isolated from each other. In the case of having a second groove T2, the first groove pattern T1 is also isolated from the second groove pattern T2. ​​The first groove pattern T1 and the second groove pattern T2 are independently circulated and are not connected to each other.

[0074] However, it is not limited thereto. In some other embodiments of the present disclosure, at least one first groove pattern T1 is connected to the gap 14. In the case of a second groove T2, the first groove pattern T1 is also connected to the second groove pattern T2. ​​In this way, the heat dissipation effect of the first groove pattern T1 connected to the gap 14 on the chip structure 12 can be further improved. Here, when the first groove pattern T1 includes a plurality of discrete sub-grooves T11, the plurality of sub-grooves T11 can all be connected to the gap 14.

[0075] Specifically, Figure 5 As shown, the first groove pattern T1 can extend to both sides of the chip structure 12 to the top of the gap 14, so as to achieve communication with the gap 14, or, in the case where there is a second groove pattern T2 above the gap 14, the plurality of sub-grooves T11 in the first groove pattern T1 can extend to both sides of the chip structure 12 to communicate with the second groove pattern T2, and then communicate with the gap 14; or, as shown Figure 6 As shown, the width of the second groove pattern T2 can also be increased so that the second groove pattern T2 extends toward the first groove pattern T1 and communicates with the first groove pattern T1; but not limited to this, a connecting groove can also be set between the first groove pattern T1 and the gap 14 or the second groove pattern T2 to connect the first groove pattern T1 with the gap 14.

[0076] In some embodiments, the plurality of first groove patterns T1 and the gap 14 are connected to each other. Specifically, the first groove patterns T1 can be connected to the gap 14 respectively, so that the plurality of first groove patterns T1 and the gap 14 are connected to each other. The connection method of the first groove pattern T1 and the gap 14 is as described above, so that the plurality of first groove patterns T1 and the gap 14 (or the second groove pattern T2 and the gap 14) can form an integrated circulation microfluidic channel to further improve the heat dissipation efficiency of the chip structure 12, and the integrated circulation microfluidic channel can be subsequently filled with circulating heat-conducting gas or heat-conducting liquid.

[0077] like Figure 1 As shown, in some embodiments, the packaging structure further includes: a first dielectric layer 15, covering the sidewalls of the chip structure 12 and the bottom surface of the gap 14; and a second dielectric layer 16, covering the upper surface of the chip structure 12 and the first dielectric layer 15. The first dielectric layer 15 and the second dielectric layer 16 are used to protect the chip structure 12, and the second substrate 17 can be bonded to the portion of the second dielectric layer 16 covering the upper surface of the chip structure 12 to achieve a fixed connection with the chip structure 12. In some embodiments, the second substrate 17 and the second dielectric layer 16 can be bonded to each other using a process such as melt bonding.

[0078] In actual operation, the material of the first dielectric layer 15 includes but is not limited to nitride, such as silicon nitride; the material of the second dielectric layer 16 includes but is not limited to oxide, such as silicon oxide.

[0079] like Figure 1 As shown, in some embodiments, the package structure further includes: a plurality of discrete pads 21, which are discretely arranged on a side of the first substrate 10 away from the chip structure 12; a third dielectric layer 19, which is located between adjacent pads 21; and a plurality of conductive vias 18, which penetrate the first substrate 10 and are respectively electrically connected to the first interconnect structure 112 and the pads 21. Solder balls can be subsequently formed on the pads 21, and the first substrate 10 can be fixed on the package substrate (e.g., a printed circuit board (PCB)) through the solder balls. The conductive vias 18 are used to realize vertical interconnection between the package substrate, the first substrate 10, and the chip structure 12.

[0080] The present disclosure also provides a method for manufacturing a packaging structure. Figure 7 As shown, the method comprises the following steps:

[0081] Step S101, providing a first substrate, and forming a plurality of spaced-apart chip structures and gaps surrounding the chip structures on the first substrate;

[0082] Step S102, providing a second substrate, and forming a plurality of first groove patterns on a surface of one side of the second substrate;

[0083] Step S103: bonding the side of the second substrate with the first groove pattern to the side of the plurality of chip structures away from the first substrate, and the plurality of first groove patterns are disposed above the plurality of chip structures in a one-to-one correspondence.

[0084] The manufacturing method of the packaging structure of the embodiment of the present disclosure is further described in detail below with reference to the accompanying drawings.

[0085] First, execute step S101, such as Figure 8 As shown, a first substrate 10 is provided, and a plurality of spaced-apart chip structures 12 and gaps 14 surrounding the chip structures 12 are formed on the first substrate 10 .

[0086] The material of the first substrate 10 may be a semiconductor material, such as silicon. More specifically, the first substrate 10 may be a silicon wafer, and the plurality of chip structures 12 are fixed on the first substrate 10 by a chip-to-wafer bonding (D2W) process. However, the first substrate 10 is not limited thereto, and may also be a substrate formed of ceramic, glass, inorganic material or any other appropriate material.

[0087] In one embodiment, a first bump 111 and a first interlayer dielectric layer 11 formed around the first bump 111 are disposed on a side of the first substrate 10 opposite to the chip structure 12, and a surface of the first bump 111 is exposed outside the first interlayer dielectric layer 11. In some embodiments, a first interconnect structure 112 is further formed in the first interlayer dielectric layer 11, and the first interconnect structure 112 and the first bump 111 are electrically connected.

[0088] Figure 8 The first interconnect structure 112 shown in the figure is 2 layers, but not limited thereto, the number of the first interconnect structure 112 can be 1 layer or more layers, for example, 3 layers, 4 layers, 5 layers or more, and two adjacent first interconnect structures 112 can be electrically connected by a conductive plug.

[0089] There are multiple chip structures 12, and multiple chip structures 12 are discretely arranged on the first substrate 10. Multiple chip structures 12 may include the same or different electronic components and have the same or different functions. At least some of the chip structures 12 are functional chips with corresponding circuits, and the functional chips include non-volatile memory (such as NOR flash memory or NAND flash memory, etc.), random access memory, etc., or other types of active devices or passive devices. Exemplarily, at least one chip structure 12 is a high bandwidth memory (HBM) chip or an image signal processor (ISP) chip. Optionally, some chip structures 12 can be filler chips, which are used to adjust the size mismatch and uneven spacing between functional chips. The number and arrangement of the chip structures 12 can be set according to the function of the three-dimensional integrated device.

[0090] In actual operation, the chip structure 12 can be manufactured by a wafer-level semiconductor process and obtained by cutting the wafer. For example, the chip structure 12 can be a single-layer chip obtained by making a single wafer, or it can be a chip stack obtained by a three-dimensional integration process. For example, the chip structure 12 can be a chip stack composed of 2, 3, 4, 5, 10, a dozen, or dozens of chips stacked in sequence in a direction perpendicular to the first substrate 10, and two adjacent chips among the multiple chips are bonded to each other.

[0091] In actual operation, the plurality of chip structures 12 and the first substrate 10 may be bonded together by hybrid bonding. Figure 1 As shown, in some embodiments, a second bump 131 and a second interlayer dielectric layer 13 formed around the second bump 131 are formed on one side of the chip structure 12 adjacent to the first substrate 10, a second interconnect structure 132 is further provided in the second interlayer dielectric layer 13, and the second bump 131 is electrically connected to the second interconnect structure 132; the surface of the second bump 131 is exposed outside the second interlayer dielectric layer 13, and the electrical connection between the first substrate 10 and the chip structure 12 is achieved by respectively bonding the second bump 131 and the second interlayer dielectric layer 13 of the chip structure 12 to the first bump 111 and the first interlayer dielectric layer 11 of the first substrate 10.

[0092] However, it is not limited to this. In some embodiments, other bonding methods that can achieve electrical connection between the first substrate 10 and the chip structure 12 can be applied in the embodiments of the present disclosure. The specific method can be selected according to actual conditions and is not specifically limited here.

[0093] In some embodiments, the material of the first interlayer dielectric layer 11 and the second interlayer dielectric layer 13 includes one or a combination of oxides, nitrides, oxynitrides, etc.; the material of the first bump 111 and the second bump 131 includes a conductive material, and the conductive material includes but is not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide or any combination thereof.

[0094] Next, execute step S102, such as Fig.12 and Fig.13 As shown, a second substrate 17 is provided, and a plurality of first groove patterns T1 are formed on one side surface of the second substrate 17 .

[0095] In some embodiments, the material of the second substrate 17 includes but is not limited to silicon, for example, the second substrate 17 may be a silicon wafer. However, the second substrate 17 may also be made of other known materials with good thermal conductivity.

[0096] In actual operation, the first groove pattern T1 may be formed by one or a combination of a mechanical scribing process, a laser scribing process, or a photolithography process, etc. The depths of the plurality of first groove patterns T1 may be the same or different.

[0097] Next, execute step S103, such as Fig.14 As shown, the side of the second substrate 17 formed with the first groove pattern T1 is bonded to the side of the plurality of chip structures 12 away from the first substrate 10 , and the plurality of first groove patterns T1 are disposed above the plurality of chip structures 12 in a one-to-one correspondence.

[0098] like Figures 9 to 11 As shown, in some embodiments, after forming a plurality of spaced chip structures 12 on the first substrate 10 and before bonding the second substrate 17 to the plurality of chip structures 12, the method further includes:

[0099] A first dielectric layer 15 is formed, and the first dielectric layer 15 covers the surfaces of the plurality of chip structures 12 and the bottom of the gap 14 (eg Fig. 9 );

[0100] A thinning process is performed on the side of the chip structure 12 away from the first substrate 10 to remove the chip structure 12 of a predetermined thickness and the first dielectric layer 15 (eg, Fig.10 );

[0101] A second dielectric layer 16 is formed, and the second dielectric layer 16 covers the thinned upper surface of the chip structure 12 and the first dielectric layer 15 (such as Fig.11 ).

[0102] The first dielectric layer 15 and the second dielectric layer 16 can be formed by one or a combination of thin film deposition processes such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc. The material of the first dielectric layer 15 includes but is not limited to nitride, such as silicon nitride, which is used to protect the chip structure 12 and the first interlayer dielectric layer 11 when the chip structure 12 is thinned; the material of the second dielectric layer 16 includes but is not limited to oxide, such as silicon oxide, which is used to protect the chip structure 12.

[0103] In some embodiments, the second substrate 17 can be fixedly connected to the chip structure 12 by bonding to a portion of the second dielectric layer 16 covering the upper surface of the chip structure 12. In some embodiments, the second substrate 17 and the second dielectric layer 16 can be bonded by a process such as melting.

[0104] In the disclosed embodiment, multiple chip structures 12 are separately arranged on the first substrate 10, the gap 14 is an open area outside the multiple chip structures 12, and the second substrate 17 is located above the multiple chip structures 12 and does not occupy the area where the gap 14 is located. Therefore, the gap 14 constitutes a cavity surrounding the multiple chip structures 12 and dissipating heat from the side thereof, so that the heat generated by the chip structure 12 when working can be quickly dissipated, so that the side heat dissipation efficiency of the chip structure 12 can be improved. In some embodiments, the gap 14 can be filled with circulating heat-conducting gas or heat-conducting liquid to further improve the heat dissipation efficiency of the chip structure 12.

[0105] At the same time, in the embodiment of the present disclosure, multiple first groove patterns T1 are arranged one by one above the multiple chip structures 12. The first groove pattern T1 enhances the heat dissipation efficiency of the upper surface of the chip structure 12. Subsequently, the first groove pattern T1 can be filled with circulating heat-conducting gas or heat-conducting liquid to further improve the heat dissipation efficiency of the chip structure 12.

[0106] Figure 2 and Figure 3 The arrangement of four chip structures 12 and the cross-sectional shapes of four first groove patterns T1 respectively corresponding to the four chip structures 12 are shown, wherein the four chip structures 12 respectively include a first chip structure 121, a second chip structure 122, a third chip structure 123 and a fourth chip structure 124. Here, the first groove pattern T1 corresponding to the chip structure 12 refers to the first groove pattern T1 disposed above the chip structure 12.

[0107] It should be noted that Figure 2 and Figure 3 The number and arrangement of the chip structures 12 and the cross-sectional shape of the first groove pattern T1 are only examples and are not intended to limit the present disclosure. In fact, the number of the chip structures 12 may be more or less, and the chip structures 12 may have any other arrangement.

[0108] like Figure 2 As shown, in some embodiments, the first groove pattern T1 may include a plurality of sub-grooves T11, the plurality of sub-grooves T11 may extend in a straight line, and the plurality of sub-grooves T11 may be arranged side by side along the first direction and / or the second direction, and the plurality of sub-grooves T11 in any first groove pattern T1 may be spaced apart from each other, or may be interconnected, or may be partially spaced apart and partially interconnected. For example:

[0109] Referring to the first groove pattern T1 corresponding to the first chip structure 121 and the fourth chip structure 124, the first groove pattern T1 may include a plurality of sub-grooves T11 extending along the first direction and arranged along the second direction; referring to the first groove pattern T1 corresponding to the third chip structure 123, the first groove pattern T1 may also include a plurality of sub-grooves T11 arranged along the first direction and a plurality of sub-grooves T11 arranged along the second direction, and the plurality of sub-grooves T11 arranged along the first direction and the plurality of sub-grooves T11 arranged along the second direction are cross-connected to form a grid-like first groove pattern T1, which can achieve a better heat dissipation effect than a plurality of sub-grooves T11 arranged at intervals. Here, the first direction and the second direction are parallel to the plane of the second substrate 17 and are perpendicular or oblique to each other.

[0110] However, the first groove pattern T1 may further include a sub-groove T11, and the sub-groove T11 may extend in a straight line and / or a curve along any direction on the second substrate 17. Figure 2 In the first groove pattern T1 corresponding to the second chip structure 122, in some embodiments, the cross-sectional shape of the first groove pattern T1 along the direction parallel to the second substrate 17 can be a zigzag shape. However, it is not limited thereto, and the cross-sectional shape of the first groove pattern T1 along the direction parallel to the second substrate 17 can also be a wave shape, a U-shaped shape, a ring shape, etc.

[0111] Figure 2 The cross-sectional shapes of the first groove pattern T1 shown in the figure along the direction parallel to the second substrate 17 are all composed of regular rectangles. However, the cross-sectional shapes of the first groove pattern T1 along the direction parallel to the second substrate 17 can also be polygons such as triangles, pentagons, hexagons, as well as circles, ellipses, and irregular shapes, or a combination thereof.

[0112] In some embodiments, before forming a plurality of first groove patterns T1 on a side surface of the second substrate 17, the method further includes: obtaining heat dissipation requirements of the plurality of chip structures 12 respectively, and determining the density of the plurality of first groove patterns T1 corresponding to the plurality of chip structures 12 respectively according to the heat dissipation requirements of the plurality of chip structures 12. In some embodiments, after determining the density of the plurality of first groove patterns T1, the method further includes: determining the cross-sectional shape of the plurality of first groove patterns T1 along a direction parallel to the second substrate 17 respectively according to the density of the plurality of first groove patterns T1; and then, forming the corresponding first groove pattern T1 on the second substrate 17 according to the cross-sectional shape.

[0113] In some embodiments, determining the density of the first groove pattern T1 corresponding to the chip structure 12 may include determining an average density of the first groove pattern T1 , where the average density of the first groove pattern T1 refers to a ratio of an area of ​​the first groove pattern T1 located above the chip structure 12 to an area of ​​the chip structure 12 .

[0114] It can be understood that the larger the total area of ​​the first groove pattern T1 in the second substrate 17, the better the heat dissipation effect on the chip structure 12; however, the total area of ​​the first groove pattern T1 cannot be too large, which will affect the mechanical strength of the second substrate 17 and its bonding strength with the chip structure 12, thereby affecting the stability of the packaging structure. In the embodiment of the present disclosure, before forming the first groove pattern T1, the density of the first groove pattern T1 corresponding to the multiple chip structures 12 is determined in advance according to the heat dissipation requirements of the multiple chip structures 12. For example, when the chip structure 12 generates a large amount of heat during operation and has a high heat dissipation requirement, the density of the first groove pattern T1 located above the chip structure 12 can be set to be larger. When the chip structure 12 generates a small amount of heat during operation and has a low heat dissipation requirement, the density of the first groove pattern T1 located above the chip structure 12 can be set to be smaller. Then, the shape of the first groove pattern T1 is designed according to the density. In this way, the total area occupied by the first groove pattern T1 on the second substrate 17 can be reasonably allocated. On the one hand, the heat dissipation requirements of the chip structure 12 can be met. On the other hand, the area ratio of the first groove pattern T1 can be controlled, thereby improving the heat dissipation efficiency of the chip structure 12 while improving the mechanical strength of the second substrate 17 and the bonding strength with the chip structure 12.

[0115] In some embodiments, at least two chip structures 12 among the plurality of chip structures 12 have different heat dissipation requirements, and the cross-sectional shapes of the first groove patterns T1 above at least two chip structures 12 among the plurality of chip structures 12 along the direction parallel to the second substrate 17 are different. For example, Figure 2 The first chip structure 121 generates a large amount of heat when working and has a high heat dissipation requirement, while the fourth chip structure 124 generates a small amount of heat when working and has a low heat dissipation requirement. The arrangement of the multiple sub-grooves T1 of the first groove pattern T1 corresponding to the first chip structure 121 can be set to be denser, and the arrangement of the multiple sub-grooves T1 of the first groove pattern T1 corresponding to the fourth chip structure 124 can be set to be sparser. In addition, this can also be achieved by adjusting the width of each sub-groove T11.

[0116] like Figure 4 As shown, the chip structure 12 includes at least one heat spot 120, and the heat spot 120 is an area in the chip structure where the operating temperature is greater than or equal to a predetermined reference temperature; the density of the portion of the first groove pattern T1 located above the heat spot 120 is greater than the density of the portion of the first groove pattern T1 located above other areas of the chip structure 12 except the heat spot 120.

[0117] Here, the density of the portion of the first groove pattern T1 located above the heat point 120 refers to the ratio of the area of ​​the portion of the first groove pattern T1 located above the heat point 120 to the area of ​​the heat point 120; the density of the portion of the first groove pattern T1 located above other regions of the chip structure 12 except the heat point 120 refers to the ratio of the area of ​​the portion of the first groove pattern T1 located above other regions to the area of ​​other regions of the chip structure 12. It can be understood that when the chip structure 12 is working, the heat point 120 generates more heat and has a higher heat dissipation requirement than other regions. Arranging a first groove pattern T1 with a higher density above the heat point 120 helps to improve the overall heat dissipation effect of the chip structure 12.

[0118] In some embodiments, respectively obtaining the heat dissipation requirements of the plurality of chip structures 12 may include obtaining the overall heat dissipation requirement of each chip structure 12 in the plurality of chip structures 12 and the heat dissipation requirement of the heat spot 120; in the case where the chip structure 12 has a heat spot 120, respectively determining the density of the plurality of first groove patterns T1 corresponding to the plurality of chip structures 12 may include determining the density of a portion of the first groove patterns T1 located above the heat spot 120 in each first groove pattern T1, and the density of a portion of the first groove patterns T1 located above other areas except the heat spot 120.

[0119] See again Fig.13 In some embodiments, the method further includes: forming a second groove pattern T2 on the same side surface of the second substrate 17 where the first groove pattern T1 is formed; then, Fig.14 As shown, after the second substrate 17 is bonded to the plurality of chip structures 12, the second groove pattern 17 is located above the gap 14 and communicates with the gap 14. In this way, the gap 14 and the second groove pattern T2 jointly dissipate heat from the side of the chip structure 12, increasing the volume of the cavity between the first substrate 10 and the second substrate 17, thereby further improving the heat dissipation efficiency of the chip structure 12.

[0120] In actual operation, the first groove pattern T1 and the second groove pattern T2 may be formed by using one or a combination of a mechanical scribing process, a laser scribing process, or a photolithography process.

[0121] like Figure 2 and Figure 3 As shown, in some embodiments, the first groove pattern T1 and the gap 14 are isolated from each other. In the case of having the second groove pattern T2, the first groove pattern T1 is also isolated from the second groove pattern T2. ​​The first groove pattern T1 and the second groove pattern T2 circulate independently and are not connected to each other.

[0122] However, it is not limited thereto. In some other embodiments of the present disclosure, at least one first groove pattern T1 is connected to the gap 14. When there is also a second groove pattern T2, the first groove pattern T1 is also connected to the second groove pattern T2. ​​In this way, the heat dissipation effect of the first groove pattern T1 connected to the gap 14 on the chip structure 12 can be further improved. Here, when the first groove pattern T1 includes a plurality of discrete sub-grooves T11, the plurality of sub-grooves T11 can all be connected to the gap 14.

[0123] Specifically, Figure 5 As shown, the first groove pattern T1 can extend to both sides of the chip structure 12 to the top of the gap 14, so as to achieve communication with the gap 14, or, in the case where there is a second groove pattern T2 above the gap 14, the plurality of sub-grooves T11 in the first groove pattern T1 can extend to both sides of the chip structure 12 to communicate with the second groove pattern T2, and then communicate with the gap 14; or, as shown Figure 6 As shown, the width of the second groove pattern T2 can also be increased so that the second groove pattern T2 extends toward the first groove pattern T1 and communicates with the first groove pattern T1; but not limited to this, a connecting groove can also be set between the first groove pattern T1 and the gap 14 or the second groove pattern T2 to connect the first groove pattern T1 with the gap 14.

[0124] In some embodiments, the plurality of first groove patterns T1 and the gap 14 are connected to each other. Specifically, the first groove patterns T1 can be connected to the gap 14 respectively, so that the plurality of first groove patterns T1 and the gap 14 are connected to each other. The connection method of the first groove pattern T1 and the gap 14 is as described above, so that the plurality of first groove patterns T1 and the gap 14 (or the second groove pattern T2 and the gap 14) can form an integrated circulation microfluidic channel to further improve the heat dissipation efficiency of the chip structure 12, and the integrated circulation microfluidic channel can be subsequently filled with circulating heat-conducting gas or heat-conducting liquid.

[0125] Then, if Figure 1 As shown, after the second substrate 17 and the chip structure 12 are bonded and connected, the method further includes: performing a thinning process on a side of the first substrate 10 away from the chip structure 12; etching from the surface of the first substrate 10 after the thinning process to the inside of the first substrate 10 to form a through hole (not marked) exposing the first interconnect structure 112, and filling the through hole with a conductive material to form a conductive through hole 18; forming a third dielectric layer 19 on a side of the first substrate 10 away from the chip structure 12, the third dielectric layer 19 covers the first substrate 10 and the conductive through hole 18, and forming a plurality of pads 21 electrically connected to the conductive through hole 18 in the third dielectric layer 19, the plurality of pads 21 are separately arranged, and the third dielectric layer 19 is located between adjacent pads 21.

[0126] It should be noted that before performing the thinning process on the first substrate 10 , the package structure can be turned over so that the surface of the first substrate 10 away from the first chip structure 12 faces upward, which facilitates the thinning process on the first substrate 10 .

[0127] The conductive via 18 passes through the first substrate 10 and electrically connects the first interconnect structure 112 and the pad 21. A solder ball can be subsequently formed on the pad 21, and the first substrate 10 can be fixed on a packaging substrate (e.g., a printed circuit board (PCB)) through the solder ball. The conductive via 18 is used to achieve vertical interconnection between the packaging substrate, the first substrate 10, and the chip structure 12.

[0128] It should be noted that the above is only a preferred embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present disclosure should be included in the scope of protection of this application.

Claims

1. A packaging structure, characterized in that: include: A first substrate, a plurality of chip structures spaced apart from each other on the first substrate, and gaps surrounding the plurality of chip structures; A second substrate, bonded to and connected to a side of the plurality of chip structures away from the first substrate; A side of the second substrate opposite to the first substrate has a plurality of first groove patterns distributed at intervals, and the plurality of first groove patterns are arranged above the plurality of chip structures in a one-to-one correspondence.

2. The packaging structure according to claim 1, characterized in that: At least one of the first groove patterns communicates with the gap.

3. The packaging structure according to claim 1, characterized in that: The chip structure includes at least one heat spot, which is an area in the chip structure where the operating temperature is greater than or equal to a predetermined reference temperature; the density of the portion of the first groove pattern located above the heat spot is greater than the density of the portion of the first groove pattern located above other areas of the chip structure except the heat spot.

4. The packaging structure according to claim 1, characterized in that: The cross-sectional shapes of the first groove patterns above at least two of the plurality of chip structures along a direction parallel to the plane of the second substrate are different.

5. The packaging structure according to claim 1, characterized in that: The packaging structure further includes: a second groove pattern located on a side of the second substrate opposite to the first substrate, the second groove pattern being located above the gap and communicating with the gap.

6. The packaging structure according to claim 1, characterized in that: The packaging structure further includes: A first dielectric layer, covering the sidewalls of the chip structure and the bottom surface of the gap; The second dielectric layer covers the upper surface of the chip structure and the first dielectric layer.

7. A method for manufacturing a packaging structure, characterized in that: include: Providing a first substrate, and forming a plurality of spaced-apart chip structures and gaps surrounding the chip structures on the first substrate; Providing a second substrate, and forming a plurality of first groove patterns on a side surface of the second substrate; The side of the second substrate formed with the first groove pattern is bonded and connected to the side of the plurality of chip structures away from the first substrate, and the plurality of first groove patterns are arranged above the plurality of chip structures in a one-to-one correspondence.

8. The manufacturing method according to claim 7, characterized in that: The method further includes: forming a second groove pattern on the same side surface of the second substrate as that on which the first groove pattern is formed; After the second substrate is bonded and connected to the plurality of chip structures in correspondence, the second groove pattern is located above the gap and communicated with the gap.

9. The manufacturing method according to claim 7, characterized in that: Before forming a plurality of first groove patterns on one side surface of the second substrate, the method further includes: respectively obtaining heat dissipation requirements of the plurality of chip structures; Densities of the plurality of first groove patterns corresponding to the plurality of chip structures are determined according to heat dissipation requirements of the plurality of chip structures.

10. The manufacturing method according to claim 7, characterized in that: After forming a plurality of chip structures spaced apart on the first substrate, and before bonding the second substrate to the plurality of chip structures accordingly, the method further includes: forming a first dielectric layer, wherein the first dielectric layer covers surfaces of the plurality of chip structures and the bottom of the gap; Performing a thinning process on a side of the chip structure away from the first substrate to remove a predetermined thickness of the chip structure and a first dielectric layer located on an upper surface and a portion of a sidewall of the chip structure; A second dielectric layer is formed, wherein the second dielectric layer covers the thinned upper surface of the chip structure and the first dielectric layer.

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