Laminated DBC planar power module

Abstract

The invention relates to the technical field of packaging, in particular to a laminated DBC planar power module which comprises an upper-layer DBC substrate assembly and a lower-layer DBC substrate assembly, the upper-layer DBC substrate assembly comprises an upper-bridge-arm upper-layer DBC substrate and a lower-bridge-arm upper-layer DBC substrate, the lower-layer DBC substrate assembly is provided with a direct-current connection area and a chip connection area, and the direct-current connection area is connected with the chip connection area. A gap is arranged between the direct current connection area and the chip connection area. The structure of the upper bridge arm and the structure of the lower bridge arm are arranged on the two DBC substrate assemblies respectively, the upper bridge arm chip and the lower bridge arm chip are arranged on the lower DBC substrate assembly, and the upper DBC substrate assembly is hollowed out, so that the chips can be connected with the upper DBC substrate assembly and the lower DBC substrate assembly in space, the overall size of the power module is reduced, and the size of the power module is reduced. The power density is improved, and a short commutation loop is realized. Through the layout mode, the advantages that the occupied tiling area is reduced, the design size is small, and the design freedom degree is high are achieved.

Description

Technical Field

[0001] The present invention relates to the field of packaging technology, and in particular to a laminated DBC planar power module. Background Art

[0002] Planar power module technology is an important research direction in the field of power electronics, especially in new energy applications such as electric vehicles. The core of this technology is to improve power density, heat dissipation efficiency and power conversion efficiency, and reduce operating temperature to meet the market's increasingly high performance requirements for power electronics devices.

[0003] Traditional power modules lay out the bridge arms, chips and gates on the same plane. This layout method will bring about problems such as occupying too much flat area, large design size and low design freedom. Summary of the invention

[0004] In view of this, the present invention provides a laminated DBC planar power module to solve the problems existing in the layout of the existing power module, such as occupying too much tile area, having a large design size and having low design freedom.

[0005] The present invention provides a laminated DBC planar power module, comprising:

[0006] An upper DBC substrate assembly and a lower DBC substrate assembly, wherein the upper DBC substrate assembly comprises an upper bridge arm upper DBC substrate and a lower bridge arm upper DBC substrate, and the lower DBC substrate assembly is provided with a DC connection area and a chip connection area, and a gap is provided between the DC connection area and the chip connection area;

[0007] An upper bridge arm chip, one end of which is connected to the lower DBC substrate assembly, and the other end is connected to the upper DBC substrate of the upper bridge arm, and the position of the upper DBC substrate of the upper bridge arm corresponding to the upper bridge arm chip is hollowed out;

[0008] A lower bridge arm chip, one end of which is connected to the chip connection area, and the other end is connected to the upper DBC substrate of the lower bridge arm, and the position of the upper DBC substrate of the lower bridge arm corresponding to the chip connection area is hollowed out;

[0009] The upper bridge arm upper layer DBC substrate is provided with an upper bridge arm chip gate connected to the upper bridge arm chip, and the lower bridge arm upper layer DBC substrate is provided with a lower bridge arm chip gate connected to the lower bridge arm chip.

[0010] The upper and lower bridge arm structures are respectively arranged on two layers of DBC substrate assemblies, and the upper bridge arm chip and the lower bridge arm chip are arranged on the lower DBC substrate assembly. By hollowing out the upper DBC substrate assembly, the chip can be spatially connected to the upper DBC substrate assembly and the lower DBC substrate assembly, respectively, thereby reducing the overall size of the power module, improving the power density, and achieving a shorter commutation loop. This layout method has the advantages of reducing the occupied tile area, having a relatively small design size, and having a relatively high degree of design freedom.

[0011] In an optional embodiment, the lower DBC substrate assembly comprises:

[0012] A first lower DBC substrate is located below the lower bridge arm upper DBC substrate, and the DC connection area and the chip connection area are arranged on the upper surface of the first lower DBC substrate;

[0013] A second lower DBC substrate is located below the upper DBC substrate of the upper bridge arm, and an upper surface of the second lower DBC substrate is connected to the bottom end of the upper bridge arm chip;

[0014] The DC connection area on the first lower DBC substrate is connected to the second lower DBC substrate. The first lower DBC substrate and the second lower DBC substrate can increase the current capacity of the power module, effectively improve the overall reliability of the power module, and increase the power density. The lower DBC substrate assembly is divided into two parts, and the area connected to the upper bridge arm chip and the area connected to the lower bridge arm chip are separated.

[0015] In an optional implementation, the DC connection area and the second lower DBC substrate are connected via a metal plate located above. Connecting the DC connection area to the upper bridge arm chip can increase the current carrying capacity of the power module via the metal plate.

[0016] In an optional embodiment, a first chip source connected to a DBC substrate is provided at the top of the upper bridge arm chip, and the lower surface of the first chip source connected to the DBC substrate is respectively connected to the top of the upper bridge arm chip and the upper surface of the upper bridge arm upper layer DBC substrate. The upper bridge arm chip located at the lower layer and the upper bridge arm upper layer DBC substrate located at the upper layer can be connected in spatial structure through the first chip source connected to the DBC substrate.

[0017] In an optional embodiment, the upper DBC substrate of the upper bridge arm is connected to the chip connection area through a metal connecting piece, and the lower surface of the metal connecting piece is connected to the upper surface of the upper DBC substrate of the upper bridge arm and the upper surface of the chip connection area respectively. The upper DBC substrate of the upper bridge arm and the chip connection area with a height difference can be connected through the metal connecting piece.

[0018] In an optional embodiment, a second chip source connected to a DBC substrate is provided at the top of the lower bridge arm chip, and the lower surface of the second chip source connected to the DBC substrate is respectively connected to the top of the lower bridge arm chip and the upper surface of the lower bridge arm upper DBC substrate.

[0019] In an optional embodiment, the upper DBC substrate assembly is divided into two groups, namely a first upper DBC substrate assembly and a second upper DBC substrate assembly, and the first upper DBC substrate assembly and the second upper DBC substrate assembly are arranged side by side to form a rectangular structure;

[0020] The lower layer DBC substrate assembly includes two groups, namely a first lower layer DBC substrate assembly and a second lower layer DBC substrate assembly, the first lower layer DBC substrate assembly and the second lower layer DBC substrate assembly are arranged side by side and form a rectangular structure;

[0021] The first upper DBC substrate assembly is located above the first lower DBC substrate assembly, and the second upper DBC substrate assembly is located above the second lower DBC substrate assembly.

[0022] The rectangular structure can make the layout structure more compact and reduce the design size of the power module. The upper DBC substrate assembly and the lower DBC substrate assembly are both set in two groups, which can make the interconnection method more flexible, and can connect more chips in parallel, which improves the design freedom and the yield rate of the module in the production process, and can realize a more complex module layout as a whole.

[0023] In an optional embodiment, the first lower DBC substrate of the first lower DBC substrate assembly and the first lower DBC substrate of the second lower DBC substrate assembly are connected by a metal plate located above;

[0024] The second lower DBC substrate of the first lower DBC substrate assembly and the second lower DBC substrate of the second lower DBC substrate assembly are connected via a metal plate located above.

[0025] In an optional embodiment, the upper bridge arm upper DBC substrate of the first upper DBC substrate assembly and the upper bridge arm upper DBC substrate of the second upper DBC substrate assembly are connected via a first gate connection DBC substrate located above, and the first gate connection DBC substrate is connected to the gate of the upper bridge arm chip;

[0026] The lower bridge arm upper DBC substrate of the first upper DBC substrate assembly and the lower bridge arm upper DBC substrate of the second upper DBC substrate assembly are connected via a second gate connection DBC substrate located above, and the second gate connection DBC substrate is connected to the gate of the lower bridge arm chip.

[0027] In an optional embodiment, a first gate current flow DBC substrate is disposed on the upper surface of the second lower DBC substrate, and the first gate current flow DBC substrate is connected to the first gate connection DBC substrate;

[0028] A second gate current flow DBC substrate is disposed on the upper surface of the chip connection region, and the second gate current flow DBC substrate is connected to the second gate connection DBC substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0030] Figure 1 It is a schematic diagram of the structure of an embodiment of the present invention;

[0031] Figure 2 This is a schematic diagram of the positions of the first chip source electrode connected to the DBC substrate and the second chip source electrode connected to the DBC substrate according to an embodiment of the present invention;

[0032] Figure 3 This is a schematic diagram of the positions of the upper bridge arm chip and the lower bridge arm chip according to an embodiment of the present invention;

[0033] Figure 4 This is a schematic diagram of the position of the metal plate in an embodiment of the present invention;

[0034] Figure 5 This is a schematic diagram of the positions of the first lower DBC substrate and the second lower DBC substrate according to an embodiment of the present invention.

[0035] Description of reference numerals:

[0036] 1. Upper bridge arm upper layer DBC substrate; 2. Lower bridge arm upper layer DBC substrate; 3. DC connection area; 4. Chip connection area; 5. Upper bridge arm chip; 6. Lower bridge arm chip; 7. Upper bridge arm chip gate; 8. Lower bridge arm chip gate; 9. First lower layer DBC substrate; 10. Second lower layer DBC substrate; 12. First chip source connected to DBC substrate; 13. Metal connecting piece; 14. Second chip source connected to DBC substrate; 15. First upper layer DBC substrate assembly; 16. Two upper DBC substrate assemblies; 17, first lower DBC substrate assembly; 18, second lower DBC substrate assembly; 19, first gate connected DBC substrate; 20, second gate connected DBC substrate; 21, first gate current flowing DBC substrate; 22, second gate current flowing DBC substrate; 23, copper substrate; 24, housing; 25, first DC terminal; 26, second DC terminal; 27, AC terminal; 28, top DBC substrate; 29, chip connected copper block. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0038] Planar power module technology is an important research direction in the field of power electronics technology, especially playing a key role in new energy applications such as electric vehicles. The core of this technology is to improve power density, operating temperature, heat dissipation efficiency and power conversion efficiency to meet the market's increasingly high performance requirements for power electronic devices. The design of planar power modules usually needs to consider the reliability of electrical connections, parasitic inductance, heat dissipation performance and packaging materials. In traditional power modules, a large number of bonding wires are used to achieve electrical connections. However, the shedding or breakage of bonding wires is one of the main factors affecting the long-term reliability of power modules. At the same time, the presence of bonding wires will also cause a large parasitic inductance inside the module, affecting the switching performance of the device. In order to solve these problems, the present application proposes a design scheme for a planar power module with no bonding wires or fewer bonding wires.

[0039] Due to the limitations of manufacturing process and cost, the current carrying capacity of a single SiC MOSFET chip is only tens of amperes. In high-power applications such as electrical transmission and new energy, modules with multiple chips in parallel are usually required. Multi-chip parallel technology is very important in power modules, which can improve power handling capabilities and reduce the current burden of a single chip. The existing power module multi-chip parallel connection faces problems such as energy loss caused by parasitic inductance, gate oscillation, local overheating and electromagnetic interference caused by uneven current distribution. In a power module with multi-chip parallel connection, the layout structure can be optimized to reduce parasitic inductance and its adverse effects. Multi-chip parallel connection can ensure balanced current distribution, reduce parasitic effects, and optimize thermal management by optimizing the packaging structure and layout design.

[0040] The traditional planar package module multi-chip parallel layout uses two layers of DBC substrates, multiple chips, and connection terminals for layout. However, this layout method will bring about problems such as occupying too much tile area, large design size, loose structure and low design freedom. The DBC substrate is a copper-ceramic-copper structure, that is, an upper copper plate, a middle ceramic plate and a lower copper plate. The stacked DBC technology is an advanced power module packaging technology. It welds two DBC substrates to form a multi-layer structure of "copper-ceramic-copper-copper-ceramic-copper", which realizes the comprehensive optimization of the parasitic capacitance and parasitic inductance inside the module. The multi-layer DBC stacking arrangement can form three to four layers of current transmission paths, which can further reduce the module size and make the structure more compact.

[0041] In the face of this problem, there is an urgent need for a new planar packaging structure that can realize multi-chip parallel connection, which can effectively improve the current carrying capacity, reduce impedance, and maintain the high efficiency and high-speed switching characteristics of SiC MOSFET, making it an ideal solution to meet the needs of high-power applications. This application uses stacked DBC technology to propose a planar 1200V1000A half-bridge power module, which divides the power module into multiple DBC units. The power units are placed on the upper surface metal layer of the upper DBC substrate. Through compact chip layout and sequential arrangement, the overall size of the power module is reduced, the power density is improved, a shorter commutation loop is achieved, and the parasitic inductance of the commutation loop inside the module is reduced.

[0042] Combine the following Figures 1 to 5 , describing an embodiment of the present invention.

[0043] According to an embodiment of the present invention, a laminated DBC planar power module is provided, which may be a 1200V 1000A laminated DBC planar power module, comprising:

[0044] An upper DBC substrate assembly and a lower DBC substrate assembly, wherein the upper DBC substrate assembly comprises an upper bridge arm upper DBC substrate 1 and a lower bridge arm upper DBC substrate 2, and the lower DBC substrate assembly is provided with a DC connection area 3 and a chip connection area 4, and there is a gap between the DC connection area 3 and the chip connection area 4; in the lower DBC substrate assembly, the surface of the DBC substrate is provided with a DC connection area 3 and a chip connection area 4 with a gap, so that the DC connection area 3 and the chip connection area 4 are in the same layer but are insulated. The DC connection area 3 can be gate-shaped, and the chip connection area 4 is located inside the DC connection area 3.

[0045] The upper bridge arm chip 5 has one end connected to the lower DBC substrate assembly, and the other end connected to the upper bridge arm upper DBC substrate 1, and the upper bridge arm upper DBC substrate 1 is hollowed out at a position corresponding to the upper bridge arm chip 5;

[0046] The lower bridge arm chip 6 has one end connected to the chip connection area 4 and the other end connected to the lower bridge arm upper DBC substrate 2. The position of the lower bridge arm upper DBC substrate 2 corresponding to the chip connection area 4 is hollowed out;

[0047] The upper bridge arm upper layer DBC substrate 1 is provided with an upper bridge arm chip gate 7 connected to the upper bridge arm chip 5 , and the lower bridge arm upper layer DBC substrate 2 is provided with a lower bridge arm chip gate 8 connected to the lower bridge arm chip 6 .

[0048] The upper and lower bridge arm structures are respectively arranged on two layers of DBC substrate assemblies, and the upper bridge arm chip 5 and the lower bridge arm chip 6 are arranged on the lower DBC substrate assembly. By hollowing out the upper DBC substrate assembly, the chips can be spatially connected to the upper DBC substrate assembly and the lower DBC substrate assembly, respectively, thereby reducing the overall size of the power module, improving the power density, and achieving a shorter commutation loop. This layout has the advantages of reducing the occupied tile area, having a relatively small design size, and having a relatively high degree of design freedom.

[0049] In an optional embodiment, the lower DBC substrate assembly comprises:

[0050] A first lower DBC substrate 9 is located below the lower bridge arm upper DBC substrate 2, and the DC connection area 3 and the chip connection area 4 are arranged on the upper surface of the first lower DBC substrate 9;

[0051] A second lower DBC substrate 10 is located below the upper bridge arm upper DBC substrate 1, and an upper surface of the second lower DBC substrate 10 is connected to the bottom end of the upper bridge arm chip 5;

[0052] The DC connection area 3 on the first lower DBC substrate 9 and the second lower DBC substrate 10 are connected to each other. The first lower DBC substrate 9 and the second lower DBC substrate 10 can increase the current carrying capacity of the power module, effectively improve the overall reliability of the power module, and increase the power density. The lower DBC substrate assembly is divided into two parts, and the area connected to the upper bridge arm chip 5 and the area connected to the lower bridge arm chip 6 are separated.

[0053] In an optional embodiment, the DC connection area 3 and the second lower DBC substrate 10 are connected by a metal plate located above, and the metal plate connecting the DC connection area 3 of the first lower DBC substrate assembly 17 and the second lower DBC substrate 10 can simultaneously connect the DC connection area 3 and the second lower DBC substrate 10 of the second lower DBC substrate assembly 18. Connecting the DC connection area 3 with the upper bridge arm chip 5 can increase the current carrying capacity of the power module through the metal plate. The metal plate can be the lower copper plate of the upper DBC substrate 1 of the upper bridge arm, and the upper DBC substrate 1 of the upper bridge arm can be located above the DC connection area 3 and the second lower DBC substrate 10, so that the lower copper plate of the upper DBC substrate 1 of the upper bridge arm can be connected to the DC connection area 3 and the second lower DBC substrate 10 respectively.

[0054] In an optional embodiment, the top of the upper bridge arm chip 5 is provided with a first chip source connection DBC substrate 12, and the lower surface of the first chip source connection DBC substrate 12 is respectively connected to the top of the upper bridge arm chip 5 and the upper surface of the upper bridge arm upper layer DBC substrate 1. The upper bridge arm chip 5 located at the lower layer and the upper bridge arm upper layer DBC substrate 1 located at the upper layer can be connected in spatial structure through the first chip source connection DBC substrate 12. The upper bridge arm chip 5 can be multiple, and parallel connection is achieved by being arranged between the first chip source connection DBC substrate 12 and the second lower layer DBC substrate 10. The upper bridge arm chips 5 in this application can be six, distributed in 3*2, and the first gate current flow DBC substrate 21 can be arranged between two rows of upper bridge arm chips 5. Among them, a chip connection copper block 29 can be set on the upper surface of the upper bridge arm chip 5, and the chip connection copper block 29 connects the upper surface of the upper bridge arm chip 5 and the lower surface of the first chip source connection DBC substrate 12. The number of the first chip source connected DBC substrates 12 can be two, which are respectively arranged at the top position of each row of upper bridge arm chips 5 . A top DBC substrate 28 can also be arranged at the top of the first chip source connected DBC substrate 12 .

[0055] In an optional embodiment, the upper bridge arm upper layer DBC substrate 1 is connected to the chip connection area 4 through a metal connecting piece 13, and the lower surface of the metal connecting piece 13 is respectively connected to the upper surface of the upper bridge arm upper layer DBC substrate 1 and the upper surface of the chip connection area 4. The upper bridge arm upper layer DBC substrate 1 and the chip connection area 4 with a height difference can be connected through the metal connecting piece 13. Thereby, the problem of bonding wire falling off or breaking is avoided, and the parasitic inductance is reduced. The material of the metal connecting piece 13 can be a copper sheet.

[0056] In an optional embodiment, a second chip source connection DBC substrate 14 is provided at the top of the lower bridge arm chip 6, and the lower surface of the second chip source connection DBC substrate 14 is respectively connected to the top of the lower bridge arm chip 6 and the upper surface of the lower bridge arm upper layer DBC substrate 2. Among them, a chip connection copper block 29 can be provided on the upper surface of the lower bridge arm chip 6, and the chip connection copper block 29 connects the upper surface of the lower bridge arm chip 6 and the lower surface of the second chip source connection DBC substrate 14.

[0057] The lower bridge arm chips 6 may be multiple, and are connected in parallel by being arranged between the second chip source connection DBC substrate 14 and the chip connection area 4. The lower bridge arm chips 6 in the present application may be six, distributed in 3*2, and the second gate current flow DBC substrate 22 may be arranged between two rows of lower bridge arm chips 6. The number of the second chip source connection DBC substrate 14 may be two, which are arranged at the top position of each row of lower bridge arm chips 6, respectively, and the top of the second chip source connection DBC substrate 14 may also be provided with a top DBC substrate 28. A water cooling plate may be arranged on the upper surface of the top DBC substrate 28 for heat dissipation.

[0058] In an optional embodiment, the upper DBC substrate assembly is divided into two groups, namely a first upper DBC substrate assembly 15 and a second upper DBC substrate assembly 16, wherein the first upper DBC substrate assembly 15 and the second upper DBC substrate assembly 16 are arranged side by side and form a rectangular structure;

[0059] The lower DBC substrate assembly includes two groups, namely a first lower DBC substrate assembly 17 and a second lower DBC substrate assembly 18. The first lower DBC substrate assembly 17 and the second lower DBC substrate assembly 18 are arranged side by side and form a rectangular structure.

[0060] The first upper DBC substrate assembly 15 is located above the first lower DBC substrate assembly 17 , and the second upper DBC substrate assembly 16 is located above the second lower DBC substrate assembly 18 .

[0061] The rectangular structure can make the layout structure more compact and reduce the design size of the power module. The upper DBC substrate assembly and the lower DBC substrate assembly are both set in two groups, which can make the interconnection method more flexible, and can connect more chips in parallel, which improves the design freedom and the yield rate of the module in the production process, and can realize a more complex module layout as a whole.

[0062] In an optional embodiment, the first lower DBC substrate 9 of the first lower DBC substrate assembly 17 and the first lower DBC substrate 9 of the second lower DBC substrate assembly 18 are connected by a metal plate located above; the metal plate may be the lower copper plate of the lower bridge arm upper DBC substrate 2 of the first upper DBC substrate assembly 15, and the lower bridge arm upper DBC substrate 2 may be located above the first lower DBC substrate 9 of the first lower DBC substrate assembly 17 and the first lower DBC substrate 9 of the second lower DBC substrate assembly 18, so that the lower copper plate of the lower bridge arm upper DBC substrate 2 can be connected to the upper surface of the first lower DBC substrate 9 of the first lower DBC substrate assembly 17 and the first lower DBC substrate 9 of the second lower DBC substrate assembly 18.

[0063] The second lower DBC substrate 10 of the first lower DBC substrate assembly 17 and the second lower DBC substrate 10 of the second lower DBC substrate assembly 18 are connected by a metal plate located above. The metal plate may be a lower copper plate of the upper bridge arm upper DBC substrate 1 of the first upper DBC substrate assembly 15, and the upper bridge arm upper DBC substrate 1 may be located above the second lower DBC substrate 10 of the first lower DBC substrate assembly 17 and the second lower DBC substrate 10 of the second lower DBC substrate assembly 18, so that the lower copper plate of the upper bridge arm upper DBC substrate 1 can connect the upper surfaces of the second lower DBC substrate 10 of the first lower DBC substrate assembly 17 and the second lower DBC substrate 10 of the second lower DBC substrate assembly 18.

[0064] In an optional embodiment, the upper bridge arm upper DBC substrate 1 of the first upper DBC substrate assembly 15 and the upper bridge arm upper DBC substrate 1 of the second upper DBC substrate assembly 16 are connected through a first gate connection DBC substrate 19 located above, and the first gate connection DBC substrate 19 is connected to the upper bridge arm chip gate 7; one terminal of the upper bridge arm chip gate 7 can be connected to the upper surface of the upper bridge arm upper DBC substrate 1, and the other terminal of the upper bridge arm chip gate 7 can be connected to the upper surface of the first gate connection DBC substrate 19, and the lower surface of the first gate connection DBC substrate 19 can be welded to the upper surface of the upper bridge arm upper DBC substrate 1, and the upper surface of the first gate connection DBC substrate 19 can be connected to the lower surface of the first gate current flowing DBC substrate 21 through a bonding wire.

[0065] The lower bridge arm upper layer DBC substrate 2 of the first upper layer DBC substrate assembly 15 and the lower bridge arm upper layer DBC substrate 2 of the second upper layer DBC substrate assembly 16 are connected through the second gate connection DBC substrate 20 located above, and the second gate connection DBC substrate 20 is connected to the lower bridge arm chip gate 8. One terminal of the lower bridge arm chip gate 8 can be connected to the upper surface of the lower bridge arm upper layer DBC substrate 2, and the other terminal of the lower bridge arm chip gate 8 can be connected to the upper surface of the second gate connection DBC substrate 20. The lower surface of the second gate connection DBC substrate 20 can be welded to the upper surface of the lower bridge arm upper layer DBC substrate 2, and the upper surface of the second gate connection DBC substrate 20 can be connected to the lower surface of the second gate current flow DBC substrate 22 through a bonding wire.

[0066] In an optional embodiment, a first gate current flow DBC substrate 21 is provided on the upper surface of the second lower layer DBC substrate 10, and the first gate current flow DBC substrate 21 is connected to the first gate connection DBC substrate 19; the lower surface of the first gate current flow DBC substrate 21 can be welded to the upper surface of the second lower layer DBC substrate 10, and the first gate current flow DBC substrate 21 can be located between two rows of upper bridge arm chips 5.

[0067] The upper surface of the chip connection area 4 is provided with a second gate current flow DBC substrate 22, and the second gate current flow DBC substrate 22 is connected to the second gate connection DBC substrate 20. The lower surface of the second gate current flow DBC substrate 22 can be welded to the upper surface of the chip connection area 4, and the second gate current flow DBC substrate 22 can be located between two rows of lower bridge arm chips 6.

[0068] The first lower DBC substrate 9 of the first lower DBC substrate assembly 17 can be welded below the upper DBC substrate 2 of the lower bridge arm of the first upper DBC substrate assembly 15 to form a first subunit; the second lower DBC substrate 10 of the first lower DBC substrate assembly 17 can be welded below the upper DBC substrate 1 of the upper bridge arm of the first upper DBC substrate assembly 15 to form a second subunit; the first lower DBC substrate 9 of the second lower DBC substrate assembly 18 can be welded below the upper DBC substrate 2 of the lower bridge arm of the second upper DBC substrate assembly 16 to form a third subunit; the second lower DBC substrate 10 of the second lower DBC substrate assembly 18 can be welded below the upper DBC substrate 1 of the upper bridge arm of the second upper DBC substrate assembly 16 to form a fourth subunit. The first subunit and the third subunit are connected in parallel, and the second subunit and the fourth subunit are connected in parallel. The traditional planar module has only two layers of DBC, upper and lower, connected by molybdenum sheets in the middle. The new module has 4 layers of DBC. The lower layer is a double-layer layout structure, which is divided into 4 sub-units. Each sub-unit can be welded and tested independently. After screening, the whole unit can be welded to improve the yield rate. The bottom layer can weld 12 upper bridge arm chips 5 and 12 lower bridge arm chips 6, which can achieve a current of 1000A. The gate of the upper bridge arm chip 7 is connected to the upper bridge arm chip 5 in the third unit and the fourth unit respectively and controls the upper bridge arm chip 5 in the third unit and the fourth unit at the same time; the gate of the lower bridge arm chip 8 is connected to the lower bridge arm chip 6 in the first unit and the second unit respectively and controls the lower bridge arm chip 6 in the first unit and the second unit at the same time.

[0069] Two first DC terminals 25 may be respectively provided on the upper surfaces of the first lower DBC substrate 9 of the first lower DBC substrate assembly 17 and the first lower DBC substrate 9 of the second lower DBC substrate assembly 18, and the first DC terminals 25 may be DC positive terminals. Openings are provided on the lower bridge arm upper DBC substrate 2 of the first upper DBC substrate assembly 15 and the lower bridge arm upper DBC substrate 2 of the second upper DBC substrate assembly 16 to facilitate the connection of the first DC terminals 25; two second DC terminals 26 may be respectively provided on the upper surfaces of the lower bridge arm upper DBC substrate 2 of the first upper DBC substrate assembly 15 and the lower bridge arm upper DBC substrate 2 of the second upper DBC substrate assembly 16, and the second DC terminals 26 may be DC negative terminals; AC terminals 27 may be provided on the upper surfaces of the upper bridge arm upper DBC substrate 1 of the first upper DBC substrate assembly 15 and the upper bridge arm upper DBC substrate 1 of the second upper DBC substrate assembly 16.

[0070] A copper substrate 23 may be provided at the bottom of the first lower DBC substrate assembly 17 and the second lower DBC substrate assembly 18 , a housing 24 may be provided on the copper substrate, and the first DC terminal 25 , the second DC terminal 26 and the AC terminal 27 may be provided on the housing 24 .

[0071] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A laminated DBC planar power module, characterized in that: include: An upper DBC substrate assembly and a lower DBC substrate assembly, wherein the upper DBC substrate assembly comprises an upper bridge arm upper DBC substrate (1) and a lower bridge arm upper DBC substrate (2), and the lower DBC substrate assembly is provided with a DC connection area (3) and a chip connection area (4), and a gap is provided between the DC connection area (3) and the chip connection area (4); An upper bridge arm chip (5) is connected to the lower DBC substrate assembly at one end and connected to the upper bridge arm upper DBC substrate (1) at the other end, and the upper bridge arm upper DBC substrate (1) is hollowed out at a position corresponding to the upper bridge arm chip (5); A lower bridge arm chip (6) having one end connected to the chip connection area (4) and the other end connected to the lower bridge arm upper DBC substrate (2), wherein the position of the lower bridge arm upper DBC substrate (2) corresponding to the chip connection area (4) is hollowed out; The upper bridge arm upper layer DBC substrate (1) is provided with an upper bridge arm chip gate (7) connected to the upper bridge arm chip (5), and the lower bridge arm upper layer DBC substrate (2) is provided with a lower bridge arm chip gate (8) connected to the lower bridge arm chip (6).

2. The laminated DBC planar power module according to claim 1, characterized in that: The lower DBC substrate assembly comprises: A first lower DBC substrate (9) is located below the lower bridge arm upper DBC substrate (2), and the DC connection area (3) and the chip connection area (4) are arranged on the upper surface of the first lower DBC substrate (9); A second lower DBC substrate (10) is located below the upper bridge arm upper DBC substrate (1), and the upper surface of the second lower DBC substrate (10) is connected to the bottom end of the upper bridge arm chip (5); The DC connection area (3) on the first lower DBC substrate (9) and the second lower DBC substrate (10) are connected to each other.

3. The laminated DBC planar power module according to claim 2, characterized in that: The DC connection area (3) and the second lower DBC substrate (10) are connected via a metal plate located above.

4. The laminated DBC planar power module according to claim 1, characterized in that: A first chip source connection DBC substrate (12) is provided at the top of the upper bridge arm chip (5), and the lower surface of the first chip source connection DBC substrate (12) is respectively connected to the top of the upper bridge arm chip (5) and the upper surface of the upper bridge arm upper layer DBC substrate (1).

5. The laminated DBC planar power module according to claim 1, characterized in that: The upper DBC substrate (1) of the upper bridge arm is connected to the chip connection area (4) via a metal connection sheet (13), and the lower surface of the metal connection sheet (13) is respectively connected to the upper surface of the upper DBC substrate (1) of the upper bridge arm and the upper surface of the chip connection area (4).

6. The laminated DBC planar power module according to claim 1, characterized in that: A second chip source connection DBC substrate (14) is provided at the top of the lower bridge arm chip (6), and the lower surface of the second chip source connection DBC substrate (14) is respectively connected to the top of the lower bridge arm chip (6) and the upper surface of the lower bridge arm upper layer DBC substrate (2).

7. The laminated DBC planar power module according to claim 1, characterized in that: The upper DBC substrate assembly comprises two groups, namely a first upper DBC substrate assembly (15) and a second upper DBC substrate assembly (16); the first upper DBC substrate assembly (15) and the second upper DBC substrate assembly (16) are arranged side by side and form a rectangular structure; The lower layer DBC substrate assembly consists of two groups, namely a first lower layer DBC substrate assembly (17) and a second lower layer DBC substrate assembly (18). The first lower layer DBC substrate assembly (17) and the second lower layer DBC substrate assembly (18) are arranged side by side and form a rectangular structure. The first upper DBC substrate assembly (15) is located above the first lower DBC substrate assembly (17), and the second upper DBC substrate assembly (16) is located above the second lower DBC substrate assembly (18).

8. The laminated DBC planar power module according to claim 7, characterized in that: The first lower DBC substrate (9) of the first lower DBC substrate assembly (17) and the first lower DBC substrate (9) of the second lower DBC substrate assembly (18) are connected via a metal plate located above; The second lower DBC substrate (10) of the first lower DBC substrate assembly (17) and the second lower DBC substrate (10) of the second lower DBC substrate assembly (18) are connected via a metal plate located above.

9. The laminated DBC planar power module according to claim 7, characterized in that: The upper bridge arm upper DBC substrate (1) of the first upper DBC substrate assembly (15) and the upper bridge arm upper DBC substrate (1) of the second upper DBC substrate assembly (16) are connected via a first gate connection DBC substrate (19) located above, and the first gate connection DBC substrate (19) is connected to the gate (7) of the upper bridge arm chip; The lower bridge arm upper layer DBC substrate (2) of the first upper layer DBC substrate assembly (15) and the lower bridge arm upper layer DBC substrate (2) of the second upper layer DBC substrate assembly (16) are connected via a second gate connection DBC substrate (20) located above, and the second gate connection DBC substrate (20) is connected to the lower bridge arm chip gate (8).

10. The laminated DBC planar power module according to claim 9, characterized in that: A first gate current flow DBC substrate (21) is provided on the upper surface of the second lower DBC substrate (10), and the first gate current flow DBC substrate (21) is connected to the first gate connection DBC substrate (19); A second gate current flow DBC substrate (22) is provided on the upper surface of the chip connection area (4), and the second gate current flow DBC substrate (22) is connected to the second gate connection DBC substrate (20).

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