Flat integrated circuit package interconnect

Abstract

Apparatuses, methods, and systems including substantially coplanar conductive pillars are generally discussed herein. According to an example, a technique can include: generating conductive pillars on respective exposed bond pads of a substrate; disposing a molding material around and over the generated conductive pillars; simultaneously removing the molding material and a portion of the generated conductive pillar such that the generated conductive pillar and the molding material are substantially flat; and electrically coupling a die to the conductive pillar.

Description

[0001] Priority claim This patent application claims the benefit of priority to U.S. Application Serial No. 15 / 198,107, filed on June 30, 2016, which is hereby incorporated by reference in its entirety. Technical Field

[0002] Examples relate generally to integrated circuit (IC) packaging and, more particularly, to processes for creating IC packages containing substantially planar conductive pillars and devices resulting from such processes. Background Art

[0003] IC packaging technology has a trend toward making ICs smaller and smaller. Smaller IC packages generally contain more signal routing per unit area than larger IC packages. Manufacturing such smaller packages can be challenging. Smaller packages can have higher yield loss than larger packages. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] In the drawings, which are not necessarily drawn to scale, like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different instances of similar components. The accompanying drawings generally illustrate various embodiments discussed in this document by way of example and not by way of limitation.

[0005] Figure 1 A cross-sectional view of an example of an IC package is shown by way of example.

[0006] Figures 2A-2H Cross-sectional views of stages of an example of a process for creating an IC package are shown by way of example.

[0007] Figures 3A-3D Cross-sectional views of stages of an example of another process for creating an IC package are shown by way of example.

[0008] Figures 4A-4D Cross-sectional views of stages of an example of another process for creating an IC package are shown by way of example.

[0009] Figure 5 A schematic diagram of an example of an electronic system is shown by way of example. DETAILED DESCRIPTION

[0010] Examples in this disclosure relate to processes for creating IC packages having conductive pillars that are substantially flat (eg, within approximately five (5) microns or less of each other). Examples also relate to devices and systems created using such processes.

[0011] The following description contains terms such as higher, lower, first, second, etc., which are used for descriptive purposes only and are not to be construed as limiting. Examples of the devices or products described herein can be manufactured, used, or shipped in multiple locations and orientations. The terms "die" and "chip" generally refer to a physical object that is a basic workpiece that is transformed into a desired integrated circuit device through various process operations. The die is typically cut from a wafer, and the wafer can be made of semiconductor, non-semiconductor, or a combination of semiconductor and non-semiconductor materials.

[0012] As IC package interconnects (e.g., flip chips or other interconnects) continue to shrink to finer pitches, the ability of the solder used in / on the interconnects to provide room for random or systematic fluctuations in surface coplanarity or bump height becomes more limited. This article discusses a process for creating an IC package with substantially coplanar conductive posts. Substantially coplanar conductive posts can help increase manufacturing yields, such as by reducing the variation in the gap between the conductive posts and the chip to be attached to the posts. Substantially coplanar conductive posts can help make spacing reduction more feasible. Due to the more predictable gap distance between the corresponding conductive posts and the pads to which the conductive posts are to be connected, finer spacing can be allowed.

[0013] In a high-level overview, the process can include creating a conductive post (e.g., approximately forty (40) microns high in some manufacturing processes) at each raised location on the surface of the package substrate. The substrate can be covered with a mold compound thicker than the height of the conductive post, so that the mold compound extends over and covers the conductive post. The conductive post can then be exposed, such as by a controlled grinding process that can remove a specified amount of mold (e.g., a few microns of mold). After grinding, a conductive adhesive material (e.g., solder balls, solder, or paste, etc.) can be attached to the post, or the post can be covered with a patterned pad, and then a conductive adhesive can be added to the pad. The die can then be attached to the conductive post, such as by the conductive adhesive material.

[0014] The coplanarity of the current substrate conductive posts combined with the current substrate distortion can result in a height variation between approximately ten (10) microns and twenty (20) microns across the die attach area on the package. This variation makes chip attachment difficult and can negatively affect the package yield. This variation also jeopardizes the advantages obtained by thermocompression bonding (TCB) tools in die placement precision and accuracy. The embodiments discussed herein can help create an absolute height variation of less than (or equal to) five (5) microns across the surface of the conductive posts. Such coplanarity can help achieve a high yield TCB chip attach process such as with a spacing of less than one hundred and thirty (130) microns. In addition, such coplanarity can help reduce the size of the substrate bonding pads under the conductive posts. Reducing the size of the bonding pads can help increase the I / O wiring density, such as without modifying the substrate patterning process.

[0015] Reference will now be made to the accompanying drawings, wherein similar structures will be provided with similar suffix reference numerals. In order to clearly illustrate the structures of various examples, the drawings included herein are graphical representations of integrated circuit structures. Therefore, the actual appearance of the fabricated structures, such as in a photomicrograph, may appear different while still incorporating the subject matter of the illustrated examples. In addition, the drawings illustrate the structures to aid in understanding the illustrated examples.

[0016] Figure 1 A cross-sectional view of an embodiment of an integrated circuit (IC) package 100 is shown by way of example before a die 103 is attached to a substrate 101. Variations in the height of the conductive pillars 102 on the substrate 101 cause gaps 108 to form between the conductive balls 106 and the contact pads 104 of the die 103. For example, the gaps 108 may cause electrical shorts if the conductive balls 106 do not span the entire gaps 108 after reflow. For example, the gaps 108 may cause the die 103 to be misaligned by causing the die 103 to shift or rotate relative to the substrate 101 after the die 103 is disposed on one or more of the conductive bumps 106.

[0017] Figure 2A A cross-sectional view of an embodiment of a device 200A is shown by way of example. The device 200A as shown includes a substrate 201, and a conductive pillar 202 is disposed on a bonding pad 204 of the substrate 201. The device 200A as shown includes an interconnect circuit 204 in and / or on the substrate 201. The device 200A as shown includes a bonding pad 206 electrically connected to the interconnect circuit 204 and on the substrate 201. The device 200A as shown includes a conductive pad 208, such as capable of being electrically and mechanically connected to a circuit, for example, electrically connecting the device 200A to a circuit.

[0018] In one or more embodiments, substrate 201 can include a bumpless build-up layer (BBUL) substrate or other substrate. Substrate 201 can be built by providing a dielectric (e.g., an Ajinomoto build-up film (ABF)), patterning the dielectric, adding a conductive material to the patterned dielectric, patterning the conductive material, and repeating until the substrate is built. In general, any number of build-up layers can be used to create substrate 201, and the layers can be of various thicknesses.

[0019] Conductive pillars 202 are generally made of copper, but can include other conductive materials such as tin, cadmium, gold, silver, palladium, rhodium, copper, bronze, brass, lead, nickel silver, beryllium copper, nickel, some combination of these materials, etc. Conductive pillars 202 can be created by placing a thin seed layer of conductive material on top of the substrate, patterning the seed layer with a photoresist, etching openings over each conductive pillar location, electroplating the conductive material in the openings in the photoresist, removing the photoresist, and then etching the seed layer that was once protected by the photoresist (e.g., where the conductive pillars were not present).

[0020] Conductive pillars 202 each include respective heights 210A, 210B, 210C, 210D, 210E, 210F, 210G, 210H, and 210I. The differences in heights 210A-H may cause chip attach issues in subsequent processing, such as for Figure 1 To help alleviate issues related to die attach, it may be beneficial to make heights 210A-H more uniform so as to reduce the distance between the conductive balls on the conductive pillars and the exposed surfaces of the contact pads of the die to be attached to the conductive pillars (see Figure 2E and 2F ).

[0021] Conductive pillars 202 can be generated with a height greater than the final height of the pillar so as to allow the conductive pillars 202 to be planarized prior to die attach. In one or more embodiments, conductive pillars 202 can be generated with a height of thirty (30) microns or more. Some embodiments may include conductive pillars shorter than 30 microns.

[0022] The interconnect circuit 204 can provide an electrical path through the substrate 201. The interconnect circuit 204 can provide an electrical path for current to flow between a die attached to the conductive pillar 202 and the contact pad 208. The interconnect circuit 204 can include electrical routing, such as can include traces, planes, redistribution layer interconnect circuits, vias, contact pads, etc. The interconnect circuit 204 can include a conductive material, such as the conductive material previously discussed for the conductive pillar 202.

[0023] The bonding pad 206 is electrically connected to the interconnect circuit 204. The bonding pad 206 can be made of a conductive material, such as the conductive material previously discussed for the conductive pillar. The bonding pad 206 provides a location to electrically and mechanically connect the conductive pillar 202 to the interconnect circuit 204.

[0024] The contact pad 208 is electrically connected to the interconnect circuit 204. The contact pad 208 provides electrical signals from the interconnect circuit 204 to an external device (e.g., a printed circuit board (PCB) such as a flexible or rigid PCB, another package, a die, or other device). The contact pad 208 can include a conductive material, such as the conductive material previously discussed for the conductive pillar 202.

[0025] Figure 2B A cross-sectional view of an embodiment of a device 200B including the device 200A is shown by way of example after a molding material 212 is disposed on the substrate 201 and the conductive pillars 202. The molding material 212 can be disposed above and around the exposed portions of the conductive pillars 202, the substrate 201, and / or the bonding pads 206. The height 213 of the molding material 212 can be greater than the height of the tallest conductive pillar 202 (e.g., greater than the height 210H in the example of the device 200A). The molding material 212 can include a polymer, a polyester film, and / or a photoimageable material (i.e., a material that can be removed using a photoimaging process) such as a polyimide. The molding material 212 can be selected based on the chemical, electrical, mechanical, or manufacturing properties of the molding material 212. The molding material 212 is generally a dielectric insulator.

[0026] Figure 2C A cross-sectional view of an embodiment of a device 200C including the device 200B is shown by way of example after the molding material 212 and the conductive pillars 202 are grounded. The conductive pillars 202 are grounded to form conductive pillars 214 having more uniform heights 216A, 216B, 216C, 216D, 216E, 216F, 216G, 216H, and 216I than the conductive pillars 202 (i.e., heights 210A-I). The grinding forms the molding material 218 having a height less than the height 213 of the molding material 212 (substantially the same as the heights 216A-I). The grinding can include mechanical grinding. After the grinding process, the heights of the molding material 218 and the conductive pillars 214 can be substantially uniform (e.g., uniform within approximately 5 microns). That is, the maximum height variation between any two points across the grounded surface is at most 5 microns.

[0027] Figure 2DBy way of example, a cross-sectional view of an embodiment of a device 200D including the device 200C is shown after a soft etch (e.g., chemical etch) has removed a portion of the conductive pillar 214 to form the pillar 220. The amount of material removed from the conductive pillar 214 can be controlled by the amount of time the conductive pillar 214 is exposed to the chemical and / or the concentration of the etchant in the chemical. The heights 222A, 222B, 222C, 222D, 222E, 222F, 222G, 222H, and 222I of the conductive pillar 220 are less than the corresponding heights 216A-I of the conductive pillar 214. The heights 222A-I of the conductive pillar 220 are less than the height of the molding material 218 (which is substantially the same as the heights 216A-I).

[0028] Reducing the height of the conductive pillars 220 can introduce greater changes in the coplanarity of the conductive pillars 220, but generally does not affect the coplanarity of the molding material 218. Reducing the height of the conductive pillars 214 can recess the conductive pillars 220 so that their heights 222A-I are smaller than the height of the molding material 218. Reducing the height of the conductive pillars 214 can help increase the conductive adhesive (see Figure 2E ) and the bonding strength between the conductive pillar 220.

[0029] Figure 2E By way of example, a cross-sectional view of an embodiment of a device 200E including the device 200D is shown after a conductive adhesive 224 has been disposed over and connected to the conductive pillars 220. The soft etching of the conductive pillars 214 can remove oxidation or other material from the contact surfaces of the conductive pillars 214 so as to form conductive pillars having surfaces that are more susceptible to forming reliable electrical and / or mechanical connections with the conductive adhesive 224. The conductive adhesive 224 will form an electrical connection between the interconnect circuitry of the die and the conductive pillars 220 (see Figure 2F ). The conductive adhesive 224 can include solder (eg, solder balls), conductive paste, or other conductive material that can form an electrical and mechanical bond between the contact pads of the die and the conductive pillars 220 (see Figure 2F ). The conductive adhesive 224 can be disposed by forming a mask that covers the molding material 218 and exposes the conductive pillars 220. The conductive adhesive 224 can be disposed over the exposed conductive pillars 220 through the holes in the mask. The conductive adhesive 224 can be heated so as to flow or at least partially cure the conductive adhesive 224 and bond the conductive adhesive 224 to the conductive pillars 220.

[0030] Figure 2FBy way of example, a cross-sectional view of an embodiment of device 200F including device 200E is shown when die 226 is being disposed over conductive adhesive 224. Conductive adhesive 224 can be softened, such as by heating conductive adhesive 224, and hardened to form electrical and mechanical connections between contact pads 228 of die 226 and conductive pillars 220. Figure 2G By way of example, a cross-sectional view of an embodiment of an IC package 200G including a device 200F is shown after a die 226 is electrically and mechanically connected to a conductive pillar 220 via a conductive adhesive 224 .

[0031] Figure 2H Shown by example Figure 2G Marked in Figure 2H ” is an exploded view of the dashed box. The conductive adhesive 224 is on top of the conductive pillar 220. The conductive adhesive 224 is above and in contact with the upper surface 230 of the molding material 218. Prior to the soft etch, the conductive adhesive 224 fills the area occupied by the conductive pillar 214. The conductive adhesive inlay extends to a portion of the sidewall 232 beyond the upper surface 234 of the conductive pillar 220.

[0032] Figure 3A By way of example, after some of the molding material 218 is removed to form the molding material 302, including Figure 2C 200C is depicted in FIG. 200A. Molding material 302 has a height 304 that is less than height 216A-I. Molding material 218 can be removed using photoimaging, laser ablation, or other processes. In embodiments where conductive adhesive 224 is attached to die 226 prior to electrically and mechanically connecting die 226 to substrate 201, such as via conductive pillars 214, molding material 302 can be recessed.

[0033] Figure 3B By way of example, a cross-sectional view of an embodiment of a device 300B including the device 300A is shown when the die 226 and the conductive adhesive 224 are being disposed on the device 300A. The conductive adhesive 224 can be softened, such as by heating the conductive adhesive 224, and hardened to form an electrical and mechanical connection between the conductive pillars 214 and the contact pads 228 of the die 226. Figure 3C By way of example, a cross-sectional view of an embodiment of an IC package 300C including a device 300B is shown after a die 226 is electrically and mechanically connected to a conductive pillar 214 via a conductive adhesive 224 .

[0034] Figure 3D Shown by example Figure 3C Marked in Figure 3D” is an exploded view of the dashed box. The conductive adhesive 224 is on the conductive pillar 214. The conductive adhesive 224 is on and in contact with the sidewalls 306A and 306B of the conductive pillar 214. Prior to the soft etch, the conductive adhesive 224 fills the area occupied by the conductive pillar 214. The conductive adhesive 224 extends beyond the sidewalls 306A-B of the conductive pillar 214 so as to overhang the conductive pillar 224.

[0035] Figure 4A By way of example, after forming contact pads 402 on corresponding conductive pillars 214, Figure 2C 4. The contact pad 402 can be used, for example, in a device where the width 408 of the conductive pillar 214 (see Figure 4D ) is too small to support direct connection to the conductive adhesive 224. The contact pad 402 can be created by disposing a layer of conductive material on the conductive pillar 214 and the molding material 218, then a patterned mask can be disposed on the conductive material, the conductive material can be etched and the mask can be removed. The width 404 of the contact pad 402 can be larger than the width 406 of the bonding pad 206. Having a narrower bonding pad width 406 can help increase the I / O density in the substrate 101.

[0036] Figure 4B By way of example, a cross-sectional view of an embodiment of a device 400B including device 400A is shown after conductive adhesive 224 is disposed on corresponding contact pads 402 and while die 226 is being disposed on the conductive adhesive. Conductive adhesive 224 can be softened, such as by heating conductive adhesive 224, and hardened to form electrical and mechanical connections between contact pads 402 and contact pads 228 of die 226. Figure 4C By way of example, a cross-sectional view of an embodiment of an IC package 400C including a device 400B is shown after the die 26 is electrically and mechanically connected to the conductive pillars 214 via the conductive adhesive 224 and the contact pads 402 .

[0037] Figure 4D Shown by example Figure 3C Marked in Figure 3D ” is an exploded view of the dashed box. The conductive adhesive 224 is on the conductive pillar 214. The conductive adhesive 224 is on and in contact with the sidewalls 306A and 306B of the conductive pillar 214. Prior to the soft etch, the conductive adhesive 224 fills the area occupied by the conductive pillar 214. The conductive adhesive 224 extends beyond the sidewalls 306A-B of the conductive pillar 214 so as to overhang the conductive pillar 224.

[0038] Figure 5A logical block diagram of an embodiment of system 500 is shown by way of example. In one or more embodiments, system 500 includes one or more components that can include a package with planar interconnects as discussed herein.

[0039] In one embodiment, processor 510 has one or more processing cores 512 and 512N, where 512N represents the Nth processor core in processor 510, where N is a positive integer. In one embodiment, system 500 includes multiple processors, including 510 and 505, where processor 505 has logic similar to or the same as that of processor 510. In some embodiments, processing core 512 includes but is not limited to: pre-fetch logic for fetching instructions, decoding logic for decoding instructions, execution logic for executing instructions, and the like. In some embodiments, processor 510 has a cache memory 516 to cache instructions and / or data for system 500. Cache memory 516 can be organized into a hierarchical structure including one or more levels of cache memory.

[0040] In some embodiments, the processor 510 includes a memory controller 514 that is operable to perform functions that enable the processor 510 to access and communicate with a memory 530, which includes a volatile memory 532 and / or a non-volatile memory 534. In some embodiments, the processor 510 is coupled to the memory 530 and the chipset 520. The processor 510 may also be coupled to a wireless antenna 578 to communicate with any device configured to transmit and / or receive wireless signals. In one embodiment, the wireless antenna interface 578 operates in accordance with (but not limited to) the IEEE 802.11 standard and its related series, Home Plug AV (HPAV), Ultra Wideband (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

[0041] In some embodiments, the volatile memory 532 includes, but is not limited to, synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), RAMBUS dynamic random access memory (RDRAM), and / or any other type of random access memory device. The non-volatile memory 534 includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.

[0042] Memory 530 stores instructions and information to be executed by processor 510. In one embodiment, memory 530 may also store temporary variables or other intermediate information while processor 510 is executing instructions. In the illustrated embodiment, chipset 520 is connected to processor 510 via point-to-point (PtP or PP) interfaces 517 and 522. Chipset 520 enables processor 510 to connect to other elements in system 500. In some embodiments of the invention, interfaces 517 and 522 are configured in accordance with, for example, The UE may operate with a PtP communication protocol such as a Quick Path Interconnect (QPI). In other embodiments, a different interconnect may be used.

[0043] In some embodiments, chipset 520 is operable to communicate with processors 510, 505N, display device 540, and other devices. Chipset 520 may also be coupled to wireless antenna 578 to communicate with any device configured to transmit and / or receive wireless signals.

[0044] Chipset 520 is connected to display device 540 via interface 526. Display 540 may be, for example, a liquid crystal display (LCD), a plasma display, a cathode ray tube (CRT) display, or any other form of visual display device. In some embodiments of the present invention, processor 510 and chipset 520 are combined into a single SOC. In addition, chipset 520 is connected to one or more buses 550 and 555 that interconnect various elements 574, 560, 562, 564, and 566. Buses 550 and 555 may be interconnected together via bus bridge 572. In one embodiment, chipset 520 is coupled to non-volatile memory 560, one or more mass storage devices 562, keyboard / mouse 564, and network interface 566 via interface 524 and / or 504, etc.

[0045] In one embodiment, the mass storage device 562 includes, but is not limited to, a solid state drive, a hard disk drive, a universal serial bus flash memory drive, or any other form of computer data storage medium. In one embodiment, the network interface 566 is implemented by any type of well-known network interface standard, including but not limited to, an Ethernet interface, a universal serial bus (USB) interface, a peripheral component interconnect (PCI) express interface, a wireless interface, and / or any other appropriate type of interface. In one embodiment, the wireless interface operates according to (but not limited to) the IEEE 802.11 standard and its related series, Home PlugAV (HPAV), Ultra-Wideband (UWB), Bluetooth, WiMax, or any form of wireless communication protocol. Although Figure 5The components shown in are depicted as separate blocks within system 500, but the functions performed by some of these blocks may be integrated within a single semiconductor circuit, or may be implemented using two or more separate integrated circuits. For example, although cache memory 516 is depicted as a separate block within processor 510, cache memory 516 (or selected aspects of 516) can be incorporated into processor core 512.

[0046] Examples and Notes The present subject matter may be described by means of several examples.

[0047] In Example 1, a method for making an integrated circuit package includes: generating conductive pillars on corresponding exposed bonding pads of a substrate; disposing a molding material around and on the generated conductive pillars; simultaneously removing a portion of the molding material and the generated conductive pillars so that the generated conductive pillars and the molding material are substantially flat, and electrically coupling a die to the conductive pillars.

[0048] In Example 2, Example 1 can further include: after removing the molding material and the generated portion of the conductive pillar, removing another portion of the conductive pillar to recess the conductive pillar in the molding material.

[0049] In Example 3, Example 2 can also include: wherein removing another portion of the conductive pillar includes etching the conductive pillar.

[0050] In Example 4, Example 2 can further include disposing a conductive adhesive over each of the conductive pillars before electrically connecting the die to the substrate.

[0051] In Example 5, Example 4 can further include: wherein electrically connecting the die to the conductive pillars includes reflowing the conductive adhesive to electrically connect contact pads of the die to corresponding ones of the conductive pillars.

[0052] In Example 6, Example 5 can further include: wherein the conductive adhesive embeds a portion of the surface and a portion of the sidewall of the molding material after reflow.

[0053] In Example 7, at least one of Examples 1-6 removes another portion of the molding material to recess the molding material relative to the conductive pillar after removing the portion of the molding material and the generated conductive pillar.

[0054] In Example 8, Example 7 can further include: wherein removing the other portion of the molding material includes photoimaging the molding material.

[0055] In Example 9, Example 7 can further include disposing a conductive adhesive over the die before electrically connecting the die to the substrate.

[0056] In Example 10, Example 9 can further include: wherein electrically connecting the die to the conductive pillars includes reflowing the conductive adhesive to electrically connect contact pads of the die to corresponding ones of the conductive pillars.

[0057] In Example 11, Example 10 can further include: wherein the conductive adhesive embeds the exposed portion of the sidewall of the conductive pillar after reflow.

[0058] In Example 12, at least one of Examples 1-11 can further include: after removing the molding material and a portion of the generated conductive pillar, forming a contact pad on the corresponding conductive pillar.

[0059] In Example 13, Example 12 can further include: wherein forming the contact pad includes forming the contact pad having a width greater than a width of the bonding pad.

[0060] In Example 14, Example 13 can further include disposing a conductive adhesive over each of the contact pads before electrically connecting the die to the substrate.

[0061] In Example 15, an IC package includes: a substrate including interconnect circuitry embedded in a build layer and a plurality of bonding pads exposed on an upper surface of the substrate; a plurality of conductive posts electrically connected to corresponding bonding pads; a molding material around at least a portion of the sidewalls of the conductive posts and on top of the substrate; and a die on the substrate, the die including contact pads electrically coupled to the interconnect circuitry through the conductive posts, wherein the conductive posts each include an upper surface that is substantially flat relative to each other within five microns.

[0062] In Example 16, Example 15 can further include: wherein the contact pad of the tube core is a first contact pad, and the package also includes a second contact pad connected to the corresponding conductive column, the second contact pad has a larger width than the bonding pad, and the second contact pad is arranged between the conductive column and the first contact pad.

[0063] In Example 17, Example 15 can further include: wherein the conductive pillar has a height greater than a height of the molding material, and the IC package further includes a conductive adhesive electrically connecting the first contact pad to the conductive pillar, wherein the conductive adhesive contacts a sidewall of the conductive pillar.

[0064] In Example 18, Example 15 can further include: wherein the conductive pillar has a height less than a height of the molding material, and the IC package further includes a conductive adhesive electrically connecting the first contact pad to the conductive pillar, wherein the conductive adhesive contacts a sidewall of the molding material.

[0065] In Example 19, a method for making an integrated circuit package can include: generating copper pillars on corresponding exposed bonding pads of a substrate; disposing a molding material around and on the generated copper pillars; simultaneously removing the molding material and a portion of the generated copper pillars so that the generated copper pillars are flat relative to each other within a deviation of five microns; and reflowing solder balls to electrically couple the contact pads of the die to the copper pillars and the interconnect circuitry of the substrate.

[0066] In Example 20, Example 19 may further include: after removing the molding material and a portion of the generated copper pillar, etching another portion of the copper pillar to recess the copper pillar in the molding material; before reflowing the solder ball, attaching the solder ball to the corresponding copper pillar; and wherein, after reflowing, the solder ball is embedded in a portion of the surface and a portion of the sidewall of the molding material.

[0067] In Example 21, Example 19 can further include: after removing the portion of the molding material and the generated conductive pillar, removing another portion of the molding material to recess the molding material relative to the conductive pillar.

[0068] In Example 22, Example 21 can also include: wherein removing the other portion of the molding material includes photoimaging the molding material.

[0069] In Example 23, Example 21 can also include disposing a conductive adhesive over the die before electrically connecting the die to the substrate.

[0070] In Example 24, Example 23 can further include: wherein electrically connecting the die to the conductive pillars includes reflowing the conductive adhesive to electrically connect contact pads of the die to corresponding ones of the conductive pillars.

[0071] In Example 25, Example 24 can further include: wherein the conductive adhesive embeds the exposed portion of the sidewall of the conductive pillar after reflow.

[0072] In Example 26, Example 25 can further include: after removing the molding material and a portion of the generated conductive pillar, forming a contact pad on the corresponding conductive pillar.

[0073] In Example 27, Example 26 can further include: wherein forming the contact pad includes forming the contact pad having a width greater than a width of the bonding pad.

[0074] In Example 28, Example 27 can further include disposing a conductive adhesive over each of the contact pads before electrically connecting the die to the substrate.

[0075] Each of these non-limiting examples can stand on its own, or can be combined in various permutations or combinations with one or more of the other examples.

[0076] The above detailed description includes reference to the accompanying drawings, which form a part of the detailed description. The accompanying drawings show specific embodiments by way of example, in which the methods, devices and systems discussed herein can be put into practice. These embodiments are also referred to as "examples" herein. Such examples can include elements other than those shown or described. However, the inventors also contemplate some examples in which only those elements shown or described are provided. In addition, or for a specific example (or one or more aspects thereof), or for other examples (or one or more aspects thereof) shown or described herein, the inventors also contemplate examples of any combination or permutation of those elements (or one or more aspects thereof) shown or described.

[0077] In this document, as is common in patent documents, the term "a" or "an" is used to include one or more than one, independent of any other instance or use of "at least one" or "one or more". In this document, unless otherwise indicated, the term "or" is used to refer to a non-exclusive or, such that "A or B" includes "A but not B", "B but not A", and "A and B". In this document, the terms "including" and "wherein" are used as the plain English equivalents of the corresponding terms "including" and "wherein". Similarly, in the claims below, the terms "including" and "comprising" are open-ended, that is, systems, devices, products, compositions, formulations, or processes that include elements other than those listed after such terms in the claim are still considered to fall within the scope of the claim. In addition, in the claims below, the terms "first", "second", and "third", etc. are used merely as labels and are not intended to impose numerical requirements on their objects.

[0078] The above description is intended to illustrate rather than limit. For example, the examples described above (or one or more aspects thereof) can be used in combination with each other. Other embodiments can be used by those of ordinary skill in the art after reviewing the above description. An abstract is provided to allow the reader to quickly determine the nature of the technical disclosure. Submitting an abstract is based on the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Similarly, in the above detailed description, various features can be grouped together to simplify the present disclosure. This should not be interpreted as an expectation that the disclosed features that are not claimed for protection are necessary for any claim. On the contrary, the subject matter of the invention may be less than all the features of the disclosed specific embodiments. Therefore, the following claims are hereby incorporated into the detailed description as examples or embodiments, wherein each claim is self-contained as a separate embodiment, and it is contemplated that such embodiments can be combined with each other in various combinations or permutations. The scope of the present invention should be determined with reference to the attached claims together with the full range of equivalents to which such claims are entitled.

Claims

1. An integrated circuit (IC) package, comprising: a substrate comprising electrical pathways; a plurality of bonding pads at a top surface of the substrate; a plurality of conductive posts electrically connected to respective bonding pads, each of the conductive posts having a height of less than 30 microns, wherein the heights of the plurality of conductive posts are within five microns of each other; an insulating material between adjacent ones of the plurality of conductive pillars, wherein a height of the insulating material is within 5 microns of a height of one of the conductive pillars; and A die is electrically coupled to the plurality of conductive pillars.

2. The IC package of claim 1, wherein: The IC package includes at least four conductive pillars.

3. The IC package of claim 1, wherein: The die is electrically coupled to the electrical vias in the substrate via the conductive pillars and the bonding pads.

4. The IC package of claim 1, wherein: Each conductive post of the plurality of conductive posts is coupled to a conductive adhesive.

5. The IC package of claim 4, wherein: The conductive adhesive is located between one of the conductive pillars and the die.

6. The IC package of claim 4, wherein: The conductive adhesive is solder.

7. The IC package of claim 6, wherein: For each of the conductive pillars, a portion of the solder extends along a sidewall of the conductive pillar.

8. The IC package of claim 1, wherein: The plurality of conductive pillars include copper.

9. The IC package of claim 1, wherein: The substrate includes a plurality of contact pads on a bottom surface of the substrate, the bottom surface opposite the top surface.

10. The IC package of claim 1, wherein: The die includes contact pads electrically coupled to the plurality of conductive pillars.

11. A package comprising: A substrate, comprising: a first surface having a plurality of contact pads; a second surface opposite to the first surface, the second surface having a plurality of bonding pads; and an electrical path between one of the contact pads and one of the bonding pads; a plurality of conductive posts electrically connected to respective ones of the plurality of bond pads, wherein heights of the plurality of conductive posts are within five microns of one another; an insulating material between adjacent ones of the plurality of conductive pillars, wherein a height of the insulating material is within 5 microns of a height of one of the conductive pillars; and A die is electrically coupled to the plurality of conductive pillars.

12. The package of claim 11, further comprising an external device coupled to the plurality of contact pads.

13. The package of claim 12, wherein: The external device is a circuit board.

14. The package of claim 12, wherein: The external device is a second die.

15. The package of claim 11, wherein: A width of one of the plurality of contact pads is greater than a width of one of the plurality of bonding pads.

16. The package of claim 11, wherein: The die is a system on a chip (SoC).

17. An integrated circuit (IC) package, comprising: a substrate comprising electrical pathways; a plurality of bonding pads at a top surface of the substrate, the bonding pads coupled to the electrical pathways in the substrate; a plurality of copper pillars electrically connected to respective bond pads, each copper pillar having a height of less than 30 microns, wherein the heights of the plurality of copper pillars are within five microns of each other; an insulating material between adjacent ones of the plurality of copper pillars, wherein a height of the insulating material is within 5 microns of a height of one of the copper pillars; solder attached to the plurality of copper pillars, wherein portions of the solder are along sidewalls of the copper pillars; as well as A die is electrically coupled to the plurality of copper pillars.

18. The IC package of claim 17, wherein: The remaining portion of the solder is located between the copper pillar and the die.

19. The IC package of claim 17, wherein: The IC package includes at least five copper pillars.

20. The IC package of claim 17, wherein: The die includes a contact pad electrically coupled to the bond pad through the plurality of copper pillars and the solder.

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