Longitudinal stacking digital isolator packaging structure and manufacturing method

Abstract

The invention provides a longitudinally stacked digital isolator packaging structure and a manufacturing method, and belongs to the technical field of isolator packaging. According to the packaging structure, a second digital isolation chip and a first digital isolation chip are longitudinally stacked, and an insulating layer is arranged between the second digital isolation chip and the first digital isolation chip; the coupling transmission structure comprises a first coupling transmission unit and a second coupling transmission unit which are oppositely arranged on the sides, close to each other, of the first digital isolation chip and the second digital isolation chip, and the first coupling transmission unit and the second coupling transmission unit are electrically connected with the first digital isolation chip and the second digital isolation chip respectively; the first electric signal conduction assembly is arranged on the side, facing the insulating layer, of the first digital isolation chip, the second electric signal conduction assembly is arranged on the side, facing the insulating layer, of the second digital isolation chip, and the first electric signal conduction assembly and the second electric signal conduction assembly are electrically connected with the first digital isolation chip and the second digital isolation chip respectively. Longitudinal stacked packaging of the digital isolator is realized.

Description

Technical Field

[0001] The present invention belongs to the technical field of digital isolators, wafer reconstruction, wafer rewiring, and flip-chip packaging, and specifically relates to a vertically stacked digital isolator packaging structure and a manufacturing method thereof. Background Art

[0002] In the prior art, a digital isolator is usually composed of more than two chips, which are divided into a high-voltage side chip and a low-voltage side chip. The high-voltage side chip and the low-voltage side chip transmit signals through a coupled transmission structure (for example, a transformer or a capacitor). The high-voltage side chip and the low-voltage side are placed horizontally on a substrate or a frame. The electrical connection between the coupled transmission structures on both sides is realized by a wire bonding process. Because high-voltage isolation needs to be ensured, the lateral spacing between the high-voltage side chip and the low-voltage side chip is relatively large, resulting in a longer bonding wire between the transformers or capacitors on both sides. The parasitic impedance introduced by the bonding wire will affect the transmission quality of the signal, and the overall volume of the digital isolator device formed by this connection method is relatively large. Secondly, the shape and height of the bonding wire in the wire bonding process are affected by many factors in actual production, and the fluctuation range is large, which leads to an uncontrolled distance between the bonding wire and the chip substrate, resulting in poor consistency in the isolator's withstand voltage capability, and a greater redundancy needs to be retained during design. Summary of the invention

[0003] The present disclosure aims to solve at least one of the technical problems existing in the prior art and provides a vertically stacked digital isolator packaging structure and a manufacturing method.

[0004] In one aspect of the present disclosure, a vertically stacked digital isolator packaging structure is provided, comprising:

[0005] A first digital isolation chip, a second digital isolation chip and an insulating layer, wherein the second digital isolation chip and the first digital isolation chip are stacked vertically with the insulating layer disposed therebetween;

[0006] A coupling transmission structure, wherein the coupling transmission structure comprises a first coupling transmission unit and a second coupling transmission unit which are arranged on a side close to the first digital isolation chip and the second digital isolation chip relative to each other, and the first coupling transmission unit and the second coupling transmission unit are electrically connected to the first digital isolation chip and the second digital isolation chip respectively;

[0007] A first electrical signal conducting component and a second electrical signal conducting component, wherein the first electrical signal conducting component is arranged on a side of the first digital isolation chip facing the insulating layer, and the second electrical signal conducting component is arranged on a side of the second digital isolation chip facing the insulating layer, and the first electrical signal conducting component and the second electrical signal conducting component are electrically connected to the first digital isolation chip and the second digital isolation chip, respectively.

[0008] Optionally, a packaging layer wrapping the first digital isolation chip is provided on a side of the first digital isolation chip facing away from the insulating layer.

[0009] Optionally, the first coupling transmission unit is arranged inside or outside the first digital isolation chip;

[0010] When the first coupling transmission unit is disposed outside the first digital isolation chip, a first interconnection structure is disposed between the first coupling transmission unit and the first digital isolation chip.

[0011] Optionally, the second coupling transmission unit is arranged inside or outside the second digital isolation chip;

[0012] When the second coupling transmission unit is disposed outside the second digital isolation chip, a second interconnection structure is disposed between the second coupling transmission unit and the second digital isolation chip.

[0013] Optionally, the first coupling transmission unit and the second coupling transmission unit are capacitor plates; or,

[0014] The first coupling transmission unit and the second coupling transmission unit are electromagnetic coils; or,

[0015] The first coupling transmission unit and the second coupling transmission unit are giant magnetoresistance coupling units.

[0016] Optionally, the first electrical signal conducting component includes at least two first electrical signal conducting members, each of which includes a first conductive portion and a first wire portion; wherein,

[0017] The first conductive portion is electrically connected to the first digital isolation chip, one end of the first wire portion is electrically connected to the first conductive portion, and the other end of the first wire portion passes through the insulating layer.

[0018] Optionally, the second electrical signal conducting component includes at least two second electrical signal conducting members, each of which includes a second conductive portion and a second wire portion; wherein,

[0019] The second conductive portion is electrically connected to the second digital isolation chip, one end of the second wire portion is electrically connected to the second conductive portion, and the other end of the second wire portion is located on the insulating layer.

[0020] Another aspect of the present disclosure provides a method for manufacturing a vertically stacked digital isolator packaging structure, the manufacturing method comprising:

[0021] S1. providing a first digital isolation chip including a first coupling transmission unit;

[0022] forming a first conductive portion on the first digital isolation chip, and forming an insulating layer on the first digital isolation chip and the first conductive portion;

[0023] A metallization layer is formed on the insulating layer, wherein the metallization layer includes a first wire portion electrically connected to the first conductive portion, a second wire portion and a second coupling transmission unit; the second coupling transmission unit and the first coupling transmission unit are arranged opposite to each other to form a coupling transmission structure;

[0024] S2, providing a second digital isolation chip;

[0025] S3. Flip-chip the second digital isolation chip onto the second conductor portion and the second coupling transmission unit.

[0026] Another aspect of the present disclosure provides a method for manufacturing a vertically stacked digital isolator packaging structure, the manufacturing method comprising:

[0027] S1. Provide a first digital isolation chip;

[0028] forming a first coupling transmission unit and a first conductive portion on the first digital isolation chip;

[0029] forming an insulating layer on the first digital isolation chip, the first coupling transmission unit and the first conductive portion;

[0030] forming a metallization layer on the insulating layer, wherein the metallization layer includes a first wire portion electrically connected to the first conductive portion, a second wire portion, and a second coupling transmission unit, wherein the second coupling transmission unit and the first coupling transmission unit are arranged opposite to each other to form a coupling transmission structure;

[0031] S2, providing a second digital isolation chip;

[0032] S3. Flip-chip the second digital isolation chip onto the second conductor portion and the second coupling transmission unit.

[0033] Optionally, the step S1 further includes:

[0034] A packaging layer wrapping the first digital isolation chip is formed on a side of the first digital isolation chip away from the insulating layer.

[0035] The present disclosure proposes a vertically stacked digital isolator packaging structure and a manufacturing method. The vertically stacked digital isolator packaging structure includes: a first digital isolation chip, a second digital isolation chip and an insulating layer, wherein the second digital isolation chip and the first digital isolation chip are stacked vertically and the insulating layer is arranged between the two; a coupling transmission structure, wherein the coupling transmission structure includes a first coupling transmission unit and a second coupling transmission unit which are arranged on the side close to the first digital isolation chip and the second digital isolation chip relative to each other, and the first coupling transmission unit and the second coupling transmission unit are respectively electrically connected to the first digital isolation chip and the second digital isolation chip; a first electrical signal conduction component and a second electrical signal conduction component, wherein the first electrical signal conduction component is arranged on the side of the first digital isolation chip facing the insulating layer, and the second electrical signal conduction component is arranged on the side of the second digital isolation chip facing the insulating layer, and the first electrical signal conduction component and the second electrical signal conduction component are respectively electrically connected to the first digital isolation chip and the second digital isolation chip. The present disclosure realizes the vertical stacking packaging of the digital isolator through wafer reconstruction, rewiring, chip flipping and other technologies, reduces the volume of the digital isolator product, improves the internal voltage resistance of the digital isolator, and reduces the parasitic impedance between the original low-voltage side inductors or capacitors. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is a structural schematic diagram of the vertically stacked digital isolator packaging structure of Embodiment 1 of the present disclosure;

[0037] Figure 2 A schematic diagram of a method for manufacturing a vertically stacked digital isolator packaging structure according to Embodiment 2 of the present disclosure;

[0038] Figure 3 A schematic diagram of the physical distance in the vertically stacked digital isolator packaging structure of Embodiment 3 of the present disclosure;

[0039] Figure 4 It is a structural schematic diagram of a vertically stacked digital isolator packaging structure of Embodiment 4 of the present disclosure;

[0040] Figure 5 A schematic diagram of a method for manufacturing a vertically stacked digital isolator packaging structure according to Embodiment 5 of the present disclosure;

[0041] Figure 6 Schematic diagram of the physical distance in the vertically stacked digital isolator packaging structure of Example 5 of the present disclosure. DETAILED DESCRIPTION

[0042] In order to enable those skilled in the art to better understand the technical solution of the present disclosure, the present disclosure is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. It should be understood that the specific embodiments described herein are only used to explain the present disclosure and are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0043] Example 1

[0044] like Figure 1 As shown, this embodiment proposes a vertically stacked digital isolator packaging structure, including: a first digital isolation chip 101, a first coupling transmission unit 102, a second digital isolation chip 201, a second coupling transmission unit 106c, an insulating layer 105, and a first electrical signal conduction component and a second electrical signal conduction component. The second digital isolation chip 201 is stacked vertically with the first digital isolation chip 101 and an insulating layer 105 is arranged between the two. The first surface of the first digital isolation chip 101 is arranged opposite to the first surface of the second digital isolation chip 201. The first coupling transmission unit 102 and the second coupling transmission unit 106c, which are arranged on the side close to the first digital isolation chip 101 and the second digital isolation chip 201, form a coupling transmission structure, that is, the first coupling transmission unit 102 is located on the side of the first digital isolation chip 101 facing the second digital isolation chip 201, and the second coupling transmission unit 106c is located on the side of the first digital isolation chip 101 facing the second digital isolation chip 201. 06c is located on the side of the second digital isolation chip 201 facing the first digital isolation chip 101, and the first coupling transmission unit 102 and the second coupling transmission unit 106c are electrically connected to the first digital isolation chip 101 and the second digital isolation chip 201 respectively; the first electrical signal conduction component is arranged on the side of the first digital isolation chip 101 facing the insulating layer 105, and the second electrical signal conduction component is arranged on the side of the second digital isolation chip 201 facing the insulating layer 105, and the first electrical signal conduction component and the second electrical signal conduction component are electrically connected to the first digital isolation chip 101 and the second digital isolation chip 201 respectively.

[0045] It should be further explained that the present embodiment does not specifically limit the positional relationship between the first digital isolation chip and the first coupling transmission unit, and between the second digital isolation chip and the second coupling transmission unit. For example, the first coupling transmission unit can be arranged inside the first digital isolation chip, or it can be arranged outside the first digital isolation chip. Of course, when the first coupling transmission unit is arranged outside the first digital isolation chip, a first interconnection structure should be arranged between the first coupling transmission unit and the first digital isolation chip. Similarly, the second coupling transmission unit can also be arranged inside the second digital isolation chip, or it can be arranged outside. When the second coupling transmission unit is arranged outside the second digital isolation chip, a second interconnection structure should be arranged between the second coupling transmission unit and the second digital isolation chip.

[0046] Specifically, Figure 1 As shown, the first coupling transmission unit 102 is disposed inside the first digital isolation chip 101 . The second coupling transmission unit 106 c is disposed outside the second digital isolation chip 201 , and the second coupling transmission unit 106 c is located on a side of the second digital isolation chip 201 facing the insulation layer 105 .

[0047] Furthermore, if Figure 1 As shown, when the second coupling transmission unit 106c is arranged outside the second digital isolation chip 201, a second interconnection structure is arranged between the second coupling transmission unit 106c and the second digital isolation chip 201. The second interconnection structure includes a first metal pad 108a and a first metal ball 109a which are sequentially arranged on the first surface of the second digital isolation chip 201 facing the insulating layer 105, the first metal pad 108a is electrically connected to the second digital isolation chip 201, and the first metal ball 109a is electrically connected to the second coupling transmission unit 106c. Of course, the second interconnection structure can also adopt an electrical connection structure such as conductive glue, which is not specifically limited.

[0048] It should be noted that this embodiment does not specifically limit the types of the first coupling transmission unit and the second coupling transmission unit. They can be capacitor plates to form capacitive coupling, electromagnetic coils to form inductive coupling, or giant magnetoresistance coupling units to form magnetic coupling.

[0049] like Figure 1 As shown, the first coupling transmission unit 102 and the second coupling transmission unit 106c are capacitor plates, that is, the first coupling transmission unit 102 is one of the capacitor plates, and the second coupling transmission unit 106c is the other capacitor plate, forming a capacitive coupling structure to achieve isolated transmission of signals.

[0050] It should be noted that the first coupling transmission unit and the second coupling transmission unit given in this embodiment are only exemplary. In other preferred embodiments, the first coupling transmission unit and the second coupling transmission unit can also be electromagnetic coils, that is, the first coupling transmission unit is one of the electromagnetic coils, and the second coupling transmission unit is another electromagnetic coil, forming an inductive coupling structure to achieve isolated transmission of signals. Alternatively, the first coupling transmission unit and the second coupling transmission unit are giant magnetoresistance coupling units, that is, the first coupling transmission unit is one of the giant magnetoresistance coupling units, and the second coupling transmission unit is another giant magnetoresistance coupling unit.

[0051] It should be further explained that this embodiment does not specifically limit the specific structures of the first electrical signal conducting component and the second electrical signal conducting component.

[0052] Specifically, Figure 1 As shown, the first electrical signal conducting component includes at least two first electrical signal conducting members, each of which includes a first conductive portion and a first wire portion; wherein the first conductive portion is electrically connected to the first digital isolation chip 101, one end of the first wire portion is electrically connected to the first conductive portion, and the other end of the first wire portion passes through the insulating layer 105. The first conductive portion adopts a third metal pad 103, and the third metal pad 103 is located on the first surface of the first digital isolation chip 101. The first wire portion includes a first metal wire 106a and a second metal wire 106b, and the first metal wire 106a is also located on the first surface of the first digital isolation chip 101 and is electrically connected above the third metal pad 103. The first end of the second metal wire 106b is electrically connected to the first metal wire 106a, and the second end of the second metal wire 106b passes through the insulating layer 105.

[0053] Specifically, Figure 1 As shown, the second electrical signal conducting component includes at least two second electrical signal conducting members, each of which includes a second conductive portion and a second wire portion; wherein the second conductive portion is electrically connected to the second digital isolation chip 201, one end of the second wire portion is electrically connected to the second conductive portion, and the other end of the second wire portion is located at the insulating layer 105. The second conductive portion includes a second metal pad 108b and a second metal ball 109b, the second metal pad 108b and the first metal pad 108a are spaced apart and arranged on the first surface of the second digital isolation chip 201, that is, on the side facing the insulating layer 105, the second metal ball 109b is electrically connected between the second metal pad 108b and the second wire portion, and the second wire portion uses a third metal wire 106d.

[0054] It should be noted that, in addition to the metal pads and metal wires, the first conductive portion, the first wire portion, the second conductive portion and the second wire portion of this embodiment may also be made of conductive adhesive.

[0055] It should be noted that the insulating layer of this embodiment may be made of polyimide, so that the first coupling transmission unit 102 and the second coupling transmission unit 106c have a high withstand voltage effect.

[0056] Furthermore, in order to provide better mechanical support and insulation protection functions, such as Figure 1 As shown, a packaging layer 104 wrapping the first digital isolation chip 101 is disposed on one side of the first digital isolation chip 101 away from the insulating layer 105 . The packaging layer 104 wraps the second surface of the first digital isolation chip 101 , and the packaging layer may be made of plastic or quartz.

[0057] Furthermore, if Figure 1 As shown, an insulating filling layer 107 wrapping the second digital isolation chip 201 is provided between the second digital isolation chip 201 and the insulating layer 105 and is used to fill the pores at the bottom of the second digital isolation chip. The filling layer may be made of filling glue.

[0058] It should be noted that this embodiment does not specifically limit the high-voltage side and the low-voltage side, and the first digital isolation chip can be used as both a high-voltage side chip and a low-voltage side chip. For example, when the first digital isolation chip is used as a high-voltage side chip, the second digital isolation chip is used as a low-voltage side chip, and when the first digital isolation chip is used as a low-voltage side chip, the second digital isolation chip is used as a high-voltage side chip.

[0059] In addition, this embodiment does not specifically limit the transmitting end and receiving end of the digital signal. One of the first digital isolation chip and the second digital isolation chip serves as the transmitting end, and the other of the first digital isolation chip and the second digital isolation chip serves as the receiving end; or, both the first digital isolation chip and the second digital isolation chip can serve as the transmitting end and the receiving end, and when one of the digital isolation chips serves as the receiving end, the other digital isolation chip serves as the transmitting end.

[0060] In this embodiment, by vertically stacking the first digital isolation chip, the first coupling transmission unit, the second digital isolation chip, and the second coupling transmission unit, vertical stacking packaging of the digital isolator is achieved, which effectively reduces the product volume of the digital isolator and improves the internal voltage resistance of the digital isolator. High-voltage isolation signal transmission on both sides of the device can be achieved inside the structure, and there is no need to set bonding wires between the coupling structures, which helps to reduce the parasitic impedance between the coupling transmission structures.

[0061] Example 2

[0062] like Figure 2 As shown, this embodiment provides a method for manufacturing a vertically stacked digital isolator packaging structure, comprising the following steps:

[0063] S1. Provide a first digital isolation chip and perform corresponding processing on the first digital isolation chip. Specifically, step S1 may include step S1A, step S1B, and step S1C.

[0064] Specifically, step S1A includes: providing a first digital isolator wafer 100, such as Figure 2 As shown in (ab), the first digital isolator wafer 100 includes multiple first digital isolation chips 101, that is, a first digital isolation chip 101 is provided, and the first digital isolation chip 101 has a first coupling transmission unit 102 inside, such as a capacitor plate, an inductor coil or a giant magnetoresistance coupling unit.

[0065] In other preferred solutions, the first digital isolation chip of this embodiment may also be a chip with an exposed pad, such as Figure 2 As shown in (b) , a third metal pad 103 is provided on the first surface of the first digital isolation chip 101 .

[0066] In some preferred embodiments, Figure 2 As shown in (cd) in FIG. 1 , the back side of the first digital isolator wafer 100 may be thinned first, and then molded with a plastic encapsulation material to form an encapsulation layer 104. That is, an encapsulation layer 104 is formed on the second surface of the first digital isolation chip 101, and vertical stacking packaging is performed on the wafer of this structure. The encapsulation layer 104 may provide better mechanical support and insulation protection functions. Of course, in some other preferred schemes, the back side of the first digital isolator wafer 100 may not be thinned or the encapsulation layer may not be formed, and vertical stacking packaging may be performed directly on the wafer of this structure.

[0067] Step S1B includes: forming a first conductive portion on the first digital isolation chip, and forming an insulating layer on the first digital isolation chip and the first conductive portion.

[0068] Specifically, Figure 2 As shown in (bd) in FIG. 1 , a third metal pad 103 is formed on the first surface of the first digital isolation chip 101. Of course, the first digital isolation chip 101 with an exposed pad may also be directly used.

[0069] Furthermore, if Figure 2 As shown in (e) in FIG. 1 , metal is electroplated on the third metal pad 103 to form a first metal wire 106 a , and then polyimide is spread on the entire surface of the digital isolator wafer 100 to form an insulating layer 105 .

[0070] Step S1C includes: forming a metallization layer on the insulating layer, the metallization layer including a first wire portion electrically connected to the first conductive portion, a second wire portion and a second coupling transmission unit; the second coupling transmission unit and the first coupling transmission unit are arranged relative to each other to form a coupling transmission structure.

[0071] Specifically, Figure 2 As shown in (ef) in FIG. 1 , a via hole 105a is etched on the insulating layer 105, and metal is electroplated on the surface of the insulating layer 105 and in the via hole 105a to form a second metal wire 106b, a second coupling transmission unit 106c, and a third metal wire 106d, respectively. The second metal wire 106b is electrically connected to the first metal wire 106a and serves as a metal wire of the input and output pads. The second coupling transmission unit 106c is a capacitor plate, an inductor coil, or a giant magnetoresistance coupling unit that corresponds to the first coupling transmission unit 102. The third metal wire 106d serves as a metal wire of the input and output pads of the second digital isolation chip 201. In other words, the third metal pad 103 forms a first conductive portion, the first metal wire 106a and the second metal wire 106b form a first wire portion, the second metal pad 108b and the second metal ball 109b form a second conductive portion, and the third metal wire 106d forms a second wire portion.

[0072] S2, providing a second digital isolation chip 201. Specifically, as Figure 2 As shown in (gi), a second digital isolator wafer 200 is provided, and the second digital isolator wafer 200 includes a plurality of second digital isolation chips 201, and a first metal pad 108a and a second metal pad 108b are arranged on the first surface of the second digital isolation chip 201, and a first metal implant ball 109a is electrically connected to a side of the first metal pad 108a away from the second digital isolation chip 201, and a second metal implant ball 109b is electrically connected to a side of the second metal pad 108b away from the second digital isolation chip 201. Specifically, as Figure 2 As shown in (gi), based on the second digital isolation chip structure, the second digital isolator wafer dicing road is cut to separate a single second digital isolation chip 201.

[0073] S3, flip-mounting the second digital isolation chip 201 on the second conductor portion and the second coupling transmission unit.

[0074] Specifically, the second digital isolation chip 201 is flipped on the second coupling transmission unit 106c and the third metal wire 106d above the first digital isolation chip 101, so that the first surface of the second digital isolation chip 201 is opposite to the first surface of the first digital isolation chip 101, and welding is performed by reflow soldering or hot pressing welding.

[0075] Furthermore, if Figure 2As shown in (kl), the bottom gap of the second digital isolation chip 201 is filled with bottom filling glue, and an insulating filling layer 107 is formed between the second digital isolation chip 201 and the insulating layer 105 to wrap the second coupling transmission unit 106c, the first metal pad 108a and the first metal planting ball 109a, the second metal pad 108b and the second metal planting ball 109b, and part of the third metal wire 106d. The first digital isolator wafer 100 that has completed the above steps is cut along the cutting path to separate the final vertically stacked digital isolator chip structure. For the specific structure, please refer to Example 1.

[0076] It should be noted that steps S1 and S2 shown in this embodiment are independent and there is no limitation on their order. Step S1 and step S2 can be performed simultaneously or in any order, as long as the contents of steps S1 and S2 are completed before step S3 without affecting the flip-chip soldering in step S3.

[0077] This embodiment realizes vertical stacking packaging of digital isolators through wafer reconstruction, rewiring, chip flipping and other technologies, reduces the volume of digital isolators, improves the internal voltage resistance and consistency of digital isolators, and reduces the parasitic impedance between coupled transmission structures.

[0078] Example 3

[0079] like Figure 3 As shown, this embodiment provides the physical distance of the vertically stacked digital isolator chip structure. The digital isolator chip structure is the same as that of Embodiment 1 and Embodiment 2. The above structure can realize high-voltage isolated signal transmission on both sides of the device. In the final packaging structure, the external filling medium is a plastic packaging material with a dielectric strength of 15V / μm, the polyimide dielectric strength of the insulating layer is 300V / μm, and the silicon dioxide dielectric strength is 600V / μm. Taking the digital isolator packaging structure meeting the DC5000V isolation withstand voltage as an example, it is necessary to pay attention to the following physical spacings in the above structure. The isolation withstand voltage capability that needs to be met is calculated according to the minimum value of the following spacings and the dielectric strength of the filling medium and air in the insulating layer:

[0080] ①, X1 is the minimum horizontal distance between the second metal wire 106b led out from the first digital isolation chip 101 and the edge of the second digital isolation chip 201. The filling medium in the middle is plastic packaging material with a dielectric strength of 15V / μm. In order to achieve a DC 5000V isolation withstand voltage, it is necessary to ensure that X1 is at least 400μm.

[0081] ②, Y1+Y2 is the shortest distance between the first coupling transmission unit 102 and the second coupling transmission unit 106c, Y1 is the thickness of the insulating layer 105, the dielectric strength is 300V / μm, and the conventional thickness is 20μm, and Y2 is the thickness of the silicon dioxide covering the metal of the second digital isolation chip 201, the dielectric strength is 600V / μm, and the conventional thickness is about 4μm, which can meet the DC 5000V isolation withstand voltage requirement.

[0082] ③. X2 is the minimum horizontal distance from the third metal wire 106d connected to the second digital isolation chip 201 to the edge of the insulating layer 105, and Y1 is the thickness of the insulating layer 105. The two together are the minimum creepage distance from the third metal wire 106d to the first digital isolation chip 101. The filling medium is plastic packaging material with a dielectric strength of 15V / μm. Therefore, in order to meet the isolation withstand voltage of DC 5000V, it is necessary to ensure that X2+Y1 is at least 400μm.

[0083] It should be understood that the values ​​of X1, X2, Y1, and Y2 given in this embodiment are only preferred values ​​and are only for illustrative purposes. In fact, the values ​​of the above distances can be greater than or equal to the above preferred values ​​and are not listed one by one here.

[0084] Example 4

[0085] like Figure 4 As shown, this embodiment proposes a vertically stacked digital isolator packaging structure, including: a first digital isolation chip 101, a first coupling transmission unit 102, a second digital isolation chip 201, a second coupling transmission unit 106c, an insulating layer 105, and a first electrical signal conduction component and a second electrical signal conduction component; wherein the second digital isolation chip 201 is vertically stacked with the first digital isolation chip 101 and an insulating layer 105 is arranged between the two, and the first surface of the first digital isolation chip 101 is arranged opposite to the first surface of the second digital isolation chip 201; the first digital isolation chip 101 and the second digital isolation chip 201 are arranged opposite to each other. The first coupling transmission unit 102 and the second coupling transmission unit 106c on the side close to the chip 201 form a coupling transmission structure, and the first coupling transmission unit 102 and the second coupling transmission unit 106c are electrically connected to the first digital isolation chip 101 and the second digital isolation chip 201 respectively; the first electrical signal conduction component is arranged on the side of the first digital isolation chip 101 facing the insulating layer 105, and the second electrical signal conduction component is arranged on the side of the second digital isolation chip 201 facing the insulating layer 105, and the first electrical signal conduction component and the second electrical signal conduction component are electrically connected to the first digital isolation chip 101 and the second digital isolation chip 201 respectively.

[0086] It should be further explained that this embodiment also does not specifically limit the positional relationship between the first digital isolation chip and the first coupling transmission unit, the second digital isolation chip and the second coupling transmission unit. For example, the first coupling transmission unit can be arranged inside the first digital isolation chip or outside. Of course, when the first coupling transmission unit is arranged outside the first digital isolation chip, a first interconnection structure should be arranged between the first coupling transmission unit and the first digital isolation chip. Similarly, the second coupling transmission unit can be arranged inside the second digital isolation chip or outside. When the second coupling transmission unit is arranged outside the second digital isolation chip, a second interconnection structure should be arranged between the second coupling transmission unit and the second digital isolation chip.

[0087] Specifically, Figure 4 As shown, the first coupling transmission unit 102 is disposed inside the first digital isolation chip 101 . The second coupling transmission unit 106 c is disposed outside the second digital isolation chip 201 , and the second coupling transmission unit 106 c is located on a side of the second digital isolation chip 201 facing the insulation layer 105 .

[0088] Furthermore, if Figure 4 As shown, when the second coupling transmission unit 106c is arranged outside the second digital isolation chip 201, a second interconnection structure is arranged between the second coupling transmission unit 106c and the second digital isolation chip 201. The second interconnection structure includes a first metal pad 108a and a first metal ball 109a which are sequentially arranged on the first surface of the second digital isolation chip 201 facing the insulating layer 105, the first metal pad 108a is electrically connected to the second digital isolation chip 201, and the first metal ball 109a is electrically connected between the first metal pad 108a and the second coupling transmission unit 106c. Of course, the second interconnection structure given in this embodiment is only an exemplary description, and the second interconnection structure can also adopt an electrical connection structure such as conductive glue.

[0089] It should be noted that this embodiment does not specifically limit the types of the first coupling transmission unit and the second coupling transmission unit. They can be capacitor plates to form capacitive coupling, electromagnetic coils to form inductive coupling, or giant magnetoresistance coupling units to form magnetic coupling.

[0090] like Figure 4 As shown, the first coupling transmission unit 102 and the second coupling transmission unit 106c are capacitor plates, that is, the first coupling transmission unit 102 is one of the capacitor plates, and the second coupling transmission unit 106c is the other capacitor plate, forming a capacitive coupling structure to achieve isolated transmission of signals.

[0091] Similarly, the first coupling transmission unit and the second coupling transmission unit given in this embodiment are also only exemplary. In other preferred embodiments, the first coupling transmission unit and the second coupling transmission unit can also be electromagnetic coils, that is, the first coupling transmission unit is one of the electromagnetic coils, and the second coupling transmission unit is another electromagnetic coil, forming an inductive coupling structure to achieve isolated transmission of signals. Alternatively, the first coupling transmission unit and the second coupling transmission unit are giant magnetoresistance coupling units, that is, the first coupling transmission unit is one of the giant magnetoresistance coupling units, and the second coupling transmission unit is another giant magnetoresistance coupling unit.

[0092] It should be further explained that the present embodiment does not impose any specific limitation on the specific structures of the first electrical signal conducting component and the second electrical signal conducting component, as long as electrical connection is achieved.

[0093] Specifically, Figure 4 As shown, the first electrical signal conducting component includes at least two first electrical signal conducting members, each of which includes a first conductive portion and a first wire portion; wherein the first conductive portion is electrically connected to the first digital isolation chip 101, one end of the first wire portion is electrically connected to the first conductive portion, and the other end of the first wire portion passes through the insulating layer 105. The first conductive portion adopts a third metal pad 103, and the third metal pad 103 is located on the first surface of the first digital isolation chip 101. The first wire portion includes a first metal wire 106a and a second metal wire 106b, and the first metal wire 106a is also located on the first surface of the first digital isolation chip 101 and is electrically connected above the third metal pad 103. The first end of the second metal wire 106b is electrically connected to the first metal wire 106a, and the second end of the second metal wire 106b passes through the insulating layer 105.

[0094] Specifically, Figure 4 As shown, the second electrical signal conducting component includes at least two second electrical signal conducting members, each of which includes a second conductive portion and a second wire portion; wherein the second conductive portion is electrically connected to the second digital isolation chip 201, one end of the second wire portion is electrically connected to the second conductive portion, and the other end of the second wire portion is located at the insulating layer 105. The second conductive portion includes a second metal pad 108b and a second metal implant ball 109b, the second metal pad 108b is spaced apart from the first metal pad 108a and is disposed on the first surface of the second digital isolation chip 201 facing the insulating layer 105, the second metal implant ball 109b is electrically connected between the second metal pad 108b and the second wire portion, and the second wire portion uses a third metal wire 106d.

[0095] It should be noted that, in addition to using structures such as metal pads and metal wires, the first conductive portion, the first wire portion, the second conductive portion and the second wire portion of this embodiment may also use conductive adhesive.

[0096] It should be noted that the insulating layer of this embodiment may be made of polyimide, so that the first coupling transmission unit 102 and the second coupling transmission unit 106c have a high withstand voltage effect.

[0097] Furthermore, in order to provide better mechanical support and insulation protection functions, such as Figure 4 As shown, a side of the first digital isolation chip 101 facing away from the insulating layer 105 and a surface adjacent to the side are provided with a packaging layer 104 that wraps the first digital isolation chip 101, that is, the packaging layer 104 wraps the second surface of the first digital isolation chip 101 and the left surface and the right surface adjacent to the second surface, that is, the peripheral side surface of the first digital isolation chip 101, which is equivalent to the first digital isolation chip being embedded in the packaging layer, which helps to increase the creepage distance, and the packaging layer can be made of plastic packaging material or quartz.

[0098] Furthermore, if Figure 4 As shown, a filling layer 107 wrapping the second digital isolation chip 201 is provided between the second digital isolation chip 201 and the insulating layer 105 and is used to fill the pores at the bottom of the second digital isolation chip 201 . The filling layer may be made of filling glue.

[0099] It should be noted that this embodiment does not specifically limit the high-voltage side and the low-voltage side, and the first digital isolation chip can be used as both a high-voltage side chip and a low-voltage side chip. For example, when the first digital isolation chip is used as a high-voltage side chip, the second digital isolation chip is used as a low-voltage side chip, and when the first digital isolation chip is used as a low-voltage side chip, the second digital isolation chip is used as a high-voltage side chip.

[0100] In addition, this embodiment does not specifically limit the transmitting end and receiving end of the digital signal. One of the first digital isolation chip and the second digital isolation chip serves as the transmitting end, and the other of the first digital isolation chip and the second digital isolation chip serves as the receiving end; or, both the first digital isolation chip and the second digital isolation chip can serve as the transmitting end and the receiving end, and when one of the digital isolation chips serves as the receiving end, the other digital isolation chip serves as the transmitting end.

[0101] In this embodiment, by vertically stacking the first digital isolation chip, the first coupling transmission unit, the second digital isolation chip, and the second coupling transmission unit, vertical stacking packaging of the digital isolator is achieved, which effectively reduces the product volume of the digital isolator and improves the internal voltage resistance of the digital isolator. High-voltage isolation signal transmission on both sides of the device can be achieved inside the structure, and there is no need to set bonding wires between the coupling structures, which helps to reduce the parasitic impedance between the coupling transmission structures.

[0102] Example 5

[0103] like Figure 5 As shown, this embodiment provides a method for manufacturing a vertically stacked digital isolator packaging structure, comprising the following steps:

[0104] S1. Provide a first digital isolation chip and perform corresponding processing on the first digital isolation chip. Specifically, step S1 may include step S1A, step S1B, and step S1C.

[0105] Specifically, step S1A includes: providing a first digital isolator wafer 100, such as Figure 5 As shown in (ab), the first digital isolator wafer 100 includes multiple first digital isolation chips 101, that is, a first digital isolation chip 101 is provided, and the first digital isolation chip 101 has a first coupling transmission unit 102 inside, such as a capacitor plate, an inductor coil or a giant magnetoresistance coupling unit.

[0106] In other preferred solutions, the first digital isolation chip of this embodiment may also be a chip with an exposed pad, such as Figure 5 As shown in (b) , a third metal pad 103 is provided on the first surface of the first digital isolation chip 101 .

[0107] In some preferred embodiments, the encapsulation layer 104 is made of a plastic encapsulation material, such as Figure 5 As shown in (cf), the back side of the first digital isolator wafer 100 can be thinned first, cut along the wafer cutting path to obtain a single first digital isolation chip 101, and one or more first digital isolation chips 101 are arranged in an array with the first surface facing downward on the temporary loading wafer 300, and the upper surface of the temporary loading wafer 300 is molded with a plastic encapsulation material to form a packaging layer 104, and then the temporary loading wafer 300 is separated from the first digital isolation chip 101 and the packaging layer 104 to obtain a wafer with a plastic encapsulation material as the base and the first digital isolation chip 101 embedded in the array. In other words, the packaging layer 104 wraps the first digital isolation chip 101 inside, so that the second surface of the first digital isolation chip 101 and the peripheral side surface adjacent to the second surface are wrapped with the packaging layer, so that the creepage distance from the second metal wire 106b and the third metal wire 106d to the first digital isolation chip 101 is increased, and the creepage path will run along the surface of the insulating layer 105, thereby enhancing the isolation withstand voltage value. Based on this structure, vertical stacking packaging is performed on the wafer.

[0108] Of course, in some other preferred embodiments, the encapsulation layer 104 can also be made of quartz. In the specific manufacturing process, for example, a first cavity for placing the first digital isolation chip 101 can be etched on the first surface of the quartz wafer substrate. Afterwards, the first digital isolation chip is bonded in the first cavity. The encapsulation layer 104 wraps the first digital isolation chip 101 inside, so that the second surface of the first digital isolation chip 101 and the peripheral side surface adjacent to the second surface are wrapped with the encapsulation layer, so that the creepage distance from the second metal wire 106b and the third metal wire 106d to the first digital isolation chip 101 is increased, and the creepage path will run along the surface of the insulating layer 105, thereby enhancing the isolation withstand voltage value. Based on this structure, vertical stacking packaging is performed on the wafer.

[0109] Step S1B includes: forming a first conductive portion on the first digital isolation chip, and forming an insulating layer on the first digital isolation chip and the first conductive portion. The specific process is the same as that of the second embodiment.

[0110] Step S1C includes: forming a metallization layer on the insulating layer, the metallization layer including a first wire portion electrically connected to the first conductive portion, a second wire portion and a second coupling transmission unit; the second coupling transmission unit and the first coupling transmission unit are arranged relative to each other to form a coupling transmission structure, and the specific process is the same as that of Example 2.

[0111] S2. Provide a second digital isolation chip 201.

[0112] The second digital isolation chip structure of this embodiment is the same as that of Embodiment 2, that is, the second digital isolator wafer 200 includes a plurality of second digital isolation chips 201, and a first metal pad 108a and a second metal pad 108b are arranged on the first surface of the second digital isolation chip 201, and a first metal implant ball 109a is electrically connected to the side of the first metal pad 108a away from the second digital isolation chip 201, and a second metal implant ball 109b is electrically connected to the side of the second metal pad 108b away from the second digital isolation chip 201. Based on the second digital isolation chip structure, the second digital isolator wafer is cut open by dicing to separate a single second digital isolation chip 201.

[0113] S3. Flip the second digital isolation chip onto the second conductor portion and the second coupling transmission unit. The specific process is the same as that of Embodiment 2.

[0114] Similarly, steps S1 and S2 shown in this embodiment are also independent, and there is no limitation on their order. Step S1 and step S2 can be performed simultaneously or in any order, as long as the contents of steps S1 and S2 are completed before step S3, and the flip-chip welding of step S3 is not affected.

[0115] This embodiment realizes vertical stacking packaging of digital isolators through wafer reconstruction, rewiring, chip flipping and other technologies, reduces the volume of digital isolator products, increases creepage paths, further improves the internal voltage resistance and consistency of digital isolators, and reduces the parasitic impedance between coupled transmission structures.

[0116] Example 6

[0117] like Figure 6 As shown, this embodiment provides the physical distance of the vertically stacked digital isolator chip structure. The digital isolator chip structure is the same as that of Embodiment 4 and Embodiment 5. The above structure can realize high-voltage isolated signal transmission on both sides of the device. In the final packaging structure, the external filling medium is a plastic packaging material with a dielectric strength of 15V / μm, the polyimide dielectric strength of the insulating layer is 300V / μm, and the silicon dioxide dielectric strength is 600V / μm. Taking the digital isolator packaging structure meeting the DC5000V isolation withstand voltage as an example, it is necessary to pay attention to the following physical spacings in the above structure. The isolation withstand voltage capability that needs to be met is calculated according to the minimum value of the following spacings and the dielectric strength of the filling medium and air in the insulating layer:

[0118] When evaluating the isolation withstand voltage capability, the distances and preferred values ​​indicated by X1, X2, Y1, and Y2 are the same as those in Example 3, except that Example 3 adds a minimum distance X3 from the first digital isolation chip 101 to the edge of the insulating layer 105, and the shortest creepage distance from the third metal conductor 106d to the first digital isolation chip 101 is X2+Y1+X3, where X3 is the minimum distance from the first digital isolation chip 101 to the edge of the insulating layer 105. When the encapsulation layer 104 is a plastic encapsulation material, the intermediate filling medium is also a plastic encapsulation material, so it is necessary to satisfy X2+Y1+X3 to be at least 400 μm. When the encapsulation layer 104 is quartz, the intermediate filling medium is also quartz, that is, silicon dioxide. Since the dielectric strength of silicon dioxide is greater than the dielectric strength of the plastic packaging material, it is no longer necessary to consider the X2+Y1 creepage distance. Quartz above 10μm (X3>10μm) can meet the DC5000V withstand voltage. Compared with the situation in Example 3 (X2+Y1 is at least 400μm, and Y1 is generally 20μm), X2 can be zero. Therefore, the size of the vertically stacked digital isolator chip in Example 6 can be further reduced than that in Example 3.

[0119] It should be understood that the values ​​of X1, X2, X3, Y1, and Y2 given in this embodiment are only preferred values ​​and are for illustrative purposes only. In fact, the values ​​of the above distances can be greater than or equal to the above preferred values ​​and are not listed one by one here.

[0120] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A vertically stacked digital isolator packaging structure, characterized in that: include: A first digital isolation chip, a second digital isolation chip and an insulating layer, wherein the second digital isolation chip and the first digital isolation chip are stacked vertically with the insulating layer disposed therebetween; A coupling transmission structure, wherein the coupling transmission structure comprises a first coupling transmission unit and a second coupling transmission unit which are arranged on a side close to the first digital isolation chip and the second digital isolation chip relative to each other, and the first coupling transmission unit and the second coupling transmission unit are electrically connected to the first digital isolation chip and the second digital isolation chip respectively; A first electrical signal conducting component and a second electrical signal conducting component, wherein the first electrical signal conducting component is arranged on a side of the first digital isolation chip facing the insulating layer, and the second electrical signal conducting component is arranged on a side of the second digital isolation chip facing the insulating layer, and the first electrical signal conducting component and the second electrical signal conducting component are electrically connected to the first digital isolation chip and the second digital isolation chip, respectively.

2. The vertically stacked digital isolator packaging structure according to claim 1, characterized in that: A packaging layer wrapping the first digital isolation chip is disposed on a side of the first digital isolation chip facing away from the insulating layer.

3. The vertically stacked digital isolator packaging structure according to claim 1, characterized in that: The first coupling transmission unit is arranged inside or outside the first digital isolation chip; When the first coupling transmission unit is arranged outside the first digital isolation chip, a first interconnection structure is arranged between the first coupling transmission unit and the first digital isolation chip.

4. The vertically stacked digital isolator packaging structure according to claim 1, characterized in that: The second coupling transmission unit is arranged inside or outside the second digital isolation chip; When the second coupling transmission unit is disposed outside the second digital isolation chip, a second interconnection structure is disposed between the second coupling transmission unit and the second digital isolation chip.

5. The vertically stacked digital isolator packaging structure according to any one of claims 1 to 4, characterized in that: The first coupling transmission unit and the second coupling transmission unit are capacitor plates; or, The first coupling transmission unit and the second coupling transmission unit are electromagnetic coils; or, The first coupling transmission unit and the second coupling transmission unit are giant magnetoresistance coupling units.

6. The vertically stacked digital isolator packaging structure according to any one of claims 1 to 4, characterized in that: The first electrical signal conducting component comprises at least two first electrical signal conducting members, each of which comprises a first conductive portion and a first wire portion; wherein, The first conductive portion is electrically connected to the first digital isolation chip, one end of the first wire portion is electrically connected to the first conductive portion, and the other end of the first wire portion passes through the insulating layer.

7. The vertically stacked digital isolator packaging structure according to any one of claims 1 to 4, characterized in that: The second electrical signal conducting component comprises at least two second electrical signal conducting members, each of which comprises a second conductive portion and a second conductor portion; wherein, The second conductive portion is electrically connected to the second digital isolation chip, one end of the second wire portion is electrically connected to the second conductive portion, and the other end of the second wire portion is located on the insulating layer.

8. A method for manufacturing a vertically stacked digital isolator packaging structure, characterized in that: The production method comprises: S1. providing a first digital isolation chip including a first coupling transmission unit; forming a first conductive portion on the first digital isolation chip, and forming an insulating layer on the first digital isolation chip and the first conductive portion; A metallization layer is formed on the insulating layer, wherein the metallization layer includes a first wire portion electrically connected to the first conductive portion, a second wire portion and a second coupling transmission unit; the second coupling transmission unit and the first coupling transmission unit are arranged opposite to each other to form a coupling transmission structure; S2, providing a second digital isolation chip; S3. Flip-chip the second digital isolation chip onto the second conductor portion and the second coupling transmission unit.

9. A method for manufacturing a vertically stacked digital isolator packaging structure, characterized in that: The production method comprises the steps of: S1. Provide a first digital isolation chip; forming a first coupling transmission unit and a first conductive portion on the first digital isolation chip; forming an insulating layer on the first digital isolation chip, the first coupling transmission unit and the first conductive portion; forming a metallization layer on the insulating layer, wherein the metallization layer includes a first wire portion electrically connected to the first conductive portion, a second wire portion, and a second coupling transmission unit, wherein the second coupling transmission unit and the first coupling transmission unit are arranged opposite to each other to form a coupling transmission structure; S2, providing a second digital isolation chip; S3. Flip-chip the second digital isolation chip onto the second conductor portion and the second coupling transmission unit.

10. The production method according to claim 8 or 9, characterized in that: The step S1 further comprises: A packaging layer wrapping the first digital isolation chip is formed on a side of the first digital isolation chip away from the insulating layer.

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