Wafer structure and manufacturing method thereof

Abstract

The invention provides a wafer structure and a manufacturing method thereof, relates to the technical field of semiconductors, and is used for solving the technical problem of low chip yield. The wafer structure comprises a chip and a cutting channel surrounding the chip, the cutting channel is provided with a blocking region and a filling region which are adjacent to each other, and the blocking region is adjacent to the chip; a buffer layer is arranged on the blocking region, at least two rows of blocking structures which are arranged at intervals in the direction away from the chip are arranged in the buffer layer, each row of blocking structures comprises a plurality of blocking holes which penetrate through the buffer layer and are arranged at intervals, the blocking holes of every two adjacent rows of blocking structures are arranged in a staggered mode, and a filling layer is formed on the filling region. The filling layer is at least located between the buffer layers. And when the crack or the broken edge extends to the blocking hole in the buffer layer, the crack or the broken edge extends along the side length direction of the blocking hole, so that the crack or the broken edge is prevented from continuously extending to the chip or weakening the expansion capability to the direction of the chip, the chip is protected, the performance of the chip is ensured, and the yield of the chip is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a wafer structure and a manufacturing method thereof. Background Art

[0002] The wafer structure includes multiple chips (dies) and scribe lines that isolate each die. An integrated circuit is formed in the chip, and a test structure is formed in the scribe line to perform a wafer acceptance test (WAT). The wafer is divided into individual chips by performing a cutting process in the scribe line to package these chips. However, the mechanical force of cutting will cause cracks or broken edges in the scribe line, and extend to the chip, affecting the chip's functionality and reliability, and the chip yield is low. Summary of the invention

[0003] In view of the above problems, the embodiments of the present disclosure provide a wafer structure and a method for manufacturing the same to improve the yield of chips.

[0004] According to some embodiments, the present disclosure provides a wafer structure, comprising a chip, and a dicing street surrounding the chip, the dicing street having a barrier region and a filling region adjacent to each other, and the barrier region is adjacent to the chip;

[0005] A buffer layer is arranged on the blocking area, and at least two rows of blocking structures are arranged in a direction away from the chip. Each row of the blocking structures includes a plurality of blocking holes that penetrate the buffer layer and are arranged at intervals. The plurality of blocking holes in two adjacent rows of the blocking structures are staggered. A filling layer is formed on the filling area, and the filling layer is at least located between the buffer layers.

[0006] In some possible examples, each row of the blocking structures surrounds the corresponding chip, at least two rows of the blocking structures are sequentially nested, and in two adjacent rows of the blocking structures, a gap between two adjacent blocking holes of one row of the blocking structures is opposite to the blocking holes of the other row of the blocking structures;

[0007] And / or, the material of the barrier layer includes metal.

[0008] In some possible examples, a test structure and an alignment structure are further disposed on the filling area, and the filling layer covers the test structure and the alignment structure;

[0009] The buffer layer includes a first area opposite to the test structure and a second area opposite to the alignment structure, and an arrangement density of the blocking holes in each row of the blocking structures in the first area is less than an arrangement density of the blocking holes in each row of the blocking structures in the second area.

[0010] In some possible examples, along the side length direction of the chip, the length of the blocking holes in each row of the blocking structures in the first region is greater than the length of the blocking holes in each row of the blocking structures in the second region.

[0011] In some possible examples, along the side length direction of the chip, two ends of the second region protrude from two ends of the corresponding alignment structure respectively.

[0012] In some possible examples, the blocking holes in the first area are arranged at equal intervals, the blocking holes in the second area are arranged at equal intervals, and the spacing between the blocking holes in the first area is equal to the spacing between the blocking holes in the second area.

[0013] In some possible examples, the buffer layer includes a third region corresponding to a corner of the chip, and a fourth region adjacent to both ends of the third region;

[0014] An arrangement density of the blocking holes in each row of the blocking structures in the fourth region is smaller than an arrangement density of the blocking holes in each row of the blocking structures in the third region.

[0015] In some possible examples, a surface of the blocking holes in each row of the blocking structures in the third region away from the chip is a curved surface, and the blocking holes in each row of the blocking structures are distributed radially.

[0016] In some possible examples, each of the blocking holes is filled with the filling layer or the dielectric layer, and the filling layer or the dielectric layer fills the corresponding blocking hole.

[0017] The wafer structure provided by the embodiment of the present disclosure has at least the following advantages:

[0018] The wafer structure provided by the embodiment of the present disclosure includes a chip and a cutting path, and the cutting path has a barrier area and a filling area adjacent to each other, and the barrier area is adjacent to the chip. A buffer layer is arranged on the barrier area, and at least two rows of barrier structures are arranged in a direction away from the chip. Each row of barrier structures includes a plurality of barrier holes that penetrate the buffer layer and are arranged in a spaced manner. The plurality of barrier holes of the two adjacent rows of barrier structures are staggered. A filling layer is formed on the filling area, and the filling layer is at least located between the buffer layers. By forming a barrier hole that penetrates the buffer layer in the buffer layer, a filling layer is formed between the buffer layers, and cracks or edge collapses generated when cutting along the filling layer extend in the filling layer and extend to the buffer layer. When the crack or edge collapse extends in the buffer layer to the barrier hole, it extends along the length direction of the barrier hole, that is, it spreads to the surroundings, thereby avoiding further extension to the chip, or weakening the ability to expand in the direction of the chip. The barrier hole can diffuse the crack effect or edge collapse effect, so that the stress that generates the crack or edge collapse is discontinuous and divergent, so as to protect the chip, ensure the performance of the chip, and improve the chip yield.

[0019] According to some embodiments, the present disclosure further provides a method for manufacturing a wafer structure, the wafer structure comprising a chip, and a dicing road surrounding the chip, the dicing road having adjacent blocking areas and filling areas, and the blocking areas are adjacent to the chip;

[0020] The production method comprises:

[0021] At least two rows of sacrificial structures are formed in the blocking area and arranged in a direction away from the chip, each row of the sacrificial structures includes a plurality of sacrificial blocks, and the plurality of sacrificial blocks of the sacrificial structures in two adjacent rows are staggered;

[0022] forming a buffer layer in the blocking area, the buffer layer surrounds the chip and wraps the plurality of sacrificial blocks, and the top surfaces of the sacrificial blocks are exposed;

[0023] removing the sacrificial block to form a blocking hole;

[0024] A filling layer is formed in the filling area, and the filling layer is filled at least between the buffer layers.

[0025] The method for manufacturing the wafer structure in the embodiment of the present disclosure is to form at least two rows of sacrificial structures in the blocking area, each row of sacrificial structures includes multiple sacrificial blocks, and the multiple sacrificial blocks of the two adjacent rows of sacrificial structures are staggered, and to form a buffer layer in the blocking area. After the buffer layer surrounds the chip and wraps the multiple sacrificial blocks, the sacrificial blocks are removed to form a blocking hole, and a filling layer is formed in the filling area, and the filling layer is at least filled between the buffer layers. The cracks or broken edges generated when cutting along the filling layer extend and expand in the filling layer, and extend and expand to the buffer layer. When the cracks or broken edges extend and expand in the buffer layer to the blocking hole, they extend and expand along the length direction of the blocking hole, that is, spread to the surroundings, thereby avoiding further extension to the chip, or weakening the ability to expand in the direction of the chip. The blocking hole can diffuse the crack effect or the broken edge effect, so that the stress that generates the crack or broken edge is discontinuous and divergent, so as to protect the chip, ensure the performance of the chip, and improve the chip yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a schematic diagram of chips and dicing lanes in a wafer structure in an embodiment of the present disclosure;

[0027] Figure 2 A schematic diagram of a buffer layer and a filling layer in a wafer structure in an embodiment of the present disclosure;

[0028] Figure 3 for Figure 2 A schematic diagram of a structure at A in the middle;

[0029] Figure 4 for Figure 2 Another structural diagram at A in the middle;

[0030] Figure 5 for Figure 2 Schematic diagram of the crack or edge collapse at A in the middle;

[0031] Figure 6 for Figure 2 Another structural schematic diagram at A in the middle;

[0032] Figure 7 for Figure 2 Another structural schematic diagram at A in the middle;

[0033] Figure 8 Another schematic diagram of a buffer layer and a filling layer in a wafer structure in an embodiment of the present disclosure;

[0034] Fig. 9 for Figure 8 A schematic diagram of a structure at B in the middle;

[0035] Fig.10 is a flow chart of a method for manufacturing a wafer structure in an embodiment of the present disclosure;

[0036] Fig.11 is a schematic diagram after forming a sacrificial structure in one embodiment of the present disclosure;

[0037] Fig.12 It is a schematic diagram after forming a buffer layer in one embodiment of the present disclosure;

[0038] Fig.13 It is a schematic diagram after removing the sacrificial structure in one embodiment of the present disclosure;

[0039] Fig.14 It is a schematic diagram after forming a filling layer in one embodiment of the present disclosure.

[0040] Description of reference numerals:

[0041] 1-wafer structure; 10-chip;

[0042] 20-cutting path; 21-blocking area;

[0043] 22-filling area; 23-test structure;

[0044] 24-alignment structure; 30-buffer layer;

[0045] 31-blocking structure; 32-blocking hole;

[0046] 40-filling layer; 50-sacrificial structure;

[0047] 51-Sacrificial block. DETAILED DESCRIPTION

[0048] The embodiment of the present disclosure provides a wafer structure, which includes a chip and a cutting path, wherein the cutting path has a barrier area and a filling area adjacent to each other, and the barrier area is adjacent to the chip. By setting a buffer layer in the barrier area, setting a barrier hole in the buffer layer, and forming a filling layer between the buffer layers, when the cracks or broken edges generated by cutting the filling layer extend to the blocking hole, they extend along the length direction of the blocking hole, thereby avoiding further extension to the chip, or weakening the extension trend in the direction of the chip, so that the stress that generates the cracks or broken edges is discontinuous and divergent, so as to protect the chip, ensure the performance of the chip, and improve the chip yield.

[0049] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more obvious and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0050] See also Figures 1 to 5 The embodiment of the present disclosure provides a wafer structure 1, which includes a chip 10 and a dicing road 20, wherein the dicing road 20 is arranged around the chip 10. The dicing road 20 may surround the chip 10 in a circumferential direction and be adjacent to the chip 10, that is, the dicing road 20 surrounds the chip 10 in a whole circumference, and the inner circumference of the dicing road 20 is in contact with the outer circumference of the chip 10.

[0051] The chip 10 is formed with semiconductor device structures, such as transistors, capacitors, etc., to form an integrated circuit to achieve specific functions. The cutting path 20 is formed with a test structure (test key) 23, etc., to detect the working performance of the integrated circuit of the chip 10 by performing a wafer acceptance test (WAT). There can be multiple chips 10, and the multiple chips 10 are arranged at intervals. The cutting path 20 surrounds each chip 10, so that each chip 10 is isolated from each other, which is convenient for cutting. Figure 1 As shown, the chip 10 has four dicing lanes 20 arranged in a cross shape.

[0052] The dicing road 20 has a barrier region 21 and a filling region 22 adjacent to each other, and the barrier region 21 is adjacent to the chip 10. Figure 1 As shown, the blocking area 21 corresponds to the chip 10, for example, each blocking area 21 fully surrounds the corresponding chip 10 in the circumferential direction and is adjacent to the chip 10. The filling area 22 is adjacent to the blocking area 21. Exemplarily, the filling area 22 is located between the blocking areas 21.

[0053] Continue reading Figures 1 to 5 , a buffer layer 30 is provided on the blocking area 21, and at least two rows of blocking structures 31 are arranged in a direction away from the chip 10. The buffer layer 30 fully surrounds the corresponding chip 10 in the circumferential direction and is adjacent to the corresponding chip 10. At least two rows of blocking structures 31 are provided in the buffer layer 30, and each row of blocking structures 31 surrounds (e.g., fully surrounds) the corresponding chip 10, and at least two rows of blocking structures 31 are arranged in sequence. By providing at least two rows of blocking structures 31, cracks or broken edges during the cutting process are prevented from extending to the chip 10, thereby ensuring the performance of the chip 10.

[0054] In order to protect the chip 10 all the way around, in some examples, such as Figure 2 and Figure 3 As shown, at least two rows of blocking structures 31 are arranged in sequence, and each row of blocking structures 31 fully surrounds the chip 10 in the circumferential direction. Figure 2Two rows of blocking structures 31 are arranged in the buffer layer 30, wherein the inner blocking structure 31 of the two rows of blocking structures 31 surrounds the chip 10 for a whole circumference, and the outer blocking structure 31 surrounds the inner blocking structure 31 for a whole circumference, so that the two rows of blocking structures 31 are sequentially sleeved on the chip 10. The outer blocking structure 31 and the inner blocking structure 31 are equidistantly distributed to improve the symmetry of the two rows of blocking structures 31.

[0055] Continue reading Figures 1 to 5 Each row of blocking structures 31 includes a plurality of blocking holes 32 penetrating the buffer layer 30 and arranged at intervals. The plurality of blocking holes 32 in two adjacent rows of blocking structures 31 are staggered so that the plurality of blocking holes 32 form a grid structure. The plurality of blocking holes 32 in each row of blocking structures 31 are spaced apart, and the plurality of blocking holes 32 in each row of blocking structures 31 are spaced apart from the plurality of blocking holes 32 in the adjacent row of blocking structures 31 in a direction away from the chip 10. The blocking holes 32 may be cylindrical holes, elliptical cylindrical holes, rectangular holes, square holes, etc.

[0056] like Figure 2 and Figure 3 As shown, in two adjacent rows of blocking structures 31, the gap between two adjacent blocking holes 32 of one row of blocking structures 31 is opposite to the blocking holes 32 of the other row of blocking structures 31, so that the blocking holes 32 of the two adjacent rows of blocking structures 31 are staggered, that is, the blocking holes 32 of different rows of blocking structures 31 are staggered, so that as many blocking holes 32 as possible are arranged along the circumference of the chip 10, thereby ensuring that protection is provided for the entire circumference of the chip 10.

[0057] Some possible examples include Figure 3 As shown, in two adjacent rows of blocking structures 31, the blocking holes 32 of one row of blocking structures 31 are directly opposite to the area between two adjacent blocking holes 32 of the other row of blocking structures 31, and directly opposite to the ends of two adjacent blocking holes 32 of the other row of blocking structures 31 that are close to each other. Along the circumferential direction of the chip 10, each blocking hole 32 spans the area between two adjacent blocking holes 32 of the adjacent row, that is, both ends of each blocking hole 32 are respectively opposite to the ends of two adjacent blocking holes 32 of the adjacent row that are close to each other.

[0058] Continue reading Figures 2 to 4 A filling layer 40 is formed on the filling area 22, and the filling layer 40 is at least located between the buffer layers 30. The filling layer 40 is formed between the buffer layers 30, and the filling layer 40 does not contact the chip 10. The buffer layer 30 is formed between the filling layer 40 and the chip 10. By forming a blocking hole 32 penetrating the buffer layer 30 in the buffer layer 30, the filling layer 40 is formed between the buffer layers 30. When cutting along the filling layer 40 ( Figure 4 The cracks or chippings generated extend and expand in the filling layer 40 ( Figure 4The crack or chipping extends in the buffer layer 30 (in the Y direction shown in FIG. Figure 4 Y direction as shown) to the blocking hole 32, along the side length direction of the blocking hole 32 ( Figure 4 The blocking hole 32 can diffuse the crack effect or edge collapse effect, making the stress of the crack or edge collapse discontinuous and divergent, so as to protect the chip 10, ensure the performance of the chip 10, and improve the yield of the chip 10.

[0059] For some examples, see Figure 3 The filling layer 40 fills the buffer layer 30, and the top surface of the filling layer 40 is flush with the top surface of the buffer layer 30. Each blocking hole 32 is filled with a dielectric layer, and the dielectric layer fills the corresponding blocking hole 32. In other examples, see Figure 6 The filling layer 40 fills the buffer layer 30 and the blocking hole 32, that is, the filling layer 40 is filled between the buffer layers 30 and in the blocking hole 32, and the top surface of the filling layer 40 is flush with the top surface of the buffer layer 30. Each blocking hole 32 is filled with the filling layer 40, and the filling layer 40 fills the corresponding blocking hole 32. In some other examples, see Figure 7 The filling layer 40 is filled between the buffer layers 30, covers the buffer layers 30, and is also filled in the blocking holes 32. The top surface of the filling layer 40 is higher than the top surface of the buffer layer 30, and the filling layer 40 is located in the filling area 22 (see Figure 1 ) and extends to the barrier region 21 (see Figure 1 ).

[0060] In some examples, the material of the barrier layer includes metal (e.g., pure metal), that is, the barrier layer is a metal layer. With such a configuration, the barrier hole 32 in the buffer layer 30 can block the extension and expansion of small chipping or cracks. When a larger chipping or crack breaks through the barrier hole 32, the chipping or crack is weakened. The metal layer between the barrier hole 32 and the chip 10 (i.e., part of the metal layer close to the chip 10) can increase the ability to resist chipping or cracks to block the weakened chipping or cracks. The metal layer between the barrier hole 32 and the chip 10 is narrower to achieve a blocking effect, that is, the distance between the barrier hole 32 and the chip 10 is smaller. In addition, providing the barrier hole 32 in the metal layer can also reduce the problem of excessive local stress caused by the full metal.

[0061] Continue reading Figures 1 to 4A test structure 23 and an alignment structure 24 are also provided on the filling area 22. The filling layer 40 covers the test structure 23 and the alignment structure 24. The test structure 23 is used to test the chip 10, and the alignment structure 24 is used for measurement and alignment of processes such as photolithography. The alignment structure 24 is manufactured at the same time as the device structure. The alignment structure 24 and the device structure have the same film layer. The device structure refers to various sizes and shapes, and the alignment structure 24 is a standard size.

[0062] The test structure 23 is a metal structure with a certain degree of ductility, which can reduce the stress of cutting and is not prone to cracks or edge collapse during cutting. The alignment structure 24 is a combination of different materials, including silicon and other elements, which is prone to cracks or edge collapse during cutting. To this end, the buffer layer 30 includes a first area (such as Figure 4 M in the figure), and a second region opposite to the alignment structure 24 (as shown in FIG. Figure 4 As shown at N in the figure, the arrangement density of the blocking holes 32 in each row of the blocking structures 31 in the first region is less than the arrangement density of the blocking holes 32 in each row of the blocking structures 31 in the second region.

[0063] The blocking holes 32 in each row of blocking structures 31 opposite to the test structure 23 are relatively sparse, and the blocking holes 32 in each row of blocking structures 31 opposite to the alignment structure 24 are relatively dense. The arrangement density of the blocking holes 32 is determined according to the possibility of cracks or edge collapse in different regions (first region and second region), and the blocking holes 32 are denser in the second region where cracks or edge collapse are prone to occur to increase the blocking effect. The arrangement of the blocking holes 32 is reasonable and the blocking efficiency is high.

[0064] Exemplarily, the arrangement density of the blocking holes 32 in each row of the blocking structures 31 in the first area is m, and the arrangement density of the blocking holes 32 in each row of the blocking structures 31 in the second area is greater than or equal to 2m, and the blocking effect of the blocking structures 31 is better.

[0065] In some possible implementations, such as Figure 4 As shown, along the length direction of the chip 10, the length of the blocking holes 32 in each row of the blocking structures 31 in the first region is greater than the length of the blocking holes 32 in each row of the blocking structures 31 in the second region. The blocking holes 32 in each row of the blocking structures 31 in the first region are longer, and the blocking holes 32 in each row of the blocking structures 31 in the second region are shorter, so as to realize the dense arrangement of the blocking holes 32 in each row of the blocking structures 31 in the second region.

[0066] Continue reading Figure 4, along the length direction of the chip 10, the two ends of the second region protrude from the two ends of the corresponding alignment structure 24. Compared with the alignment structure 24, the second region is longer, and the two ends of the second region protrude from the two ends of the corresponding alignment structure 24, so that the second region can block cracks or edge collapse generated by the entire alignment structure 24 to ensure the blocking effect.

[0067] The blocking holes 32 in the first area are arranged at equal intervals, the blocking holes 32 in the second area are arranged at equal intervals, and the spacing between the blocking holes 32 in the first area is equal to the spacing between the blocking holes 32 in the second area. In this way, the blocking holes 32 in the first area and the second area are arranged at equal intervals, and the spacing between adjacent blocking holes 32 is uniform, so as to better ensure that the blocking holes 32 in two adjacent rows of blocking structures 31 are staggered.

[0068] See also Figure 8 and Fig. 9 The buffer layer 30 also includes a third region (such as Fig. 9 The third region corresponds to the corner of the chip 10. During the cutting process, the cutting path 20 is subjected to two cuts in the vertical and horizontal directions, and the corner of the chip 10 is subjected to greater stress. The blocking holes 32 in the third region are arranged at a higher density to improve the blocking ability against cracks or edge collapse to protect the corner of the chip 10. The chip 10 can be rectangular, and the third region can be fan-shaped. For example, the arc length of the third region can be greater than or equal to 1 / 10 of the side length of the chip 10.

[0069] The surface of the blocking holes 32 in each row of blocking structures 31 in the third region away from the chip 10 is a curved surface. By forming the surface of the blocking holes 32 in each row of blocking structures 31 in the third region away from the chip 10 into a curved surface (e.g., a circular arc surface), the stress that generates cracks or edge collapse can be dispersed. The blocking holes 32 in each row of blocking structures 31 are radially distributed so that the blocking holes 32 are evenly arranged in the third region. Exemplarily, the curved surfaces of the blocking holes 32 in the same row of blocking structures 31 in the third region form a virtual curved surface.

[0070] In some examples, the buffer layer 30 further includes a fourth region (eg, Fig. 9 As shown in F in the figure, that is, the two ends of the third area are respectively connected to the fourth area. The arrangement density of the blocking holes 32 in each row of the blocking structures 31 in the fourth area is less than the arrangement density of the blocking holes 32 in each row of the blocking structures 31 in the third area. The arrangement density of the blocking holes 32 in each row of the blocking structures 31 in the fourth area can be the same as the arrangement density of the blocking holes 32 in each row of the blocking structures 31 in the first area. The arrangement density of the blocking holes 32 in each row of the blocking structures 31 in the third area can be the same as the arrangement density of the blocking holes 32 in each row of the blocking structures 31 in the second area.

[0071] Exemplarily, the arrangement density of the blocking holes 32 in each row of the blocking structures 31 in the first area is m, the arrangement density of the blocking holes 32 in each row of the blocking structures 31 in the fourth area is m, and the arrangement density of the blocking holes 32 in each row of the blocking structures 31 in the third area is greater than or equal to 2m.

[0072] In summary, the wafer structure 1 provided in the embodiment of the present disclosure includes a chip 10 and a cutting path 20, wherein the cutting path 20 has a barrier area 21 and a filling area 22 adjacent to each other, and the barrier area 21 is adjacent to the chip 10. A buffer layer 30 is provided on the barrier area 21, and at least two rows of barrier structures 31 are arranged in a direction away from the chip 10. Each row of barrier structures 31 includes a plurality of barrier holes 32 penetrating the buffer layer 30 and arranged in a spaced relationship, and the plurality of barrier holes 32 of two adjacent rows of barrier structures 31 are staggered. A filling layer 40 is formed on the filling area 22, and the filling layer 40 is at least located between the buffer layers 30. By forming the barrier holes 32 penetrating the buffer layers 30 in the buffer layers 30, a filling layer 40 is formed between the buffer layers 30, and cracks or broken edges generated when cutting along the filling layer 40 extend and expand in the filling layer 40, and extend and expand to the buffer layer 30. When the crack or edge collapse extends in the buffer layer 30 to the blocking hole 32, it extends along the length direction of the blocking hole 32, that is, spreads to the surroundings, thereby avoiding further extension to the chip 10, or weakening the ability to expand toward the chip 10. The blocking hole 32 can diffuse the crack effect or edge collapse effect, making the stress that generates the crack or edge collapse discontinuous and divergent, so as to protect the chip 10, ensure the performance of the chip 10, and improve the yield of the chip 10.

[0073] The present disclosure also provides a method for manufacturing a wafer structure. Figures 1 to 9 The wafer structure 1 includes a chip 10 and a dicing street 20, and the dicing street 20 is arranged around the chip 10. The dicing street 20 can surround the chip 10 in a circumferential direction and be adjacent to the chip 10, that is, the dicing street 20 surrounds the chip 10 for a whole circumference, and the inner circumference of the dicing street 20 is in contact with the outer circumference of the chip 10.

[0074] The chip 10 is formed with a semiconductor device structure, such as a transistor, a capacitor, etc., to form an integrated circuit to achieve a specific function. The cutting path 20 is formed with a test structure 23, etc., to detect the working performance of the integrated circuit by performing a wafer acceptance test. There can be multiple chips 10, and the multiple chips 10 are arranged at intervals. The cutting path 20 surrounds each chip 10, so that the chips 10 are isolated from each other and are easy to cut.

[0075] The dicing road 20 has a barrier region 21 and a filling region 22 adjacent to each other, and the barrier region 21 is adjacent to the chip 10. Figure 1As shown, the blocking area 21 corresponds to the chip 10, each blocking area 21 completely surrounds the corresponding chip 10 in the circumferential direction, and the filling area 22 is adjacent to the blocking area 21. Exemplarily, the filling area 22 is located between the blocking areas 21.

[0076] See also Fig.10 The method for manufacturing the wafer structure 1 may specifically include the following steps:

[0077] Step S100: forming at least two rows of sacrificial structures spaced apart in a direction away from the chip in the blocking region, each row of sacrificial structures comprising a plurality of sacrificial blocks, and the plurality of sacrificial blocks in two adjacent rows of sacrificial structures are staggered.

[0078] See also Figure 1 and Fig.11 At least two rows of sacrificial structures 50 are formed in the blocking area 21, and the at least two rows of sacrificial structures 50 are arranged at intervals in a direction away from the chip 10. That is, at least two rows of sacrificial structures 50 are arranged in sequence, and the innermost row of sacrificial structures 50 is arranged on the chip 10. Each row of sacrificial structures 50 is arranged at intervals and is arranged at intervals from the chip 10.

[0079] Each row of sacrificial structures 50 includes a plurality of sacrificial blocks 51. The sacrificial blocks 51 in the same row are arranged at intervals, and the sacrificial blocks 51 in two adjacent rows are arranged in a staggered manner. Fig.13 ), the plurality of blocking holes 32 of two adjacent rows of blocking structures 31 are staggered. The sacrificial block 51 may be a cylinder, an elliptical cylinder, a rectangular cylinder or a square cylinder, etc., and the material of the sacrificial block 51 may be photoresist (photoresist). Fig.11 As shown, the blocking area 21 forms two rows of sacrificial structures 50 , and a plurality of sacrificial blocks 51 in the same row are arranged at equal intervals, and the sacrificial blocks 51 are rectangular columns.

[0080] In some examples, in two adjacent rows of sacrificial structures 50, a gap between two adjacent sacrificial blocks 51 of one row of sacrificial structures 50 is opposite to the sacrificial blocks 51 of the other row of sacrificial structures 50, so that the sacrificial blocks 51 of the two adjacent rows of sacrificial structures 50 are staggered, so that as many sacrificial blocks 51 as possible are arranged along the circumference of the chip 10, thereby ensuring that protection is provided for the entire circumference of the chip 10.

[0081] Among the two adjacent rows of sacrificial structures 50, the sacrificial blocks 51 of one row of sacrificial structures 50 are directly opposite to the area between the two adjacent sacrificial blocks 51 of the other row of sacrificial structures 50, and directly opposite to the ends of the two adjacent sacrificial blocks 51 of the other row of sacrificial structures 50 that are close to each other. Each sacrificial block 51 spans the area between the two adjacent sacrificial blocks 51 of the adjacent row, that is, the two ends of each sacrificial block 51 are respectively opposite to the ends of the two adjacent sacrificial blocks 51 of the adjacent row that are close to each other.

[0082] like Fig.11 As shown, in two adjacent rows of sacrificial structures 50, the left end of any sacrificial block 51 is directly opposite to the right end of the sacrificial block 51 on the left side of the two adjacent sacrificial blocks 51 in the adjacent row, and the left and right sides of any sacrificial block 51 are directly opposite to the left end of the sacrificial block 51 on the right side of the two adjacent sacrificial blocks 51 in the adjacent row. In this way, along the circumference of the chip 10, the multiple sacrificial blocks 51 in the two adjacent rows of sacrificial structures 50 partially overlap, so that the sacrificial blocks 51 are directly opposite to each other around the entire circumference of the chip 10, providing a barrier for the entire circumference of the chip 10.

[0083] Step S200: forming a buffer layer in the barrier region, the buffer layer surrounds the chip and wraps a plurality of sacrificial blocks, and the top surfaces of the sacrificial blocks are exposed.

[0084] See also Fig.12 , the buffer layer 30 wraps the multiple sacrificial blocks 51 and forms an integral body along the circumference of the chip 10, that is, the buffer layer 30 fully surrounds the chip 10 in the circumferential direction. The buffer layer 30 covers the sides of the multiple sacrificial blocks 51 so that the top surface of the sacrificial blocks 51 is exposed, which facilitates the removal of the sacrificial layer. The buffer layer 30 can be a metal with good ductility to prevent cracks or chipping from extending to the chip 10. Exemplarily, the buffer layer 30 can be formed in the remaining blocking area 21 by a sputtering process, and the alignment structure 24 and / or the test structure 23 can be formed in the filling area 22.

[0085] Step S300: removing the sacrificial block to form a blocking hole.

[0086] See also Fig.12 and Fig.13 , remove the sacrificial block 51, for example, remove all the sacrificial blocks 51 through a development process, and form a blocking hole 32 in the buffer layer 30. When the crack or edge collapse extends to the blocking hole 32 in the buffer layer 30, it extends along the length direction of the blocking hole 32, that is, diffuses to the surroundings, thereby avoiding further extension to the chip 10, or weakening the extension trend in the direction of the chip 10. The blocking hole 32 can diffuse the crack effect or edge collapse effect, so that the stress that generates the crack or edge collapse is discontinuous and divergent, so as to protect the chip 10 and ensure the performance of the chip 10. In addition, the provision of the blocking hole 32 in the buffer layer 30 can also reduce the problem of excessive local stress caused by the full buffer layer 30.

[0087] Step S400: forming a filling layer in the filling area, wherein the filling layer is at least filled between the buffer layers.

[0088] See also Fig.14, the filling layer 40 is located between the buffer layers 30 and does not contact the chip 10. The cracks or chippings generated when cutting along the filling layer 40 extend in the filling layer 40 and extend to the buffer layer 30. When the cracks or chippings break through the blocking hole 32 in the buffer layer 30 and extend to between the blocking hole 32 and the chip 10, the cracks or chippings can also be blocked.

[0089] In some examples, the filling layer 40 fills up the buffer layer 30, and the top surface of the filling layer 40 is flush with the top surface of the buffer layer 30. In other examples, the filling layer 40 fills up the buffer layer 30 and the blocking hole 32, that is, the filling layer 40 is filled between the buffer layers 30 and filled in the blocking layer, and the top surface of the filling layer 40 is flush with the top surface of the buffer layer 30. In still other examples, the filling fills up the buffer layer 30 and the blocking hole 32 and covers the buffer layer 30, that is, the top surface of the filling layer 40 is higher than the top surface of the buffer layer 30, and the filling layer 40 is located in the filling area 22 and extends to the blocking area 21.

[0090] In summary, the manufacturing method of the wafer structure 1 in the embodiment of the present disclosure forms at least two rows of sacrificial structures 50 in the blocking area 21, each row of sacrificial structures 50 includes a plurality of sacrificial blocks 51, and the plurality of sacrificial blocks 51 of the two adjacent rows of sacrificial structures 50 are staggered, and a buffer layer 30 is formed in the blocking area 21, the buffer layer 30 surrounds the chip 10 and wraps the plurality of sacrificial blocks 51, and then the sacrificial blocks 51 are removed to form a blocking hole 32, and a filling layer 40 is formed in the filling area 22, and the filling layer 40 is at least filled between the buffer layers 30. The cracks or broken edges generated when cutting along the filling layer 40 extend and expand in the filling layer 40, and extend and expand to the buffer layer 30. When the cracks or broken edges extend and expand in the buffer layer 30 to the blocking hole 32, they extend and expand along the length direction of the blocking hole 32, that is, they spread to the surroundings, thereby avoiding further extension to the chip 10, or weakening the ability to extend in the direction of the chip 10. The blocking hole 32 can diffuse the crack effect or edge collapse effect, making the stress causing the crack or edge collapse discontinuous and divergent, so as to protect the chip 10 , ensure the performance of the chip 10 , and improve the yield of the chip 10 .

[0091] In this specification, each embodiment or implementation is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referenced to each other. The description of reference terms such as "one implementation", "some implementations", "illustrative implementations", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the implementation or example are included in at least one implementation or example of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily refer to the same implementation or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more implementations or examples in a suitable manner.

[0092] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A wafer structure, characterized in that: A chip and a dicing road surrounding the chip, wherein the dicing road has a barrier area and a filling area adjacent to each other, and the barrier area is adjacent to the chip; A buffer layer is arranged on the blocking area, and at least two rows of blocking structures are arranged in a direction away from the chip. Each row of the blocking structures includes a plurality of blocking holes that penetrate the buffer layer and are arranged at intervals. The plurality of blocking holes in two adjacent rows of the blocking structures are staggered. A filling layer is formed on the filling area, and the filling layer is at least located between the buffer layers.

2. The wafer structure according to claim 1, characterized in that: Each row of the blocking structures surrounds the corresponding chip, and at least two rows of the blocking structures are sequentially arranged. In two adjacent rows of the blocking structures, the gap between two adjacent blocking holes of one row of the blocking structures is opposite to the blocking holes of the other row of the blocking structures; And / or, the material of the barrier layer includes metal.

3. The wafer structure according to claim 1 or 2, characterized in that: A test structure and an alignment structure are also arranged on the filling area, and the filling layer covers the test structure and the alignment structure; The buffer layer includes a first area opposite to the test structure and a second area opposite to the alignment structure, and an arrangement density of the blocking holes in each row of the blocking structures in the first area is less than an arrangement density of the blocking holes in each row of the blocking structures in the second area.

4. The wafer structure according to claim 3, characterized in that: Along the side length direction of the chip, the length of the blocking holes in each row of the blocking structures in the first region is greater than the length of the blocking holes in each row of the blocking structures in the second region.

5. The wafer structure according to claim 3, characterized in that: Along the side length direction of the chip, two ends of the second region protrude from two ends of the corresponding alignment structure respectively.

6. The wafer structure according to claim 3, characterized in that: The blocking holes in the first region are arranged at equal intervals, the blocking holes in the second region are arranged at equal intervals, and the spacing between the blocking holes in the first region is equal to the spacing between the blocking holes in the second region.

7. The wafer structure according to claim 1 or 2, characterized in that: The buffer layer includes a third region corresponding to a corner of the chip, and a fourth region adjacent to both ends of the third region; An arrangement density of the blocking holes in each row of the blocking structures in the fourth region is smaller than an arrangement density of the blocking holes in each row of the blocking structures in the third region.

8. The wafer structure according to claim 7, characterized in that: The surface of the blocking holes in each row of the blocking structures in the third region away from the chip is a curved surface, and the blocking holes in each row of the blocking structures are distributed radially.

9. The wafer structure according to claim 1 or 2, characterized in that: Each of the blocking holes is filled with the filling layer or the dielectric layer, and the filling layer or the dielectric layer fills up the corresponding blocking hole.

10. A method for manufacturing a wafer structure, characterized in that: The wafer structure includes a chip and a dicing road surrounding the chip, wherein the dicing road has a barrier area and a filling area adjacent to each other, and the barrier area is adjacent to the chip; The production method comprises: At least two rows of sacrificial structures are formed in the blocking area and arranged in a direction away from the chip, each row of the sacrificial structures includes a plurality of sacrificial blocks, and the plurality of sacrificial blocks of the sacrificial structures in two adjacent rows are staggered; forming a buffer layer in the blocking area, the buffer layer surrounds the chip and wraps the plurality of sacrificial blocks, and the top surfaces of the sacrificial blocks are exposed; removing the sacrificial block to form a blocking hole; A filling layer is formed in the filling area, and the filling layer is filled at least between the buffer layers.

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