Chip antenna integrated packaging integrated structure

Abstract

The invention discloses a chip and antenna integrated packaging integrated structure which comprises a planar aperture antenna, a first glass dielectric layer, a first wiring layer, a first dielectric layer, a second wiring layer, a second glass dielectric layer, a chip, a third wiring layer, a second dielectric layer and a solder ball. The planar aperture antenna, the first glass dielectric layer, the first dielectric layer, the second glass dielectric layer, the second dielectric layer and the solder ball are sequentially stacked from top to bottom; the first wiring layer and the second wiring layer are arranged in the first dielectric layer, the third wiring layer is arranged in the second dielectric layer, the chip is arranged in the second glass dielectric layer, the planar aperture antenna is connected with the chip through the first wiring layer, and the third wiring layer is connected with the chip through the second wiring layer; and the third wiring layer is connected with the solder ball. According to the structure, the feed distance from the radio frequency port of the chip to the planar aperture antenna is shortened, the loss is reduced, the signal quality is improved, the structure is compact, and a better miniaturization effect is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit chip packaging, and in particular to a chip antenna integrated packaging structure. Background Art

[0002] The chip antenna system integration structure mainly integrates the packaged antenna and the chip in a package structure. Although the existing chip antenna system integration structure meets the needs of miniaturization and integration to a certain extent, it is limited by factors such as materials, processes and design; the existing chip antenna system integration structure is difficult to achieve a better miniaturization effect, and the existing chip antenna system integration structure will also introduce certain signal transmission losses, resulting in a decrease in signal quality. Summary of the invention

[0003] The purpose of the present invention is to overcome the above-mentioned problems and provide a chip antenna integrated packaging structure, which shortens the feeding distance from the chip's RF port to the planar aperture antenna, reduces losses, improves signal quality, and has a compact structure and better miniaturization effect.

[0004] The purpose of the present invention is achieved through the following technical solutions:

[0005] A chip antenna integrated packaging structure includes a planar aperture antenna, a first glass dielectric layer, a first wiring layer, a first dielectric layer, a second wiring layer, a second glass dielectric layer, a chip, a third wiring layer, a second dielectric layer and solder balls; wherein:

[0006] The planar aperture antenna, the first glass dielectric layer, the first dielectric layer, the second glass dielectric layer, the second dielectric layer and the solder balls are stacked in sequence from top to bottom; the first wiring layer and the second wiring layer are arranged in the first dielectric layer, the third wiring layer is arranged in the second dielectric layer, the chip is arranged in the second glass dielectric layer, the planar aperture antenna is connected to the chip through the first wiring layer, the third wiring layer is connected to the chip through the second wiring layer; the third wiring layer is connected to the solder balls.

[0007] The working principle of the above chip antenna integrated packaging structure is:

[0008] The chip antenna integrated package integrated structure of the present invention adopts an integrated package integration method of chip antenna stacking, which can shorten the feeding distance from the chip's RF port to the planar aperture antenna as much as possible. The first glass dielectric layer and the second glass dielectric layer are used as glass substrates, which have the advantage of low loss. The chip is set in the second glass dielectric layer, and the planar aperture antenna, the first glass dielectric layer, the first dielectric layer, the second glass dielectric layer, the second dielectric layer and the solder ball are stacked in layers from top to bottom, which can reduce the parasitic loss from the chip to the package and the package size.

[0009] In a preferred embodiment of the present invention, a cavity is provided in the middle of the second glass medium layer, and the chip is placed in the cavity.

[0010] Preferably, the first glass dielectric layer is provided with a first glass through hole, and the planar aperture antenna is connected to the first wiring layer through the first glass through hole penetrating the first glass dielectric layer.

[0011] Preferably, the second glass dielectric layer is provided with a second through-glass hole, and the second wiring layer and the third wiring layer are connected via the second through-glass hole penetrating the second glass dielectric layer.

[0012] Preferably, copper pillars are provided in the first dielectric layer, and the first wiring layer and the chip as well as the second wiring layer and the chip are connected via the copper pillars.

[0013] Preferably, the chip is a CMOS terahertz transceiver chip.

[0014] Compared with the prior art, the present invention has the following beneficial effects:

[0015] 1. The chip antenna integrated packaging structure of the present invention adopts an integrated packaging integration method of chip antenna stacking, which can shorten the feeding distance from the chip's RF port to the planar aperture antenna as much as possible, reduce losses, and improve signal quality.

[0016] 2. The chip antenna integrated packaging structure of the present invention has the advantage of low loss, with the first glass dielectric layer and the second glass dielectric layer serving as glass substrates.

[0017] 3. The chip antenna integrated package integrated structure of the present invention sets the chip in the second glass dielectric layer, and the planar aperture antenna, the first glass dielectric layer, the first dielectric layer, the second glass dielectric layer, the second dielectric layer and the solder balls are stacked in layers from top to bottom, which can reduce the parasitic loss from the chip to the package and the package size. The structure is very compact and has a better miniaturization effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram of a chip antenna integrated packaging structure in the present invention.

[0019] Figure 2 It is a schematic diagram of a preliminary simulation comparison of the losses of the fan-out interconnect transfer structure in the present invention and the flip-chip bonding in the prior art. DETAILED DESCRIPTION

[0020] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described below in conjunction with embodiments and drawings, but the embodiments of the present invention are not limited thereto.

[0021] See also Figure 1 The present embodiment discloses a chip antenna integrated packaging structure, including a planar aperture antenna 1, a first glass dielectric layer 2, a first wiring layer 3, a first dielectric layer 5, a second wiring layer 6, a second glass dielectric layer 8, a chip 10, a third wiring layer 11, a second dielectric layer 12 and a solder ball 14.

[0022] See also Figure 1 The planar aperture antenna 1, the first glass dielectric layer 2, the first dielectric layer 5, the second glass dielectric layer 8, the second dielectric layer 12 and the solder ball 14 are stacked in sequence from top to bottom; the first wiring layer 3 and the second wiring layer 6 are arranged in the first dielectric layer 5, the third wiring layer 11 is arranged in the second dielectric layer 12, the chip 10 is arranged in the second glass dielectric layer 8, the planar aperture antenna 1 is connected to the chip 10 through the first wiring layer 3, the third wiring layer 11 is connected to the chip 10 through the second wiring layer 6; the third wiring layer 11 is connected to the solder ball 14.

[0023] See also Figure 1 A cavity is provided in the middle of the second glass medium layer 8, and the chip 10 is placed in the cavity. The purpose is to make the structure more compact.

[0024] See also Figure 1 The first glass dielectric layer 2 is provided with a first glass through hole 4, and the planar aperture antenna 1 is connected to the first wiring layer 3 through the first glass through hole 4 penetrating the first glass dielectric layer 2.

[0025] See also Figure 1 The second glass dielectric layer 8 is provided with a second glass through hole 9 , and the second wiring layer 6 is connected to the third wiring layer 11 through the second glass through hole 9 penetrating the second glass dielectric layer 8 .

[0026] See also Figure 1 By setting the first through-glass via 4 and the second through-glass via 9, the connection between the planar aperture antenna 1 and the first wiring layer 3, and the connection between the second wiring layer 6 and the third wiring is more compact. The first through-glass via 4 and the second through-glass via 9 are filled with metal fillers, for example, the metal fillers are copper, and the connection is made through copper as a conductor; specifically, the planar aperture antenna 1 is connected to the first wiring layer 3 through the metal filler in the first through-glass via 4; the second wiring layer 6 and the third wiring layer 11 are connected through the metal filler in the second through-glass via 9.

[0027] See also Figure 1The third wiring layer 11 and the solder ball 14 are connected by a metal vertical interconnect structure 13 , and are vertically connected by the metal vertical interconnect structure 13 .

[0028] See also Figure 1 The first through-glass hole 4 and the second through-glass hole 9 are arranged vertically to the horizontal plane, so that the planar aperture antenna 1 is connected to the first wiring layer 3, and the second wiring layer 6 is connected to the third wiring layer 11 to form a three-dimensional interconnection structure. The three-dimensional interconnection structure is used to vertically connect the planar aperture antenna 1 to the chip 10, shortening the feeding distance from the RF port of the chip 10 to the antenna. The advantage of using the three-dimensional interconnection structure is that it optimizes space utilization, shortens the interconnection length, and reduces signal crosstalk and loss.

[0029] See also Figure 1-Figure 2 , copper pillars are provided in the first dielectric layer 5, and the first wiring layer 3 and the chip 10, as well as the second wiring layer 6 and the chip 10 are connected via copper pillars. This embodiment adopts a fan-out interconnect transfer structure in which the chip 10 is embedded in the substrate (the first glass dielectric layer 2), and copper pillars are used to replace the flip-chip bonding of the prior art. The fan-out interconnect transfer structure is designed by wiring the I / O port in an area outside the chip size, and the wiring area is extended outside the chip using the rewiring layer (RDL) process. After the fan-out packaging technology completes the chip solder ball connection, it can be directly soldered on the printed circuit board without the use of a packaging carrier, which can shorten the signal transmission distance and improve the electrical performance. Figure 2 In the figure, a preliminary simulation comparison of the losses of the fan-out interconnect transfer structure in this embodiment and the flip-chip bonding in the prior art is performed, and the comparison results are as follows: as the operating frequency continues to increase, the S21 performance change of the fan-out interconnect transfer structure is more stable, and the loss is lower than that of the flip-chip bonding.

[0030] See also Figure 1 , the chip 10 is a CMOS terahertz transceiver chip. The chip antenna system integration structure in the prior art will introduce certain signal transmission losses, which may be particularly significant in the millimeter wave frequency band and may cause signal quality degradation. This embodiment uses a CMOS terahertz transceiver chip to solve the problem of large signal transmission losses from the terahertz frequency band chip 10 to the planar aperture antenna 1. By replacing the core layer material (the second glass dielectric layer 8) and the excellent structure (stacked structure), the purpose of reducing transmission losses can be achieved, and the problem of low gain and low efficiency of the terahertz frequency band antenna can also be improved.

[0031] See also Figure 1 The first dielectric layer 5 and the second dielectric layer 12 are made of LCP material.

[0032] See also Figure 1This embodiment optimizes the traditional HDI process, uses a low-loss second glass substrate to replace the organic core layer, and uses low-loss materials such as LCP to realize the rewiring layer, thereby reducing the transmission loss of the three-dimensional interconnection structure in the terahertz frequency band. In addition, the fan-out interconnection transfer structure in which the chip 10 is embedded in the substrate can reduce the parasitic loss from the chip 10 to the package and the package size; the planar aperture antenna 1 used is designed using a planar packaging process such as low-loss HDI, thereby achieving high efficiency and high gain in the terahertz frequency band.

[0033] See also Figure 1 The working principle of the above chip antenna integrated packaging structure is:

[0034] The chip antenna integrated package integrated structure of the present invention adopts an integrated package integration method of chip antenna stacking, which can shorten the feeding distance from the RF port of the chip 10 to the planar aperture antenna 1 as much as possible. The first glass dielectric layer 2 and the second glass dielectric layer 8 are used as glass substrates, which have the advantage of low loss. The chip 10 is arranged in the second glass dielectric layer 8, and the planar aperture antenna 1, the first glass dielectric layer 2, the first dielectric layer 5, the second glass dielectric layer 8, the second dielectric layer 12 and the solder ball 14 are stacked in layers from top to bottom, which can reduce the parasitic loss from the chip 10 to the package and the package size.

[0035] This embodiment adopts an integrated packaging integration method of chip antenna stacking, which has the following main advantages:

[0036] 1. Improve integration and miniaturization: reduce the connection lines and interfaces between components, and reduce the complexity and volume of the overall system; through stacking, more functions can be realized in a limited space, thus meeting the needs of miniaturized equipment.

[0037] 2. Optimize signal transmission: The close integration between chip and antenna helps reduce loss and interference during signal transmission, thereby improving the quality and stability of signal transmission.

[0038] 3. Improve system efficiency: Integrated packaging integration technology can reduce energy loss and heat accumulation between components, thereby improving the efficiency of the entire system.

[0039] 4. Improve reliability and stability: The integrated packaging integration method of chip antenna stacking adopts advanced packaging materials and processes to ensure strong connection and stability between components; this helps to improve the structural strength and durability of the entire system.

[0040] The above is a preferred embodiment of the present invention, but the embodiment of the present invention is not limited to the above content. Any other changes, modifications, substitutions, combinations, and simplifications made without departing from the spirit and principles of the present invention should be equivalent replacement methods and are included in the protection scope of the present invention.

Claims

1. A chip antenna integrated packaging structure, characterized in that: It includes a planar aperture antenna, a first glass dielectric layer, a first wiring layer, a first dielectric layer, a second wiring layer, a second glass dielectric layer, a chip, a third wiring layer, a second dielectric layer and solder balls; wherein, The planar aperture antenna, the first glass dielectric layer, the first dielectric layer, the second glass dielectric layer, the second dielectric layer and the solder balls are stacked in sequence from top to bottom; the first wiring layer and the second wiring layer are arranged in the first dielectric layer, the third wiring layer is arranged in the second dielectric layer, the chip is arranged in the second glass dielectric layer, the planar aperture antenna is connected to the chip through the first wiring layer, the third wiring layer is connected to the chip through the second wiring layer; the third wiring layer is connected to the solder balls.

2. The chip antenna integrated packaging structure according to claim 1, characterized in that: A cavity is provided in the middle of the second glass medium layer, and the chip is placed in the cavity.

3. The chip antenna integrated packaging structure according to claim 2, characterized in that: The first glass dielectric layer is provided with a first glass through hole, and the planar aperture antenna is connected to the first wiring layer through the first glass through hole penetrating the first glass dielectric layer.

4. The chip antenna integrated packaging structure according to claim 3, characterized in that: The second glass dielectric layer is provided with a second through-glass hole, and the second wiring layer and the third wiring layer are connected via the second through-glass hole penetrating through the second glass dielectric layer.

5. The chip antenna integrated packaging structure according to claim 1, characterized in that: Copper pillars are arranged in the first dielectric layer, and the first wiring layer and the chip are connected as well as the second wiring layer and the chip are connected via the copper pillars.

6. The chip antenna integrated packaging structure according to claim 1, characterized in that: The chip is a CMOS terahertz transceiver chip.

Images