Digital self-calibration for automatic offset cancellation

Abstract

The embodiment of the invention relates to digital self-calibration for automatic offset cancellation. A method for calibrating a DC operating point of a PWM receiver circuit is disclosed. A PWM receiver circuit includes an envelope detector having a first resistor string, and includes a bias circuit having a second resistor string and a plurality of switches. The second resistor string is coupled between the supply voltage and the reference voltage and acts as a voltage divider. When closed, each switch has a second voltage at a node of a second resistor string connected to the closed switch. To perform the calibration process, the plurality of switches are closed one at a time and the second voltage is compared to the first voltage at the first node of the first resistor string. A switch that generates a minimum difference between the first voltage and the second voltage when closed remains closed after the calibration process and is used to demodulate the PWM signal.

Description

[0001] This application is a divisional application of the invention patent application with the application date of December 5, 2022 (priority date of December 3, 2021), the Chinese national application number 202211578773.9, and the name “Digital Self-Calibration for Automatic Offset Elimination”. Technical Field

[0002] The present invention relates generally to electronic circuits and, in a particular embodiment, to circuits for automatic offset cancellation. Background Art

[0003] Receiver circuits are widely used in electronic devices for communication purposes. In a typical receiver circuit, the received signal is subjected to front-end processing, such as filtering and / or amplification, before being digitized into digital data for further processing to recover the transmitted data. In some receiver circuits, the input signal of the analog amplifier includes a signal voltage and a reference voltage, and the voltage difference between the signal voltage and the reference voltage is amplified and digitized for processing. The signal voltage and the reference voltage are generated by a circuit designed with components having corresponding nominal values ​​(e.g., nominal resistance values). However, the actual values ​​of the electrical components in the circuit may deviate from their nominal values, which may cause an offset in the voltage difference. Due to the high gain of the analog amplifier, a small offset in the voltage difference at the input of the amplifier may cause a large voltage offset at the output of the amplifier, which may cause errors in the subsequent demodulation or decoding process.

[0004] A calibration process may be performed to remove or reduce the offset. However, a typical calibration process is performed manually, such as at a manufacturing facility, which is time consuming and expensive. Furthermore, once the electrical device is deployed in the field, factors such as component aging and temperature variations may change the receiver circuit characteristics, which may require additional calibration. There is a need in the art for a calibration process that can be performed automatically (e.g., without human intervention) and on-demand in the field so that receiver performance is maintained through the life of the electrical device. Summary of the invention

[0005] In some embodiments, a receiver circuit includes: a first resistor string including a plurality of resistors coupled in series; a second resistor string including a plurality of resistors coupled in series; a first transistor and a second transistor coupled in parallel, wherein a first load path terminal of the first transistor and a first load path terminal of the second transistor are coupled to a reference voltage node, wherein a second load path terminal of the first transistor and a second load path terminal of the second transistor are coupled to a first end of the first resistor string, and a second end of the first resistor string is coupled to a power supply voltage node, wherein a first control terminal of the first transistor and a second control terminal of the second transistor are coupled to a first input terminal of the receiver circuit and a second input terminal of the receiver circuit, respectively; and a third transistor, wherein a first load path terminal of the first transistor and a first load path terminal of the second transistor are coupled to a reference voltage node. A first load path terminal of the third transistor is coupled to the reference voltage node, and a second load path terminal of the third transistor is coupled to a first end of the second resistor string, a second end of the second resistor string is coupled to the power supply voltage node, wherein a control terminal of the third transistor is coupled to a bias voltage node; a plurality of switches coupled in parallel, wherein each of the plurality of switches has a first terminal and a second terminal, wherein the first terminal of the plurality of switches is coupled to a first node, wherein the second terminal of each switch is coupled to a terminal of a corresponding resistor in the second resistor string; and an amplifier, wherein a first input terminal of the amplifier is coupled to the first node, and a second input terminal of the amplifier is coupled to a second node in the first resistor string.

[0006] In some embodiments, a circuit for demodulating an on-off keying (OOK) modulated pulse width modulation (PWM) signal includes: an envelope detector configured to detect an envelope of the OOK modulated PWM signal, including: a first resistor string including resistors coupled in series; and a first transistor and a second transistor coupled in parallel between a first end of the first resistor string and a reference voltage node, wherein the second end of the first resistor string is coupled to a power supply voltage node; a bias circuit configured to provide a reference voltage, including: a second resistor string including resistors coupled in series; and a third transistor coupled between a first end of the second resistor string and the reference voltage node, wherein the second end of the second resistor string is coupled to the power supply voltage node; a plurality of switches coupled in parallel, wherein each of the plurality of switches has a first terminal and a second terminal, wherein the first terminal of each switch is coupled to a first node, and the second terminal of each switch is coupled to a terminal of a corresponding resistor in the second resistor string; an amplifier, a first input of the amplifier being coupled to the first node, and a second input of the amplifier being coupled to a second node in the first resistor string; and a comparator coupled to an output of the amplifier.

[0007] In some embodiments, a method of calibrating a receiver circuit includes: measuring a voltage difference between a first node of the receiver circuit and a second node of the receiver circuit, wherein the receiver circuit includes: an envelope detector configured to detect an envelope of an input signal of the receiver circuit, wherein the envelope detector includes a first resistor string coupled to a first transistor and a second transistor coupled in parallel, wherein the first resistor string includes a first resistor coupled in series and a second resistor coupled in series, the first resistor and the second resistor being connected at the second node; a bias circuit configured to provide a reference voltage, wherein the bias circuit includes a second resistor string coupled to a third transistor, wherein the second resistor string includes a third resistor coupled in series and a fourth resistor coupled in series, the third resistor and the fourth resistor being connected at a third node; a plurality of switches coupled in parallel, wherein the plurality of switches include a first switch, a second switch, and a third switch, wherein each of the first switches is coupled between the first node and a corresponding third resistor in the third resistor away from the third node. a first terminal of a resistor, wherein each of the second switches is coupled between the first node and a second terminal of a corresponding fourth resistor in the fourth resistor away from the third node, and wherein the third switch is coupled between the first node and the third node; and an amplifier, wherein a first input terminal of the amplifier is coupled to the first node and a second input terminal of the amplifier is coupled to the second node, wherein the voltage difference is generated at an output terminal of the amplifier; opening the plurality of switches; after opening the plurality of switches, closing the third switch; after closing the third switch, selecting a switch set from the plurality of switches based on a sign of the voltage difference, wherein if the sign is positive, the switch set is the first switch, or if the sign is negative, the switch set is the second switch; while the sign remains unchanged, closing the switch set one at a time in a first direction from the third switch toward a last switch in the switch set away from the third switch; and stopping calibrating the receiver circuit when the sign changes. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Details of one or more embodiments of the present invention are set forth in the accompanying drawings and the following description. Other features, objects, and advantages of the present invention will be apparent from the description and drawings, as well as from the claims. In the drawings, the same reference numerals generally represent the same components in the various views, and for the sake of brevity, they are generally not re-described. For a more complete understanding of the present invention, reference is now made to the following description in conjunction with the accompanying drawings, in which:

[0009] Figure 1A block diagram of a system with electrical isolation in one embodiment is shown;

[0010] Figure 2 A block diagram of a communication system with electrical isolation in one embodiment is shown;

[0011] Figure 3 A schematic diagram of a receiver circuit with self-calibration capability in an embodiment is shown;

[0012] Figure 4 A pulse width modulation (PWM) signal of on-off keying (OOK) modulation in another embodiment is shown;

[0013] Figure 5 In the embodiment shown Figure 3 A block diagram of signal processing in a receiver circuit;

[0014] Figure 6 A schematic diagram of a calibration control circuit in one embodiment is shown;

[0015] Figure 7 A schematic diagram of a calibration control circuit in another embodiment is shown;

[0016] Figure 8 An embodiment is shown Figure 3 Timing diagram of the receiver circuit;

[0017] Fig. 9 A block diagram of a motor control system in one embodiment is shown; and

[0018] Fig. 10A and 10B Together, a flow chart of a method of calibrating a receiver circuit in one embodiment is shown. DETAILED DESCRIPTION

[0019] The manufacture and use of the currently preferred embodiments are discussed in detail below. However, it should be understood that the present invention provides many applicable inventive concepts that can be implemented in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of the specific ways of making and using the present invention, and do not limit the scope of the present invention.

[0020] The present invention will be described with reference to exemplary embodiments in a specific context, namely a receiver circuit for an offset cancellation circuit that automatically calibrates the DC operating point of the receiver circuit.

[0021] Figure 1 A block diagram of an electrical system with electrical isolation in one embodiment is shown. Figure 1 The electrical system includes a first power supply voltage (eg, V DD1) and a first electrical ground level (eg, GND1), and a first circuit 13 having a second power supply voltage (eg, V DD2 ) and a second circuit 15 connected to a second electrical ground level (e.g., GND2), and an isolation barrier 11 therebetween. Electrical isolation is used in electrical systems to isolate functional parts of an electrical system to prevent current from flowing between the isolated functional parts. Energy or information can still be exchanged between the parts by other means, such as capacitance, induction, or electromagnetic waves, or by optical, acoustic, or mechanical means. Electrical isolation can be used in situations where two or more circuits need to communicate with each other, but their grounds can be at different potentials. Electrical isolation can also be used for safety purposes. For example, optocouplers can be used within an electrical system to decouple a functional block from another block connected to a power grid or other high voltage for safety and equipment protection. As another example, a power semiconductor connected to a line voltage can be switched by an optocoupler driven by a low-voltage circuit that does not need to be insulated for higher line voltages.

[0022] Figure 2 A block diagram of a communication system 20 with galvanic isolation in one embodiment is shown. Figure 2 The communication system 20 in the embodiment includes a semiconductor chip 27 and a semiconductor chip 37. The semiconductor chip 27 includes a modulator 21 (e.g., a PWM modulator) for modulating an input data signal, a transmitting (Tx) circuit 23 that may include a digital-to-analog converter (DAC), an amplifier, a filter, etc., and an antenna 25 (e.g., a micro-antenna) for transmitting a modulated radio frequency (RF) signal. The semiconductor chip 37 includes an antenna 31 (e.g., a micro-antenna) for receiving the transmitted RF signal from the antenna 25. The semiconductor chip 37 also includes a receiving (Rx) circuit 33 and a demodulator 35 (e.g., a PWM demodulator), and the receiving (Rx) circuit 33 may include a filter, an amplifier, an analog-to-digital converter (ADC), etc., and the demodulator 35 is used to digitally demodulate the received signal. The semiconductor chip 27 and the semiconductor chip 37 may be placed adjacent to each other in the same electrical device, such as in a motor control device. The electrical isolation between semiconductor chip 27 and semiconductor chip 37 is achieved by the mold compound of the package that separates the semiconductor chips (e.g., 27 and 37) and by maintaining the appropriate spacing of the lead frame bonded to the semiconductor chips. The RF signal transmission between the semiconductor chips is achieved by electromagnetic coupling between antennas 25 and 31.

[0023] Figure 3 FIG. 1 is a schematic diagram of a receiver circuit 100 with self-calibration capability in an embodiment. Note that for simplicity, Figure 3 Not all features of receiver circuit 100 are shown. Figure 3Connections or couplings are shown between the receiver circuit 100 and other devices (eg, 51 , 55 , 57 , and 125 ), which may not be part of the receiver circuit 100 .

[0024] refer to Figure 3 , the receiver circuit 100 includes an input terminal 102 (e.g., 102A and 102B) for receiving an input signal. The input terminals 102A and 102B are coupled to a bias voltage node Vb through coupling resistors 101A and 101B, respectively. The bias voltage node Vb is configured to receive a bias voltage. In some embodiments, the coupling resistors 101A and 101B have the same nominal resistance value. In the discussion herein, unless otherwise stated, "coupling" is used to refer to electrical coupling, and the term "coupling" is used to describe a situation where a first electrical component is directly or indirectly coupled to a second electrical component, while "direct coupling" is used to describe a direct electrical connection (e.g., via a copper wire) between a first electrical component and a second electrical component without an intermediate electrical component.

[0025] exist Figure 3 In the example of FIG. 1 , box 53 shows electrical isolation between Tx module 51 and receiver circuit 100. In particular, as a non-limiting example of electrical isolation, box 53 shows primary winding 55 electromagnetically coupled to secondary winding 57. A person skilled in the art will readily appreciate that, in addition to coils, other coupling methods, such as via micro-antennas (see, e.g. Figure 2 25 and 31) are also possible and are fully intended to be included within the scope of this disclosure. As an example, Figure 3 The Tx module 51 in may correspond to Figure 2 The modulator 21 and Tx circuit 23 in the embodiment.

[0026] exist Figure 3 In the example, the signal arriving at the input terminal 102 is an OOK modulated PWM signal, such as Figure 4 For temporary reference Figure 4 , which shows a PWM signal 201 and an OOK modulated PWM signal 203. The OOK modulated PWM signal 203 is generated by modulating a high-frequency RF signal by the PWM signal 201, so that during a time period when the PWM signal 201 is logic high, a high-frequency RF signal (e.g., a high-frequency sinusoidal signal) is transmitted, and during a time period when the PWM signal 201 is logic low, the high-frequency RF signal is not transmitted, and the signal 203 is maintained at logic low.

[0027] Refer to Figure 3 , the receiver circuit 100 further includes an envelope detector 104 (also referred to as an envelope detector circuit), a bias circuit 108, an amplifier 111, a comparator 121, and a driver circuit 123. The envelope detector 104 is configured to detect the envelope of the received signal. Figure 3 In the example of FIG. 1 , the envelope detector 104 includes a transistor M1 and a transistor M2 coupled in parallel between a node 105 and a reference voltage node 103 (eg, electrical ground). The transistors M1 and M2 may be any suitable type of transistor, such as a metal oxide semiconductor field effect transistor (MOSFET), a bipolar junction transistor (BJT), etc. Figure 3 As shown, a first load path terminal of transistor M1 (e.g., a drain terminal of a MOSFET or a collector terminal of a BJT) and a first load path terminal of transistor M2 (e.g., a drain terminal of a MOSFET or a collector terminal of a BJT) are coupled to node 105. A second load path terminal of transistor M1 (e.g., a source terminal of a MOSFET or an emitter terminal of a BJT) and a second load path terminal of transistor M2 (e.g., a source terminal of a MOSFET or an emitter terminal of a BJT) are coupled to reference voltage node 103. A control terminal of transistor M1 (e.g., a gate terminal of a MOSFET or a base terminal of a BJT) is coupled to input terminal 102A, and a control terminal of transistor M2 (e.g., a gate terminal of a MOSFET or a base terminal of a BJT) is coupled to input terminal 102B.

[0028] The envelope detector 104 further includes a resistor string 106, which includes a plurality of resistors, such as a resistor R An , resistor R Bn and resistor R L , where n=1, 2, ... N. The first end of the resistor string 106 (eg, Figure 3 ) is coupled to node 105, and a second end of resistor string 106 (eg, Figure 3 The upper end of the power supply voltage node 109 is coupled to the power supply voltage node 109, and the power supply voltage node 109 is configured to be coupled to the power supply voltage V DD .

[0029] In the illustrated embodiment, the resistor R An and resistor R Bn have the same number (eg, N) of resistors, and the resistors R An and R Bn The resistance (also referred to as resistance value) of the components is substantially the same (also referred to as nominally the same). In the discussion herein, when the phrase "substantially the same" (or "approximately the same") is used to describe components, it means that the components are manufactured to have the same nominal value or to have the same nominal physical / electrical properties. Those skilled in the art will readily appreciate that due to process variations during manufacturing, even components manufactured in the same batch may actually be slightly different from each other. For example, the resistor R An and resistor R Bn(n=1, 2...N) have the same nominal resistance value R, but the actual resistance value may deviate from the nominal resistance value R by, for example, less than 5% or less than 10%, depending on, for example, process control during manufacturing. Figure 3 In the example, the resistor R An and resistor R Bn The resistors R have the same number (eg, N). An and resistor R Bn There may be a different number of resistors. These and other variations are fully intended to be included within the scope of the present disclosure. As an example, depending on factors such as the bias current and the magnitude of the voltage correction to be performed, the resistor R An and resistor R Bn The resistance (eg, nominal value) may be between 250Ω and 1.25KΩ, such as 750Ω, and the resistor R L The resistance may be between 20KΩ and 100KΩ, such as 60KΩ.

[0030] Still refer to Figure 3 , the bias circuit 108 is configured to provide a reference voltage. Figure 3 In the example of FIG. 1 , the bias circuit 108 includes a first end (eg, Figure 3 The transistor M3 is connected between the lower end of the resistor string 110 (eg, Figure 3 The higher end of ) is coupled to the power supply voltage node 109.

[0031] In the illustrated embodiment, resistor string 110 is substantially identical to resistor string 106. In other words, resistor string 110 includes the same resistors R as resistor string 106. An , resistor R Bn and resistor R L , where n=1, 2, ... N. In some embodiments, the value N is the number of correction steps used to correct the voltage offset, the details of which will be discussed below. For example, a possible implementation may use 15 correction steps (e.g., N=15). Due to process variations during manufacturing, for example, the corresponding resistors in resistor strings 110 and 106 may have slightly different resistance values.

[0032] The difference between the reference voltage at node 115 of resistor string 110 and the signal voltage at node 107 of resistor string 106 is amplified by amplifier 111. The output of amplifier 111 is transmitted to comparator 121, which may be a hysteresis comparator. The output of comparator 121 is a demodulated PWM signal. The output of comparator 121 is transmitted to driver circuit 123, which drives, for example, a power switch 125 coupled between a power supply voltage node 127 and a reference voltage node (e.g., electrical ground). Power switch 125 may be, for example, a power switch (e.g., a power MOSFET) in a power converter (e.g., a buck converter, a boost converter, etc.).

[0033] Figure 5 In the embodiment shown Figure 3 A block diagram of signal processing in a receiver circuit 100. Figure 5 , the RF signal received by antenna 301 (eg, a miniature antenna) is transmitted to envelope detector 303 to generate envelope signal 311. Envelope detector 303 may correspond to Figure 3 The output of the envelope detector 303 (eg, envelope signal 311) is transmitted to the amplifier 305, which may correspond to Figure 3 The amplifier 305 amplifies the difference between the reference voltage (eg, zero voltage) and the envelope signal 311 to generate an amplified signal 313 at the output of the amplifier 305. The amplified signal 313 is transmitted to the hysteresis comparator 307, which may correspond to Figure 3 The output of the hysteresis comparator 307 is the demodulated PWM signal 315.

[0034] Return to reference Figure 3 In an ideal case, resistor string 106 and resistor string 110 are matched (e.g., identical), and transistors M1, M2, and M3 are matched (e.g., identical), in which case the input voltage of amplifier 111 is node 107 (which is the resistor R in resistor string 106). An and resistor R Bn and the voltage at node 115 (which is a resistor R in resistor string 110). An and resistor R Bn107 and 115). When no RF signal is received at input terminal 102, or when the OOK modulated PWM signal has a zero value, the voltages at nodes 107 and 115 should ideally be the same, thereby generating a zero voltage at the output of amplifier 111. However, due to, for example, process variations, resistor string 106 and resistor string 110 are not matched (e.g., the corresponding resistors may have slightly different resistance values), and / or transistors M1, M2, and M3 are not matched. As a result, there is a small voltage difference between the voltage at node 115 and the voltage at node 107. When the small voltage difference is greater than a certain threshold value (e.g., greater than about 100 mV or about 200 mV), after amplifier 111 amplifies the small voltage difference, the output signal V amp_out The supply voltage V DD Therefore, an error occurs in the output of the comparator 121 (which is a demodulated PWM signal).

[0035] As described above, when there is no RF input signal or when the RF input signal is zero, the mismatch between resistor strings 106 and 108 and / or the mismatch between transistors M1, M2, and M3 will cause the output signal V amp_out An offset is generated in the DC operating point of the amplifier 111 (e.g., an offset from zero voltage). This offset is also referred to as an offset in the DC operating point of the amplifier 111, or an offset in the DC operating point of the receiver circuit 100. The present disclosure discloses an embodiment calibration circuit that can automatically adjust the DC operating point of the receiver circuit to a small near-zero (e.g., less than 20 mV) value so that the input signal of the comparator 121 is at the correct voltage level and the PWM signal can be correctly demodulated.

[0036] like Figure 3 As shown, the calibration circuit includes a plurality of switches, such as switch S An , switch S Bn and switches S*, where n=1, 2...N. The calibration circuit also includes a calibration control circuit (eg, see Figure 6 400A or Figure 7 400B in the example). Multiple switches in Figure 3 Each switch has a first terminal (eg, Figure 3 The left terminal in) and the second terminal (for example, Figure 3 The first terminal of each switch is coupled to node 113, which is coupled to a first input terminal (e.g., a positive input terminal) of amplifier 111. The second terminal of each switch is coupled to a terminal of a corresponding resistor in resistor string 110. Specifically, switch S An (n=1, 2...N) second terminal (for example, Figure 3 The right terminal of the resistor R is coupled to a resistor R away from the node 115. An (n = 1, 2 ... N) terminals (for example, Figure 3 The lower terminal of the switch S Bn (n=1, 2...N) of the second terminal (e.g., Figure 3 The right terminal of the resistor R is coupled to a resistor R away from the node 115. Bn (n = 1, 2 ... N) terminals (for example, Figure 3 The switch S* is coupled between the node 113 and the node 115. The plurality of switches are controlled by corresponding control bits. For example, if the corresponding control bit A n (or B n ) is "1", then switch S An (or S Bn ) is closed, and if the corresponding control bit is "0", the switch S An (or S Bn )disconnect.

[0037] A calibration process for adjusting the DC operating point of the receiver circuit 100 using a calibration circuit is now described. The calibration process can be performed during startup of the receiver circuit 100 when PWM communication has not yet been started. The calibration process can also be performed on demand during operation of the receiver circuit 100 when, for example, large temperature changes cause further shifts in the DC operating point. For example, when a large temperature change is detected, an interrupt signal is transmitted to the receiver circuit 100, which sets the receiver circuit 100 to an interrupt mode. During the interrupt mode, demodulation of the PWM signal is stopped, and the receiver circuit 100 performs a calibration process to compensate for the shift in the DC operating point. The interrupt mode can last for several microseconds, for example. Compared to a one-time calibration or fine-tuning process performed during the initial programming phase or just after chip packaging, the currently disclosed calibration circuit and method allow for on-demand real-time calibration to compensate for DC operating point shifts caused by, for example, temperature changes or component aging.

[0038] In some embodiments, to perform the calibration process, all switches S An , S Bn and S* are opened at the beginning of the calibration process. Then the switch S* is closed and the output signal V of the amplifier 111 is determined. amp_out For example, if the voltage at node 113 (which is now connected to node 115 via switch S*) is higher than the voltage at node 107, the output signal V amp_out The sign is positive, and if the voltage at node 113 is lower than the voltage at node 107, the output signal V amp_out The sign of is negative. In an ideal situation (for example, all corresponding components match), when S* is closed, the output signal Vamp_out is zero, in which case the calibration process is not required and can be stopped at this stage.

[0039] Output signal V amp_out The sign of is used to select the set of switches to adjust during the calibration process. In particular, if the output signal V amp_out With a positive sign, select switch S An (n=1, 2, ... N). On the other hand, if the output signal V amp_out With a negative sign, select switch S Bn (n=1, 2…N).

[0040] The calibration process is performed by opening the switch S*. Next, the switch S* is moved in a direction from the switch S* to the last switch in the selected set of switches away from the switch S* (e.g., along the direction from S* to the last switch in the selected set of switches). A1 To S An direction, or along the B1 To S Bn direction) closes the selected set of switches one at a time until the output signal V amp_out The sign of the switch changes (e.g., from , or from positive to negative), or until the last switch (e.g., S An or S Bn ) has been closed.

[0041] For example, if switch S is selected An , then first close switch S A1 , and at switch S A1 First, check the output signal V after closing amp_out If the sign changes, the calibration process ends. If the sign does not change, the calibration process ends by opening switch S A1 Continue, then close switch S A2 And switch S A2 After closing, check the output signal V amp_out Repeat this process until the output signal V amp_out until the sign of the selected switch set (e.g., S An ) has been closed, at which point the calibration process is complete. Note that during the calibration process, only one switch is closed at a time, and at most one switch is closed at any time.

[0042] Those skilled in the art will readily appreciate that after the calibration process is successfully completed (for example, when the output signal V amp_out When the sign of changes), the voltage difference between the voltage at the node 113 and the voltage at the node 107 is at most ε=RI bias , where R is the resistor R An and RBn The resistance of each of the bias is the current value flowing through the resistor string 110. The gain of the amplifier 111 is represented by G, and the maximum offset in the DC operating point is εG. By appropriately selecting the resistor R, the maximum offset in the DC operating point can be controlled below the target level, for example, less than 50mV or less than 20mV. As an example, the resistor R can be selected to be less than 750Ω.

[0043] As another example, if switch S is selected Bn , then switch S B1 , S B2 …S Bn Close one at a time until the output signal V amp_out until the sign of the selected switch set (e.g., S Bn ) is closed, and the calibration process is now complete. The details are similar to those above for the selector switch S An The details discussed in the example are therefore not repeated here.

[0044] After the calibration process is completed, the switches that were closed just before the calibration process is completed remain closed after the calibration process. After the calibration process is completed, the positions of the switches represent the optimal configuration of the switches for minimizing the DC operating point, and this configuration is used for a normal operating mode, where an RF signal (e.g., an OOK modulated PWM signal) is applied to input terminals 102A and 102B and demodulated by receiver circuit 100.

[0045] Figure 6 FIG. 4 is a schematic diagram of a calibration control circuit 400A in one embodiment. The calibration control circuit 400A may be used to control the calibration process during the calibration process. Figure 3 Switching (e.g., opening and closing) of multiple switches in.

[0046] The calibration control circuit 400A includes a comparator switch detector circuit 450. The comparator switch detector circuit 450 is configured to generate a calibration enable signal 459 (eg, an efficient enable signal) for a calibration process. Figure 6 In the example of FIG. 4 , the calibration enable signal 459 (also referred to as the T_CAL signal) rises from low to high at the beginning of the calibration process, remains high during the calibration process, and falls from high to low at the end of the calibration process. In the illustrated embodiment, during the calibration process, the comparator switching detector circuit 450 monitors the voltage V at the node 113. 113 (See Figure 3 ) and the voltage V at the node 107 107 (See Figure 3). Once the sign of the voltage difference changes, the comparator switching detector circuit 450 drops the calibration enable signal 459 from high to low, thereby disabling (eg, ending) the calibration process. Figure 6 As shown, the calibration enable signal 459 enables or disables (eg, inhibits) the calibration process by gating the clock signal CK using the AND gate 431. The clock signal CK is generated by the oscillator 433 and is used to drive the counter 415 or 425 of the calibration control circuit 400A.

[0047] like Figure 6 As shown, the calibration control circuit 400A further includes a comparator 411 for comparing the voltage V 113 and voltage V 107 , the output of comparator 411 is voltage V 113 and voltage V 107 In some embodiments, comparator 411 may be Figure 3 The output of comparator 411 is used to select a switch set (eg, S An or S Bn ) to operate (e.g., switch) in calibration mode.

[0048] For example, during the calibration process, when the output of comparator 411 is logic high, AND gate 413 allows clock signal CK to pass to drive counter 415. The output of counter 415 is transmitted to multiplexer circuit (MUX) 417, which is configured to generate control bit A. n , n = 1, 2..., N, where the control bit A n Each control bit is used to control Figure 3 The corresponding switch S in An As each clock cycle enters, the output of counter 415 increases by 1 to generate the output sequence 1, 2, 3, etc. MUX 417 acts as a decoder circuit that switches control bit A when the output of counter 415 is n. n Set to 1 and set all other control bits A m is set to 0 (m≠n). Therefore, as each clock cycle enters the counter 415, the switch S A1 , S A2 …S An Since inverter 419 inverts the logic high signal at the output of comparator 411, AND gate 421 is closed (e.g., forced to logic zero), and clock signal CK cannot drive counter 425 through AND gate 421. In other words, counter 425 is frozen and its output remains at zero.

[0049] As another example, when the output of comparator 411 is logic low, AND gate 413 is closed, thereby freezing counter 415. AND gate 421 is now open to allow clock signal CK to drive counter 425 coupled to MUX 427. MUX 427 operates in a similar manner to MUX 417, providing a switch S Bn Generate control bit B n The details will not be repeated here.

[0050] Further details of the comparator switching detector circuit 450 are discussed below to understand its operation. Figure 6 As shown, the comparator switch detector circuit 450 includes D flip-flops 441, 447, and 457. The data input terminals D of the D flip-flops 441 and 457 are connected to a logic high signal (e.g., V DD ), and the data input terminal D of the D flip-flop 447 is connected to the output of the comparator 411. A calibration enable signal 459 is generated.

[0051] To start the calibration process, a signal 440 (also referred to as S_CAL signal) having a step function shape is applied to the clock terminal CK of a D flip-flop 441, which turns a logic high value (e.g., V DD ) is latched to its output terminal Q. The output of the D flip-flop 441 is delayed by the delay element 443 and applied to its reset terminal R, which forces the output at its output terminal Q back to logic low, thereby generating a reset pulse RESET. The reset pulse RESET is used to reset other components (e.g., 447, 457, 415, 425) in the calibration control circuit 400A. The reset pulse RESET can also be used as Figure 3 The control bit of switch S* in FIG. 4 is a control bit of switch S*, which closes switch S* for a short time and then opens switch S*. Another option for generating the control bit of switch S* is to connect the A1 and B1 control bits to the input of an OR gate and use the output of the OR gate as the control bit of switch S*.

[0052] like Figure 6 As shown, the reset pulse RESET is inverted by the inverter 445 and used as the clock signal CK of the D flip-flop 447, which latches the output value of the comparator 411 at its output terminal Q at the beginning of the calibration process. Before the end of the calibration process, the output of the comparator 411 remains unchanged. As a result, the XOR gate 449 receives two identical input signals and generates a logic low output, which forces the output of the AND gate 453 to be logic low. Note that the last switch (e.g., S An or S Bn ) before closing, control position A n and B nis zero, which results in a zero (e.g., logic low) output at OR gate 451. Therefore, before the calibration process is completed, the output of OR gate 455 is also zero, forcing the clock terminal CK of D flip-flop 457 to zero. As a result, the inverter output of D flip-flop 457 is Maintains a logic high value after reset throughout the calibration process.

[0053] When the output of comparator 411 changes sign, the output at the Q terminal of D flip-flop 447 does not change because there is no clock signal to latch the new value. As a result, the two input signals of XOR gate 449 are different, and the output of XOR gate 449 is 1 (e.g., logic high), which turns off AND gate 453 to allow the inverted clock signal to Through and drives D flip-flop 457. The inverted clock signal At the next clock cycle, a logic high value (e.g., V DD ) is latched into the D flip-flop 457, and the inverting output terminal of the D flip-flop 457 goes low, which signals the end of the calibration process. Note that another trigger event for ending the calibration process is when A n or B n When the last switch in the selected switch set is closed, in this case, OR gate 451 outputs a logic high signal, which in turn causes the output of OR gate 455 to become logic high, thereby generating a rising edge at the clock terminal CK of D flip-flop 457 to latch the logic high value (e.g., V DD ). The output of the inverting output terminal of the D flip-flop 457 becomes a logic low value to end the calibration process.

[0054] Figure 7 4 is a schematic diagram of a calibration control circuit 400B in another embodiment. The calibration control circuit 400B can be used to control the calibration process similar to the calibration control circuit 400A. The calibration control circuit 400B is similar to the calibration control circuit 400A (e.g., having the same comparator switching detector circuit 450), but instead of using Figure 6 The counters 415 / 425 and MUX 417 / 427 in Figure 7 Shift registers 505 and 515 are used to simplify the design.

[0055] See also Figure 7 , the comparator switching detector circuit 450 generates a reset signal RESET and a calibration enable signal T_CAL, as described above with reference to Figure 6The reset signal RESET resets the D flip-flops 507 and 517 and the shift registers 505 and 515. The clock signal CK is transmitted to drive the shift registers 505 and 515. The input signal applied to the input terminal D of the shift register 505 (or 515) is 1 or 0 according to the output of the comparator 411, as described below.

[0056] For example, after the calibration process starts, the outputs of the D flip-flops 507 and 517 are reset to zero. When the output of the comparator 411 is 1, the output of the XOR gate 503 is 1, which is transmitted to the input terminal D of the shift register 505. In the first input clock cycle, the value "1" is shifted into the first register A1 (e.g., the leftmost register) of the shift register 505. The output of the first register A1 is connected to the clock terminal CK of the D flip-flop 507. When the value "1" is shifted into the first register A1, a rising edge is generated at the clock terminal CK of the D flip-flop 507, which latches a logic high signal (e.g., V DD ), and the output terminal Q of the D flip-flop 507 rises to high (e.g., a "1" value), thereby generating a zero output at the XOR gate 503. This ensures that the subsequent input data to the shift register 505 is zero, and the value "1" in the first register A1 is shifted to the right in subsequent clock cycles. Registers A1, A2, ... A N The value is used as Figure 3 Control bit A in n (n=1, 2, . . . , N) Note that when the output of the comparator 411 is 1, the output of the NOR gate 513 is 0, which is transmitted to the input terminal D of the shift register 515. The register B of the shift register 515 n The value of (n=1, 2, ... N) remains at zero, and Figure 3 Used as control bit B n (n=1, 2…N).

[0057] As another example, when the output of the comparator 411 is zero, the value "1" is shifted down to the shift register 515 to control the switch S Bn The value "0" is shifted down to the shift register 505 so that the switch S An Keep it disconnected during the calibration process. After reading the discussion of the previous example, those skilled in the art should be able to easily analyze the operation of the calibration control circuit 400B of the current example. The details are not discussed here.

[0058] Figure 8 In one embodiment, Figure 3 FIG. 1 is a timing diagram of the receiver circuit 100 during a calibration process. Figure 8 In the signal 801, Figure 6 or Figure 7 The clock signal CK in FIG. 8 is a clock signal CK in FIG. 801 , and the signal 803 illustrates the calibration enable signal T_CAL. Signals 805, 807 and 809 respectively illustrate the first three bit control signals, such as A1, A2 and A3 (or B1, B2 and B3). Signal 811 illustrates the node 113 (see FIG. 1 ) provided by the bias circuit 108. Figure 3 ), signal 813 shows the voltage at node 107 provided by envelope detector 104, and signal 815 shows Figure 3 The output signal V of the amplifier 111 amp_out .

[0059] like Figure 8 As shown, before the calibration process begins, due to component mismatch, there is a relatively large (eg, greater than 200 mV, such as 250 mV) voltage difference between signals 811 and 813, which causes the output signal V amp_out In V DD The voltage level (e.g., 3V) is saturated. When the calibration process begins at time t1, the control bits sequentially close the switches in the selected switch set one at a time. The difference between signals 811 and 813 decreases with each clock cycle. At time t2, the calibration process ends, as shown by the falling edge of T_CAL signal 803. The output signal V of amplifier 111 is amp_out The DC operating point of the receiver circuit 100 has been adjusted to a level small enough to avoid or reduce demodulation errors.

[0060] Fig. 9 900 is a block diagram of a motor control system in one embodiment. The motor control system 900 includes a transmitter 930, which includes a PWM modulator 901 and a micro-antenna 903. The motor control system 900 also includes a receiver circuit 940, which includes a micro-antenna 905, a PWM demodulator 907, and a gate driver circuit 909. The receiver circuit 940 may correspond to Figure 3 Receiver circuit 100. The motor control system 900 also includes an output device 911, such as a power converter including a power switch (e.g., an IGBT power switch or a MOSFET power switch). The output of the output device 911 is used to drive the motor 913. In some embodiments, the transmitter 930 transmits an OOK modulated PWM signal. The receiver circuit 940 receives and demodulates the OOK modulated PWM signal. The output of the PWM demodulator 907 is a demodulated PWM signal, which is used to control the output device 911 (e.g., a power converter) to provide a drive voltage / current to the motor 913.

[0061] Fig. 10A and10B 1 and 2 show a flow chart of a method of calibrating a receiver circuit according to some embodiments. It should be understood that Fig. 10A and 10B The embodiment methods shown are merely examples of many possible embodiment methods. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, the present invention may be added, removed, replaced, rearranged, or repeated. Fig. 10A and 10B The steps shown.

[0062] refer to Fig. 10A and 10B At block 1010, a voltage difference between a first node of a receiver circuit and a second node of the receiver circuit is measured, wherein the receiver circuit comprises: an envelope detector configured to detect an envelope of an input signal of the receiver circuit, wherein the envelope detector comprises a first resistor string coupled to a first transistor and a second transistor coupled in parallel, wherein the first resistor string comprises a first resistor coupled in series and a second resistor coupled in series, the first resistor and the second resistor being connected at the second node; a bias circuit configured to provide a reference voltage, wherein the bias circuit comprises a second resistor string coupled to a third transistor, wherein the second resistor string comprises a third resistor coupled in series and a fourth resistor coupled in series, the third resistor and the fourth resistor being connected at A plurality of switches coupled in parallel, wherein the plurality of switches include a first switch, a second switch, and a third switch, wherein each of the first switches is coupled between the first node and a first terminal of a corresponding third resistor in the third resistors away from the third node, wherein each of the second switches is coupled between the first node and a second terminal of a corresponding fourth resistor in the fourth resistors away from the third node, and wherein the third switch is coupled between the first node and the third node; and an amplifier, wherein a first input terminal of the amplifier is coupled to the first node, and a second input terminal of the amplifier is coupled to the second node, wherein the voltage difference is generated at an output terminal of the amplifier. At block 1020, the plurality of switches are opened. At block 1030, after the plurality of switches are opened, the third switch is closed. At block 1040, after the third switch is closed, a switch set is selected from the plurality of switches based on the sign of the voltage difference, wherein if the sign is positive, the switch set is the first switch, or if the sign is negative, the switch set is the second switch. At block 1050, while the sign remains unchanged, the set of switches is closed one at a time in a first direction from the third switch to a last switch in the set of switches away from the third switch. At block 1060, when the sign changes, the calibration process stops.

[0063] The disclosed embodiments can achieve advantages. The disclosed embodiment receiver circuit has a calibration circuit that allows the DC operating point of the receiver circuit to be automatically adjusted. A calibration process can be performed during a calibration mode to reduce the offset in the DC operating point to a target level so that the received RF signal can be properly demodulated. The calibration process can be performed as needed, such as in the field where the device is deployed, to compensate for factors such as temperature drift and component aging. As a result, the receiver achieves improved performance and provides robustness to adverse effects such as temperature changes and component aging.

[0064] Exemplary embodiments of the present invention are summarized here. Other embodiments may also be understood from the entirety of the specification and claims submitted here.

[0065] Example 1. In the example, a receiver circuit includes: a first resistor string including a plurality of resistors coupled in series; a second resistor string including a plurality of resistors coupled in series; a first transistor and a second transistor coupled in parallel, wherein a first load path terminal of the first transistor and a first load path terminal of the second transistor are coupled to a reference voltage node, wherein a second load path terminal of the first transistor and a second load path terminal of the second transistor are coupled to a first end of the first resistor string, and a second end of the first resistor string is coupled to a power supply voltage node, wherein a first control terminal of the first transistor and a second control terminal of the second transistor are coupled to a first input terminal of the receiver circuit and a second input terminal of the receiver circuit, respectively; a third transistor, wherein the a first load path terminal of the third transistor coupled to the reference voltage node, and a second load path terminal of the third transistor coupled to a first end of the second resistor string, a second end of the second resistor string coupled to the supply voltage node, wherein a control terminal of the third transistor is coupled to a bias voltage node; a plurality of switches coupled in parallel, wherein each switch of the plurality of switches has a first terminal and a second terminal, wherein the first terminal of the plurality of switches is coupled to a first node, wherein the second terminal of each switch is coupled to a terminal of a corresponding resistor in the second resistor string; and an amplifier, wherein a first input terminal of the amplifier is coupled to the first node, and a second input terminal of the amplifier is coupled to a second node in the first resistor string.

[0066] Example 2. The receiver circuit according to Example 1, wherein the amplifier is configured to amplify a voltage difference between the first node and the second node, wherein the receiver circuit further comprises a hysteresis comparator coupled to an output terminal of the amplifier.

[0067] Example 3. The receiver circuit of Example 1, wherein the first transistor, the second transistor, and the third transistor are substantially identical, wherein the first resistor string and the second resistor string are substantially identical.

[0068] Example 4. The receiver circuit of Example 3, wherein the bias voltage node is coupled to a first control terminal of the first transistor and a second control terminal of the second transistor through a first coupling resistor and a second coupling resistor, respectively, wherein the first coupling resistor and the second coupling resistor have the same nominal resistance value.

[0069] Example 5 A receiver circuit of Example 3, wherein the multiple resistors in the second resistor string include: a first resistor, which is coupled in series between the first end of the second resistor string and a third node; a second resistor coupled in series between the third node and a fourth node; and a third resistor coupled between the fourth node and the second end of the second resistor string, and wherein the multiple switches include: a first switch, wherein each of the first switches is coupled between the first node and a first terminal of a corresponding first resistor in the first resistors, the first terminal being away from the third node; a second switch, wherein each of the second switches is coupled between the first node and a second terminal of a corresponding second resistor in the second resistors, the second terminal being away from the third node; and a third switch coupled between the first node and the third node.

[0070] Example 6. A receiver circuit according to Example 5, wherein the receiver circuit is configured to perform a calibration process by: opening the plurality of switches; after opening the plurality of switches, closing the third switch; after closing the third switch, determining the sign of the voltage difference between the first node and the second node; and in response to determining that the sign is positive: opening the third switch; after opening the third switch, when the sign is positive, closing the first switches one at a time in a first direction from the third node toward the first end of the second resistor string; and stopping the calibration process when the sign becomes negative.

[0071] Example 7. The receiver circuit of Example 6, wherein closing the first switches one at a time comprises: closing a first switch of the first switches that is immediately adjacent to the third switch; determining whether the sign changes after closing the first switch of the first switches; and continuing the calibration process if the sign does not change.

[0072] Example 8. The receiver circuit according to Example 7, wherein continuing the calibration process comprises: opening a first one of the first switches; after opening the first one of the first switches, closing a second one of the first switches that is adjacent to the first one of the first switches; determining whether the sign changes after closing the second one of the first switches; and continuing the calibration process if the sign does not change.

[0073] Example 9. The receiver circuit according to Example 6, wherein the receiver circuit is further configured to perform the calibration process by: in response to determining that the sign is negative: opening the third switch; and after opening the third switch, when the sign is negative, closing the second switches one at a time in a second direction from the third node toward the second end of the second resistor string; and stopping the calibration process when the sign becomes positive.

[0074] Example 10. The receiver circuit of Example 6, wherein after stopping the calibration process, a single switch of the plurality of switches is closed, wherein the receiver circuit is further configured to, after stopping the calibration process: keep the single switch of the plurality of switches closed; and demodulate received signals coupled to the first and second input terminals of the receiver circuit.

[0075] Example 11. In one example, a circuit for demodulating an on-off keying (OOK) modulated pulse width modulation (PWM) signal includes: an envelope detector configured to detect an envelope of the OOK modulated PWM signal, including: a first resistor string including resistors coupled in series; and a first transistor and a second transistor coupled in parallel between a first end of the first resistor string and a reference voltage node, wherein the second end of the first resistor string is coupled to a power supply voltage node; a bias circuit configured to provide a reference voltage, including: a second resistor string including resistors coupled in series; and a third transistor coupled between a first end of the second resistor string and the reference voltage node, wherein the second end of the second resistor string is coupled to the power supply voltage node; a plurality of switches coupled in parallel, wherein each of the plurality of switches has a first terminal and a second terminal, wherein the first terminal of each switch is coupled to a first node, and the second terminal of each switch is coupled to a terminal of a corresponding resistor in the second resistor string; an amplifier, a first input of the amplifier being coupled to the first node, and a second input of the amplifier being coupled to a second node in the first resistor string; and a comparator coupled to an output of the amplifier.

[0076] Example 12. The circuit of Example 11, wherein the first resistor string and the second resistor string have the same number of resistors, wherein each resistor in the first resistor string has a corresponding resistor in the second resistor string, wherein each resistor in the first resistor string and the corresponding resistor in the second resistor string have the same nominal resistance value.

[0077] Example 13. The circuit of Example 12, wherein the second resistor string includes: a first resistor coupled in series between the first end of the second resistor string and a third node; a second resistor coupled in series between the third node and a fourth node; and a third resistor coupled between the fourth node and the power supply voltage node, and wherein the plurality of switches includes: a first switch, wherein each of the first switches is coupled between the first node and a first terminal of a corresponding one of the first resistors away from the third node; a second switch, wherein each of the second switches is coupled between the first node and a second terminal of a corresponding one of the second resistors away from the third node; and a third switch coupled between the first node and the third node.

[0078] Example 14. The circuit of Example 13, wherein the circuit is configured to perform a calibration process by: opening the plurality of switches; after opening the plurality of switches, closing the third switch; after closing the third switch, determining a sign of a voltage difference between the first node and the second node; selecting a set of switches based on the sign of the voltage difference, wherein if the sign is positive, the set of switches is the first switch, or if the sign is negative, the set of switches is the second switch; while the sign remains unchanged, closing the set of switches one at a time in a first direction from the third switch toward a last switch in the set of switches away from the third switch; and stopping the calibration process when the sign changes.

[0079] Example 15. The circuit according to Example 14, wherein closing the set of switches one at a time comprises: closing a first switch in the set of switches that is closest to the third switch; after closing the first switch in the set of switches, opening the first switch in the set of switches; and after opening the first switch in the set of switches, closing a second switch in the set of switches that is closest to the first switch in the set of switches.

[0080] Example 16. The circuit of Example 13, wherein the first resistor string comprises: a fourth resistor coupled in series between the first end of the first resistor string and the second node; a fifth resistor coupled in series between the second node and a fifth node; and a sixth resistor coupled between the fifth node and the power supply voltage node.

[0081] Example 17. In one example, a method of calibrating a receiver circuit includes: measuring a voltage difference between a first node of the receiver circuit and a second node of the receiver circuit, wherein the receiver circuit includes: an envelope detector configured to detect an envelope of an input signal of the receiver circuit, wherein the envelope detector includes a first resistor string coupled to a first transistor and a second transistor coupled in parallel, wherein the first resistor string includes a first resistor coupled in series and a second resistor coupled in series, the first resistor and the second resistor being connected at the second node; a bias circuit configured to provide a reference voltage, wherein the bias circuit includes a second resistor string coupled to a third transistor, wherein the second resistor string includes a third resistor coupled in series and a fourth resistor coupled in series, the third resistor and the fourth resistor being connected at a third node; a plurality of switches coupled in parallel, wherein the plurality of switches include a first switch, a second switch, and a third switch, wherein each of the first switches is coupled in phase with the first node and the third resistor away from the third node. a first terminal of a fourth resistor remote from the third node, wherein each of the second switches is coupled between the first node and a second terminal of a corresponding one of the fourth resistors remote from the third node, and wherein the third switch is coupled between the first node and the third node; and an amplifier, wherein a first input terminal of the amplifier is coupled to the first node and a second input terminal of the amplifier is coupled to the second node, wherein the voltage difference is generated at an output terminal of the amplifier; opening the plurality of switches; after opening the plurality of switches, closing the third switch; after closing the third switch, selecting a set of switches from the plurality of switches based on a sign of the voltage difference, wherein if the sign is positive, the set of switches is the first switch, or if the sign is negative, the set of switches is the second switch; while the sign remains unchanged, closing the set of switches one at a time in a first direction from the third switch toward a last switch in the set of switches remote from the third switch; and stopping calibrating the receiver circuit when the sign changes.

[0082] Example 18. The method of Example 17, wherein the first transistor and the second transistor are coupled between the first resistor and a reference voltage node, wherein the third transistor is coupled between the third resistor and the reference voltage node.

[0083] Example 19. The method of Example 18, wherein closing the set of switches one at a time comprises: closing a first switch in the set of switches that is closest to the third switch; after closing the first switch in the set of switches, opening the first switch in the set of switches; and after opening the first switch in the set of switches, closing a second switch in the set of switches that is closest to the first switch in the set of switches.

[0084] Example 20. The method of Example 19, wherein after stopping calibrating the receiver circuit, only one switch of the plurality of switches is closed.

[0085] Although the present invention has been described with reference to illustrative embodiments, this description is not intended to be interpreted in a limiting sense. Various modifications and combinations of the illustrative embodiments and other embodiments of the present invention will be apparent to those skilled in the art, based on the reference specification. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A receiver circuit comprising: a first resistor string comprising a first plurality of resistors coupled in series, wherein the first plurality of resistors comprises a first resistor and a second resistor connected at a first node; a first transistor and a second transistor coupled in parallel between a first end of the first resistor string and a reference voltage node, wherein a second end of the first resistor string is coupled to a supply voltage node; a second resistor string comprising a second plurality of resistors coupled in series, wherein the second plurality of resistors comprises a third resistor and a fourth resistor connected at a second node; a third transistor coupled between a first end of the second resistor string and the reference voltage node, wherein a second end of the second resistor string is coupled to the supply voltage node; a plurality of switches coupled in parallel, wherein each switch of the plurality of switches is coupled between a corresponding node in the second resistor string and a third node; as well as An amplifier, wherein a first input terminal of the amplifier is coupled to the first node and a second input terminal of the amplifier is coupled to the third node.

2. The receiver circuit of claim 1 , further comprising: a hysteresis comparator coupled to the output terminal of the amplifier; as well as A driver circuit is coupled to the output terminal of the hysteresis comparator.

3. The receiver circuit of claim 1 , wherein a first control terminal of the first transistor and a second control terminal of the second transistor are coupled to a first input terminal of the receiver circuit and a second input terminal of the receiver circuit, respectively, and wherein a third control terminal of the third transistor is coupled to a bias voltage node.

4. The receiver circuit of claim 3, further comprising: a first coupling resistor coupled between the first control terminal of the first transistor and the bias voltage node; as well as A second coupling resistor is coupled between the second control terminal of the second transistor and the bias voltage node.

5. The receiver circuit of claim 1 , wherein the plurality of switches comprises: first switches, wherein each of the first switches is coupled between the third node and a first terminal of a respective one of the third resistors, the first terminal being remote from the second node; second switches, wherein each of the second switches is coupled between the third node and a second terminal of a respective one of the fourth resistors, the second terminal being remote from the second node; as well as A third switch is coupled between the third node and the second node.

6. The receiver circuit of claim 5, wherein the third resistor is between the fourth resistor and the third transistor, wherein the receiver circuit further comprises a calibration control circuit configured to generate control signals for the plurality of switches during a calibration process.

7. The receiver circuit of claim 6 , wherein the calibration control circuit is configured to perform the calibration process by: opening the plurality of switches; After opening the plurality of switches, closing the third switch; After closing the third switch, comparing the voltage at the first node with the voltage at the third node; as well as In response to determining that the voltage at the third node is higher than the voltage at the first node: Disconnecting the third switch; After opening the third switch, when the voltage at the third node is higher than the voltage at the first node, closing the first switches one at a time in a first direction from the second node toward the first end of the second resistor string; as well as When the voltage at the third node is lower than or equal to the voltage at the first node, the calibration process is stopped.

8. The receiver circuit of claim 7, wherein closing the first switches one at a time comprises: closing a first one of the first switches that is adjacent to the third switch; after closing the first one of the first switches, determining whether a voltage at the third node is higher than a voltage at the first node; as well as If the voltage at the third node is higher than the voltage at the first node, the calibration process continues.

9. The receiver circuit of claim 8, wherein continuing the calibration process comprises: Disconnecting the first one of the first switches; After opening the first one of the first switches, closing a second one of the first switches that is adjacent to the first one of the first switches; after closing the second one of the first switches, determining whether a voltage at the third node is higher than a voltage at the first node; and If the voltage at the third node is higher than the voltage at the first node, the calibration process continues.

10. The receiver circuit of claim 6, wherein the calibration control circuit comprises: A first circuit is configured to generate a calibration enable signal, wherein the first circuit comprises: a first D flip-flop, wherein an input terminal of the first D flip-flop is configured to be coupled to a logic high signal, and a clock terminal of the first D flip-flop is configured to be provided with a step function signal when the calibration process starts; a delay element coupled between an output terminal of the first D flip-flop and a reset terminal of the first D flip-flop; a second D flip-flop, wherein an input terminal of the second D flip-flop is coupled to an output terminal of the amplifier; a first inverter coupled between the output terminal of the first D flip-flop and a clock terminal of the second D flip-flop; a first XOR gate, wherein a first input terminal of the first XOR gate is coupled to an output terminal of the second D flip-flop, and a second input terminal of the first XOR gate is coupled to the output terminal of the amplifier; a first AND gate, wherein a first input terminal of the first AND gate is coupled to the output terminal of the first XOR gate, and a second input terminal of the first AND gate is coupled to an inverted clock signal; and a third D flip-flop, wherein a clock terminal of the third D flip-flop is coupled to the output terminal of the first AND gate, an input terminal of the third D flip-flop is configured to be coupled to the logic high signal, wherein the calibration enable signal is generated at an inverting output terminal of the third D flip-flop.

11. The receiver circuit of claim 10, wherein the calibration control circuit further comprises: a second AND gate, wherein a first input terminal of the second AND gate is coupled to the calibration enable signal and a second input terminal of the second AND gate is coupled to a clock signal; a third AND gate and a fourth AND gate, wherein a first input terminal of the third AND gate and a first input terminal of the fourth AND gate are coupled to an output terminal of the third AND gate, wherein a second input terminal of the third AND gate is coupled to the output terminal of the amplifier; a second inverter coupled between the output terminal of the amplifier and the second input terminal of the fourth AND gate; a first counter and a second counter, wherein a first clock terminal of the first counter and a second clock terminal of the second counter are coupled to an output terminal of the third AND gate and an output terminal of the fourth AND gate, respectively; as well as a first multiplexer coupled to the first counter and a second multiplexer coupled to the second counter, wherein the first multiplexer is configured to convert an output of the first counter into a first plurality of control bits for the first switch, and wherein the second multiplexer is configured to convert an output of the second counter into a second plurality of control bits for the second switch.

12. The receiver circuit of claim 10 , wherein the calibration control circuit further comprises: a second AND gate, wherein a first input terminal of the second AND gate is coupled to the calibration enable signal and a second input terminal of the second AND gate is coupled to the clock signal; a second XOR gate, wherein a first input terminal of the second XOR gate is coupled to the output terminal of the amplifier; a fourth D flip-flop, wherein an input terminal of the fourth D flip-flop is configured to be coupled to the logic high signal, and an output terminal of the fourth D flip-flop is coupled to a second input terminal of the second XOR gate; a first shift register, wherein an input terminal of the first shift register is coupled to an output terminal of the second XOR gate, a clock terminal of the first shift register is coupled to an output terminal of the second AND gate, wherein an output of a first register in the first shift register is coupled to a clock terminal of the fourth D flip-flop; a NOR gate, wherein a first input terminal of the NOR gate is coupled to the output terminal of the amplifier; a fifth D flip-flop, wherein an input terminal of the fifth D flip-flop is configured to be coupled to the logic high signal, and an output terminal of the fifth D flip-flop is coupled to a second input terminal of the NOR gate; as well as A second shift register, wherein an input terminal of the second shift register is coupled to an output terminal of the NOR gate, a clock terminal of the second shift register is coupled to an output terminal of the second AND gate, and an output of a first register in the second shift register is coupled to a clock terminal of the fifth D flip-flop.

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