A signal processing chip and a signal monitoring system
By integrating RISC-V data driver baseband processor and main control module in the signal processing chip, baseband demodulation processing is implemented, which solves the problem that existing monitoring equipment cannot achieve full-band signal monitoring, improves monitoring accuracy and signal quality, and simplifies the deployment process.
Patent Information
- Application Number
- CN202411929568.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-25
- Publication Date
- 2025-04-04
AI Technical Summary
Existing monitoring equipment cannot achieve full-band signal monitoring, resulting in low monitoring accuracy and signal quality, and requires separate deployment, which is relatively high.
By integrating the data-driven baseband processor and main control module based on the streamlined instruction set open source architecture RISC-V in the signal processing chip, baseband demodulation processing is realized, time division duplex TDD synchronization is supported, and full-band signal monitoring is performed.
It significantly improves the accuracy and signal quality of full-band monitoring, simplifies the deployment process, reduces deployment costs, and improves integration.
Smart Images
Figure CN119766269A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of wireless communication technology, and in particular to a signal processing chip and a signal monitoring system. Background Art
[0002] With the development of wireless communication technology, people can meet various network needs in buildings. In order to achieve comprehensive network coverage, the application of passive signal monitoring system plays a very important role.
[0003] In order to ensure the normal operation of the passive signal monitoring system, the relevant technology usually requires the configuration of monitoring equipment to monitor the corresponding signal frequency band.
[0004] However, most of the existing monitoring equipment performs one-to-one monitoring of signals. No monitoring equipment can monitor frequencies and frequency bands other than the target frequency, resulting in low monitoring accuracy and signal quality. In addition, the equipment needs to be deployed separately, so the deployment cost is high. Summary of the invention
[0005] The embodiments of the present disclosure at least provide a signal processing chip and a signal monitoring system to achieve full-band signal monitoring through baseband demodulation processing, greatly improving monitoring accuracy and signal quality, and only requiring simple deployment with higher integration.
[0006] In a first aspect, an embodiment of the present disclosure provides a signal processing chip, including: a data-driven baseband processor and a main control module built on the basis of a reduced instruction set open source architecture RISC-V;
[0007] The data-driven baseband processor is used to process baseband signals, support time division duplex (TDD) synchronization, and provide an antenna address interface; in response to a signal monitoring instruction for a signal monitoring system, receive a radio frequency signal sent by a radio frequency transceiver, and transmit the radio frequency signal to the main control module;
[0008] The main control module is used to control the start and stop of the signal processing chip and obtain the signal analysis situation for the signal monitoring system, and the signal analysis situation is used to characterize the signal monitoring results within the full frequency band.
[0009] In a possible implementation manner, when the radio frequency transceiver is applied to a base station signal source connected to the signal monitoring system, the data-driven baseband processor is specifically used to:
[0010] In the environment where the signal monitoring system is located, the base station synchronization signal is detected, and the first radio frequency signal sent by the base station source is baseband demodulated, and the synchronization signal and the time slot indication signal are output while the first baseband demodulation signal is output.
[0011] In a possible implementation manner, when the radio frequency transceiver is applied to a user equipment connected to the signal monitoring system, the data-driven baseband processor is specifically used to:
[0012] In the environment where the signal monitoring system is located, baseband demodulation is performed on the second radio frequency signal sent by the user equipment, and a second baseband demodulated signal is output for signal analysis for the signal monitoring system.
[0013] In a possible implementation manner, when multiple antennas are configured, a frequency mixing chip is further included, which is used to:
[0014] The signal power transmitted by the user equipment and / or the antenna is determined, and the signal of the monitored frequency band is mixed, and the obtained mixed signal is output to the main control module.
[0015] In a possible implementation, it further includes an expandable interface and an auxiliary function module, wherein the expandable interface is arranged on a bus, and the expandable interface performs signal transmission with both the data-driven baseband processor and the main control module;
[0016] The auxiliary function module transmits signals with the main control module via the peripheral bus to support the control logic of the main control module.
[0017] In a possible implementation, the auxiliary function module includes one or more of the following components:
[0018] A debug controller for port debugging;
[0019] A clock manager for synchronizing the system clock with the internal clock;
[0020] A general purpose input / output port controller for input / output interactive control;
[0021] Asynchronous serial interface controller for receiving system instructions and transmitting data;
[0022] Controller for external Flash storage control;
[0023] A controller for enabling a low power consumption power saving mode;
[0024] A dog timer used to implement a timing function.
[0025] In a second aspect, the present disclosure further provides a signal monitoring system, comprising: the signal processing chip according to any one of the first aspect and various embodiments thereof;
[0026] The signal processing chip is used to perform signal monitoring on the signal monitoring system and determine the signal monitoring results within the full frequency band.
[0027] In a possible implementation, the device further includes a receiving antenna, a frequency shifter, a power management chip and a networking communication module, wherein the frequency shifter, the signal processing chip and the networking communication module are connected in sequence;
[0028] The frequency shifter determines the signal power transmitted by the user equipment and / or the antenna, mixes the signal of the frequency band to be monitored, and transmits the obtained mixed signal to the signal processing chip;
[0029] The signal processing chip is used to determine a signal monitoring result based on the mixing signal during the start-up control process of the power management chip, and transmit the signal monitoring result to the networking communication module;
[0030] The networked communication module is used to report the signal monitoring results generated by the signal processing chip to the cloud.
[0031] In a possible implementation, the networking communication module is further used to report antenna monitoring information of the receiving antenna to the cloud.
[0032] The above-mentioned signal processing chip and signal monitoring system are adopted, and the data-driven baseband processor in the signal processing chip processes the baseband signal, supports time division duplex TDD synchronization, and provides an antenna address interface; in response to the signal monitoring instruction for the signal monitoring system, the RF signal sent by the RF transceiver is received, and the main control module controls the start and stop of the signal processing chip to obtain the signal analysis situation for the signal monitoring system, and the signal analysis situation is used to characterize the signal monitoring results within the full frequency band. It can be seen that the data-driven baseband processor and the main control module constructed based on the reduced instruction set open source architecture RISC-V in the present disclosure integrate the signal processing chip, with a high degree of integration, and the corresponding signal monitoring function can be realized by simple deployment. At the same time, the use of the reduced instruction set open source architecture can realize baseband demodulation processing for RF signals, which significantly improves the accuracy and signal quality of full-band monitoring.
[0033] Other advantages of the present disclosure will be explained in more detail in conjunction with the following description and drawings.
[0034] It should be understood that the above description is only an overview of the technical solution of the present disclosure, so that the technical means of the present disclosure can be generally understood and then implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific implementation methods of the present disclosure are specifically described below with examples. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used together with the specification to illustrate the technical solutions of the present disclosure. It should be understood that the drawings only illustrate certain embodiments of the present disclosure and therefore should not be regarded as limiting the scope of protection. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work. Moreover, the same reference numerals are used to represent the same components throughout the drawings. In the drawings:
[0036] Figure 1 A schematic diagram of a module of a signal processing chip provided by an embodiment of the present disclosure is shown;
[0037] Figure 2 A pin diagram of a signal processing chip provided by an embodiment of the present disclosure is shown;
[0038] Figure 3 A frame diagram of a signal processing chip provided by an embodiment of the present disclosure is shown;
[0039] Figure 4 A frame diagram of a signal processing chip provided by another embodiment of the present disclosure is shown;
[0040] Figure 5 A system architecture diagram of a signal monitoring system provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION
[0041] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.
[0042] In the description of the embodiments of the present disclosure, it should be understood that terms such as "including" or "having" are intended to indicate the presence of the disclosed features, numbers, steps, behaviors, components, parts, or a combination thereof in the specification, and do not exclude the possibility of the presence of one or more other features, numbers, steps, behaviors, components, parts, or a combination thereof.
[0043] Unless otherwise specified, “ / ” means or. For example, A / B can mean A or B. The “and / or” in this article is merely a way to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.
[0044] The terms "first", "second", etc. are used only to distinguish the same or similar technical features for the convenience of description, and should not be understood as indicating or implying the relative importance or quantity of these technical features. Thus, the features defined by "first", "second", etc. may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present disclosure, unless otherwise specified, the term "plurality" means two or more than two.
[0045] Research has found that most of the existing monitoring equipment performs one-to-one monitoring of signals. No monitoring device can monitor frequencies and frequency bands other than the target frequency, resulting in low monitoring accuracy and signal quality. In addition, they need to be deployed separately, so the deployment cost is high.
[0046] In order to at least partially solve one or more of the above-mentioned problems and other potential problems, the present disclosure provides at least one signal processing chip and a signal monitoring system to achieve full-band signal monitoring through baseband demodulation processing, greatly improving the monitoring accuracy and signal quality, and only requiring simple deployment and higher integration.
[0047] In order to clearly explain the embodiments of the present disclosure, some concepts that may appear in subsequent embodiments will first be introduced.
[0048] Digital Front End: Data interaction interface with the Radio Frequency Transceiver (TRX) chip to realize digital in-phase / quadrature (I / Q) data transmission and reception processing.
[0049] L1 shared memory: It is a shared memory that can be read and written by the master core of the Reduced Instruction Set Computing Verilog (RISC-V) open source architecture, and can also be read and written by direct memory access (DMA).
[0050] Reduced Instruction Set Open Source Architecture (RISC-V): A main control central processing unit (CPU) based on RISC-V.
[0051] I / D Cache (Instruction / Data Cache, I / D Cache): RISC-V's instruction cache and data cache improve RISC-V processing efficiency.
[0052] BOOTROM: is a read-only memory (ROM) where the boot code is placed.
[0053] AXI4 Interconnect: AXI4 is an advanced extensible interface (Advanced extensibleInterface), which is widely used in various processor architectures and application scenarios. It has the advantages of high performance, high bandwidth, scalability, flow control, flexibility and standardization. It is suitable for high-speed data transmission requirements between various components in complex system-on-chip (System on Chip, SOC).
[0054] Advanced Peripheral Bus (APB): A peripheral bus.
[0055] Direct Memory Access (DMA): Direct memory access.
[0056] Data-driven baseband processor (Baseband Processor): is a multi-core RISC-V core-based computing cluster that performs baseband demodulation functions.
[0057] Debug Controller: performs chip port debugging control.
[0058] Chip Clock Manager (Clock Management): implements system clock synchronization and internal clock generation and distribution.
[0059] General purpose input and output port controller (GPIO Controller): used for interactive control with the TRX chip.
[0060] Asynchronous serial interface controller (UART Controller): receives system instructions and transmits data.
[0061] Flash Controller: controls external Flash memory.
[0062] Low Power Controller: performs low power saving mode control.
[0063] Watch Dog Timer (WDT): realizes the timing function.
[0064] QoS (Quality of Service) refers to a technology that enables a network to use various basic technologies to provide better service capabilities for specified network communications and to solve problems such as network delays and congestion.
[0065] Considering the key role of the signal processing chip in the entire signal monitoring system, the signal processing chip provided by the embodiment of the present disclosure will be described in detail below. Figure 1 As shown, the signal processing chip 11 in the embodiment of the present disclosure mainly includes a data-driven baseband processor 111 and a main control module 112 built based on the reduced instruction set open source architecture RISC-V; wherein:
[0066] The data driven baseband processor 111 is used to process baseband signals, support time division duplex (TDD) synchronization, and provide an antenna address interface; in response to a signal monitoring instruction for a signal monitoring system, receive a radio frequency signal sent by a radio frequency transceiver, and transmit the radio frequency signal to the main control module 112;
[0067] The main control module 112 is used to control the start and stop of the signal processing chip 11 to obtain the signal analysis situation of the signal monitoring system, and the signal analysis situation is used to characterize the signal monitoring results within the full frequency band.
[0068] In order to facilitate understanding of the signal processing chip 11 provided in the embodiment of the present disclosure, the application scenario of the signal processing chip 11 is briefly introduced below. Considering that most of the monitoring devices currently used for signal quality monitoring in the signal monitoring system perform one-to-one monitoring of signals, any monitoring device cannot monitor frequency points and frequency bands other than the target frequency point, resulting in low monitoring accuracy and signal quality, and requires separate deployment, so the deployment cost is high.
[0069] In addition, the baseband signal processing is usually not completed, so there is an urgent need for more integrated monitoring equipment to achieve full-band signal monitoring, and this can be done with one module / chip, which will be sufficient to adapt to the application needs of more scenarios.
[0070] Based on this, the embodiment of the present disclosure provides a signal processing chip 11 that realizes full-band signal monitoring through baseband demodulation processing, the monitoring accuracy and signal quality are greatly improved, and only simple deployment is required, with higher integration.
[0071] In practical applications, the signal processing chip 11 can be a high-performance, especially highly integrated 4G / 5G, or even 6G baseband demodulation SOC (system on chips) based on a reduced instruction set open source architecture (RISC-V) architecture, with a monolithic integrated microcontroller unit (MCU), a baseband processor, and an on-chip static random access memory (SRAM), supporting a flexible and upgradeable software reconfigurable architecture.
[0072] Among them, the chip register read and write control can use the standard four-wire serial peripheral interface (Serial Peripheral Interface, SPI). It uses a 10mm×10mm, 100-pin quad flat no-leads package (Quad Flat No-leads Package, QFN) package. Therefore, it can be widely used in 4G and 5G indoor signal monitoring, repeater time division duplexing (TDD) synchronization, and 5G private network such as satellite Internet of Things applications, with better applicability.
[0073] The data-driven baseband processor 111 here can, on the one hand, process full-band baseband signals, support TDD synchronization, and provide an antenna address interface; on the other hand, it can also receive the RF signal sent by the RF transceiver when it is determined that signal monitoring is required, and can implement signal analysis for the signal monitoring system through baseband demodulation of the RF signal; specifically, the main control module 112 here can control the start and stop of the signal processing chip 11, and determine the signal monitoring results used to characterize the full-band range.
[0074] Among them, this chip can complete baseband signal processing, thereby ensuring signal reception and transmission, synchronization and demodulation, etc., in order to perform signal monitoring, fault location and analysis.
[0075] In addition, the data-driven baseband processor 111 and the main control module 112 constructed using RISC-V are better integrated and more efficient in computing, so that the full frequency range can be achieved. In particular, the signal synchronization and monitoring of 4G-5G and even 6G, in other words, compared with the prior art, which implements one-to-one monitoring without integration, any monitoring device cannot monitor frequency points and frequency bands other than the frequency point, so the accuracy is low. The disclosed embodiment can achieve one-to-many monitoring, with higher integration and stronger applicability.
[0076] The signal processing chip 11 provided in the embodiment of the present disclosure can be applied to the base station signal source connected to the signal monitoring system on the one hand, so as to perform signal monitoring through the signal strength of the base station signal source, and can also be applied to the user equipment connected to the signal monitoring system on the other hand, so as to perform signal monitoring through the signal strength of the user equipment. The following will explain in detail from the following two aspects respectively.
[0077] The first aspect: when the RF transceiver is applied to the base station signal source connected to the signal monitoring system, the data-driven baseband processor 111 is specifically used to: detect the base station synchronization signal in the environment where the signal monitoring system is located, and baseband demodulate the first RF signal sent by the base station signal source, and output the first baseband demodulation signal while outputting a synchronization signal and a time slot indication signal; wherein the first baseband demodulation signal is used to perform signal analysis for the signal monitoring system, and the synchronization signal is used to achieve synchronization between the signal monitoring system and the base station signal source.
[0078] In practical applications, the signal processing chip 11 provided in the embodiment of the present disclosure can perform baseband demodulation on 4G and 5G base station downlink signals, accurately detect the signal strength transmitted by the indoor antenna, and realize effective monitoring, automatic inspection, fault location and intelligent analysis of 5G traditional indoor antenna networks.
[0079] On the second aspect, when the RF transceiver is applied to a user device connected to the signal monitoring system, the data-driven baseband processor 111 is specifically used to: perform baseband demodulation on a second RF signal sent by the user device in the environment of the signal monitoring system, and output a second baseband demodulated signal for signal analysis for the signal monitoring system.
[0080] In practical applications, the signal processing chip 11 provided in the embodiment of the present disclosure also supports baseband analysis of uplink signals of user equipment (UE), and can determine problems such as abnormal QOS of the indoor network and user complaints.
[0081] In addition, the embodiments of the present disclosure can also be configured with multiple antennas. The signal power obtained by the user equipment under each antenna (the signal obtained by transmitting under each antenna is a mixed signal here) is used to determine the signal changes of mobile phone users under different antennas in the indoor environment, so as to achieve precise positioning, that is, the antenna IP function, to help operators quickly and effectively locate and solve indoor network QOS problems.
[0082] In practical applications, the signal processing chip 11 provided in the embodiment of the present disclosure can be used as an integrated chip, and the integrated chip can also integrate various functions to adapt to more complex application scenarios.
[0083] like Figure 1 As shown, the signal processing chip 11 provided in the embodiment of the present disclosure includes not only a RISC-V data driven baseband processor 111 and a main control module 112, but also a storage module 113. The storage module 113 here includes at least a shared memory for the main control module 112 and other control modules to access together, for example, it can be as follows Figure 2 The L1 shared memory (L1 Shared memory) shown in the figure, as a shared memory, the L1 shared memory can be read and written by the RISC-V main control core, and can also be read and written by DMA.
[0084] like Figure 2 As shown, the storage module 113 in the embodiment of the present disclosure also includes an instruction-data cache (I / DCache) and a read-only memory (BOOTROM) for storing boot code. The former is used for fast instruction caching and fast data caching to improve the processing efficiency of RISC-V, and the latter is used to place the boot code.
[0085] Depend on Figure 1 It is known that the signal processing chip 11 provided in the embodiment of the present disclosure further includes an expandable interface 114 and a direct memory access module 115 for directly performing signal transmission with the expandable interface 114 to adapt to data transmission requirements of various complex scenarios.
[0086] like Figure 2 As shown, the extensible interface 114 here can be AXI4 Interconnect. As an advanced extensible interface 114, AXI4 is widely used in various processor architectures and application scenarios, and has advantages such as high performance, high bandwidth, scalability, flow control, flexibility and standardization, and is suitable for high-speed data transmission requirements between various components in complex SOCs. In the embodiment of the present disclosure, signal transmission can be performed with the data-driven baseband processor 111 (Baseband Processor). In addition, it can also be connected to direct memory access (DMA) to achieve direct data transmission between peripheral devices and the storage module 113 through DMA.
[0087] like Figure 1 It can be seen that the expandable interface 114 in the signal processing chip 11 provided in the embodiment of the present disclosure is set on the bus, and the expandable interface transmits signals with both the data drive baseband processor 111 and the main control module 112. In addition, the auxiliary function module 116 transmits signals with the main control module through the peripheral bus to support the control logic of the main control module 112.
[0088] The peripheral bus here can be, for example, Figure 2The APB shown may also be other peripheral buses; the auxiliary function module 116 here may be one or more of the following components:
[0089] Debug controller for port debugging (such as Figure 2 Debug Controller shown);
[0090] A clock manager used to synchronize the system clock with the internal clock (such as Figure 2 ClockManagement as shown);
[0091] A general purpose input / output port controller (such as Figure 2 GPIOController shown);
[0092] Asynchronous serial interface controller for receiving system instructions and transmitting data (such as Figure 2 UARTController as shown);
[0093] Controller for external Flash storage control (such as Figure 2 Flash Controller shown);
[0094] Controller used to enable low power consumption mode (such as Figure 2 Low Power Controller shown);
[0095] The open dog timer used to realize the timing function (such as Figure 2 WDT shown).
[0096] It should be noted that in actual applications, any one or any combination of the above components can be selected based on actual application requirements, and no specific restrictions are made here. In addition, other auxiliary function components can also be set to support application requirements of more complex scenarios.
[0097] In order to further understand the signal processing chip 11 provided in the embodiment of the present disclosure, Figure 2 The signal processing chip 11 shown in the figure has a pin configuration and Figure 3 The frame diagram shown provides an expanded description of the signal processing chip 11 .
[0098] The system-on-chip (SOC) is a high-performance, highly integrated 4G / 5G baseband demodulation SOC based on the RISC-V architecture. It can integrate controllers, peripheral interfaces, general logic output pins, external flash, test interfaces, static random access memory, digital data interfaces, phase-locked loops and other functional modules on a single chip. It has a higher degree of integration, full coverage of monitoring effects, and is more applicable.
[0099] Based on the signal processing chip 11 provided in the embodiment of the present disclosure, Figure 4 As shown, the signal processing chip 11 may also integrate a mixing chip 117 in different integrated forms. The mixing chip 117 determines the signal power transmitted by the user equipment and / or the antenna, and mixes the signal in the monitored frequency band.
[0100] The present disclosure also provides a signal monitoring system. Figure 5 As shown, the signal monitoring system provided by the embodiment of the present disclosure mainly includes a signal processing chip 11 for signal monitoring, and also includes a receiving antenna 22, a frequency shifter 33, a power management chip 44 and a networking communication module 55, wherein the frequency shifter 33, the signal processing chip 11 and the networking communication module 55 are connected in sequence; wherein:
[0101] The frequency shifter 33 determines the signal power transmitted by the user equipment and / or the antenna 22, mixes the signal of the monitored frequency band, and transmits the obtained mixed signal to the signal processing chip 11;
[0102] The signal processing chip 11 is used to determine the signal monitoring result based on the mixing signal during the start-up control process of the power management chip 44, and transmit the signal monitoring result to the networking communication module 55;
[0103] The network communication module 55 is used to report the signal monitoring result generated by the signal processing chip 11 to the cloud.
[0104] In addition, the networking communication module 55 here can also report the antenna monitoring information of the receiving antenna 22 to the cloud.
[0105] As disclosed above, the signal monitoring system, whose signal processing chip 11 can realize signal monitoring for the signal monitoring system through the shutdown control of the power management chip 44 (Power Management Unit, PMU), can determine the signal monitoring results within the full frequency band.
[0106] The receiving antenna 22 here can receive downlink signals from 4G and 5G base stations, thereby realizing effective monitoring, automatic inspection, fault location and intelligent analysis of 4G and 5G traditional indoor antenna networks through signal analysis of the signal processing chip 11, thereby filling the market gap of 4G / 5G dual-mode low-cost baseband solutions; it can also receive uplink signals from user equipment (UE), which can solve problems such as abnormal quality of service (Quality of Service, QOS) and user complaints in indoor networks, monitor the signal changes of mobile phone users under different antennas in indoor environments, and realize precise positioning, that is, the antenna Internet Protocol Address (IP) function, to help operators quickly and effectively locate and solve indoor network QOS problems.
[0107] In the description of this specification, the description with reference to the terms "some possible embodiments", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure, and the above terms do not necessarily represent the same embodiment or example. Moreover, the described specific features, structures, materials or characteristics may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.
[0108] Although the spirit and principle of the present disclosure have been described above with reference to several specific embodiments, it should be understood that the present disclosure is not limited to the disclosed specific embodiments, and the division of various aspects does not mean that the features in these aspects cannot be combined. The present disclosure is intended to cover various modifications and equivalent arrangements included in the spirit and scope of the attached claims.
Claims
1. A signal processing chip, characterized in that: include: Data-driven baseband processor and main control module built on RISC-V, an open source architecture based on the reduced instruction set; The data-driven baseband processor is used to process baseband signals, support time division duplex (TDD) synchronization, and provide an antenna address interface; in response to a signal monitoring instruction for a signal monitoring system, receive a radio frequency signal sent by a radio frequency transceiver, and transmit the radio frequency signal to the main control module; The main control module is used to control the start and stop of the signal processing chip and obtain the signal analysis situation for the signal monitoring system, and the signal analysis situation is used to characterize the signal monitoring results within the full frequency band.
2. The signal processing chip according to claim 1, characterized in that: When the radio frequency transceiver is applied to a base station signal source connected to the signal monitoring system, the data-driven baseband processor is specifically used to: In the environment where the signal monitoring system is located, the base station synchronization signal is detected, and the first radio frequency signal sent by the base station source is baseband demodulated, and the synchronization signal and the time slot indication signal are output while the first baseband demodulation signal is output.
3. The signal processing chip according to claim 1, characterized in that: When the radio frequency transceiver is applied to a user equipment connected to the signal monitoring system, the data-driven baseband processor is specifically used to: In the environment where the signal monitoring system is located, baseband demodulation is performed on the second radio frequency signal sent by the user equipment, and a second baseband demodulated signal is output for signal analysis for the signal monitoring system.
4. The signal processing chip according to claim 1, characterized in that: When multiple antennas are configured, a frequency mixing chip is also included to: The signal power transmitted by the user equipment and / or the antenna is determined, and the signal of the monitored frequency band is mixed, and the obtained mixed signal is output to the main control module.
5. The signal processing chip according to any one of claims 1 to 4, characterized in that: It also includes an expandable interface and an auxiliary function module, wherein the expandable interface is arranged on the bus, and the expandable interface performs signal transmission with both the data drive baseband processor and the main control module; The auxiliary function module performs signal transmission with the main control module via the peripheral bus, so as to support the control logic of the main control module.
6. The signal processing chip according to claim 5, characterized in that: The auxiliary function module includes one or more of the following components: A debug controller for port debugging; A clock manager for synchronizing the system clock with the internal clock; A general purpose input / output port controller for input / output interactive control; Asynchronous serial interface controller for receiving system instructions and transmitting data; Controller for external Flash storage control; A controller for enabling a low power consumption power saving mode; A dog timer used to implement a timing function.
7. A signal monitoring system, characterized in that: include: The signal processing chip according to any one of claims 1 to 6; The signal processing chip is used to perform signal monitoring on the signal monitoring system and determine the signal monitoring results within the full frequency band.
8. The signal monitoring system according to claim 7, characterized in that: It also includes a receiving antenna, a frequency shifter, a power management chip and a networking communication module, wherein the frequency shifter, the signal processing chip and the networking communication module are connected in sequence; The frequency shifter determines the signal power transmitted by the user equipment and / or the antenna, mixes the signal of the monitored frequency band, and transmits the obtained mixed signal to the signal processing chip; The signal processing chip is used to determine a signal monitoring result based on the mixing signal during the start-up control process of the power management chip, and transmit the signal monitoring result to the networking communication module; The networked communication module is used to report the signal monitoring results generated by the signal processing chip to the cloud.
9. The signal monitoring system according to claim 8, characterized in that: The networked communication module is also used to report the antenna monitoring information of the receiving antenna to the cloud.