Network transmission system of video data, system-on-chip chip and server

Abstract

The invention discloses a video data network transmission system, a system-on-chip chip and a server, and relates to the technical field of chip design, the system is applied to the system-on-chip chip, and the system comprises a video data output control module used for writing video data to be transmitted into a target area of a video memory in a segmented ping-pong mode; wherein the target area comprises a first segmented area and a second segmented area; the network module is used for alternately reading target video data from the first segmented region and the second segmented region; sending each frame of video image data corresponding to the target video data to remote end equipment for display; the video data output control module and the hardware module of the network module are arranged, so that the video data to be transmitted can be written into the on-chip cache of the network module in a sectional ping-pong mode, time division multiplexing of a target area of a video memory is realized, occupation of video network transmission on storage bandwidth and system bus resources is reduced, and the video network transmission efficiency is improved. And the overall performance of the SoC chip is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip design, and in particular to a network transmission system for video data, a system-on-chip chip and a server. Background Art

[0002] At present, the processing flow of the video function of the traditional SoC (System on Chip) chip is to first convert the original RGB (red, green and blue) format data into a color space to generate YUV (brightness, chroma and density) format video data, compress the YUV format data (such as JPEG and AVS video compression formats) or directly transmit the YUV format data; write the compressed data or YUV format data to the external video memory (such as double data rate synchronous dynamic random access memory DDR) through the video data output control module of the SoC chip; then read the compressed data YUV format data from the video memory by an external network driver, and transmit it to the remote end for display through the network module of the SoC chip.

[0003] like Figure 1 As shown, the video data output control module in the server management control chip (a SoC chip with video and network functions, such as a baseboard management controller BMC) of the server needs to write the video data (such as the compressed data output by the video core compression module) transmitted over the network into the agreed DDR area B, and the network driver of the CPU (central processing unit) reads the video data in area B to the area C of the DDR agreed by the network module, and then the network driver creates a descriptor at the software level and sends it to the designated DDR area D, and the network module first obtains the descriptor from area D, and then parses the descriptor to obtain the address and length of the video data to be sent in area C of the DDR, and then initiates a DMA operation to read DDR (Data Memory Access, direct memory access) to read back the video data to be sent. The above process involves the reading and writing of a large amount of DDR data, which greatly occupies the system bus bandwidth and storage bandwidth of the SoC chip, and reduces the overall performance of the SoC chip.

[0004] Therefore, how to reduce the occupation of storage bandwidth and system bus resources by network transmission of video data and improve the overall performance of SoC chips is an urgent problem to be solved today. Summary of the invention

[0005] The purpose of the present invention is to provide a network transmission system for video data, a system-on-chip chip and a server, so as to reduce the occupation of storage bandwidth and system bus resources by network transmission of video data and improve the overall performance of the SoC chip.

[0006] In order to solve the above technical problems, the present invention provides a network transmission system for video data, which is applied to a system-on-chip chip, comprising:

[0007] A video data output control module, used for writing the video data to be transmitted into a target area of ​​the video memory in a segmented ping-pong manner; wherein the target area includes a first segmented area and a second segmented area, the video data to be transmitted includes a first segmented data and a second segmented data, the first segmented area is used to store the first segmented data, and the second segmented area is used to store the second segmented data;

[0008] A network module is used to alternately read target video data from the first segmented area and the second segmented area; send each frame of video image data corresponding to the target video data to a remote device for display; wherein the target video data is the first segmented data or the second segmented data.

[0009] On the other hand, the first segmented area and the second segmented area each include n block areas; n is a positive integer greater than or equal to 2;

[0010] The video data output control module is specifically used to write the segmented storage data corresponding to the current first segmented data into each block area in the first segmented area in sequence and in a loop according to a preset length; wherein the current first segmented data is any of the first segmented data, and the data length of the segmented storage data is less than or equal to the preset length.

[0011] On the other hand, the step of writing the segmented storage data corresponding to the current first segmented data into the block areas in the first segment area in sequence according to the preset length includes:

[0012] The ath segment storage data of the current first segment data is written into the ith block area in the first segment area; wherein i is a positive integer less than or equal to n, a=i+(n*j), and j is an integer greater than or equal to 0.

[0013] On the other hand, each of the first segmented data and the second segmented data is a frame of video image data.

[0014] On the other hand, the alternately reading the target video data from the first segment area and the second segment area comprises:

[0015] When the target video data is the first segmented data, each segmented storage data corresponding to the current first segmented data is read cyclically into the on-chip cache of each of the n channels in sequence; wherein the current first segmented data is any of the first segmented data, the data length of the segmented storage data is less than or equal to the preset length, and n is a positive integer greater than or equal to 2; the sum of the segmented storage data of the current first segmented data stored in the on-chip cache of the n channels is the current first segmented data.

[0016] In another aspect, the network module includes: a scheduling submodule, a direct memory access controller, n channel submodules, and a framing submodule;

[0017] The scheduling submodule is used to control the direct memory access controller to sequentially read the segmented storage data corresponding to the current target video data from the video memory, and sequentially and cyclically store the segmented storage data corresponding to the read current target video data into the on-chip caches of the n channel submodules; wherein the current target video data is any of the target video data, and the on-chip cache of the i-th channel submodule is used to store the a-th segmented storage data of the current target video data, i is a positive integer less than or equal to n, a=i+(n*j), and j is an integer greater than or equal to 0;

[0018] The framing submodule is used to cyclically read the segmented storage data corresponding to each of the target video data from the on-chip cache of the n channel submodules and perform framing to obtain the video image data of each frame corresponding to the target video data; and send the video image data of each frame obtained by framing to the remote device for display in turn.

[0019] On the other hand, the scheduling submodule is specifically used to initiate a direct memory access read data command corresponding to the first segmented storage data of the current target video data to the direct memory access controller; obtain the first segmented storage data read by the direct memory access controller from the first block area of ​​the current segmented area; write the first segmented storage data into the on-chip cache of the first channel submodule, so that the framing submodule reads the first segmented storage data from the on-chip cache of the first channel submodule; wherein the current target video data is any of the target video data; the current segmented area is the first segmented area or the second segmented area;

[0020] The scheduling submodule is further specifically used for initiating a direct memory access read data command corresponding to the b-th segmented storage data to the direct memory access controller after initiating a direct memory access read data command corresponding to the b-th segmented storage data to the direct memory access controller when the b-1th segmented storage data of the current target video data is not the last segmented storage data of the current target video data; obtaining the b-th segmented storage data read by the direct memory access controller from the j-th block area of ​​the current segment area; writing the b-th segmented storage data into the on-chip cache of the j-th channel submodule, so that the framing submodule reads the b-th segmented storage data from the on-chip cache of the j-th channel submodule; wherein b is a positive integer greater than or equal to 2, j=b-(n*j), j is a positive integer less than or equal to n, and j is an integer greater than or equal to 0.

[0021] In another aspect, n is four.

[0022] On the other hand, the first segment area and the second segment area each include n block areas, each of the block areas is used to store the segmented storage data that needs to be cached by the on-chip cache of a corresponding channel submodule;

[0023] The controlling the direct memory access controller to sequentially read each segment storage data corresponding to the current target video data from the video memory includes:

[0024] According to the identification information corresponding to each segmented storage data of the current target video data, the direct memory access controller is controlled to sequentially read each segmented storage data corresponding to the current target video data from the video memory; wherein the identification information includes a segmented area identification corresponding to the first segmented area or the second segmented area where the segmented storage data is located, a block area identification corresponding to the block area where the segmented storage data is located, and a block area reading order identification corresponding to the position of the segmented storage data in the block area.

[0025] On the other hand, when the current target video data is stored in the first segmented area, the segmented area identifier in the identification information corresponding to the a-th segmented storage data in the current target video data is 0, the block area identifier is i-1, and the block area reading order identifier is j;

[0026] When the current target video data is stored in the second segmented area, the segmented area identifier in the identification information corresponding to the a-th segmented storage data in the current target video data is 1, the block area identifier is i-1, and the block area reading order identifier is j; wherein i is a positive integer less than or equal to n, a=i+(n*j), and j is an integer greater than or equal to 0.

[0027] In another aspect, each channel submodule includes: a channel controller and an on-chip cache;

[0028] The channel controller is used to store the segmented storage data transmitted by the scheduling submodule into the corresponding on-chip cache in sequence according to the control of the scheduling submodule.

[0029] In another aspect, the network module further comprises:

[0030] The descriptor generation submodule is used to generate direct memory access read data commands corresponding to each segment storage data corresponding to the current target video data according to the control of the scheduling submodule; and send the direct memory access read data commands to the direct memory access controller in sequence to control the direct memory access controller to read each segment storage data corresponding to the current target video data from the video memory in sequence according to the received direct memory access read data commands.

[0031] On the other hand, the descriptor generation submodule includes: a descriptor address information generation unit, a read length generation unit, a descriptor control information generation unit and a descriptor building unit;

[0032] The descriptor address information generating unit is used to generate the descriptor address information of each segment storage data corresponding to the current target video data according to the address information of the target area and the control of the scheduling submodule;

[0033] The read length generating unit is used to generate the descriptor read length information corresponding to the preset length;

[0034] The descriptor control information generating unit is used to generate descriptor control information of each segment storage data corresponding to the current target video data;

[0035] The descriptor forming unit is used to generate direct memory access read data commands corresponding to each segment storage data corresponding to the current target video data according to the descriptor address information, the descriptor read length information and the descriptor control information.

[0036] On the other hand, the first segment area and the second segment area each include n block areas, each of the block areas is used to store the segmented storage data that needs to be cached by the on-chip cache of a corresponding channel submodule;

[0037] The descriptor address information generating unit is specifically used to generate descriptor address information of each segmented storage data corresponding to the current target video data according to the address range information of the target area and the identification information corresponding to each segmented storage data of the current target video data sent by the scheduling submodule; wherein the address range information includes the first address and address range of the first segmented area and the second segmented area, the descriptor address information includes the first address of each segmented storage data in the target area, and the identification information includes a segmented area identifier, a block area identifier and a block area reading order identifier.

[0038] On the other hand, the block area in the identification information corresponding to the a-th segment storage data in the current target video data is identified as i-1 and the block area reading order is identified as j; wherein i is a positive integer less than or equal to n, a=i+(n*j), and j is an integer greater than or equal to 0;

[0039] The starting address of the a-th segmented storage data in the target area is BEGIN_ADDR+SIZE / n*(i-1)+j*DMA_LENGTH; wherein BEGIN_ADDR is the starting address of the first segmented area or the second segmented area corresponding to the segmented area identifier in the identification information corresponding to the a-th segmented storage data, SIZE is the address range of the first segmented area or the second segmented area corresponding to the segmented area identifier in the identification information corresponding to the a-th segmented storage data, and DMA_LENGTH is the preset length.

[0040] On the other hand, the read length generating unit is specifically configured to use the length information stored in the preset length register as the preset length, and generate the descriptor read length information corresponding to the preset length.

[0041] On the other hand, the network module is further configured to send the length information to the video data output control module when the length information stored in the preset length register changes.

[0042] On the other hand, the system-on-chip chip is specifically a baseboard management controller.

[0043] The present invention also provides a system-on-chip chip, comprising: the network transmission system for video data as described above.

[0044] In addition, the present invention also provides a server, comprising: the system-on-chip chip as described above.

[0045] A network transmission system for video data provided by the present invention is applied to a system-on-chip chip, comprising: a video data output control module, used for writing the video data to be transmitted into a target area of ​​a video memory in a segmented ping-pong manner; wherein the target area comprises a first segmented area and a second segmented area, the video data to be transmitted comprises the first segmented data and the second segmented data, the first segmented area is used to store the first segmented data, and the second segmented area is used to store the second segmented data; a network module, used for alternately reading the target video data from the first segmented area and the second segmented area; sending each frame of video image data corresponding to the target video data to a remote terminal device for display; wherein the target video data is the first segmented data or the second segmented data.

[0046] It can be seen that the present invention writes the video data to be transmitted into the target area of ​​the video memory in a segmented ping-pong manner through the video data output control module, and the network module alternately reads the target video data from the first segment area and the second segment area, and can write the video data to be transmitted into the on-chip cache of the network module in a segmented ping-pong manner, thereby realizing the time-sharing multiplexing of the target area of ​​the video memory by the two hardware modules of the video data output control module and the network module, greatly reducing the occupation of storage bandwidth and system bus resources by network transmission of video data, and improving the overall performance of the SoC chip. In addition, the present invention also provides a system-on-chip chip and a server, which also have the above-mentioned beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0048] Figure 1 A schematic diagram of a remote video transmission solution of a BMC in a server in the related art;

[0049] Figure 2 A structural block diagram of a network transmission system for video data provided by an embodiment of the present invention;

[0050] Figure 3 A schematic diagram of time-sharing multiplexing of a video memory space provided by an embodiment of the present invention;

[0051] Figure 4 A schematic diagram of storing data in segments in a first segment area and a second segment area provided by an embodiment of the present invention;

[0052] Figure 5 It is a structural diagram of a network module in the related art;

[0053] Figure 6 A schematic diagram of the structure of a network module provided by an embodiment of the present invention;

[0054] Figure 7 A schematic diagram of the structure of a descriptor generation submodule provided by an embodiment of the present invention;

[0055] Figure 8 A schematic diagram of a flow chart of a 4-channel video data pipeline processing provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0056] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0057] Please refer to Figure 2 , Figure 2 This is a structural block diagram of a network transmission system for video data provided by an embodiment of the present invention. The system is applied to a system-on-chip (Soc) chip and may include:

[0058] The video data output control module 10 is used to write the video data to be transmitted into the target area of ​​the video memory in a segmented ping-pong manner; wherein the target area includes a first segmented area and a second segmented area, the video data to be transmitted includes the first segmented data and the second segmented data, the first segmented area is used to store the first segmented data, and the second segmented area is used to store the second segmented data;

[0059] The network module 20 is used to alternately read the target video data from the first segment area and the second segment area; send each frame of video image data corresponding to the target video data to the remote device for display; wherein the target video data is the first segment data or the second segment data.

[0060] It is understandable that the Soc chip in this embodiment can be a single chip that integrates one or more of a microprocessor, an analog IP (Intellectual Property) core, a digital IP core, and a memory (or an off-chip memory control interface), such as a server management controller (such as a BMC) in a server; for example, the network transmission system for video data provided in this embodiment can be applied to the BMC of a server. The video memory in this embodiment can be a memory (i.e., an off-chip memory) outside the SOC chip for storing video data to be transmitted, such as DDR.

[0061] Correspondingly, in this embodiment, the video data output control module 10 (i.e., the video function module) and the network module 20 (i.e., the network function module) in the SoC chip are set as hardware modules to achieve time-sharing multiplexing of the same video memory space (i.e., the target area of ​​the video memory, such as Figure 3 The B area in the video data output control module 10 allows the video data to be transmitted (such as compressed data or YUV format data) to be written to the on-chip cache of the network module 20 via the target area of ​​the video memory in a segmented ping-pong manner. Figure 3 As shown, when the video data output control module 10 writes the first segmented data after the video data to be transmitted is segmented into the B0 area (i.e., the first segmented area), the network module 20 can read the second segmented data written in the B1 area (i.e., the second segmented area); when the video data output control module 10 writes the second segmented data after the video data to be transmitted is segmented into the B1 area, the network module 20 can read the first segmented data written in the B0 area, which greatly reduces the occupation of the storage bandwidth (such as DDR memory bandwidth) and the system bus by the network transmission of the video function.

[0062] That is to say, in this embodiment, the process in which the network module 20 alternately reads the target video data from the first segment area and the second segment area may include reading the second segment data from the second segment area when the video data output control module 10 writes the first segment data to the first segment area; and reading the first segment data from the first segment area when the video data output control module 10 writes the second segment data to the second segment area.

[0063] Among them, in this embodiment, the area for storing the video data to be transmitted (i.e., the target area) in the video memory shared by the video data output control module 10 and the network module 20 is divided into two areas, namely a first segmented area and a second segmented area, so that the video data output control module 10 and the network module 20 can use these two areas alternately in a ping-pong manner, thereby realizing time-sharing multiplexing of different functions of the target area (i.e., video function and network function) by these two hardware modules, avoiding the disadvantage of the related technology that the network transmission of video data requires first moving the video data from the DDR area corresponding to the video function to the DDR area corresponding to the network function, greatly reducing the occupation of memory bandwidth and system bus resources by the network transmission of video data, and greatly improving the overall performance of the SoC chip.

[0064] Correspondingly, the specific manner in which the video data output control module 10 in this embodiment writes the video data to be transmitted into the target area of ​​the video memory in a segmented ping-pong manner can be set by the designer according to practical scenarios and user needs. For example, the video data output control module 10 can directly write the current part of the video data to be transmitted (such as the first segmented data or the second segmented data) into the first segmented area or the second segmented area, that is, the video data to be transmitted can be segmented directly according to the length (i.e., capacity) of the first segmented area and the second segmented area or the pre-set length of the first segmented data and the second segmented data, so that the segmented video data to be transmitted (i.e., the first segmented data and the second segmented data) can be written into their respective corresponding first segmented areas or second segmented areas.

[0065] Correspondingly, in order to facilitate the network module 20 to use multiple channels (i.e., n channels) to read the video data in the target area, in this embodiment, the first segmented area and the second segmented area can be divided into n block areas respectively, and each first segmented data and each second segmented data can be further segmented according to a preset length (such as an agreed or register configured length), so that the segmented data (i.e., segmented storage data) corresponding to each first segmented data and each second segmented data can be written into each block area in the first segmented area in turn and cyclically, so that each subsequent channel can read the corresponding segmented storage data from a block area corresponding to each of the first segmented area and the second segmented area.

[0066] For example, in some embodiments, the first segment area and the second segment area may each include n block areas; n is a positive integer greater than or equal to 2; the video data output control module 10 may be specifically used to write the segment storage data corresponding to the current first segment data into the block areas in the first segment area in turn and in a loop according to the preset length; wherein the current first segment data is any first segment data, and the data length of the segment storage data is less than or equal to the preset length. That is, when the video data output control module 10 writes the current first segment data into the first segment area, it may divide the first segment data into the segment storage data according to the preset length, and write them into the block areas in the first segment area in turn and in a loop.

[0067] Correspondingly, the video data output control module 10 can also be specifically used to write the segmented storage data corresponding to the current second segmented data into the block areas in the second segmented area in turn and in a loop according to the preset length; wherein the current second segmented data is any second segmented data. That is to say, when the video data output control module 10 writes the current second segmented data into the second segmented area, it can divide the second segmented data into the segmented storage data according to the preset length, and write them into the block areas in the second segmented area in turn and in a loop.

[0068] The specific method of writing the segmented storage data corresponding to the current first segmented data into the block areas in the first segmented area in turn according to the preset length can be set by the designer according to the usage scenario and user needs. For example, the video data output control module 10 can write the a-th segmented storage data of the current first segmented data into the i-th block area in the first segmented area; wherein i is a positive integer less than or equal to n, a=i+(n*j), and j is an integer greater than or equal to 0. For example, when n is 4, Figure 3 and Figure 4 As shown, the starting address of the B0 area (i.e., the first segment area) can be B0_BEGIN_ADDR, and the total address range of the B0 area is B0_SIZE; the B0 area is divided into 4 equal parts, the first block area (i.e., the first block area) is recorded as the B0_0 area, and its starting address is B0_BEGIN_ADDR, and its address range is B0_SIZE / 4; the second block area (i.e., the second block area) is recorded as the B0_1 area, and its starting address is B0_BEGIN_ADDR+B0_SIZE / 4, and its address range is B0_SIZE / 4; the third block area (i.e., the third block area) is recorded as the B0_2 area, and its starting address is B0_BEGIN_ADDR+B0_SIZE / 4, and its address range is B0_SIZE / 4; The first block area is recorded as B0_2 area, whose starting address is B0_BEGIN_ADDR+B0_SIZE / 2, and the address range is B0_SIZE / 4; the fourth block area (i.e., the fourth block area) is recorded as B0_3 area, whose starting address is B0_BEGIN_ADDR+B0_SIZE*3 / 4, and the address range is B0_SIZE / 4; the video data to be transmitted (i.e., the current first segment data) is written into B0_0, B0_1, B0_2 and B0_3 areas respectively according to the preset length (DMA_LENGTH), and is written in sequence in a loop, that is, Figure 7 As shown, the 1st / 5th / 9th / 13th... segmented storage data are written into B0_0, the 2nd / 6th / 10th / 14th... segmented storage data are written into B0_1, the 3rd / 7th / 11th / 15th... segmented storage data are written into B0_2, and the 4th / 8th / 12th / 16th... segmented storage data are written into B0_3.

[0069] Correspondingly, the implementation method of writing the segmented storage data corresponding to the current second segmented data into the block areas in the second segmented area in turn according to the preset length is similar to the above process. The video data output control module 10 can write the a-th segmented storage data of the current second segmented data into the i-th block area in the second segmented area; wherein i is a positive integer less than or equal to n, a=i+(n*j), and j is an integer greater than or equal to 0. For example, when n is 4, Figure 3 and Figure 4As shown, the starting address of the B1 area (i.e., the second segment area) can be B1_BEGIN_ADDR, and the total address range of the B1 area is B1_SIZE; the B1 area is divided into 4 equal parts, the first block area (i.e., the first block area) is recorded as the B1_0 area, whose starting address is B1_BEGIN_ADDR, and the address range is B1_SIZE / 4; the second block area (i.e., the second block area) is recorded as the B1_1 area, whose starting address is B1_BEGIN_ADDR+B0_SIZE / 4, and the address range is B1_SIZE / 4; the third block area (i.e., the third block area) is recorded as the B1_2 area, whose starting address is B1_BEGIN_ADDR+B0_SIZE / 4, and the address range is B1_SIZE / 4; The first block area is recorded as B1_2 area, whose starting address is B1_BEGIN_ADDR+B0_SIZE / 2, and the address range is B1_SIZE / 4; the fourth block area (i.e. the fourth block area) is recorded as B1_3 area, whose starting address is B1_BEGIN_ADDR+B0_SIZE*3 / 4, and the address range is B1_SIZE / 4; the video data to be transmitted (i.e. the current second segment data) is written into B1_0, B1_1, B1_2 and B1_3 areas respectively according to the preset length (DMA_LENGTH), and is written in sequence in a loop, that is, Figure 7 As shown, the 1st / 5th / 9th / 13th... segmented storage data are written into B1_0, the 2nd / 6th / 10th / 14th... segmented storage data are written into B1_1, the 3rd / 7th / 11th / 15th... segmented storage data are written into B1_2, and the 4th / 8th / 12th / 16th... segmented storage data are written into B1_3.

[0070] Correspondingly, in some embodiments, the sizes of the n block areas in the first segmented area may be the same, such as the n block areas in the first segmented area may be obtained by dividing the first segmented area into n equal parts; correspondingly, the sizes of the n block areas in the second segmented area may be the same, such as the n block areas in the second segmented area may be obtained by dividing the first segmented area into n equal parts.

[0071] Among them, the specific data length of each first segmented data and second segmented data corresponding to the video data to be transmitted in this embodiment can be set by the designer according to the usage scenario and user needs. For example, since the first segmented area in this embodiment can completely store a first segmented data, and the second segmented area can completely store a second segmented data, in order to realize the alternating use of the first segmented area and the second segmented area, the data length (i.e., data size) of the first segmented data and the second segmented data in this embodiment is set according to the capacity of the first segmented area and the second segmented area. In order to facilitate the subsequent framing operation, in some embodiments, each first segmented data and the second segmented data can be a frame of video image data, that is, the capacity of the first segmented area and the second segmented area can be greater than or equal to the data length of a frame of video image data; accordingly, when the first segmented data and the second segmented data are segmented according to the preset length, the data length of the segmented storage data is less than or equal to the preset length, such as the data length of the segmented storage data before the last segmented storage data of the first segmented data can be equal to the preset length, and the last segmented storage data can be less than or equal to the preset length.

[0072] Correspondingly, when the video data to be transmitted is directly segmented according to the preset length, the data length of the segmented storage data of the first segmented data and the second segmented data can be equal to the preset length.

[0073] It can be understood that the network module 20 in this embodiment can alternately read the respective currently stored target video data (i.e., the first segmented data or the second segmented data) from the first segmented area and the second segmented area. For example, the network module 20 can read the second segmented data from the second segmented area when the video data output control module 10 writes the first segmented data to the first segmented area; and read the first segmented data from the first segmented area when the video data output control module 10 writes the second segmented data to the second segmented area.

[0074] Correspondingly, the specific manner in which the network module 20 can alternately read the currently stored target video data from the first segment area and the second segment area can be set by the designer according to the practical scenario and user needs. For example, the network module 20 can alternately read the currently stored target video data from the first segment area and the second segment area to the on-chip cache as in the related art. In order to improve the processing efficiency of the network module 20, in this embodiment, the video data reading mechanism of n channels processed by the n-stage pipeline can be set to realize the parallel processing of video data; for example, when the network module 20 reads the current first segment data in the first segment data (that is, when the target video data is the first segment data), the segment storage data corresponding to the current first segment data can be read into the on-chip cache of each of the n channels in turn in a loop; wherein the current first segment data is any first segment data, the data length of the segment storage data is less than or equal to the preset length, and n is a positive integer greater than or equal to 2; the sum of the segment storage data of the current first segment data stored in the on-chip cache of the n channels is the current first segment data.

[0075] Correspondingly, when the target video data is the second segmented data, the network module 20 can read the segmented storage data corresponding to the current second segmented data into the on-chip cache of each of the n channels in turn. Figure 5 In the related art shown, the network module 20 needs to wait for the framing submodule (such as the Ethernet framing submodule) to read the on-chip cache before initiating the DMA read operation in order to ensure that the data returned by the DMA read has enough space in the TX_FIFO (transmit first-in first-out queue), otherwise the data will be lost due to untimely caching, which will lead to transmission errors. Therefore, the related art can only realize serial processing of the DMA controller, the on-chip cache controller and the subsequent framing submodule, and the processing efficiency is low, so that the video data is cached in the DDR for too long, resulting in a large network transmission delay, affecting the video display quality of the remote terminal device. In this embodiment, the setting of the video data reading mechanism of n channels processed by the n-stage pipeline can realize parallel processing of video data and improve the video display quality of the remote terminal device.

[0076] For example, the network module 20 may include: a scheduling submodule, a direct memory access controller (DMA controller), n channel submodules, and a framing submodule;

[0077] The scheduling submodule is used to control the direct memory access controller to sequentially read the segmented storage data corresponding to the current target video data from the video memory, and sequentially and cyclically store the segmented storage data corresponding to the read current target video data into the on-chip caches of the n channel submodules; wherein the current target video data is any target video data, and the on-chip cache of the i-th channel submodule is used to store the a-th segmented storage data of the current target video data, i is a positive integer less than or equal to n, a=i+(n*j), and j is an integer greater than or equal to 0;

[0078] The framing submodule is used to cyclically read the segmented storage data corresponding to the target video data from the on-chip cache of the n channel submodules and perform framing to obtain the video image data of each frame corresponding to the target video data; and send the video image data of each frame obtained by framing to the remote device for display in turn.

[0079] That is to say, the scheduling submodule can control the DMA controller, and through the DMA read operation, sequentially and cyclically store the segmented storage data corresponding to the current target video data into the on-chip cache of the n channel submodules, so that the framing submodule can sequentially and cyclically read the segmented storage data from the on-chip cache of the n channel submodules and perform framing, and obtain the video image data of each frame corresponding to the target video data, thereby improving the processing efficiency of the video data to be transmitted.

[0080] Among them, the process of the network module 20 processing the data to be transmitted may include the following four processes: 1. Initiate a DMA read operation; 2. Wait for the return of the DMA read data; 3. Write the read data returned into the on-chip cache (such as TX_FIFO or random access memory RAM); 4. The framing submodule reads the on-chip cache and adds the video data to the Ethernet frame for transmission. In this embodiment, four channels can be set for these four processes, that is, n can be 4, so that each channel can complete the above four processes, and these four channels can perform different processes at the same time, thereby realizing a 4-channel video data reading mechanism based on a 4-stage pipeline processing; accordingly, 2 or 3 channels can also be set, and this embodiment does not impose any restrictions on this.

[0081] For example, in some embodiments, the scheduling submodule is specifically used to initiate a direct memory access read data command corresponding to the first segmented storage data of the current target video data to the direct memory access controller (such as the above process 1); obtain the first segmented storage data read by the direct memory access controller from the first block area of ​​the current segmented area (such as the above process 1); write the first segmented storage data to the on-chip cache of the first channel submodule (such as the above process 3), so that the framing submodule reads the first segmented storage data from the on-chip cache of the first channel submodule (such as the above process 4). Among them, the current target video data is any target video data; the current segmented area is the first segmented area or the second segmented area;

[0082] The scheduling submodule is also specifically used for initiating a direct memory access read data command corresponding to the b-th segmented storage data to the direct memory access controller after initiating a direct memory access read data command corresponding to the b-1th segmented storage data to the direct memory access controller when the b-1th segmented storage data of the current target video data is not the last segmented storage data of the current target video data; obtaining the b-th segmented storage data read by the direct memory access controller from the j-th block area of ​​the current segment area; writing the b-th segmented storage data into the on-chip cache of the j-th channel submodule, so that the framing submodule reads the b-th segmented storage data from the on-chip cache of the j-th channel submodule; wherein b is a positive integer greater than or equal to 2, j=b-(n*j), j is a positive integer less than or equal to n, and j is an integer greater than or equal to 0.

[0083] Correspondingly, the specific manner in which the above-mentioned scheduling submodule controls the direct memory access controller to sequentially read the various segmented storage data corresponding to the current target video data from the video memory can be set by the designer according to the usage scenario and user needs. For example, when the first segment area and the second segment area both include n block areas, and each block area is used to store the segmented storage data that needs to be cached by the on-chip cache of a corresponding channel submodule, the scheduling submodule can control the direct memory access controller according to the identification information corresponding to each segmented storage data of the current target video data, and sequentially read the various segmented storage data corresponding to the current target video data from the video memory; wherein the identification information includes the segment area identification corresponding to the first segment area or the second segment area where the segmented storage data is located, the block area identification corresponding to the block area where the segmented storage data is located, and the block area reading order identification corresponding to the position of the segmented storage data in the block area.

[0084] That is to say, the segmented area identifier can be used to indicate whether the segmented storage data currently required to be read by the DMA controller is stored in the first segmented area or the second segmented area, the segmented storage data can be used to indicate in which block area of ​​the first segmented area or the second segmented area the segmented storage data currently required to be read by the DMA controller is stored, and the block area reading order identifier can be used to indicate the order in which the segmented storage data currently required to be read by the DMA controller is stored in the block area. When the data length of the segmented storage data is a preset length, the position of the segmented storage data in the block area can be determined by the block area reading order identifier.

[0085] For example, in some embodiments, when the current target video data is stored in the first segmented area, the segmented area identifier in the identification information corresponding to the a-th segmented storage data in the current target video data is 0, the block area identifier is i-1, and the block area reading order identifier is j; when the current target video data is stored in the second segmented area, the segmented area identifier in the identification information corresponding to the a-th segmented storage data in the current target video data is 1, the block area identifier is i-1, and the block area reading order identifier is j; wherein i is a positive integer less than or equal to n, a=i+(n*j), and j is an integer greater than or equal to 0.

[0086] Correspondingly, in other embodiments, when the current target video data is stored in the first segmented area, the segmented area identifier in the identification information corresponding to the a-th segmented storage data in the current target video data is 1, the block area identifier is i, and the block area reading order identifier is j+1; when the current target video data is stored in the second segmented area, the segmented area identifier in the identification information corresponding to the a-th segmented storage data in the current target video data is 2, the block area identifier is i, and the block area reading order identifier is j+1; wherein i is a positive integer less than or equal to n, a=i+(n*j), and j is an integer greater than or equal to 0.

[0087] Further, in the related art, the creation of the descriptor for controlling the DMA controller in the network module 20 is created by the network driver software running on the CPU. After the creation is completed, the descriptor is first written to the DDR specified area (such as Figure 1 In order to reduce the resource usage of the CPU and improve the overall performance of the SoC chip, the process of creating descriptors by the CPU can be offloaded in this embodiment, and the network module 20 in the hardware of the SoC chip is responsible for creating descriptors and executing functions. In other words, the process of the network module 20 alternately reading the target video data from the first segmented area and the second segmented area can create a descriptor (i.e., a DMA read data command) for the network module 20, and control its internal DMA controller to alternately read the target video data from the first segmented area and the second segmented area. Figure 6 As shown, the network module 20 may also include: a descriptor generation submodule, which is used to generate direct memory access read data commands (i.e., descriptors) corresponding to each segmented storage data corresponding to the current target video data according to the control of the scheduling submodule; and send the direct memory access read data commands to the direct memory access controller (DMA controller) in sequence, so as to control the direct memory access controller to read each segmented storage data corresponding to the current target video data from the video memory in sequence according to the received direct memory access read data commands. That is to say, in the process of the scheduling submodule initiating the direct memory access read data command corresponding to the first segmented storage data (or the b-1th segmented storage data) of the current target video data to the DMA controller, the scheduling submodule may control the descriptor generation submodule to generate and send the DMA read data command corresponding to the first segmented storage data to the DMA controller.

[0088] For example, if Figure 7 As shown, the descriptor generation submodule may include: a descriptor address information generation unit, a read length generation unit, a descriptor control information generation unit and a descriptor assembly unit; the descriptor address information generation unit is used to generate the descriptor address information of each segmented storage data corresponding to the current target video data according to the address information of the target area and the control of the scheduling submodule; the read length generation unit is used to generate the descriptor read length information corresponding to the preset length; the descriptor control information generation unit is used to generate the descriptor control information of each segmented storage data corresponding to the current target video data; the descriptor assembly unit is used to generate the direct memory access read data command corresponding to each segmented storage data corresponding to the current target video data according to the descriptor address information, the descriptor read length information and the descriptor control information.

[0089] The descriptor address information generating unit may be responsible for generating address information in the descriptor, such as Figure 3The video data output control module 10 can transmit the area address range division (i.e., the address information of the target area) of the first segment area (B0 area) and the second segment area (B1 area) to the network module 20, so that the descriptor address information generating unit can determine the first address information of the block area of ​​each of the first segment area and the second segment area, and then the descriptor address information generating unit generates the descriptor address information of each segment storage data corresponding to the current target video data to be read according to the identification information of each segment storage data corresponding to the current target video data to be read transmitted by the scheduling submodule (such as the above-mentioned segment area identification, block area identification and block area reading order identification). That is to say, when the first segment area and the second segment area each include n block areas, and each block area is used to store the segmented storage data that needs to be cached by the on-chip cache of a corresponding channel sub-module, the descriptor address information generating unit can be specifically used to generate the descriptor address information of each segmented storage data corresponding to the current target video data according to the address range information of the target area and the identification information corresponding to each segmented storage data of the current target video data sent by the scheduling sub-module; wherein the address range information includes the first address and address range of each of the first segment area and the second segment area, the descriptor address information includes the first address of each segmented storage data in the target area, and the identification information includes the segment area identifier, the block area identifier and the block area reading order identifier.

[0090] Correspondingly, when the block area identifier in the identification information corresponding to the a-th segmented storage data in the current target video data is i-1 and the block area reading order identifier is j, the starting address of the a-th segmented storage data in the target area in the descriptor address information of the a-th segmented storage data generated by the descriptor address information generating unit can be BEGIN_ADDR+SIZE / n*(i-1)+j*DMA_LENGTH; wherein i is a positive integer less than or equal to n, a=i+(n*j), j is an integer greater than or equal to 0, BEGIN_ADDR is the starting address of the first segmented area or the second segmented area corresponding to the segmented area identifier in the identification information corresponding to the a-th segmented storage data, SIZE is the address range of the first segmented area or the second segmented area corresponding to the segmented area identifier in the identification information corresponding to the a-th segmented storage data, and DMA_LENGTH is a preset length.

[0091] For example, when n is 4, if the segment area identifier in the identification information of a certain segmented storage data sent by the scheduling submodule is 0, the block area identifier is 0 (i.e., i-1=0), and the block area reading order identifier is 0 (i.e., j=0), that is, it means that the first block area of ​​the B0 area (i.e., the first segment area) is to be read, and the reading order is the first read, the DMA read data command corresponding to the segmented storage data generated by the descriptor address information generating unit can be B0_BEGIN_ADDR+B0_SIZE / 4*(i-1)+j*DMA_LENGTH; if the segment area identifier in the identification information of a certain segmented storage data sent by the scheduling submodule is 1, and the block area identifier is 0 (i.e., i-1=0) and the block area reading order identifier is 0 (i.e., j=0), which means that the first block area of ​​the B1 area (i.e., the second segment area) is to be read, and the reading order is the first read. The DMA read data command corresponding to the segmented storage data generated by the descriptor address information generating unit can be B1_BEGIN_ADDR+B1_SIZE / 4*(i-1)+j*DMA_LENGTH; wherein, B0_BEGIN_ADDR and B1_BEGIN_ADDR represent the first addresses of the first segment area and the second segment area respectively; B0_SIZE and B1_SIZE represent the address ranges of the first segment area and the second segment area respectively.

[0092] Correspondingly, the read length generating unit can be responsible for generating the length of the DMA read data command (i.e., DMA read operation), i.e., DMA_LENGTH; such as the configuration of the read length generating unit receiving register (e.g., preset length register), so that the user can change DMA_LENGTH, and after the change, the network module 20 can synchronously pass it to the video data output control module 10. In other words, the read length generating unit can be specifically used to use the length information stored in the preset length register as the preset length to generate the descriptor read length information corresponding to the preset length. The network module 20 can also be used to send the length information to the video data output control module 10 when the length information stored in the preset length register changes.

[0093] Correspondingly, the descriptor control information generating unit may be responsible for generating control information of the descriptor (i.e., descriptor control information). For example, the descriptor control information may include control information for expressing whether the current descriptor (i.e., DMA read data command) is the first or last descriptor of the current network Packet and control information for expressing whether SA / DA (source address or destination address) is to be inserted into the current network Packet, etc. Part of the control information may be generated by the descriptor control information generating unit itself, and part of the control information may be directly sent by the network driver to the internal register of the descriptor control information generating unit.

[0094] Among them, the descriptor assembly unit is responsible for packaging the output information of the above three units, combining them into the corresponding descriptor structure (i.e., DMA read data command), and passing it to the DMA controller to initiate a DMA read operation (i.e., read the B0 / B1 area).

[0095] For example, when n is 4, Figure 8 The 4-stage pipeline mechanism shown can maximize the use of the internal functions of the network module 20 to achieve parallel processing of the video data to be transmitted. Figure 6 and Figure 8 As shown, the scheduling submodule can first respond to the read request of channel 0 (i.e., the first channel), generate corresponding identification information (such as segment area identification, block area identification and block area reading order identification), and pass it to the descriptor generation submodule. After the descriptor generation submodule generates the corresponding descriptor (i.e., DMA read data command), it is passed to the DMA controller, and the DMA controller initiates a read operation on the specified address space of the B0 / B1 area (i.e., the first segment area or the second segment area); while waiting for the DMA controller to return the read data, the scheduling submodule can respond to the read request of channel 1 (i.e., the second channel), generate identification information of the next segment storage data, and pass it to the descriptor generation word module. After the descriptor generation submodule generates the corresponding descriptor, it is passed to the DMA controller, and the DMA controller again initiates a read operation on the specified address space of the B0 / B1 area; the scheduling submodule receives the read return data from the DMA controller and sends the returned data to the DMA controller. The data is written into the on-chip cache 0 through the channel 0 controller, while waiting for the DMA data initiated by channel 1 to return. At the same time, the scheduling submodule responds to the read request of channel 2, generates the identification information of the next segmented storage data, and passes it to the descriptor generation submodule. After the descriptor generation submodule generates the corresponding descriptor, it is passed to the DMA, and the DMA initiates the read operation of the specified address space of the B0 / B1 area; the subsequent framing word module reads the video data in the on-chip cache of channel 0, and the scheduling submodule writes the read return data corresponding to channel 1 into the on-chip cache corresponding to channel 1, while waiting for the read data of channel 2 to return, and responds to the read request of channel 3, generates the identification information of the next segmented storage data, and passes it to the descriptor generation submodule. After the descriptor generation submodule generates the corresponding descriptor, it is passed to the DMA, and the DMA initiates the read operation of the specified address space of the B0 / B1 area, thereby realizing the data parallel processing of the 4-level pipeline mechanism.

[0096] Correspondingly, from the perspective of the descriptor generating word module, the identification information it receives (segment area identification, block area identification and block area reading order identification) is as follows: (0,0,0), (0,1,0), (0,2,0), (0,3,0), (0,0,1), (0,1,1), (0,2,1), (0,3,1), (0,0,2), (0,1,2), (0,2,2), (0,3,0), (0,0,1), (0,1,1), (0,2,1), (0,3,1), (0,0,2), (0,1,2), (0,2,2), (0,3 ,2), (0,0,3), (0,1,3), (0,2,3), (0,3,3)…; currently it is necessary to read the B1 area (that is, the second segment area), then the identification information received in sequence can be as follows: (1,0,0), (1,1,0), (1,2,0), (1,3,0), (1,0,1), (1,1,1), (1,2,1), (1,3,1), (1,0,2), (1,1,2), (1,2,2), (1,3,2), (1,0,3), (1,1,3), (1,2,3), (1,3,3)… The 4-level pipeline reading mechanism described above can be combined with the segmented ping-pong operation writing mechanism of the video data to be transmitted into the video memory (such as DDR), so that the video data to be transmitted can be read back to the network module 20 in parallel through a 4-channel 4-level pipeline and framed, and then sent to the remote device, which greatly reduces the cache time of the video data to be transmitted in the video memory, greatly reduces the network delay of the video data to be transmitted, and at the same time improves the parallelism and utilization of the internal functions of the hardware network module 20, greatly improving the display quality of the remote device.

[0097] It should be noted that the present embodiment does not limit the specific application scenario of the system on chip (SoC) chip. For example, the SoC chip may be a BMC of a server. Accordingly, the SoC chip may also include Figure 1 The VGA (Video Graphics Array) module, video data capture module, color space conversion module and video core compression module shown in the figure. For example, when the KVM (abbreviation of keyboard, video and mouse) function is started, the server host will need to transmit the original video data displayed remotely (i.e., the operating system remote display image, such as the real-time interface of the operating system) to the VGA module of the BMC through PCIe (a high-speed serial computer expansion bus standard). The VGA module generates the original video data in RGB format. This process needs to interact with the external DDR (i.e., video memory), such as Figure 1A area of ​​DDR in the video data capture module; the video data capture module obtains the original video data in RGB format from the VGA module and transmits it to the color space conversion module; the color space conversion module can perform color space conversion on the original video data in RGB format to obtain data in YUV format, and the conversion process can be adopted by the following formulas: Y=(0.257*R)+(0.504*G)+(0.098*B)+16, U=0.148*R–0.291*G+0.439*B+128 and V=0.439*R-0.368*G-0.071*B+128.

[0098] Correspondingly, the video core compression module can perform video compression in the corresponding video compression format (such as H.264, JPEG, AVS and other video compression formats) on the received YUV format data to obtain compressed video data; the compressed video output control module can receive compressed video data or uncompressed YUV format data as video data to be transmitted.

[0099] In this embodiment, the embodiment of the present invention writes the video data to be transmitted into the target area of ​​the video memory in a segmented ping-pong manner through the video data output control module 10, and the network module 20 alternately reads the target video data from the first segment area and the second segment area, and can write the video data to be transmitted into the on-chip cache of the network module 20 in a segmented ping-pong manner, thereby realizing time-sharing multiplexing of the target area of ​​the video memory by the two hardware modules, the video data output control module 10 and the network module 20, greatly reducing the occupation of storage bandwidth and system bus resources by network transmission of video data, and improving the overall performance of the SoC chip.

[0100] Corresponding to the above system embodiment, the embodiment of the present invention further provides a system-on-chip chip. The system-on-chip chip described below and the network transmission system for video data described above can refer to each other.

[0101] A system-on-chip chip includes: a network transmission system for video data as provided in the above embodiment.

[0102] The system-on-chip chip provided in this embodiment may specifically be a BMC.

[0103] Corresponding to the above system embodiment, the embodiment of the present invention further provides a server. The server described below and the system-on-chip chip described above can refer to each other.

[0104] A server includes: the system-on-chip chip provided by the above embodiment.

[0105] The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other. For the system-on-chip chip and server disclosed in the embodiment, since they correspond to the system disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the system part description.

[0106] The above is a detailed introduction to a network transmission system, a system-on-chip chip and a server for video data provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the present invention.

Claims

1. A network transmission system for video data, characterized in that: Applications in system-on-chips, including: A video data output control module, used for writing the video data to be transmitted into a target area of ​​the video memory in a segmented ping-pong manner; wherein the target area includes a first segmented area and a second segmented area, the video data to be transmitted includes a first segmented data and a second segmented data, the first segmented area is used to store the first segmented data, and the second segmented area is used to store the second segmented data; A network module is used to alternately read target video data from the first segmented area and the second segmented area; send each frame of video image data corresponding to the target video data to a remote device for display; wherein the target video data is the first segmented data or the second segmented data.

2. The network transmission system for video data according to claim 1, characterized in that: The first segmented area and the second segmented area each include n block areas; n is a positive integer greater than or equal to 2; The video data output control module is specifically used to write the segmented storage data corresponding to the current first segmented data into each block area in the first segmented area in sequence and in a loop according to a preset length; wherein the current first segmented data is any of the first segmented data, and the data length of the segmented storage data is less than or equal to the preset length.

3. The network transmission system for video data according to claim 2, characterized in that: The step of writing the segmented storage data corresponding to the current first segmented data into each block area in the first segment area in turn according to the preset length includes: The ath segment storage data of the current first segment data is written into the ith block area in the first segment area; wherein i is a positive integer less than or equal to n, a=i+(n*j), and j is an integer greater than or equal to 0.

4. The network transmission system for video data according to claim 1, characterized in that: Each of the first segmented data and the second segmented data is a frame of video image data.

5. The network transmission system for video data according to claim 1, characterized in that: The alternately reading target video data from the first segment area and the second segment area comprises: When the target video data is the first segmented data, each segmented storage data corresponding to the current first segmented data is read cyclically into the on-chip cache of each of the n channels in sequence; wherein the current first segmented data is any of the first segmented data, the data length of the segmented storage data is less than or equal to the preset length, and n is a positive integer greater than or equal to 2; the sum of the segmented storage data of the current first segmented data stored in the on-chip cache of the n channels is the current first segmented data.

6. The network transmission system for video data according to claim 5, characterized in that: The network module includes: a scheduling submodule, a direct memory access controller, n channel submodules and a framing submodule; The scheduling submodule is used to control the direct memory access controller to sequentially read the segmented storage data corresponding to the current target video data from the video memory, and sequentially and cyclically store the segmented storage data corresponding to the read current target video data into the on-chip caches of the n channel submodules; wherein the current target video data is any of the target video data, and the on-chip cache of the i-th channel submodule is used to store the a-th segmented storage data of the current target video data, i is a positive integer less than or equal to n, a=i+(n*j), and j is an integer greater than or equal to 0; The framing submodule is used to cyclically read the segmented storage data corresponding to each of the target video data from the on-chip cache of the n channel submodules and perform framing to obtain the video image data of each frame corresponding to the target video data; and send the video image data of each frame obtained by framing to the remote device for display in turn.

7. The network transmission system for video data according to claim 6, characterized in that: The scheduling submodule is specifically used to initiate a direct memory access read data command corresponding to the first segment storage data of the current target video data to the direct memory access controller; obtain the first segment storage data read by the direct memory access controller from the first block area of ​​the current segment area; write the first segment storage data into the on-chip cache of the first channel submodule, so that the framing submodule reads the first segment storage data from the on-chip cache of the first channel submodule; wherein the current target video data is any of the target video data; the current segment area is the first segment area or the second segment area; The scheduling submodule is further specifically used for initiating a direct memory access read data command corresponding to the b-th segmented storage data to the direct memory access controller after initiating a direct memory access read data command corresponding to the b-th segmented storage data to the direct memory access controller when the b-1th segmented storage data of the current target video data is not the last segmented storage data of the current target video data; obtaining the b-th segmented storage data read by the direct memory access controller from the j-th block area of ​​the current segment area; writing the b-th segmented storage data into the on-chip cache of the j-th channel submodule, so that the framing submodule reads the b-th segmented storage data from the on-chip cache of the j-th channel submodule; wherein b is a positive integer greater than or equal to 2, j=b-(n*j), j is a positive integer less than or equal to n, and j is an integer greater than or equal to 0.

8. The network transmission system for video data according to claim 7, characterized in that: n is 4.

9. The network transmission system for video data according to claim 6, characterized in that: The first segment area and the second segment area each include n block areas, each of the block areas is used to store the segmented storage data that needs to be cached by the on-chip cache of a corresponding channel submodule; The controlling the direct memory access controller to sequentially read each segment storage data corresponding to the current target video data from the video memory includes: According to the identification information corresponding to each segmented storage data of the current target video data, the direct memory access controller is controlled to sequentially read each segmented storage data corresponding to the current target video data from the video memory; wherein the identification information includes a segmented area identification corresponding to the first segmented area or the second segmented area where the segmented storage data is located, a block area identification corresponding to the block area where the segmented storage data is located, and a block area reading order identification corresponding to the position of the segmented storage data in the block area.

10. The network transmission system for video data according to claim 9, characterized in that: When the current target video data is stored in the first segmented area, the segmented area identifier in the identification information corresponding to the a-th segmented storage data in the current target video data is 0, the block area identifier is i-1, and the block area reading order identifier is j; When the current target video data is stored in the second segmented area, the segmented area identifier in the identification information corresponding to the a-th segmented storage data in the current target video data is 1, the block area identifier is i-1, and the block area reading order identifier is j; wherein i is a positive integer less than or equal to n, a=i+(n*j), and j is an integer greater than or equal to 0.

11. The network transmission system of video data according to claim 6, characterized in that: Each channel submodule includes: a channel controller and an on-chip cache; The channel controller is used to store the segmented storage data transmitted by the scheduling submodule into the corresponding on-chip cache in sequence according to the control of the scheduling submodule.

12. The network transmission system for video data according to any one of claims 6 to 11, characterized in that: The network module also includes: The descriptor generation submodule is used to generate direct memory access read data commands corresponding to each segment storage data corresponding to the current target video data according to the control of the scheduling submodule; and send the direct memory access read data commands to the direct memory access controller in sequence to control the direct memory access controller to read each segment storage data corresponding to the current target video data from the video memory in sequence according to the received direct memory access read data commands.

13. The network transmission system for video data according to claim 12, characterized in that: The descriptor generation submodule includes: a descriptor address information generation unit, a read length generation unit, a descriptor control information generation unit and a descriptor formation unit; The descriptor address information generating unit is used to generate the descriptor address information of each segment storage data corresponding to the current target video data according to the address information of the target area and the control of the scheduling submodule; The read length generating unit is used to generate the descriptor read length information corresponding to the preset length; The descriptor control information generating unit is used to generate descriptor control information of each segment storage data corresponding to the current target video data; The descriptor forming unit is used to generate direct memory access read data commands corresponding to each segment storage data corresponding to the current target video data according to the descriptor address information, the descriptor read length information and the descriptor control information.

14. The network transmission system for video data according to claim 13, characterized in that: The first segment area and the second segment area each include n block areas, each of the block areas is used to store the segmented storage data that needs to be cached by the on-chip cache of a corresponding channel submodule; The descriptor address information generating unit is specifically used to generate descriptor address information of each segmented storage data corresponding to the current target video data according to the address range information of the target area and the identification information corresponding to each segmented storage data of the current target video data sent by the scheduling submodule; wherein the address range information includes the first address and address range of the first segmented area and the second segmented area, the descriptor address information includes the first address of each segmented storage data in the target area, and the identification information includes a segmented area identifier, a block area identifier and a block area reading order identifier.

15. The network transmission system for video data according to claim 14, characterized in that: The block area in the identification information corresponding to the a-th segment storage data in the current target video data is identified as i-1 and the block area reading order is identified as j; wherein i is a positive integer less than or equal to n, a=i+(n*j), and j is an integer greater than or equal to 0; The starting address of the a-th segmented storage data in the target area is BEGIN_ADDR+SIZE / n*(i-1)+j*DMA_LENGTH; wherein BEGIN_ADDR is the starting address of the first segmented area or the second segmented area corresponding to the segmented area identifier in the identification information corresponding to the a-th segmented storage data, SIZE is the address range of the first segmented area or the second segmented area corresponding to the segmented area identifier in the identification information corresponding to the a-th segmented storage data, and DMA_LENGTH is the preset length.

16. The network transmission system of video data according to claim 13, characterized in that: The read length generating unit is specifically configured to use the length information stored in the preset length register as the preset length, and generate the descriptor read length information corresponding to the preset length.

17. The network transmission system for video data according to claim 16, characterized in that: The network module is further configured to send the length information to the video data output control module when the length information stored in the preset length register changes.

18. The network transmission system for video data according to claim 1, characterized in that: The system-on-chip chip is specifically a baseboard management controller.

19. A system-on-chip chip, characterized in that: include: A network transmission system for video data as claimed in any one of claims 1 to 18.

20. A server, characterized in that: include: The system-on-chip as claimed in claim 19.

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