Edge detection wake-up circuit-based region of interest imaging method and imaging system

Abstract

The application provides a region of interest imaging method and imaging system based on edge detection wake-up circuit, and belongs to the technical field of image sensors. The system supports three working modes and shares a read-out circuit: in a standard imaging mode, an image is output in a full resolution manner at a low frame rate; in an edge detection wake-up mode, an edge image is generated by continuously comparing the difference between the gray scale values of two adjacent columns of pixels; and in a ROI mode, which is triggered, after a digital logic determines and updates a ROI region based on the edge image, the pixels in the region are quantized by the read-out circuit, and the system outputs a ROI image in a reduced resolution manner at a high frame rate. The application solves the problems of data storage and region of interest imaging on-chip without additional storage circuits and image processors. The image information is compressed through edge detection, and the system runs at a high frame rate only in the ROI imaging mode, so that the system power consumption and transmission bandwidth are reduced without changing the pixel characteristics and introducing additional storage circuits.

Description

Technical Field

[0001] This invention relates to a region-of-interest imaging method and imaging system based on an edge detection wake-up circuit, belonging to the field of image sensor technology. Background Technology

[0002] In the era of artificial intelligence, an increasing number of computer vision tasks (such as object detection and tracking) are being deployed in edge applications such as drones, smart cars, and wearable devices. These edge devices are typically packaged in compact systems and powered by batteries with limited capacity. It is well known that traditional imaging systems consist of a CMOS image sensor (CIS) and a back-end image signal processor (ISP). The CMOS image sensor converts light signals captured from the scene into image data that the machine can recognize, while the back-end image signal processor processes the image data to extract the desired information. This approach heavily relies on the amount of image data obtained by the ISP from the raw image data. If all the raw image data is used as the basis for processing, the system will generate higher power consumption and greater bandwidth due to the excessive redundant data contained in the raw image data. However, to meet the requirements of low power consumption and low bandwidth in edge applications, scene-adaptive edge computing is needed to filter the raw image data.

[0003] In current scene-adaptive edge computing, even with low-power sensors or in-sensor image compression, high frame rate target tracking and data transmission still consume significant bandwidth. Therefore, edge detection is applied. By integrating edge detection functionality into the sensor, the amount of data that needs to be transmitted and processed can be significantly reduced, thereby lowering the overall system power consumption. However, continuous edge detection also introduces significant power and bandwidth burdens. Therefore, edge detection is widely used as a trigger to minimize redundant target detection while ensuring that targets of interest are not missed. Typically, effective targets only occupy a portion of the entire image frame; for example, in traffic monitoring applications of Video Internet of Things (IoVT), bicycles and trucks occupy only 0.7% and 12% of the full frame size (240×180), respectively. Therefore, energy-efficient, dedicated hardware circuitry is needed to always be on to activate the region of interest (ROI) imaging, enabling always-on, low-power target detection and high frame rate target tracking.

[0004] Chinese patent CN118450237A discloses a multi-frame-rate imaging method for tracking regions of interest (ROIs). It triggers high-frame-rate ROI imaging through motion detection that is always online at a low frame rate, reducing system power consumption and alleviating output bandwidth issues. However, this scheme relies on the storage of background information, which means a background memory matching the array size is required, leading to increased chip area and circuit complexity. Chinese patent CN105432072A proposes a multi-mode image sensing method for ROI capture. It continuously captures image frames and transmits them to an image processor. The image processor uses image processing algorithms to identify events of interest and further processes the image to recognize human activity, thereby determining the event location and capturing target feature data of the ROI. This method relies on three image sensors, one image processor, and a host computer, and requires data transmission between the image sensors and the image processor, significantly increasing system complexity and transmission bandwidth. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a region-of-interest imaging system and method based on an edge detection wake-up circuit; this method achieves region-of-interest imaging by constructing an imaging system with a novel readout circuit and an edge detection wake-up circuit.

[0006] The first objective of this invention is to provide a region-of-interest imaging system based on an edge detection wake-up circuit, the system comprising a pixel array, a ramp circuit, a readout circuit, an edge detection wake-up circuit, a column selector, a high-voltage drive circuit, a row decoder, and a PLL (phase-locked loop) and digital logic circuits.

[0007] The ramp circuit is connected to the high-voltage drive circuit, which in turn is connected to the pixel array. By applying different operating voltages to the pixel array, the circuit controls the pixel array to enter standby, reset, exposure, and readout modes in three different modes: standard imaging mode, edge detection wake-up mode, and ROI imaging mode. The edge detection wake-up circuit outputs an edge image by sampling and comparing the grayscale values ​​of any two adjacent pixels. The digital logic circuit is connected to both the row decoder and the column selector, which determines and updates the ROI region based on the edge image and generates address signals for row and column control. The readout circuit quantizes the current signals of the pixel units in the corresponding rows and columns of the pixel array based on the address signals and outputs a standard image or ROI image. The PLL is connected to both the digital logic circuit and the readout circuit, providing clock signals of different frequencies for the imaging system.

[0008] Optionally, the readout circuit includes a clamping circuit, a current mirror module, a readout capacitor, an analog comparator, an AND logic gate, a counter, and an output channel, and uses multiple switches to achieve different copy ratios of current sampling in different operating modes.

[0009] The pixel array is connected to the current mirror module via a clamping circuit. The current mirror module, analog comparator, logic gates, and counter are connected in turn. The counter is connected to the output channel via a switch and to the edge detection wake-up circuit via another switch. The readout capacitor is connected to both the analog comparator and the current mirror module.

[0010] Optionally, in the readout circuit, the readout capacitor is pre-charged to the power supply voltage. When the ramp voltage generated by the ramp circuit begins to rise, the AND logic gate output is high, the counter starts counting, and the pixel array gradually generates pixel current. After the pixel current is sampled by the current mirror module, it discharges the readout capacitor. When the ramp voltage rises to the pixel threshold voltage, the pixel current changes abruptly, the readout capacitor is discharged to the analog comparator reference voltage, the analog comparator output flips, the AND logic gate output is low, and the counter stops counting. At this time, the digital code value in the counter is the threshold voltage reflecting the pixel light intensity information. In standard imaging and edge detection wake-up modes, the pixel current is copied 1:1 by the current mirror; in ROI imaging mode, the pixel current is copied 1:1 / 4.

[0011] Optionally, the edge detection wake-up circuit includes an XOR gate, a multiplexer, and a digital comparator; the input of the XOR gate is connected to the output of the AND logic gate in the current column and adjacent column readout circuits, and the output is connected to one of the inputs of the multiplexer; the other input of the multiplexer is connected to the AND logic gate in the adjacent column readout circuit, and the output is connected to the enable terminal of the counter in the readout circuit; the input of the digital comparator is connected to the output of the counter in the current column readout circuit.

[0012] Optionally, in standard imaging and ROI imaging modes, the multiplexer selects the control signal for the current column, the digital comparator is bypassed, and the counter outputs the pixel information of the current column; in edge detection wake-up mode, the multiplexer selects the difference control signal between the current column and the adjacent column, and the difference in gray values ​​between the two adjacent columns is sent to the digital comparator for comparison with the edge threshold; when the difference in gray values ​​is greater than the edge threshold, the digital comparator outputs 1 bit 1, otherwise it outputs 1 bit 0.

[0013] Optionally, the gate interconnection of each row of pixels in the pixel array forms a control terminal, the drain interconnection of each column of pixels forms an output terminal, and the source of all pixels is grounded; the control terminal corresponding to each row of pixels is connected to a ramp circuit through a switch, and the output terminal corresponding to each column of pixels is connected to a readout circuit through a switch.

[0014] The clamping circuit in the readout circuit is implemented using a single transistor, and the output terminal corresponding to each column of pixels is connected to the source of the single transistor through a switch; the current mirror module consists of a Cascode structure composed of six transistors.

[0015] The second objective of this invention is to provide a region of interest imaging method based on an edge detection wake-up circuit, which implements a standard imaging mode, an edge detection wake-up mode, or a ROI imaging mode based on the above-mentioned system.

[0016] In standard imaging mode, the system operates at low frame rate at full resolution, continuously capturing images within the field of view. The readout circuit uses a rolling shutter timing to quantize pixel information line by line, and the system outputs a normal image.

[0017] In edge detection wake-up mode, the system maintains full-resolution operation, continuously samples and compares grayscale values ​​of any two adjacent pixels. When the difference between the grayscale values ​​of adjacent pixels is greater than the edge threshold, the system outputs an edge image. The digital logic uses the edge image to determine the ROI region for tracking the target.

[0018] In ROI imaging mode, after the system determines and updates the ROI region based on the edge image, the pixels in the region are averaged by the readout circuit, and the system outputs the ROI image at a high frame rate in a reduced resolution manner.

[0019] Optionally, the readout capacitor in the readout circuit is pre-charged to the power supply voltage. In standard imaging mode, the readout circuit samples the current of two columns of pixels simultaneously. The pixel current is copied 1:1 by the upper current mirror, and the readout capacitor begins to discharge. When the ramp voltage rises to the pixel device threshold voltage, the pixel current changes abruptly, the voltage on the upper plate of the readout capacitor is discharged to the comparator reference voltage, the comparator output flips, causing the counter enable signal EN to become 0, and the counter stops counting. At this time, the gray value stored in the counter is the threshold voltage reflecting the light response intensity, completing the readout of the first row of pixel information. Following the above working process, the system reads out each row of pixels in sequence, and the final image is output through the output channel.

[0020] Optionally, in edge detection wake-up mode, the grayscale value stored in the counter is the difference between the grayscale values ​​of adjacent pixels. This difference is sent to the edge detection module for comparison with the edge threshold. When the difference is greater than the edge threshold, the edge detection module outputs 1 bit 1, otherwise it outputs 1 bit 0. Following the above process, the system performs edge detection on each row of pixels in sequence, and finally outputs the edge image through the output channel.

[0021] Optionally, in ROI imaging mode, the edge detection wake-up circuit simultaneously enables two rows of pixels in the pixel array, the current mirror copies the pixel current at a ratio of 1:1 / 4, it is then quantized by the counter, and finally the ROI image is output through the output channel.

[0022] The beneficial effects of this invention are:

[0023] This invention proposes a region-of-interest (ROI) imaging method and system based on an edge detection wake-up circuit. The ROI imaging system is constructed by designing a readout circuit and an edge detection wake-up circuit. This imaging system supports three operating modes and shares the same readout circuit. In standard imaging mode, the system outputs a normal image at full resolution and a low frame rate. In edge detection wake-up mode, the system generates an edge image by continuously comparing the difference in grayscale values ​​between two adjacent columns of pixels. The ROI mode is triggered; after the digital logic determines and updates the ROI region based on the edge image, the pixels within the region are averaged by the readout circuit, and the system outputs the ROI image at a lower resolution and a higher frame rate.

[0024] The edge detection wake-up circuit proposed in this invention obtains the pulse width difference signal of the adjacent pixel counter enable signal through logical operations with logic gates and XOR logic gates without introducing additional storage circuits and complex calculation circuits. This signal is then used to control the counter to count the difference, effectively obtaining the absolute value of the difference between the grayscale values ​​of adjacent pixels without the need for additional absolute value circuitry. This value is directly compared with an edge threshold on a digital comparator to output the edge image, thus solving the problems of requiring additional storage and computational complexity on-chip.

[0025] The readout circuit proposed in this invention achieves compatibility with three operating modes by switching the timing. It can sample and quantize pixel currents one-to-one in standard imaging and edge detection wake-up modes; and quantize the average pixel current in ROI mode. This allows the system to output normal images at a low frame rate in standard imaging and edge detection wake-up modes, and output ROI images at a high frame rate in ROI mode, effectively reducing spatial resolution and increasing frame rate.

[0026] Therefore, the region of interest imaging method and imaging system based on edge detection wake-up circuit proposed in this invention can significantly compress image information through edge detection, and the system only runs at a high frame rate in ROI imaging mode, thereby significantly reducing system power consumption and transmission bandwidth. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a schematic diagram of a region of interest imaging system based on an edge detection wake-up circuit according to an embodiment of the present invention;

[0029] Figure 2 This is a readout circuit architecture diagram of a region of interest imaging system based on an edge detection wake-up circuit according to an embodiment of the present invention;

[0030] Figure 3 This is a timing diagram of the readout circuit of a region of interest imaging system based on an edge detection wake-up circuit provided in an embodiment of the present invention under different operating modes;

[0031] Figure 4 This is a diagram of the edge detection wake-up circuit architecture of a region of interest imaging system based on an edge detection wake-up circuit according to an embodiment of the present invention;

[0032] Figure 5 This is a timing diagram of the edge detection wake-up circuit of a region of interest imaging system based on an edge detection wake-up circuit, provided in an embodiment of the present invention. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0034] Example 1

[0035] This embodiment provides a region-of-interest imaging system based on an edge detection wake-up circuit. A schematic diagram of the system is shown below. Figure 1 As shown, the system includes a pixel array, a ramp circuit, a readout circuit, an edge detection wake-up circuit, a column selector, a high-voltage drive circuit, a row decoder, a PLL (phase-locked loop), and digital logic circuits.

[0036] In this imaging system, the pixel array comprises N×N pixel units. The control terminals of pixel units in the same row are connected together, and the output terminals of pixel units in the same column are connected together. A ramp circuit provides a ramp voltage and is connected to a high-voltage drive circuit, which in turn is connected to the pixel array. By applying different operating voltages to the pixel array, the circuit controls the pixel array to enter standby, reset, exposure, and readout modes in three different modes: standard imaging mode, edge detection wake-up mode, or ROI imaging mode. The edge detection wake-up circuit outputs an edge image by comparing the difference in grayscale values ​​between any two adjacent pixels with an edge threshold. This edge image is also transmitted to the digital logic circuit. The digital logic circuit is connected to both the row decoder and the column selector. It determines and updates the ROI region based on the edge image and generates address signals for row and column control. The readout circuit quantizes the current signals of the pixel units in the corresponding rows and columns of the pixel array based on the address signals and outputs a standard image or ROI image. A PLL is connected to both the digital logic circuit and the readout circuit, providing clock signals of different frequencies for the imaging system.

[0037] In this embodiment, the pixel array consists of floating gate devices with a size of 2500×2500. The control terminals of devices in the same row are connected together, and the output terminals of devices in the same column are connected together.

[0038] In standard imaging and edge detection wake-up mode, the control and output terminals of the device are not merged, resulting in a total of 2500 control terminals and 2500 output terminals.

[0039] In ROI mode, the control and output terminals are spatially merged, resulting in 1250 control terminals and 1250 output terminals. The system has 2500 readout circuits, each connected to each control terminal of the pixel array, responsible for sampling and quantizing the output current after photoelectric conversion. The edge detection wake-up circuit operates only in edge detection wake-up mode, continuously comparing the grayscale difference between any two adjacent pixels along both horizontal and vertical directions. When the grayscale difference is greater than the edge threshold, the system outputs 1 bit 1; otherwise, it outputs 1 bit 0. The ramp circuit provides appropriate operating voltage to the array and peripheral circuits. The high-voltage drive circuit provides different operating voltages to the array, controlling the system to enter different operating modes. Row decoders and column selectors provide gating control for each pixel, preparing for image data readout. Digital logic circuits transmit timing control logic to the system and continuously determine and update ROI regions using edge images, generating address signals for row and column control. In addition, the PLL is connected to the digital logic circuit and the readout circuit to provide clock signals of different frequencies for the imaging system.

[0040] The system supports three imaging modes: standard imaging, edge detection wake-up, and ROI imaging. In standard imaging mode, the system operates at full resolution and a low frame rate, continuously capturing images within the field of view. The readout circuit uses a rolling shutter timing to quantize pixel information line by line, outputting a 10-bit normal image. The other two modes are in standby mode. In edge detection wake-up mode, the system maintains full resolution operation, continuously sampling and comparing the grayscale values ​​of any two adjacent pixels. When the difference in grayscale values ​​between adjacent pixels exceeds an edge threshold, the system outputs a 1-bit edge image, which wakes up the ROI function. Digital logic uses the edge image to determine the ROI region for target tracking. Within the ROI region, the resolution is reduced by a factor of four, and information from four pixels is averaged to achieve real-time target tracking at the maximum frame rate. All three imaging modes share the same readout circuitry without increasing pixel size or area. Furthermore, since high frame rate readout is performed only within the ROI, system bandwidth and power consumption are significantly reduced.

[0041] Example 2

[0042] This embodiment provides a region-of-interest (ROI) imaging method based on an edge detection wake-up circuit. This method is implemented based on the ROI imaging system based on an edge detection wake-up circuit provided in Embodiment 1. The system architecture is as follows: Figure 1 As shown, it includes a pixel array, ramp circuit, readout circuit, edge detection wake-up circuit, column selector, high voltage drive circuit, row decoder, PLL (phase-locked loop), and digital logic circuit.

[0043] The architecture of the readout circuit is as follows: Figure 2 As shown, the readout circuit includes a clamping circuit, a current mirror module, a readout capacitor, an analog comparator, an AND logic gate, a counter, and an output channel. It uses multiple switches to achieve current sampling at different copy ratios under different operating modes. The pixel array is connected to the current mirror module through the clamping circuit. The current mirror module, analog comparator, AND logic gate, and counter are connected in sequence. The counter is connected to the output channel through a switch and to the edge detection circuit through another switch. The readout capacitor is connected to both the analog comparator and the current mirror module.

[0044] This embodiment uses a pixel array consisting of 2×2 pixel units as an example for illustration. Figure 2 As shown, the pixel array includes a first pixel unit P1, a second pixel unit P2, a third pixel unit P3, and a fourth pixel unit P4; the gate interconnection of pixel units in the same row of the pixel array forms control terminal 0 and control terminal 1, the drain interconnection of pixel units in the same column of the pixel array forms output terminal 0 and output terminal 1, and the source of all pixel units is grounded; each column of pixel devices shares a readout circuit.

[0045] Figure 2 In the diagram, the gates of the first pixel unit P1 and the second pixel unit P2, which are in the same row, are interconnected to form control terminal 0. The gates of the third pixel unit P3 and the fourth pixel unit P4 are interconnected to form control terminal 1. Control terminal 0 and control terminal 1 are connected to the ramp circuit through the fourth switch S3 and the fifth switch S4, respectively. The drains of the first pixel unit P1 and the third pixel unit P3, which are in the same column, are interconnected to form output terminal 0. The drains of the second pixel unit P2 and the fourth pixel unit P4 are interconnected to form output terminal 1. Output terminal 0 and output terminal 1 are connected to a readout circuit through the first switch S0 and the second switch S1, respectively.

[0046] Taking output terminal 0 as an example, the connection relationship between the pixel array and the readout circuit is described: Output terminal 0 is connected to the clamping circuit through the first switch S0, and the clamping circuit is connected to the current mirror module; the current mirror module consists of transistors M2-M7, forming a Cascode structure, where the sources of transistors M6 and M7 are connected to the power supply voltage VDD through the sixth switch S5 and the seventh switch S6, respectively. The sixth switch S5 and the seventh switch S6 control the current copy ratio of the current mirror. When the sixth switch S5 is closed, the current is copied at a 1:1 ratio, and when the seventh switch S6 is closed, the current is copied at a 1:1 / 4 ratio; the output terminal of the current mirror module is connected to the upper stage board of the readout capacitor, and the lower stage board of the readout capacitor is grounded; the output terminal of the current mirror module is also connected to the inverting input terminal of the analog comparator, and the non-inverting input terminal of the analog comparator is connected to the voltage signal V. com The output of the analog comparator is connected to one input of a logic gate, and the other input of the logic gate is connected to C. start The signal is connected to the input of the counter via the output of the logic gate, and the output of the counter is connected to the output channel via the ninth switch S8; the counter is also connected to the edge detection circuit via the eighth switch S7.

[0047] The timing sequence of the readout circuit is as follows Figure 3 As shown, after the system is powered on, the pixel array completes photoelectric conversion, and the system enters readout mode. The ramp circuit provides the reference voltage and ramp voltage for the readout circuit and the pixel array, respectively. The clamping circuit, transistor M1, fixes the drain-source potential of the pixel device at V1-V. TH V TH This is the threshold voltage of transistor M1. The readout capacitor is pre-charged to the power supply voltage VDD under the control of the Precharge signal. At this time, the voltage at the negative input terminal of the analog comparator is greater than the voltage at the positive input terminal VDD. com Therefore, the analog comparator output signal Out is 1. Because C... start The signal and the ramp are synchronized, therefore C start The signal is also 1. After passing through the AND gate, the enable signal EN of the counter becomes 1, and the counter starts counting.

[0048] In standard imaging mode, switches S0, S1, S3, S5, and S8 are simultaneously closed, while switches S2, S4, S6, and S7 are open. The readout circuit simultaneously samples the pixel currents of two columns. The pixel currents are copied 1:1 by the upper current mirror, and the reading capacitor C is then sampled. read Discharge. When the ramp voltage rises to the pixel device threshold voltage, the pixel current changes abruptly, and the readout capacitor C... read The voltage on the upper plate is discharged to the comparator reference voltage V. com The comparator output flips, causing the counter enable signal EN to become 0, and the counter stops counting. At this time, the value stored in the counter is the threshold voltage reflecting the light response intensity, completing the reading of the first row of pixel information. Following the above working process, the system will sequentially read the second row, the third row, and up to the 2500th row of pixels, and finally the image is transmitted off-chip through the output channel.

[0049] In edge detection wake-up mode, switches S0, S1, S3, S5, and S7 are closed, while switches S2, S4, S6, and S8 are open. The sampling and quantization process is consistent with the standard imaging mode, except that the grayscale values ​​stored in the counter are not directly output but are transmitted to the edge detection module along with the grayscale values ​​of adjacent columns. The edge detection module compares the difference between the grayscale values ​​of two adjacent columns with an edge threshold. When the difference is greater than the edge threshold, the edge detection module outputs 1 bit 1; otherwise, it outputs 1 bit 0. Following this process, the system sequentially performs edge detection on the second row, the third row, and up to the 2500th row of pixels, finally outputting the edge image through the output channel.

[0050] In ROI imaging mode, switches S0, S2, S3, S4, S6, and S8 are closed, while switches S1, S5, and S7 are open. The pixel array within the ROI area is merged in a 2×2 configuration. Unlike the other two modes, this mode enables two rows of pixels simultaneously. The pixel currents from the four devices are accumulated and copied by a current mirror at a 1:1 / 4 ratio, then quantized by a counter. Finally, the ROI image is output through the output channel.

[0051] The structure of the edge detection wake-up circuit is as follows: Figure 4 As shown, it includes XOR logic gates, multiplexers, and digital comparators.

[0052] In this embodiment, the edge detection wake-up scheme is illustrated using three adjacent pixels as an example. The three pixels are denoted as pixel [N-1], pixel [N], and pixel [N+1]. The output of the AND logic gate in the readout circuit is connected to a multiplexer and an XOR logic gate, respectively. The output of the XOR logic gate is connected to the multiplexer, and the output of the multiplexer is connected to the enable terminal of the counter. The outputs of counter [N-1] and counter [N] are connected to switches SW [N-1] and SW [N], and also to the negative input terminal of the digital comparator.

[0053] The timing sequence of the edge detection wake-up circuit is as follows: Figure 5 As shown. In standard imaging mode, the SEL signal is 0. The start time of the counter is determined by C. start The output of the comparator determines C when the ramp is input. start The output is high because the read capacitor is pre-charged to the supply voltage, therefore the comparator output OUT is high. comp Also high, the counter counts normally until the comparator flips (generally, there is no count overflow C). start When SEL becomes 0, the counter directly outputs the standard image. In edge detection mode, SEL is 1, and the counter's counting period is determined by the XOR gate outputting CTR. diff The decision, and CTR diff The pulse width is exactly the difference between the counting cycles of two adjacent pixels, so the output of the counter at this time is the difference in grayscale values ​​between two adjacent pixels. This difference in grayscale values ​​is fed into the negative input of the digital comparator and compared with the edge threshold D. TH The comparison is performed. When the difference in grayscale values ​​is greater than the edge threshold, it indicates that an edge exists, and the digital comparator outputs 1 bit 1; otherwise, it indicates that no edge exists, and the digital comparator outputs 1 bit 0.

[0054] Some steps in the embodiments of the present invention can be implemented using software, and the corresponding software program can be stored in a readable storage medium, such as an optical disc or a hard disk.

[0055] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A region-of-interest imaging system based on an edge detection wake-up circuit, characterized in that, The system includes a pixel array, a ramp circuit, a readout circuit, an edge detection wake-up circuit, a column selector, a high-voltage drive circuit, a row decoder, a PLL, and digital logic circuits. The ramp circuit is connected to the high-voltage drive circuit, which in turn is connected to the pixel array. By applying different operating voltages to the pixel array, the circuit controls the array to enter standby, reset, exposure, and readout modes in three different modes: standard imaging mode, edge detection wake-up mode, or ROI imaging mode. The edge detection wake-up circuit outputs an edge image by comparing the difference in grayscale values ​​between two pixels in any adjacent column with an edge threshold. This edge image is also transmitted to the digital logic circuit. The digital logic circuit is connected to both the row decoder and the column selector, determining and updating the ROI region based on the edge image and generating address signals for row and column control. The readout circuit quantizes the current signals of the pixel units in the corresponding rows and columns of the pixel array based on the address signals, outputting a standard image or an ROI image. The PLL is connected to both the digital logic circuit and the readout circuit, providing clock signals of different frequencies to the imaging system. The edge detection wake-up circuit includes an XOR gate, a multiplexer, and a digital comparator; the input of the XOR gate is connected to the output of the AND logic gate in the current column and adjacent column readout circuits, and the output is connected to one of the inputs of the multiplexer; the other input of the multiplexer is connected to the AND logic gate in the current column readout circuit, and the output is connected to the enable terminal of the counter in the readout circuit; the input of the digital comparator is connected to the output of the counter in the current column readout circuit. In standard imaging and ROI imaging modes, the multiplexer selects the control signal for the current column, and the counter outputs the pixel information of the current column. In edge detection wake-up mode, the multiplexer selects the difference control signal between the current column and the adjacent column. The difference between the gray values ​​of the two adjacent columns is sent to the digital comparator for comparison with the edge threshold. When the difference between the gray values ​​is greater than the edge threshold, the digital comparator outputs 1 bit 1, otherwise it outputs 1 bit 0.

2. The system according to claim 1, characterized in that, The readout circuit includes a clamping circuit, a current mirror module, a readout capacitor, an analog comparator, an AND logic gate, a counter, and an output channel, and uses multiple switches to achieve current sampling at different copy ratios under different operating modes. The pixel array is connected to the current mirror module via a clamping circuit. The current mirror module, analog comparator, logic gate, and counter are connected in sequence. The counter is connected to the output channel via a switch and to the edge detection wake-up circuit via another switch. The readout capacitor is connected to both the analog comparator and the current mirror module.

3. The system according to claim 2, characterized in that, In the readout circuit, the readout capacitor is precharged to the power supply voltage. When the ramp voltage generated by the ramp circuit begins to rise, the output of the logic gate is high, the counter starts counting, and the pixel array gradually generates pixel current. After the pixel current is sampled by the current mirror module, the readout capacitor is discharged. When the ramp voltage rises to the pixel threshold voltage, the pixel current changes abruptly, the readout capacitor is discharged to the analog comparator reference voltage, the analog comparator output flips, the AND logic gate output goes low, and the counter stops counting. At this time, the digital code value in the counter is the threshold voltage reflecting the pixel light intensity information. In standard imaging and edge detection wake-up modes, the pixel current is copied 1:1 by the current mirror. In ROI imaging mode, the pixel current is copied 1:1 / 4.

4. The system according to claim 3, characterized in that, In the pixel array, the gate interconnection of each row of pixels forms a control terminal, the drain interconnection of each column of pixels forms an output terminal, and the source of all pixels is grounded; the control terminal corresponding to each row of pixels is connected to a ramp circuit through a switch, and the output terminal corresponding to each column of pixels is connected to a readout circuit through a switch. The clamping circuit in the readout circuit is implemented using a single transistor, and the output terminal corresponding to each column of pixels is connected to the source of the single transistor through a switch; the current mirror module consists of a Cascode structure composed of six transistors.

5. A region-of-interest imaging method based on an edge detection wake-up circuit, characterized in that, The method implements a standard imaging mode, an edge detection wake-up mode, or a ROI imaging mode based on the system described in any one of claims 1-4. In standard imaging mode, the system operates at low frame rate at full resolution, continuously capturing images within the field of view. The readout circuit uses a rolling shutter timing to quantize pixel information line by line, and the system outputs a normal image. In edge detection wake-up mode, the system maintains full-resolution operation, continuously samples and compares grayscale values ​​of any two adjacent pixels. When the difference between the grayscale values ​​of adjacent pixels is greater than the edge threshold, the system outputs an edge image. The digital logic circuit uses the edge image to determine the ROI region for tracking the target. In ROI imaging mode, after the system determines and updates the ROI region based on the edge image, the pixels in the region are averaged by the readout circuit, and the system outputs the ROI image at a high frame rate in a reduced resolution manner.

6. The method according to claim 5, characterized in that, The readout capacitor in the readout circuit is pre-charged to the power supply voltage. In standard imaging mode, the readout circuit corresponding to the pixel column samples the current of two columns of pixels simultaneously. The pixel current is copied 1:1 by the upper current mirror and begins to discharge the readout capacitor. When the ramp voltage rises to the pixel device threshold voltage, the pixel current changes abruptly. The voltage of the upper plate of the readout capacitor is discharged to the comparator reference voltage. The comparator output flips, causing the counter enable signal EN to become 0, and the counter stops counting. At this point, the gray value stored in the counter is the threshold voltage that reflects the light response intensity, completing the reading of the first row of pixel information; following the above working process, the system reads out each row of pixels in sequence, and finally the image is output through the output channel.

7. The method according to claim 6, characterized in that, In edge detection wake-up mode, the gray value stored in the counter is the difference between the gray values ​​of adjacent pixels. This difference is sent to the edge detection wake-up circuit and compared with the edge threshold. When the difference is greater than the edge threshold, the edge detection wake-up circuit outputs 1 bit 1, otherwise it outputs 1 bit 0. Following the above process, the system performs edge detection on each row of pixels in sequence and finally outputs the edge image through the output channel.

8. The method according to claim 7, characterized in that, In ROI imaging mode, the system simultaneously enables two rows of pixels in the pixel array, and the current mirror copies the pixel current at a ratio of 1:1 / 4. The current is then quantized by a counter and finally output as an ROI image through the output channel.

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