A voltage stabilizing diode structure, packaging structure and manufacturing method thereof

Abstract

The present invention relates to a voltage regulator diode structure, a packaging structure and a manufacturing method thereof. The present invention comprises a substrate; an AlN nucleation layer, a GaN buffer layer, a U‑GaN layer, a U‑GaN repair layer, a U‑GaN channel layer, an AlN space layer, an AlGaN barrier layer, a GaN contact layer, a metal pattern layer, a pad metal layer and an insulating layer; the metal pattern layer comprises an ohmic contact metal layer and a Schottky contact metal layer arranged at intervals on the GaN contact layer, and a portion of the GaN contact layer surface is exposed; the pad metal layer comprises a first pad metal layer and a second pad metal layer, the first pad metal layer contacts the surface of the ohmic contact metal layer, and the second pad metal layer contacts the surface of the Schottky contact metal layer; the insulating layer at least covers the metal pattern layer, the exposed surface of the GaN contact layer and a portion of the pad metal layer surface. The present invention simplifies the voltage regulator diode structure and its manufacturing process, and improves the chip yield.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor\GaN-based voltage regulator diodes, and in particular to a voltage regulator diode structure, a packaging structure and a manufacturing method thereof. Background Art

[0002] The Zener diode (also called Zener diode) is an important component widely used in electronic circuits, mainly used to stabilize the DC operating voltage. In addition, the Zener diode can also be used for signal processing, such as limiting the signal. During circuit operation, the Zener diode is in a reverse breakdown state, which is different from the characteristic of ordinary diodes that will be damaged during reverse breakdown. When the reverse voltage reaches the breakdown voltage of the Zener diode, the reverse current will suddenly increase, and the Zener diode will enter the breakdown region, but its structure and function will not be damaged, but will enter a normal working state.

[0003] After the Zener diode enters the breakdown state, even if the reverse current changes within a large range, the reverse voltage across its two ends can remain relatively stable. This characteristic is called the voltage stabilization characteristic. However, if the reverse current continues to increase beyond the design limit, the Zener diode will not be able to withstand it and will eventually be completely broken down and damaged. Therefore, in practical applications, it is necessary to ensure that the operating current is within a safe range.

[0004] The Zener diodes currently on the market are usually made of silicon-based materials, and the breakdown voltage is formed through the doping and diffusion process of dopants and oxidants. This manufacturing process is technically complex and requires precise control of doping concentration and diffusion conditions. At the same time, the device yield is low and the production cost is high. In addition, due to the limitations of materials and manufacturing processes, the voltage regulation performance of traditional silicon-based Zener diodes may not be sufficient to meet the needs of some high-precision or high-reliability applications. Summary of the invention

[0005] To this end, the present invention provides a voltage stabilizing diode structure, a packaging structure and a manufacturing method thereof, which simplifies the voltage stabilizing diode structure and its manufacturing process, improves the chip yield, and provides better voltage stabilizing performance; and the chip size is small and can be sealed with the LED chip, thereby improving the brightness consistency of the light strip or COB (chip on board packaging) and improving the lighting efficiency.

[0006] In order to solve the above technical problems, the present invention provides a voltage stabilizing diode structure, comprising:

[0007] substrate;

[0008] An AlN nucleation layer is disposed on the substrate;

[0009] A GaN buffer layer, disposed on the AlN nucleation layer;

[0010] A U-GaN layer, disposed on the GaN buffer layer;

[0011] A U-GaN repair layer, disposed on the U-GaN layer;

[0012] A U-GaN channel layer is disposed on the U-GaN repair layer;

[0013] An AlN space layer is disposed on the GaN channel layer;

[0014] An AlGaN barrier layer is disposed on the AlN space layer;

[0015] A GaN contact layer, disposed on the AlGaN barrier layer;

[0016] A metal pattern layer, comprising an ohmic contact metal layer and a Schottky contact metal layer which are arranged on the GaN contact layer at intervals and expose a portion of the surface of the GaN contact layer;

[0017] A pad metal layer, comprising a first pad metal layer and a second pad metal layer, wherein the first pad metal layer contacts the surface of the ohmic contact metal layer, and the second pad metal layer contacts the surface of the Schottky contact metal layer;

[0018] The insulating layer at least covers the metal pattern layer, the exposed surface of the GaN contact layer and a portion of the surface of the pad metal layer.

[0019] In one embodiment of the present invention, the size of a single pattern of the voltage zener diode structure is 60 μm to 1500 μm in length and 65 μm to 1500 μm in width.

[0020] In one embodiment of the present invention, the ohmic contact metal layer includes Ti / Al / Ti / Au or Ti / Al / Ni / Au arranged in sequence from bottom to top.

[0021] In one embodiment of the present invention, the Schottky contact metal layer adopts a structure of stacking multiple layers of high stress metals Ni, Pt, Cr, Rh, Ti or alloys composed of the above metals.

[0022] In one embodiment of the present invention, the distance between the ohmic contact metal layer and the Schottky contact metal layer is 3 um-100 um.

[0023] In one embodiment of the present invention, the substrate is a sapphire or GaN-based substrate.

[0024] The present invention also provides a packaging structure, comprising at least one LED chip and at least one voltage-stabilizing diode structure, wherein the LED chip and the voltage-stabilizing diode structure are packaged in SMD or COB.

[0025] In one embodiment of the present invention, the ratio of the number of the voltage stabilizing diode structures to the number of the LED chips is 1:1 to 1:50.

[0026] In one embodiment of the present invention, a reverse breakdown protection device including a Zener diode is not additionally added to the packaging structure.

[0027] The present invention also provides a method for manufacturing a voltage regulator diode structure, comprising the following steps:

[0028] S1. Providing a sapphire or GaN-based substrate, growing a stacked epitaxial structure on the substrate, including an AlN nucleation layer, a GaN buffer layer, a U-GaN layer, a U-GaN repair layer, a U-GaN channel layer, an AlN space layer, an AlGaN barrier layer and a GaN contact layer grown in sequence; obtaining an epitaxial wafer;

[0029] S2, cleaning the surface of the epitaxial wafer to remove pollutants including organic matter and particles;

[0030] S3, coating the ohmic contact area on the GaN contact layer with photoresist;

[0031] S4, forming a pattern required for an ohmic contact metal layer on the photoresist through ultraviolet exposure and development;

[0032] S5, developing the photoresist to remove the unexposed portion of the photoresist, thereby obtaining a pattern window required for ohmic contact metal deposition on the surface of the epitaxial wafer;

[0033] S6, evaporating an ohmic contact metal layer in the formed pattern window, including Ti / Al / Ti / Au or Ti / Al / Ni / Au from bottom to top, to achieve low resistance contact with the GaN contact layer;

[0034] S7, removing excess metal and photoresist by a stripping process, retaining the ohmic contact metal pattern, and forming an ohmic contact metal layer;

[0035] S8, performing high temperature alloy treatment on the ohmic contact metal layer to form alloy contact and reduce contact resistance;

[0036] S9, coating the Schottky contact area on the GaN contact layer with photoresist again;

[0037] S10, exposing and developing the Schottky area to define a Schottky metal pattern window, and obtaining a window of the Schottky metal deposition position after development;

[0038] S11, depositing a plurality of Schottky metal layers stacked with high stress to form a Schottky contact;

[0039] S12, stripping off excess metal and photoresist to obtain a desired Schottky contact metal pattern, thereby forming a Schottky contact metal layer;

[0040] S13, coating the pad regions on the respective surfaces of the ohmic contact metal layer and the Schottky contact metal layer with photoresist to prepare for subsequent pad metal deposition;

[0041] S14, exposing and developing the pad area to form a pad metal pattern window;

[0042] S15, after development, a window area of ​​the pad metal deposition is clearly defined;

[0043] S16, evaporating a pad metal layer in the window area;

[0044] S17, removing excess metal and photoresist, retaining the required pad metal pattern, and forming a first pad metal layer in contact with the surface of the ohmic contact metal layer, and a second pad metal layer in contact with the surface of the Schottky contact metal layer;

[0045] S18, depositing an insulating layer to cover the surface of the device to provide insulation and protection;

[0046] S19, coating a photoresist on the surface of the insulating layer;

[0047] S20, exposing and developing the photoresist on the insulating layer to form an insulating layer etching window;

[0048] S21, after development, an area to be etched is obtained in the insulating layer;

[0049] S22, removing the photoresist used for patterning the insulating layer, so that the insulating layer has a desired opening and pattern structure;

[0050] S23, perform thick film test, measure film thickness, use probe to perform electrical test on the device, check the characteristics of ohmic and Schottky contacts and the voltage regulation performance of the device;

[0051] S24, thinning and grinding the back side of the device to reduce the thickness of the substrate;

[0052] S25, marking the device surface with a laser, cutting the wafer, and obtaining a chip;

[0053] S26. Carry out final appearance inspection, thin film testing, optical inspection and data archiving of the chips to ensure that the quality meets the requirements;

[0054] S27. Classify and sort the chips according to the test results for subsequent packaging.

[0055] In one embodiment of the present invention, growing a stacked epitaxial structure on the substrate comprises:

[0056] Generating a first AlN layer on the substrate by physical vapor deposition;

[0057] Further growing a second AlN layer on the first AlN layer by metal organic chemical vapor deposition;

[0058] forming a GaN buffer layer on the second AlN layer by low temperature epitaxial growth;

[0059] Growing a layer of undoped GaN material on the GaN buffer layer to form a U-GaN layer;

[0060] Growing a U-GaN repair layer on the U-GaN layer to repair lattice defects generated during the growth process in the previous stage;

[0061] Growing a U-GaN channel layer on the U-GaN repair layer;

[0062] Growing an AlN space layer on the U-GaN channel layer;

[0063] Growing an AlGaN barrier layer on the AlN space layer;

[0064] A GaN contact layer is grown on the AlGaN barrier layer.

[0065] The above technical solution of the present invention has the following advantages compared with the prior art:

[0066] The voltage stabilizing diode structure, packaging structure and manufacturing method thereof described in the present invention improve the yield rate in the production process and reduce the scrap rate by optimizing the manufacturing process and structural design, thereby reducing the overall manufacturing cost.

[0067] The voltage zener diode structure of the present invention can select sapphire or GaN-based substrates to adapt to different application requirements and manufacturing environments. The Schottky contact metal layer adopts a multi-layer high-stress metal stacking structure to improve the reliability and durability of the device in a high-stress environment. The use of Ti / Al / Ti / Au or Ti / Al / Ni / Au multi-layer ohmic contact metal layers ensures low-resistance contact with the GaN contact layer, reduces contact resistance, and reduces device failure rate.

[0068] The spacing between the ohmic contact metal layer and the Schottky contact metal layer in the voltage stabilizing diode structure of the present invention is controlled within the range of 3 μm-100 μm, thereby realizing a high-precision microstructure and further reducing the chip size.

[0069] The voltage-stabilizing diode structure of the present invention can realize SMD (surface mount device) packaging and COB (chip on board packaging) packaging to meet the needs of different application scenarios. The number ratio of voltage-stabilizing diodes to LED chips can reach 1:1 to 1:50, which greatly improves the integration of the packaging and reduces the volume and weight of the overall component. Through the integrated packaging with the LED chip, the consistency of the electrical performance between each voltage-stabilizing diode and the LED chip is ensured, and the brightness consistency and overall light effect of the light strip or COB are improved. There is no need to add additional reverse breakdown protection devices such as Zener tubes in the packaging structure, which simplifies the circuit design and reduces the complexity and cost of the device.

[0070] The manufacturing method of the present invention significantly reduces lattice defects and improves the quality of epitaxial wafers by precisely controlling the growth of AlN nucleation layer, GaN buffer layer and U-GaN layer on sapphire or GaN-based substrate. The stacking sequence and structural layout of each layer of material are optimized to simplify the overall structure, and the manufacturing process of the voltage regulator diode is optimized by adopting multi-step photolithography, evaporation and rapid thermal processing and other process steps to improve production efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0071] In order to make the contents of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments of the present invention in conjunction with the accompanying drawings.

[0072] Figure 1 It is a schematic diagram of the overall structure of the voltage regulator diode structure in Example 1 of the present invention.

[0073] Figure 2 It is a schematic diagram of the structure of the packaging structure in Example 2 of the present invention (using SMD packaging).

[0074] Figure 3 It is a schematic diagram of the packaging structure in Example 2 of the present invention (using COB packaging).

[0075] Figure 4 It is a flow chart of the method for manufacturing the voltage regulator diode structure in Example 3 of the present invention.

[0076] Description of the Figures in the Specification:

[0077] 100, Zener diode structure; 101, substrate; 102, AlN nucleation layer; 102a, first AlN layer; 102b, second AlN layer; 103, GaN buffer layer; 104, U-GaN layer; 105, U-GaN repair layer; 106, U-GaN channel layer; 107, AlN space layer; 108, AlGaN barrier layer; 109, GaN contact layer; 110, Ohmic contact metal layer; 111, Schottky contact metal layer; 112, first pad metal layer; 113, second pad metal layer; 114, insulating layer;

[0078] 200.LED chips. DETAILED DESCRIPTION

[0079] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it, but the embodiments are not intended to limit the present invention.

[0080] In the present invention, if directions (up, down, left, right, front and back) are described, it is only for the convenience of describing the technical solution of the present invention, and does not indicate or imply that the technical features referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it cannot be understood as a limitation of the present invention.

[0081] In the present invention, "several" means one or more, "multiple" means more than two, "greater than", "less than", "exceed" and the like are understood to exclude the number itself; "above", "below", "within" and the like are understood to include the number itself. In the description of the present invention, if there is a description of "first" or "second", it is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0082] In the present invention, unless otherwise clearly defined, the words "set", "install", "connect" and the like should be understood in a broad sense, for example, they can be directly connected or indirectly connected through an intermediate medium; they can be fixedly connected or detachably connected or integrally formed; they can be mechanically connected or electrically connected or able to communicate with each other; they can be the internal connection of two elements or the interaction relationship between two elements. Those skilled in the art can reasonably determine the specific meanings of the above words in the present invention in combination with the specific content of the technical solution.

[0083] Example 1

[0084] Reference Figure 1 As shown, this embodiment provides a voltage zener diode structure 100, including:

[0085] Substrate 101;

[0086] The AlN nucleation layer 102 is disposed on the substrate 101. The AlN nucleation layer 102 is used to provide a flat base surface suitable for the growth of the GaN buffer layer 103, thereby improving the crystal quality of the subsequent GaN buffer layer 103;

[0087] A GaN buffer layer 103 is disposed on the AlN nucleation layer 102; the GaN buffer layer 103 is used to relieve stress between the AlN nucleation layer 102 and the subsequent U-GaN layer 104, and improve the crystal quality of the entire epitaxial structure;

[0088] U-GaN layer 104 (undoped GaN), disposed on the GaN buffer layer 103, to ensure the stability and reliability of the device in a reverse breakdown state;

[0089] The U-GaN repair layer 105 is disposed on the U-GaN layer 104 and is used to repair the lattice defects that may be generated in the growth process of the U-GaN layer 104, thereby improving the crystal quality. By repairing the lattice defects, the perfection of the entire epitaxial structure is improved, and the stability and life of the device are enhanced;

[0090] The U-GaN channel layer 106 is disposed on the U-GaN repair layer 105 and is used to control the flow of current and determine the breakdown voltage;

[0091] An AlN space layer 107 is disposed on the GaN channel layer to provide electrical isolation and optimize electric field distribution;

[0092] An AlGaN barrier layer 108 (low doping) is disposed on the AlN space layer 107; by adjusting the composition ratio of AlGaN, the height and current-voltage characteristics of the Schottky barrier can be accurately controlled, the barrier layer structure can be optimized, and the performance and reliability of the Zener diode in the reverse breakdown state can be improved;

[0093] The GaN contact layer 109 is disposed on the AlGaN barrier layer 108 and is used for contacting with metal to ensure good electrical connection and low contact resistance;

[0094] A metal pattern layer, comprising an ohmic contact metal layer 110 and a Schottky contact metal layer 111 which are arranged on the GaN contact layer 109 at intervals and expose a portion of the surface of the GaN contact layer 109;

[0095] The pad metal layer includes a first pad metal layer 112 and a second pad metal layer 113, which may be made of materials such as aluminum (Al) and gold (Au), wherein the first pad metal layer 112 contacts the surface of the ohmic contact metal layer 110, and the second pad metal layer 113 contacts the surface of the Schottky contact metal layer 111;

[0096] The insulating layer 114 at least covers the metal pattern layer, the exposed surface of the GaN contact layer (109) and part of the surface of the pad metal layer, and can be made of materials such as silicon nitride (Si3N4) and silicon dioxide (SiO2), so as to protect the internal metal layer from corrosion and mechanical damage from the external environment and extend the service life of the device.

[0097] Specifically, the size of a single pattern of the voltage stabilizing diode structure is 60 μm to 1500 μm in length and 65 μm to 1500 μm in width.

[0098] Specifically, the ohmic contact metal layer 110 includes Ti / Al / Ti or Ni / Au arranged in sequence from bottom to top. The multilayer structure of Ti / Al / Ti or Ni / Au ensures efficient electrical connection with the GaN contact layer 109 and reduces contact resistance. Each layer needs to be set with a suitable thickness and matching high-temperature alloy conditions to more effectively reduce contact resistance. Among them, the thickness of each layer of the ohmic contact metal layer 110 is as follows: the contact layer (Ti) is 1-5000 angstroms, the activation layer (Al) is 1-10000 angstroms, the transition layer (Ti or Ni) is 1-10000 angstroms, and the protective layer (Au) is 1-30000 angstroms; the high-temperature alloy temperature range of each layer is 600-1200°C.

[0099] Specifically, the Schottky contact metal layer 111 adopts a multi-layer high stress metal Ni, Pt, Cr, Rh, Ti or an alloy of the above metals stacked structure.

[0100] The high stress metal stack structure improves the mechanical and electrical stability of the Schottky junction and reduces contact surface defects.

[0101] Specifically, the distance between the ohmic contact metal layer 110 and the Schottky contact metal layer 111 is 3 um to 100 um, thereby realizing a high-precision microstructure and further reducing the chip size.

[0102] Specifically, the substrate 101 is a sapphire or GaN-based substrate 101. The use of a sapphire or GaN-based substrate 101 can meet the needs of different application scenarios. Sapphire and GaN-based substrates 101 have good lattice matching, which helps to reduce lattice defects in the epitaxial layer and improve the overall quality of the device.

[0103] Example 2

[0104] Reference Figure 2 , Figure 3 As shown, this embodiment provides a packaging structure, including at least one LED chip 200 and at least one Zener diode structure 100, wherein the LED chip 200 and the Zener diode structure 100 are packaged in SMD or COB. Surface mount device (SMD) or chip on board (COB) packaging technology is used to achieve efficient packaging and assembly.

[0105] Specifically, the ratio of the number of the voltage stabilizing diode structure 100 to the number of the LED chips 200 is 1:1 to 1:50. According to different requirements, the ratio of the voltage stabilizing diode to the LED chips 200 can be flexibly adjusted to meet diverse application requirements.

[0106] Specifically, the packaging structure does not include an additional reverse breakdown protection device including a Zener diode.

[0107] Through the above arrangement, the voltage stabilizing diode is integrated with the LED chip 200, which greatly improves the integration of the package and reduces the volume and weight of the overall component. Through the integrated package with the LED chip 200, the electrical performance consistency between each voltage stabilizing diode and the LED chip 200 is ensured, and the brightness consistency and overall light efficiency of the light strip or COB are improved. There is no need to add a reverse breakdown protection device such as a Zener tube in the package structure, which simplifies the circuit design and reduces the complexity and cost of the device.

[0108] Example 3

[0109] This embodiment provides a method for manufacturing a voltage regulator diode structure 100, comprising the following steps:

[0110] S1. Provide a sapphire or GaN-based substrate 101, and grow a stacked epitaxial structure on the substrate 101, including an AlN nucleation layer 102, a GaN buffer layer 103, a U-GaN layer 104, a U-GaN repair layer 105, a U-GaN channel layer 106, an AlN space layer 107, an AlGaN barrier layer 108 and a GaN contact layer 109 grown in sequence; and obtain an epitaxial wafer.

[0111] Wherein, growing a stacked epitaxial structure on the substrate 101 includes:

[0112] Generating a first AlN layer 102a on the substrate 101 by physical vapor deposition;

[0113] Further growing a second AlN layer 102b on the first AlN layer 102a by metal organic chemical vapor deposition;

[0114] Forming a GaN buffer layer 103 on the second AlN layer 102b by low temperature epitaxial growth;

[0115] Growing a layer of undoped GaN material on the GaN buffer layer 103 to form a U-GaN layer 104;

[0116] Growing a U-GaN repairing layer 105 on the U-GaN layer 104 to repair the lattice defects generated in the previous growth process;

[0117] Growing a U-GaN channel layer 106 on the U-GaN repair layer 105;

[0118] Growing an AlN space layer 107 on the U-GaN channel layer 106;

[0119] Growing an AlGaN barrier layer 108 on the AlN space layer 107;

[0120] A GaN contact layer 109 is grown on the AlGaN barrier layer 108 .

[0121] S2. Clean the surface of the epitaxial wafer to remove pollutants including organic matter and particles, thereby ensuring the quality of subsequent photolithography and metal deposition processes.

[0122] S3, coating the ohmic contact region on the GaN contact layer 109 with photoresist;

[0123] S4, forming a pattern required for the ohmic contact metal layer 110 on the photoresist through ultraviolet exposure and development;

[0124] S5, developing the photoresist to remove the unexposed portion of the photoresist, thereby obtaining a pattern window required for ohmic contact metal deposition on the surface of the epitaxial wafer;

[0125] S6, evaporating an ohmic contact metal layer 110 in the formed pattern window, including Ti / Al / Ni / Au or Ti / Al / Ni / Au from bottom to top, to achieve low resistance contact with the GaN contact layer 109;

[0126] S7, removing excess metal and photoresist by a stripping process, retaining the ohmic contact metal pattern, and forming an ohmic contact metal layer 110;

[0127] S8, performing high temperature alloy treatment on the ohmic contact metal layer 110 to form alloy contact and reduce contact resistance;

[0128] S9, coating the Schottky contact area on the GaN contact layer 109 with photoresist again;

[0129] S10, exposing and developing the Schottky area to define a Schottky metal pattern window, and obtaining a window of the Schottky metal deposition position after development;

[0130] S11, depositing a plurality of Schottky metal layers stacked with high stress to form a Schottky contact;

[0131] S12, stripping off excess metal and photoresist to obtain a desired Schottky contact metal pattern, forming a Schottky contact metal layer 111;

[0132] S13, coating the pad regions on the respective surfaces of the ohmic contact metal layer 110 and the Schottky contact metal layer 111 with photoresist to prepare for subsequent pad metal deposition;

[0133] S14, exposing and developing the pad area to form a pad metal pattern window;

[0134] S15, after development, a window area of ​​the pad metal deposition is clearly defined;

[0135] S16, evaporating a pad metal layer in the window area;

[0136] S17, removing excess metal and photoresist, retaining the required pad metal pattern, forming a first pad metal layer 112 in contact with the surface of the ohmic contact metal layer 110, and a second pad metal layer 113 in contact with the surface of the Schottky contact metal layer 111;

[0137] S18, depositing an insulating layer to cover the surface of the device to provide insulation and protection;

[0138] S19, coating a photoresist on the surface of the insulating layer;

[0139] S20, exposing and developing the photoresist on the insulating layer to form an insulating layer etching window;

[0140] S21, after development, an area to be etched is obtained in the insulating layer;

[0141] S22, removing the photoresist used for patterning the insulating layer, so that the insulating layer has a desired opening and pattern structure;

[0142] S23, perform thick film test, measure film thickness, use probe to perform electrical test on the device, check the characteristics of ohmic and Schottky contacts and the voltage regulation performance of the device;

[0143] S24, thinning and grinding the back side of the device to reduce the thickness of the substrate 101;

[0144] S25, marking the device surface with a laser, cutting the wafer, and obtaining a chip;

[0145] S26. Carry out final appearance inspection, thin film testing, optical inspection and data archiving of the chips to ensure that the quality meets the requirements;

[0146] S27. Classify and sort the chips according to the test results for subsequent packaging.

[0147] The manufacturing method significantly reduces lattice defects and improves the quality of epitaxial wafers by precisely controlling the growth of AlN nucleation layer 102, GaN buffer layer 103 and U-GaN layer 104 on sapphire or GaN-based substrate 101. The stacking sequence and structural layout of each layer of material are optimized to simplify the overall structure, and the manufacturing process of the Zener diode is optimized by adopting multi-step photolithography, evaporation and rapid thermal processing and other process steps to improve production efficiency.

[0148] Finally, it should be noted that the above specific implementation methods are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to examples, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present invention, which should be included in the scope of the claims of the present invention.

Claims

1. A voltage zener diode structure, characterized in that: include: Substrate (101); An AlN nucleation layer (102) is disposed on the substrate (101); A GaN buffer layer (103) is disposed on the AlN nucleation layer (102); A U-GaN layer (104) is disposed on the GaN buffer layer (103); A U-GaN repair layer (105) is disposed on the U-GaN layer (104); A U-GaN channel layer (106) is disposed on the U-GaN repair layer (105); An AlN space layer (107) is disposed on the GaN channel layer; An AlGaN barrier layer (108) is disposed on the AlN space layer (107); A GaN contact layer (109) is disposed on the AlGaN barrier layer (108); A metal pattern layer, comprising an ohmic contact metal layer (110) and a Schottky contact metal layer (111) which are arranged at intervals on the GaN contact layer (109) and partially expose a surface of the GaN contact layer (109); A pad metal layer, comprising a first pad metal layer (112) and a second pad metal layer (113), wherein the first pad metal layer (112) contacts the surface of the ohmic contact metal layer (110), and the second pad metal layer (113) contacts the surface of the Schottky contact metal layer (111); The insulating layer (114) at least covers the metal pattern layer, the exposed surface of the GaN contact layer (109) and a portion of the surface of the pad metal layer.

2. A voltage zener diode structure according to claim 1, characterized in that: The size of a single pattern of the voltage-stabilizing diode structure is 60 μm to 1500 μm in length and 65 μm to 1500 μm in width.

3. A voltage zener diode structure according to claim 1, characterized in that: The ohmic contact metal layer (110) comprises Ti / Al / Ti / Au or Ti / Al / Ni / Au arranged in sequence from bottom to top.

4. A voltage zener diode structure according to claim 1, characterized in that: The Schottky contact metal layer (111) adopts a structure of stacking multiple layers of high stress metals Ni, Pt, Cr, Rh, Ti or alloys composed of the above metals.

5. A voltage zener diode structure according to claim 1, characterized in that: The distance between the ohmic contact metal layer (110) and the Schottky contact metal layer (111) is 3 um to 100 um.

6. A voltage zener diode structure according to claim 1, characterized in that: The substrate (101) is a sapphire or GaN-based substrate (101).

7. A packaging structure, characterized in that: It comprises at least one LED chip (200) and at least one Zener diode structure (100) according to any one of claims 1 to 5, wherein the LED chip (200) and the Zener diode structure (100) are packaged in SMD or COB.

8. The packaging structure according to claim 6, characterized in that: The quantity ratio of the voltage stabilizing diode structure (100) to the LED chip (200) is 1:1-1:

50.

9. A method for manufacturing a voltage stabilizing diode structure, characterized in that: The steps include: S1. Providing a sapphire or GaN-based substrate (101), growing a stacked epitaxial structure on the substrate (101), comprising an AlN nucleation layer (102), a GaN buffer layer (103), a U-GaN layer (104), a U-GaN repair layer (105), a U-GaN channel layer (106), an AlN space layer (107), an AlGaN barrier layer (108), and a GaN contact layer (109) grown in sequence; obtaining an epitaxial wafer; S2, cleaning the surface of the epitaxial wafer to remove pollutants including organic matter and particles; S3, coating the ohmic contact region on the GaN contact layer (109) with photoresist; S4, forming a pattern required for the ohmic contact metal layer (110) on the photoresist by ultraviolet exposure and development; S5, developing the photoresist to remove the unexposed portion of the photoresist, thereby obtaining a pattern window required for ohmic contact metal deposition on the surface of the epitaxial wafer; S6, vapor-depositing an ohmic contact metal layer (110) in the formed pattern window, including Ti / Al / Ti / Au or Ti / Al / Ni / Au from bottom to top, to achieve low-resistance contact with the GaN contact layer (109); S7, removing excess metal and photoresist by a stripping process, retaining the ohmic contact metal pattern, and forming an ohmic contact metal layer (110); S8, performing high temperature alloy treatment on the ohmic contact metal layer (110) to form alloy contact and reduce contact resistance; S9, coating the Schottky contact region on the GaN contact layer (109) with photoresist again; S10, exposing and developing the Schottky area to define a Schottky metal pattern window, and obtaining a window of the Schottky metal deposition position after development; S11, depositing a plurality of Schottky metal layers stacked with high stress to form a Schottky contact; S12, stripping off excess metal and photoresist to obtain a desired Schottky contact metal pattern, thereby forming a Schottky contact metal layer (111); S13, coating the pad regions on the surfaces of the ohmic contact metal layer (110) and the Schottky contact metal layer (111) with photoresist to prepare for subsequent pad metal deposition; S14, exposing and developing the pad area to form a pad metal pattern window; S15, after development, a window area of ​​the pad metal deposition is clearly defined; S16, evaporating a pad metal layer in the window area; S17, removing excess metal and photoresist, retaining the required pad metal pattern, and forming a first pad metal layer (112) in contact with the surface of the ohmic contact metal layer (110), and a second pad metal layer (113) in contact with the surface of the Schottky contact metal layer (111); S18, depositing an insulating layer 114 to cover the device surface and play an insulating and protective role; S19, coating a photoresist on the surface of the insulating layer 114; S20, exposing and developing the photoresist on the insulating layer 114 to form an insulating layer etching window; S21, after development, an area to be etched is obtained in the insulating layer 114; S22, removing the photoresist used for patterning the insulating layer, so that the insulating layer has a desired opening and pattern structure; S23, perform thick film test, measure film thickness, use probe to perform electrical test on the device, check the characteristics of ohmic and Schottky contacts and the voltage regulation performance of the device; S24, performing thinning and grinding on the back side of the device to reduce the thickness of the substrate (101); S25, marking the device surface with a laser, cutting the wafer, and obtaining a chip; S26. Carry out final appearance inspection, thin film testing, optical inspection and data archiving of the chips to ensure that the quality meets the requirements; S27. Classify and sort the chips according to the test results for subsequent packaging.

10. The method for manufacturing a voltage zener diode structure according to claim 9, characterized in that: A stacked epitaxial structure is grown on the substrate (101), comprising: Generating a first AlN layer (102a) on the substrate (101) by physical vapor deposition; Further growing a second AlN layer (102b) on the first AlN layer (102a) by using organic metal chemical vapor deposition; forming a GaN buffer layer (103) on the second AlN layer (102b) by low-temperature epitaxial growth; Growing a layer of undoped GaN material on the GaN buffer layer (103) to form a U-GaN layer (104); Growing a U-GaN repair layer (105) on the U-GaN layer (104) to repair lattice defects generated during the growth process at the previous stage; Growing a U-GaN channel layer (106) on the U-GaN repair layer (105); Growing an AlN space layer (107) on the U-GaN channel layer (106); Growing an AlGaN barrier layer (108) on the AlN space layer (107); A GaN contact layer (109) is grown on the AlGaN barrier layer (108).

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