ESD structure, ESD device and ESD chip

Abstract

The invention provides an ESD (Electro-Static Discharge) structure which comprises a substrate, a buried layer and an epitaxy which are stacked in sequence, a first well region is located in the epitaxy, a second well region extends from the epitaxy to be in contact with the buried layer, M third well regions which are separated from one another are located in the second well region, a first isolation structure is bridged on the first well region and the second well region, and a second isolation structure is bridged on the second well region. The first active region is located on a part of the first well region and a part of each third well region, the second active region is located on the second well region which is not covered by the first active region and the first isolation structure, and the first active region and the second active region on the second well region are isolated by the second isolation structure. High breakdown voltage and high ESD protection capacity can be achieved under the small area, the maintaining voltage is high, the voltage application range is wide, the hysteresis effect is greatly reduced, and the latch-up risk can be avoided.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an ESD structure, an ESD device and an ESD chip. Background Art

[0002] BCD (Bipolar-CMOS-DMOS) technology is a monolithic integration process technology that can produce Bipolar, CMOS and DMOS structures on the same chip. Among them, the BCD process with a voltage specification of 45V to 100V is widely used in DC-DC power supplies and motor drive products. These products often work in environments with high current, high voltage and strong electromagnetic interference. Therefore, it is usually necessary to design an ESD (Electro-Static discharge) structure in the chip for ESD protection.

[0003] Conventional ESD structures can be diodes, thyristor rectifiers, bipolar transistors and other structures, but these ESD structures either have large resistance and relatively poor ESD capabilities, or have large hysteresis and are prone to latch-up effects. Therefore, high-voltage power tubes (such as LDMOS) are often used to achieve ESD protection by using their own high current and high-voltage resistance characteristics as both power drive tubes and ESD structures. However, in practical applications, the ESD capability of high-voltage power tubes is still insufficient. Under the action of high-voltage ESD pulses, once the power tube triggers hysteresis, latch-up effects are still prone to occur, which can easily cause device damage and have weak robustness. In recent years, an ESD structure combining thyristor rectifiers and high-voltage power tubes has been proposed. Although the robustness of this ESD structure has been improved, it still has the characteristics of high trigger voltage and low holding voltage, and the latch-up risk is relatively high. At the same time, multiple structures with low breakdown voltage and high ESD capability are often connected in series to achieve a higher breakdown voltage and enhance the ESD capability, but this will also cause the ESD structure to occupy too large an area. Summary of the invention

[0004] The object of the present invention is to provide an ESD structure, an ESD device and an ESD chip to solve the problems of weak ESD capability, low breakdown voltage and high latch-up risk of the existing ESD structure.

[0005] In order to achieve the above object, the present invention provides an ESD structure, comprising:

[0006] a substrate of a first doping type;

[0007] A buried layer of a second doping type, located on the substrate;

[0008] an epitaxial layer of a first doping type, located on the buried layer;

[0009] a first well region of a first doping type, located in the epitaxy and extending from the upper surface of the epitaxy into the epitaxy;

[0010] A second well region of a second doping type, located in the epitaxy, extending from the upper surface of the epitaxy to the lower surface of the epitaxy and contacting the buried layer;

[0011] The second well region and the first well region are arranged in sequence along the direction from the first side to the second side of the ESD structure, and the first side and the second side of the ESD structure are opposite to and perpendicular to the substrate;

[0012] M third well regions of the first doping type are located in the second well region and extend from the upper surface of the epitaxial extension into the second well region, the M third well regions are separated from each other, and M is a positive integer greater than or equal to 1;

[0013] A first isolation structure straddling the first well region and the second well region;

[0014] A first active region of a first doping type, located on a portion of the first well region and a portion of each of the third well regions;

[0015] A second active region of a second doping type, located on the second well region not covered by the first active region and the first isolation structure;

[0016] The first active region and the second active region on the second well region are isolated by a second isolation structure.

[0017] Optionally, M is 1, there is one third well region, and the epitaxy includes the second active region on the second well region, the second isolation structure, the first active region on the third well region, the second isolation structure, the second active region on the second well region, the first isolation structure, and the first active region on the first well region, which are arranged in sequence.

[0018] Optionally, M is 2, there are two third well regions, and the epitaxy includes the second active region on the second well region, the second isolation structure, the first active region on the third well region, the second isolation structure, the second active region on the second well region, the second isolation structure, the first active region on the second well region, the second isolation structure, the second active region on the second well region, the first isolation structure, and the first active region on the first well region, which are arranged in sequence.

[0019] Optionally, also include:

[0020] A polycrystalline field plate, wherein the first isolation structure comprises a first end and a second end, the first end of the first isolation structure is located on the first well region, the second end of the first isolation structure is located on the second well region, the polycrystalline field plate is located on the first isolation structure and close to the first end of the first isolation structure, and a partial projection of the polycrystalline field plate is located at an edge of the first well region;

[0021] A dielectric layer covers the first active region, the first isolation structure, the polycrystalline field plate, the second isolation structure and the second active region, and a hole is opened in the dielectric layer on the first active region, the polycrystalline field plate and the second active region;

[0022] a first metal layer, located on the dielectric layer and filling the openings of the dielectric layer on the first active region on the first well region and the dielectric layer on the polycrystalline field plate, wherein the first metal layer connects the first active region on the first well region and the polycrystalline field plate;

[0023] The second metal layer is located on the dielectric layer and fills the openings of the dielectric layer on the first active area of ​​the third well region and the dielectric layer on the second active area of ​​the second well region. The second metal layer connects the first active area of ​​the third well region and the second active area of ​​the second well region.

[0024] Optionally, the second well region and the epitaxy are equivalent to a diode, the second well region serves as the cathode of the diode, and the epitaxy serves as the anode of the diode; the third well region, the second well region and the epitaxy are equivalent to a first parasitic transistor, the third well region serves as the emitter of the first parasitic transistor, the second well region serves as the base of the first parasitic transistor, the epitaxy serves as the collector of the first parasitic transistor, and the second well region serves as a first equivalent resistor; the third well region, the second well region, the buried layer and the epitaxy are equivalent to a second parasitic transistor, the third well region serves as the emitter of the second parasitic transistor, the second well region and the buried layer serve as the base of the second parasitic transistor, the epitaxy serves as the collector of the second parasitic transistor, and the second well region and the buried layer serve as a second equivalent resistor.

[0025] Optionally, the second metal layer is connected to a high potential, the first metal layer is connected to a low potential, the diode is reversely broken down to discharge current, and the potential at the bottom of the third well region decreases accordingly, causing the first parasitic transistor and the second parasitic transistor to turn on and discharge current.

[0026] Optionally, the first doping type is P type, and the second doping type is N type.

[0027] Optionally, the doping concentration of the first well region is 1e15cm -3 ~1e17cm-3 The doping concentration of the second well region is 1e14cm -3 ~1e16cm -3 The doping concentration of the buried layer is 1e16cm -3 ~1e18cm -3 .

[0028] Optionally, the breakdown voltage of the ESD structure is increased by reducing the doping concentration of at least one of the first well region, the second well region or the buried layer; or, the breakdown voltage of the ESD structure is reduced by increasing the doping concentration of at least one of the first well region, the second well region or the buried layer.

[0029] Optionally, a first lateral gap is provided between the first well region and the second well region, and a width of the first lateral gap is 0 to 10 micrometers.

[0030] Optionally, the breakdown voltage of the ESD structure is increased by increasing the first lateral gap; or, the breakdown voltage of the ESD structure is reduced by reducing the first lateral gap.

[0031] Optionally, the first well region contacts a side wall of the second well region; or, at least a portion of the first well region is located in the second well region; or, the first well region and the second well region are separated from each other.

[0032] Optionally, a distance between an edge of the polycrystalline field plate and the first end of the first isolation structure is 1 micrometer to 2 micrometers, and a lateral width of the polycrystalline field plate is 2 micrometers to 4 micrometers.

[0033] Optionally, the thickness of the first well region is equal to or less than the thickness of the second well region.

[0034] The present invention provides an ESD device, comprising the ESD structure.

[0035] The present invention provides an ESD chip, comprising the ESD structure.

[0036] Optionally, the ESD structure is connected between two functional pins of the ESD chip that require electrostatic protection, thereby achieving electrostatic protection for the two functional pins.

[0037] Optionally, the ESD chip is a high-voltage gate driver chip, the ESD structure is a bootstrap diode in the high-voltage gate driver chip, the ESD structure has the function of a bootstrap diode, and realizes electrostatic protection between two functional pins that require electrostatic protection.

[0038] The present invention provides an ESD structure, an ESD device and an ESD chip, comprising a substrate, a buried layer, an epitaxial layer, a first well region, a second well region, a third well region, a first active region and a second active region, wherein the substrate, the buried layer and the epitaxial layer are stacked in sequence, the second well region and the third well region are located in the epitaxial layer, a first isolation structure is connected across the first well region and the second well region, the first active region is located on a portion of the first well region and a portion of each of the third well regions, the second active region is located on the second well region not covered by the first active region and the first isolation structure, and the first active region and the second active region on the second well region are isolated by a second isolation structure. The present invention can achieve a higher breakdown voltage and a stronger ESD protection capability in a smaller area, and has a high maintenance voltage, a wide voltage application range, a greatly reduced hysteresis effect, and can avoid latch-up risks. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 A schematic diagram of the structure of the ESD structure provided in the first embodiment of the present invention;

[0040] Figure 2 A schematic diagram of a current discharge path of an ESD structure provided in Embodiment 1 of the present invention during reverse breakdown;

[0041] Figure 3 A schematic diagram of a parasitic transistor of an ESD structure provided in Embodiment 1 of the present invention;

[0042] Figure 4 The IV curve of the ESD structure provided in the first embodiment of the present invention under the TLP test;

[0043] Figure 5 A schematic diagram of the structure of the ESD structure provided in the second embodiment of the present invention;

[0044] Figure 6 A schematic diagram of an ESD chip provided in Embodiment 3 of the present invention;

[0045] Figure 7 A schematic diagram of an ESD chip provided in Embodiment 4 of the present invention;

[0046] Figure 8 Schematic diagram of the ESD structure provided in the fifth embodiment of the present invention

[0047] Wherein, the accompanying drawings are marked as follows:

[0048] 100-substrate; 200-buried layer; 300-epitaxial; 301-first well region; 302-second well region; 303, 303A, 303B-third well region; 401-first active region on the first well region; 402B, 402D-first active region on the second well region; 402A, 402C, 402E-second active region on the second well region; 500-dielectric layer; 601-first isolation structure; 602-second isolation structure; 700-polycrystalline field plate; 801-first metal layer; 802-second metal layer; D-diode; Q1-first parasitic transistor; Q2-second parasitic transistor. DETAILED DESCRIPTION

[0049] The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0050] Embodiment 1

[0051] Figure 1 The schematic diagram of the ESD structure provided in this embodiment. Figure 1 As shown, the ESD structure includes a substrate 100, a buried layer 200 and an epitaxial layer 300. The substrate 100, the buried layer 200 and the epitaxial layer 300 are stacked in sequence from bottom to top. The substrate 100 and the epitaxial layer 300 have a first doping type, and the buried layer 200 has a second doping type. In this embodiment, the first doping type is P type, and the second doping type is N type. The ESD structure has a first side and a second side, the first side is opposite to the second side, and the first side and the second side are perpendicular to the substrate 100.

[0052] The ESD structure further includes a first well region 301, a second well region 302 and M third well regions 303, wherein M is a positive integer greater than or equal to 1, and the M third well regions 303 are separated from each other. The first well region 301 and the second well region 302 are both located in the epitaxy 300, the first well region 301 extends from the upper surface of the epitaxy 300 to the inside of the substrate 100, the second well region 302 extends from the upper surface of the epitaxy 300 to the lower surface of the substrate 100 and contacts the buried layer 200, and the third well region 303 is located in the second well region 302 and extends from the upper surface of the epitaxy 300 to the inside of the second well region 302. In this embodiment, the first well region 301 and the third well region 303 have the first doping type, and the second well region 302 has the second doping type.

[0053] In this embodiment, the first well region 301 is a low-voltage well whose bottom does not contact the buried layer 200, while the second well region 302 is a high-voltage well whose bottom contacts the buried layer 200. The thickness of the first well region 301 is equal to or less than the thickness of the second well region 302.

[0054] Please continue reading Figure 1 In this embodiment, the first well region 301 and the second well region 302 are not in contact with each other, but are separated from each other, and there is a first lateral gap between the first well region 301 and the second well region 302. Optionally, the width of the first lateral gap may be 0 to 10 microns.

[0055] In some embodiments, the first well region 301 and the second well region 302 may also be in contact with or even overlap with each other. For example, the sidewalls of the first well region 301 and the second well region 302 may just be in contact with each other, or at least a portion of the first well region 301 may be located in the second well region 302. That is, the first well region 301 and the second well region 302 are separated from each other, intersected, or overlapped in the epitaxial region 300.

[0056] Please continue reading Figure 1 In this embodiment, the ESD structure further includes a first isolation structure 601. The first isolation structure 601 is connected across the first well region 301 and the second well region 302.

[0057] The ESD structure further includes first active regions 401 and 402B, wherein the first active region 401 is located above a portion of the first well region 301 and the first active region 402B is located above a portion of each third well region 303. The first active regions 401 and 402B have the first doping type.

[0058] The ESD structure further includes second active regions 402A and 402C, which are located above the second well region 302 not covered by the first active regions 401 and 402B and the first isolation structure 601. The second active regions 402A and 402C have the second doping type. The first active region 402B and the second active regions 402A and 402C on the second well region 302 are isolated by the second isolation structure 602.

[0059] In this embodiment, Figure 1In the ESD structure shown, M is 1, there is one third well region 303 of the first doping type, and on the epitaxial 300, the second active region 402A on the second well region 302, the second isolation structure 602, the first active region 402B on the third well region 303, the second isolation structure 602, the second active region 402C on the second well region 302, the first isolation structure 601, and the first active region 401 on the first well region 301 are arranged in sequence.

[0060] It can be understood that the first active region 402B in the second well region 302 is located above the corresponding third well region 303. Therefore, the number of the third well regions 303 is the same as the number of the first active regions 402B in the second well region 302. For example, the number of the first active regions 402B in the second well region 302 in this embodiment is 1.

[0061] Optionally, the first isolation structure 601 and the second isolation structure 602 may be trench isolation structures or field oxide layers.

[0062] Furthermore, in this embodiment, the first isolation structure 601 includes a first end and a second end, the first end of the first isolation structure 601 is located on the first well region 301, the second end of the first isolation structure 601 is located on the second well region 302, the polycrystalline field plate 700 is located on the first isolation structure 601 and close to the first end of the first isolation structure 601, and a partial projection of the polycrystalline field plate 700 is located at the edge of the first well region 301.

[0063] The distance between the edge of the polycrystalline field plate 700 and the first end of the first isolation structure 601 is 1 micron to 2 microns. The lateral width of the polycrystalline field plate 700 may be 2 microns to 4 microns. The function of the polycrystalline field plate 700 will be described below.

[0064] Optionally, the material of the polycrystalline field plate 700 may generally be polycrystalline silicon, but should not be limited thereto.

[0065] In some embodiments, the polycrystalline field plate 700 may also be omitted.

[0066] Please continue reading Figure 1The ESD structure further includes a dielectric layer 500, the dielectric layer 500 covers the first active regions 401, 402B, the first isolation structure 601, the polycrystalline field plate 700, the second isolation structure 602, the second active regions 402A, 402C, and holes are opened on the dielectric layer 500 on the first active regions 401, 402B, the polycrystalline field plate 700, and the second active regions 402A, 402C. The dielectric layer 500 may be a single layer or a multilayer film, and its material may be, for example, one of silicon oxide, silicon nitride, silicon oxynitride, and NDC (Nitrogen doped Silicon Carbide, nitrogen-doped silicon carbide) or a combination thereof, and may also include borophosphosilicate glass (BPSG), undoped silicate glass (USG), spin-on glass (SOG), or tetraethyl orthosilicate (TEOS), etc.

[0067] Furthermore, the dielectric layer 500 has a first metal layer 801 and a second metal layer 802 .

[0068] The first metal layer 801 is located on the dielectric layer 500 and fills the openings of the dielectric layer 500 on the first active region 401 on the first well region 301 and the dielectric layer 500 on the polycrystalline field plate 700. The first metal layer 801 connects the first active region 401 on the first well region 301 and the polycrystalline field plate 700.

[0069] The second metal layer 802 is located on the dielectric layer 500 and fills the openings of the dielectric layer 500 on the first active area 402B of the third well region 303 and the second active areas 402A and 402C of the second well region 302. The second metal layer 802 connects the first active area 402B of the third well region 303 and the second active area of ​​the second well region 302.

[0070] The first metal layer 801 is used as an anode to apply the same voltage to the first active area 401 of the first well area 301 and the polycrystalline field plate 700, and the second metal layer 802 is used as a cathode to apply the same voltage to the second active areas 402A, 402C and the first active area 402B of the second well area 302.

[0071] Furthermore, the ESD structure can be generally prepared in an ESD chip by a BCD process to provide ESD protection for the ESD chip. The operating voltage of the ESD chip can be 45V to 120V, but should not be limited thereto.

[0072] Figure 2 The schematic diagram of the current discharge path of the ESD structure provided in this embodiment during reverse breakdown. Figure 2As shown, when the second metal layer 802 is connected to a high potential and the first metal layer 801 is connected to a low potential, electrons can enter the second well region 302 through the epitaxy 300 or the buried layer 200, and the diode is reversely broken down to discharge current.

[0073] Figure 3 Schematic diagram of the parasitic transistor of the ESD structure provided in this embodiment. Figure 3 As shown, the second well region 302 and the epitaxy 300 can be equivalent to a diode D, the second well region 302 serves as the cathode of the diode D, and the epitaxy 300 serves as the anode of the diode D. The third well region 303, the second well region 302 and the epitaxy 300 can be equivalent to a first parasitic transistor Q1, the third well region 303 serves as the emitter of the first parasitic transistor Q1, the second well region 302 serves as the base of the first parasitic transistor Q1, the epitaxy 300 serves as the collector of the first parasitic transistor Q1, and the second well region 302 serves as a first equivalent resistor R1. The third well region 303, the second well region 302, the buried layer 200 and the epitaxy 300 can be equivalent to a second parasitic transistor Q2, the third well region 303 serves as the emitter of the second parasitic transistor Q2, the second well region 302 and the buried layer 200 serve as the base of the second parasitic transistor Q2, the epitaxy 300 serves as the collector of the second parasitic transistor Q2, and the second well region 302 and the buried layer 200 serve as a second equivalent resistor R2.

[0074] Electrons can enter the second well region 302 through the epitaxy 300 or the buried layer 200. Since the second active region 402C is closer to the first well region 301, the second active region 402C is more likely to absorb electrons, forming a current discharge path. At this time, the diode D is reversely broken down to discharge current. Another part of the electrons will move in the second well region 302 until they reach the second active region 402A farther from the first well region 301. Since the second well region 302 itself has a certain resistance, when the electrons pass under the third well region 303, the potential of the area of ​​the second well region 302 located under the third well region 303 will be reduced. When the potential difference between the third well region 303 and the area of ​​the second well region 302 located under the third well region 303 is greater than the turn-on voltage of the first parasitic transistor Q1, the first parasitic transistor Q1 is turned on to form a current discharge path. At this time, the current can be discharged through the first parasitic transistor Q1. At the same time, since the second well region 302 and the buried layer 200 are basically at the same potential, as the current increases, the second parasitic transistor Q2 will also turn on to form a current discharge path, and the current can be discharged through the second parasitic transistor Q2. At this time, the buried layer 200 can avoid the leakage of the parasitic transistor formed between the epitaxy 300, the first well region 301 and the substrate 100, and realize the isolation of the substrate 100 to reduce the leakage of the substrate 100. The end of the polycrystalline field plate 700 close to the first well region 301 will have an electric field concentration phenomenon, thereby alleviating the electric field concentration phenomenon at the first end of the first isolation structure 601, thereby suppressing the surface electric field of the first well region 301.

[0075] It can be seen that in this embodiment, the diode D1 is first used for current discharge, and then the first parasitic transistor Q1 and the second parasitic transistor Q2 are used to assist in current discharge, thereby achieving ESD protection. In addition, since the discharge capacity of the transistor is much greater than the discharge capacity of the diode, the ESD structure in this embodiment has a strong charge discharge capacity and high charge discharge efficiency. A single structure can provide a strong ESD capability without using multiple ESD structures in series, which can greatly reduce the chip area.

[0076] It is understandable that the ESD structure has three important parameters: trigger voltage, sustain voltage and secondary breakdown voltage. The sustain voltage of the ESD structure needs to be greater than the internal working voltage of the chip to discharge the charge and protect the internal circuits of the chip. Therefore, the sustain voltage and the trigger voltage basically determine the voltage application range of the ESD structure, and the larger the sustain voltage, the wider the voltage application range of the ESD structure. Figure 4The IV curve of the ESD structure provided in this embodiment under the TLP (Transmission Line Pulse) test. Figure 4 As shown, the sustaining point and triggering point of the ESD structure in this embodiment are basically coincident, the sustaining voltage and the triggering voltage are both around 112V, and the secondary breakdown will not occur until 128V, and the ESD capability under the HBMI model reaches more than 4.5KV. Figure 4 It can also be seen that the IV curve of the ESD structure in this embodiment is similar to the IV curve of a diode, indicating that the holding voltage is very close to the trigger voltage, the hysteresis effect is greatly reduced, and it can be used for ESD protection in high-voltage occasions. At the same time, the limit operating voltage under transient conditions is also very high.

[0077] It can be seen that the ESD structure in this embodiment also has the advantages of high breakdown voltage and high holding voltage, the application voltage range is also very wide, and the hysteresis effect is greatly reduced, which can avoid the risk of latch-up.

[0078] It should be noted that, due to the movement of electrons, the potential of the area of ​​the second well region 302 located below the third well region 303 is reduced. The smaller the doping concentration of the second well region 302, the larger the lateral distance between the two second active regions 402A and 402C, the greater the amplitude of the potential reduction of the area of ​​the second well region 302 located below the third well region 303, and the first parasitic transistor Q1 and the second parasitic transistor Q2 can be turned on faster, thereby improving the dynamic response capability of the ESD structure.

[0079] Furthermore, this embodiment controls the breakdown point of the ESD structure to be located in the epitaxial 300 below the first well region 301 by reasonably designing the lateral width of the first lateral gap, the doping concentration of the first well region 301, the second well region 302 and the buried layer 200, and the breakdown point appears at the in-body junction to avoid premature breakdown between the first well region 301 and the second well region 302, thereby achieving a breakdown voltage exceeding 100V (for example, 100V to 200V). At the same time, the breakdown voltage of the ESD structure can also be adjusted by adjusting the lateral width of the first lateral gap, the doping concentration of the first well region 301, the second well region 302 and the buried layer 200, so as to achieve different breakdown voltage ranges.

[0080] Specifically, the breakdown voltage of the ESD structure is positively correlated with the width of the first lateral gap, but negatively correlated with the doping concentration of the first well region 301, the doping concentration of the second well region 302, or the doping concentration of the buried layer 200. Increasing the lateral width of the first lateral gap, reducing the doping concentration of the first well region 301, reducing the doping concentration of the second well region 302, or reducing the doping concentration of the buried layer 200 can increase the breakdown voltage of the ESD structure; conversely, reducing the lateral width of the first lateral gap (even allowing the first well region 301 to contact or at least partially overlap with the second well region 302), increasing the doping concentration of the first well region 301, increasing the doping concentration of the second well region 302, or increasing the doping concentration of the buried layer 200 can reduce the breakdown voltage of the ESD structure. That is, the doping concentration of at least one of the first well region 301, the second well region 302 or the buried layer 200 is reduced to increase the breakdown voltage of the ESD structure; or, the doping concentration of at least one of the first well region 301, the second well region 302 or the buried layer 200 is increased to reduce the breakdown voltage of the ESD structure; the first lateral gap is increased to increase the breakdown voltage of the ESD structure; or, the first lateral gap is reduced to reduce the breakdown voltage of the ESD structure.

[0081] For example, the doping concentration of the buried layer 200 may be 1e16 cm -3 ~1e18cm -3 , the doping concentration of the second well region 302 may be 1e14cm -3 ~1e16cm -3 , the doping concentration of the first well region 301 may be 1e15cm -3 ~1e17cm -3 , but it should not be limited to this.

[0082] Correspondingly, this embodiment also provides an ESD device, including the ESD structure.

[0083] Correspondingly, this embodiment also provides an ESD chip, including the ESD structure.

[0084] Embodiment 2

[0085] Figure 5 The schematic diagram of the ESD structure provided in this embodiment. Figure 5 As shown, the difference from the first embodiment is that in this embodiment, the first well region 301 is also a high-voltage well, and its bottom contacts the buried layer 200. The thickness of the first well region 301 is equal to the thickness of the second well region 302.

[0086] Since there is always a limit to the amplitude of increasing the breakdown voltage of the ESD structure by increasing the lateral width of the first lateral gap, reducing the doping concentration of the first well region 301, reducing the doping concentration of the second well region 302, or reducing the doping concentration of the buried layer 200 (it is impossible to infinitely increase the lateral width of the first lateral gap, reduce the doping concentration of the first well region 301, reduce the doping concentration of the second well region 302, or reduce the doping concentration of the buried layer 200), this embodiment sets the first well region 301 as a high-voltage well, so that the breakdown point of the ESD structure can be located at the junction of the first well region 301 and the buried layer 200, thereby increasing the breakdown voltage.

[0087] In this embodiment, the breakdown voltage between the first well region 301 and the buried layer 200 can be further increased by reducing the doping concentration of the first well region 301, so that the ESD structure can be applied to application scenarios with a higher voltage range.

[0088] For example, the doping concentration of the buried layer 200 may be 1e16 cm -3 ~1e18cm -3 , the doping concentration of the second well region 302 may be 1e14cm -3 ~1e16cm -3 , the doping concentration of the first well region 301 may be 1e15cm -3 ~1e17cm -3 , but it should not be limited to this.

[0089] Embodiment 3

[0090] Figure 6 Schematic diagram of the ESD chip provided in this embodiment. Figure 6 As shown, in this embodiment, the ESD structure can be prepared in an ESD chip. In this embodiment, the ESD chip is a high-voltage gate driver chip, and the ESD structure is a bootstrap diode (DM) in the high-voltage gate driver chip. The ESD structure not only has the function of a bootstrap diode, but also can realize electrostatic protection between two functional pins that require electrostatic protection (such as a floating power pin and a floating ground pin).

[0091] Specifically, the high-voltage gate driver chip includes a high-side driver circuit, a low-side driver circuit and a level shift circuit. The low-side driver circuit receives the high-side control signal and the low-side control signal through the high-side control signal pin HIN and the low-side control signal LIN respectively, and performs signal processing on the high-side control signal and the low-side control signal; the low-side driver circuit also generates a low-side driver signal according to the low-side control signal, and the low-side driver signal is output through the low-side driver signal pin PWML to drive the low-side power tube; the level shift circuit includes at least one LDMOS structure, which transmits the signal of the low-side driver circuit to the high-side driver circuit. The high-side driver circuit generates a high-side driver signal according to the signal output by the level shift circuit, and the high-side driver signal is output through the high-side driver signal pin PWMH to drive the high-side power tube, and the function of the bootstrap circuit DM is used to realize that the high-side power tube is in a long-term open state.

[0092] The high-voltage gate driver chip has a VB pin, a VS pin, a VCC pin and a GND pin. The VCC pin is the power supply voltage pin of the entire high-voltage gate driver chip. The VB pin and the VS pin are the floating power pin and the floating ground pin of the high-side drive circuit, respectively. The VS pin is connected to the VB pin through an off-chip capacitor and an internal circuit. The ESD structure (DM) is connected between the VB pin and the VCC pin. The VCC pin is connected to the GND pin through a clamping circuit.

[0093] Furthermore, the breakdown voltage of the ESD structure (DM) needs to be smaller than the breakdown voltage of the LDMOS structure but larger than the operating voltage of the LDMOS structure. When the VB pin or the VS pin receives an ESD pulse, since the breakdown voltage of the ESD structure (DM) is the lowest, most of the electrostatic charges will pass through the ESD structure (DM) and then through the VCC pin and the clamping circuit to the GND pin to complete the electrostatic charge discharge. Only a small part of the electrostatic charge will choose to be released through the LDMOS structure to the GND pin. Therefore, the ESD structure (DM) not only realizes the function of the bootstrap diode, but also can protect the LDMOS structure and other structures in the chip, greatly improving the ESD capability of the chip.

[0094] Embodiment 4

[0095] Figure 7 Schematic diagram of the ESD chip provided in this embodiment. Figure 7 As shown, in this embodiment, the ESD structure (DM) can be prepared in the ESD chip, and one ESD structure (DM) is connected between two functional pins that need electrostatic protection to achieve electrostatic protection of the functional pins. When the functional pin receives an electrostatic pulse, the ESD structure (DM) can release the electrostatic charge to the ground, thereby protecting the functional modules inside the chip.

[0096] Figure 7 The internal structure of the chip is simplified, and only the BST pin, VIN pin, SW pin and GND pin are shown as examples. One ESD structure DM is connected between the GND pin and the BST pin, and between the GND pin and the VIN pin. Since the SW pin is connected to the BST pin through a clamping circuit, the SW pin and the BST pin share one ESD structure DM, and it can be regarded that one ESD structure DM is also connected between the SW pin and the GND pin.

[0097] It can be understood that when the BST pin, the VIN pin or the SW pin receives an ESD pulse, the electrostatic charge is discharged to the GND pin through the ESD structure DM to achieve electrostatic protection.

[0098] Embodiment 5

[0099] Figure 8 The schematic diagram of the ESD structure provided in this embodiment. Figure 8 As shown, the difference from the first embodiment is that in this embodiment, the M is 2, there are two third well regions of the first doping type, namely the third well regions 303A and 303B, the first active region on the third well region also has two, namely the first active regions 402B and 402D, and the second active region has three, namely the second active regions 402A, 402C and 402E. The epitaxial 300 includes the second active region 402A on the second well region 302, the second isolation structure 602, the first active region 402B on the third well region 303A, the second isolation structure 602, the second active region 402C on the second well region 302, the second isolation structure 602, the first active region 402D on the second well region 302, the second isolation structure 602, the second active region 402E on the second well region 302, the first isolation structure 601, and the first active region 401 on the first well region 301.

[0100] In summary, the embodiments of the present invention provide an ESD structure, an ESD device and an ESD structure, including a substrate, a buried layer, an epitaxial layer, a first well region, a second well region, a third well region, a first active region and a second active region, wherein the substrate, the buried layer and the epitaxial layer are stacked in sequence, the second well region and the third well region are located in the epitaxial layer, a first isolation structure is connected across the first well region and the second well region, the first active region is located on a portion of the first well region and a portion of each of the third well regions, the second active region is located on the second well region not covered by the first active region and the first isolation structure, and the first active region and the second active region on the second well region are isolated by a second isolation structure. The present invention can achieve a higher breakdown voltage and a stronger ESD protection capability in a smaller area, and has a high maintenance voltage, a wide voltage application range, a greatly reduced hysteresis effect, and can avoid latch-up risks.

[0101] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0102] It should also be noted that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

[0103] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are merely used to distinguish between the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0104] It should also be recognized that the terms described herein are only used to describe specific embodiments and are not intended to limit the scope of the invention. It should be noted that the singular forms "a" and "an" used herein and in the appended claims include plural references unless the context clearly indicates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps and secondary devices. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or", rather than a logical "exclusive or", unless the context clearly indicates otherwise. In addition, the implementation of the method and / or device in the embodiments of the present invention may include performing the selected task manually, automatically, or in combination.

Claims

1. An ESD structure, characterized in that: include: a substrate of a first doping type; A buried layer of a second doping type, located on the substrate; an epitaxial layer of a first doping type, located on the buried layer; a first well region of a first doping type, located in the epitaxy and extending from the upper surface of the epitaxy into the epitaxy; A second well region of a second doping type, located in the epitaxy, extending from the upper surface of the epitaxy to the lower surface of the epitaxy and contacting the buried layer; The second well region and the first well region are arranged in sequence along the direction from the first side to the second side of the ESD structure, and the first side and the second side of the ESD structure are opposite to and perpendicular to the substrate; M third well regions of the first doping type are located in the second well region and extend from the upper surface of the epitaxial extension into the second well region, the M third well regions are separated from each other, and M is a positive integer greater than or equal to 1; A first isolation structure straddling the first well region and the second well region; A first active region of a first doping type, located on a portion of the first well region and a portion of each of the third well regions; A second active region of a second doping type, located on the second well region not covered by the first active region and the first isolation structure; The first active region and the second active region on the second well region are isolated by a second isolation structure.

2. The ESD structure according to claim 1, wherein: The M is 1, the third well region is one, and the epitaxy includes the second active region on the second well region, the second isolation structure, the first active region on the third well region, the second isolation structure, the second active region on the second well region, the first isolation structure, and the first active region on the first well region, which are arranged in sequence.

3. The ESD structure according to claim 1, wherein: The M is 2, there are two third well regions, and the epitaxy includes the second active region on the second well region, the second isolation structure, the first active region on the third well region, the second isolation structure, the second active region on the second well region, the second isolation structure, the first active region on the second well region, the second isolation structure, the second active region on the second well region, the first isolation structure, and the first active region on the first well region, which are arranged in sequence.

4. The ESD structure according to any one of claims 1 to 3, wherein: Also includes: A polycrystalline field plate, wherein the first isolation structure comprises a first end and a second end, the first end of the first isolation structure is located on the first well region, the second end of the first isolation structure is located on the second well region, the polycrystalline field plate is located on the first isolation structure and close to the first end of the first isolation structure, and a partial projection of the polycrystalline field plate is located at an edge of the first well region; A dielectric layer covers the first active region, the first isolation structure, the polycrystalline field plate, the second isolation structure and the second active region, and a hole is opened in the dielectric layer on the first active region, the polycrystalline field plate and the second active region; a first metal layer, located on the dielectric layer and filling the openings of the dielectric layer on the first active region on the first well region and the dielectric layer on the polycrystalline field plate, wherein the first metal layer connects the first active region on the first well region and the polycrystalline field plate; The second metal layer is located on the dielectric layer and fills the openings of the dielectric layer on the first active area of ​​the third well region and the dielectric layer on the second active area of ​​the second well region. The second metal layer connects the first active area of ​​the third well region and the second active area of ​​the second well region.

5. The ESD structure according to claim 4, characterized in that: The second well region and the epitaxy are equivalent to a diode, the second well region serves as the cathode of the diode, and the epitaxy serves as the anode of the diode; the third well region, the second well region and the epitaxy are equivalent to a first parasitic transistor, the third well region serves as the emitter of the first parasitic transistor, the second well region serves as the base of the first parasitic transistor, the epitaxy serves as the collector of the first parasitic transistor, and the second well region serves as a first equivalent resistor; the third well region, the second well region, the buried layer and the epitaxy are equivalent to a second parasitic transistor, the third well region serves as the emitter of the second parasitic transistor, the second well region and the buried layer serve as the base of the second parasitic transistor, the epitaxy serves as the collector of the second parasitic transistor, and the second well region and the buried layer serve as a second equivalent resistor.

6. The ESD structure according to claim 5, characterized in that The second metal layer is connected to a high potential, the first metal layer is connected to a low potential, the diode is reversely broken down to discharge current, and the potential at the bottom of the third well region decreases accordingly, turning on the first parasitic transistor and the second parasitic transistor to discharge current.

7. The ESD structure according to any one of claims 1 to 3, wherein: The first doping type is P type, and the second doping type is N type.

8. The ESD structure according to any one of claims 1 to 3, wherein: The doping concentration of the first well region is 1e15cm -3 ~1e17cm -3 The doping concentration of the second well region is 1e14cm -3 ~1e16cm -3 The doping concentration of the buried layer is 1e16cm -3 ~1e18cm -3 .

9. The ESD structure according to any one of claims 1 to 3, wherein: The breakdown voltage of the ESD structure is increased by reducing the doping concentration of at least one of the first well region, the second well region or the buried layer; or, the breakdown voltage of the ESD structure is reduced by increasing the doping concentration of at least one of the first well region, the second well region or the buried layer.

10. The ESD structure according to any one of claims 1 to 3, wherein: A first lateral gap is provided between the first well region and the second well region, and a width of the first lateral gap is 0 to 10 micrometers.

11. The ESD structure according to claim 10, wherein: Increasing the first lateral gap increases the breakdown voltage of the ESD structure; or decreasing the first lateral gap decreases the breakdown voltage of the ESD structure.

12. The ESD structure according to any one of claims 1 to 3, wherein: The first well region contacts a side wall of the second well region; or, at least a portion of the first well region is located in the second well region; or, the first well region and the second well region are separated from each other.

13. The ESD structure according to claim 4, wherein: The distance between the edge of the polycrystalline field plate and the first end of the first isolation structure is 1 micrometer to 2 micrometers, and the lateral width of the polycrystalline field plate is 2 micrometers to 4 micrometers.

14. The ESD structure according to any one of claims 1 to 3, wherein: The thickness of the first well region is equal to or smaller than the thickness of the second well region.

15. An ESD device, characterized in that: Comprising the ESD structure according to any one of claims 1 to 14.

16. An ESD chip, characterized in that: Comprising the ESD structure according to any one of claims 1 to 14.

17. The ESD chip according to claim 16, characterized in that: The ESD structure is connected between two functional pins of the ESD chip that need to be electrostatically protected, thereby achieving electrostatic protection for the two functional pins.

18. The ESD chip according to claim 16, characterized in that: The ESD chip is a high-voltage gate driver chip, and the ESD structure is a bootstrap diode in the high-voltage gate driver chip. The ESD structure has the function of a bootstrap diode and realizes electrostatic protection between two functional pins that require electrostatic protection.

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