Array substrate, driving method and display device

Abstract

The present disclosure provides an array substrate, a driving method, and a display device. The array substrate includes a plurality of pixels, each pixel including at least three sub-pixels having different colors; data lines are provided on both sides of the sub-pixels in a first direction, and scan lines are provided on both sides of the sub-pixels in a second direction; in two adjacent rows of sub-pixels, two sub-pixels electrically connected to the same data line have the same color, and the two sub-pixels are electrically connected to different scan lines, respectively; the sub-pixels include pixel electrodes; the length of the pixel electrodes along the first direction is greater than the length of the pixel electrodes along the second direction. The present disclosure can, in a frequency doubling mode, ensure that adjacent sub-pixels on the same data line have the same color, thereby improving image quality.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of the People's Republic of China on July 28, 2023, with application number 202310943335.6 and invention name "Array substrate, driving method and display device", the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to an array substrate, a driving method, and a display device. Background Art

[0004] In the relevant array substrate, multiple sub-pixels within a pixel are arranged in a row. Two scan lines are located between two adjacent rows of pixels, and one data line is located between two adjacent columns of sub-pixels. Each data line connects sub-pixels with a color range of two or more. The relevant design does not support the frequency doubling method. In frequency doubling mode, adjacent sub-pixels on the same data line have different colors, resulting in a mixed display of the adjacent sub-pixels' colors rather than the expected single color, causing image distortion. Summary of the Invention

[0005] The main purpose of the present disclosure is to provide an array substrate, a driving method and a display device to solve the problem in the prior art that in the frequency doubling mode, adjacent sub-pixels on the same data line have different colors, which causes the color to be displayed as a mixed color of adjacent sub-pixels rather than the expected single color, resulting in an abnormal picture.

[0006] The array substrate according to the embodiment of the present disclosure includes a plurality of pixels, each pixel including at least three sub-pixels with different colors;

[0007] The sub-pixel is provided with data lines on both sides in the first direction, and the sub-pixel is provided with scan lines on both sides in the second direction;

[0008] In two adjacent rows of sub-pixels, two sub-pixels electrically connected to the same data line have the same color, and the two sub-pixels are electrically connected to different scan lines respectively;

[0009] The sub-pixel includes a pixel electrode;

[0010] The length of the pixel electrode along the first direction is greater than the length of the pixel electrode along the second direction.

[0011] In one possible implementation, the pixel includes three sub-pixels with different colors;

[0012] The two sub-pixels included in the pixel are located in the 2n-1th row, and the sub-pixels included in the pixel other than the two sub-pixels are located in the 2nth row; wherein n is a positive integer.

[0013] In a possible implementation, the array substrate includes: a plurality of pixel rows; the pixel rows include: a plurality of first pixels and a plurality of second pixels; the first pixels and the second pixels are alternately arranged along the first direction;

[0014] The first pixel includes: a first sub-pixel, a second sub-pixel, and a third sub-pixel; wherein the first sub-pixel and the second sub-pixel are located in the 2n-1th row; and the third sub-pixel is located in the 2nth row;

[0015] The second pixel includes: a fourth sub-pixel, a fifth sub-pixel, and a sixth sub-pixel; wherein the fourth sub-pixel is located in the 2n-1th row; the fifth sub-pixel and the sixth sub-pixel are located in the 2nth row.

[0016] In one possible implementation, the pixel electrode of the first sub-pixel has a first axis, which extends along the second direction and passes through a central area of ​​the pixel electrode of the first sub-pixel; the pixel electrode of the second sub-pixel has a second axis, which extends along the second direction and passes through a central area of ​​the pixel electrode of the second sub-pixel; and the pixel electrode of the third sub-pixel has a third axis, which extends along the second direction and passes through a central area of ​​the pixel electrode of the third sub-pixel.

[0017] The pixel electrode of the fourth subpixel has a fourth axis, which extends along the second direction and passes through a central area of ​​the pixel electrode of the fourth subpixel; the pixel electrode of the fifth subpixel has a fifth axis, which extends along the second direction and passes through a central area of ​​the pixel electrode of the fifth subpixel; and the pixel electrode of the sixth subpixel has a sixth axis, which extends along the second direction and passes through a central area of ​​the pixel electrode of the sixth subpixel.

[0018] The orthographic projection of the third axis on the substrate is located between the orthographic projection of the first axis and the orthographic projection of the second axis on the substrate; the orthographic projection of the fourth axis on the substrate is located between the orthographic projection of the fifth axis and the orthographic projection of the sixth axis on the substrate.

[0019] In a possible implementation, the distance between the first axis and the third axis is d1, and the distance between the fourth axis and the fifth axis is d2, and d1 and d2 satisfy the following relationship:

[0020] 0≤d1≤w / 2;

[0021] 0≤d2≤w2; wherein w represents the width of the pixel electrode.

[0022] In a possible implementation, the center of the pixel electrode of the first sub-pixel, the center of the pixel electrode of the second sub-pixel, the center of the pixel electrode of the third sub-pixel, and the center of the pixel electrode of the fifth sub-pixel form a parallelogram;

[0023] The center of the pixel electrode of the second sub-pixel, the center of the pixel electrode of the fourth sub-pixel, the center of the pixel electrode of the fifth sub-pixel, and the center of the pixel electrode of the sixth sub-pixel form a parallelogram.

[0024] In one possible implementation, the pixel electrode of the first sub-pixel has a first axis, which extends along the second direction and passes through a central area of ​​the pixel electrode of the first sub-pixel; the pixel electrode of the second sub-pixel has a second axis, which extends along the second direction and passes through a central area of ​​the pixel electrode of the second sub-pixel; and the pixel electrode of the third sub-pixel has a third axis, which extends along the second direction and passes through a central area of ​​the pixel electrode of the third sub-pixel.

[0025] The pixel electrode of the fourth subpixel has a fourth axis, which extends along the second direction and passes through a central area of ​​the pixel electrode of the fourth subpixel; the pixel electrode of the fifth subpixel has a fifth axis, which extends along the second direction and passes through a central area of ​​the pixel electrode of the fifth subpixel; and the pixel electrode of the sixth subpixel has a sixth axis, which extends along the second direction and passes through a central area of ​​the pixel electrode of the sixth subpixel.

[0026] The orthographic projection of the third axis on the substrate coincides with the orthographic projection of the first axis on the substrate; the orthographic projection of the fifth axis on the substrate coincides with the orthographic projection of the second axis on the substrate; the orthographic projection of the fourth axis on the substrate coincides with the orthographic projection of the sixth axis on the substrate.

[0027] In a possible implementation, the plurality of sub-pixels are distributed in an array; the first sub-pixel is located in the 2n-1th row and the 3m-2th column, the second sub-pixel is located in the 2n-1th row and the 3m-1th column, and the third sub-pixel is located in the 2nth row and the 3m-2th column;

[0028] The fourth sub-pixel is located at the 2n-1th row and the 3mth column, the fifth sub-pixel is located at the 2nth row and the 3m-1th column, and the sixth sub-pixel is located at the 2nth row and the 3mth column; wherein m is a positive integer.

[0029] In a possible implementation, the first sub-pixel is electrically connected to the 2n-1th scan line and the 3m-1th data line, respectively; the second sub-pixel is electrically connected to the 2n-1th scan line and the 3mth data line, respectively; and the third sub-pixel is electrically connected to the 2nth scan line and the 3m-2th data line, respectively.

[0030] The fourth sub-pixel is electrically connected to the 2n-1th scan line and the 3m+1th data line respectively, the fifth sub-pixel is electrically connected to the 2nth scan line and the 3m-1th data line respectively, and the sixth sub-pixel is electrically connected to the 2nth scan line and the 3mth data line respectively.

[0031] In a possible implementation manner, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel;

[0032] The fourth sub-pixel is a blue sub-pixel, the fifth sub-pixel is a red sub-pixel, and the sixth sub-pixel is a green sub-pixel.

[0033] In a possible implementation manner, the first sub-pixel is a red sub-pixel, the second sub-pixel is a blue sub-pixel, and the third sub-pixel is a green sub-pixel;

[0034] The fourth sub-pixel is a green sub-pixel, the fifth sub-pixel is a red sub-pixel, and the sixth sub-pixel is a blue sub-pixel.

[0035] In a possible implementation manner, the first sub-pixel is a blue sub-pixel, the second sub-pixel is a red sub-pixel, and the third sub-pixel is a green sub-pixel;

[0036] The fourth sub-pixel is a green sub-pixel, the fifth sub-pixel is a blue sub-pixel, and the sixth sub-pixel is a red sub-pixel.

[0037] In a possible implementation manner, the at least three sub-pixels with different colors included in the pixel are located in the same row.

[0038] In a possible implementation, the plurality of sub-pixels are distributed in an array; the pixel includes three sub-pixels with different colors;

[0039] The sub-pixel in the 2n-1th row and the 3m-2th column, the sub-pixel in the 2n-1th row and the 3m-1th column, and the sub-pixel in the 2n-1th row and the 3mth column constitute a pixel;

[0040] The sub-pixel in the 3m-1 column of the 2nth row, the sub-pixel in the 3mth column of the 2nth row, and the sub-pixel in the 3m-1th column of the 2nth row constitute a pixel;

[0041] The sub-pixel in the 2n-1th row and the 3m-2th column is electrically connected to the 2n-1th scan line and the 3m-1th data line respectively, the sub-pixel in the 2n-1th row and the 3m-1th column is electrically connected to the 2n-1th scan line and the 3mth data line respectively, and the sub-pixel in the 2n-1th row and the 3mth column is electrically connected to the 2n-1th scan line and the 3m+1th data line respectively;

[0042] The sub-pixel in the 2nth row and the 3m-1th column is electrically connected to the 2nth scan line and the 3m-1th data line respectively, the sub-pixel in the 2nth row and the 3mth column is electrically connected to the 2nth scan line and the 3mth data line respectively, and the sub-pixel in the 2nth row and the 3m+1th column is electrically connected to the 2nth scan line and the 3m+1th data line respectively; wherein n and m are positive integers.

[0043] In one possible implementation, the color of the sub-pixel in the 2n-1th row and the 3m-2th column is the same as the color of the sub-pixel in the 2nth row and the 3m-1th column;

[0044] The color of the sub-pixel in the 2n-1th row and the 3m-1th column is the same as the color of the sub-pixel in the 2nth row and the 3mth column;

[0045] The color of the sub-pixel in the 2n-1th row and the 3mth column is the same as the color of the sub-pixel in the 2nth row and the 3m+1th column.

[0046] In one possible implementation, the pixel includes three sub-pixels with different colors;

[0047] The sub-pixel in the 2n-1th row and the 3m-2th column, the sub-pixel in the 2n-1th row and the 3m-1th column, and the sub-pixel in the 2n-1th row and the 3mth column constitute a pixel;

[0048] The sub-pixel in the 2nth row and 3mth column, the sub-pixel in the 2nth row and 3m+1th column, and the sub-pixel in the 2nth row and 3m+2th column constitute a pixel;

[0049] The sub-pixel in the 2n-1th row and the 3m-2th column is electrically connected to the 2n-1th scan line and the 3m-1th data line respectively, the sub-pixel in the 2n-1th row and the 3m-1th column is electrically connected to the 2n-1th scan line and the 3mth data line respectively, and the sub-pixel in the 2n-1th row and the 3mth column is electrically connected to the 2n-1th scan line and the 3m+1th data line respectively;

[0050] The sub-pixel in the 2nth row and 3mth column is electrically connected to the 2nth scan line and the 3mth data line respectively, the sub-pixel in the 2nth row and 3m+1th column is electrically connected to the 2nth scan line and the 3m+1th data line respectively, and the sub-pixel in the 2nth row and 3m+2th column is electrically connected to the 2nth scan line and the 3m+2th data line respectively; wherein n and m are positive integers.

[0051] In one possible implementation, the color of the sub-pixel in the 2n-1th row and the 3m-2th column is the same as the color of the sub-pixel in the 2nth row and the 3mth column;

[0052] The color of the sub-pixel in the 2n-1th row and the 3m-1th column is the same as the color of the sub-pixel in the 2nth row and the 3m+1th column;

[0053] The color of the sub-pixel in the 2n-1th row and the 3mth column is the same as the color of the sub-pixel in the 2nth row and the 3m+2nd column.

[0054] In a possible implementation, a ratio of a length of the pixel electrode along the first direction to a length of the pixel electrode along the second direction is greater than 1 and less than or equal to 2.

[0055] In a possible implementation, a ratio of a length of two adjacent rows and two columns of pixel electrodes along the first direction to a length of two adjacent rows and two columns of pixel electrodes along the second direction is greater than or equal to 1.2 and less than or equal to 1.8.

[0056] In a possible implementation manner, the lengths of pixel electrodes in sub-pixels with the same color in different pixels along the first direction are the same;

[0057] The lengths of the pixel electrodes in sub-pixels of the same color in different pixels along the second direction are the same.

[0058] In a possible implementation, the pixel electrodes of at least two sub-pixels included in the same pixel have the same length along the first direction.

[0059] In a possible implementation manner, the lengths of pixel electrodes in at least two sub-pixels included in the same pixel along the first direction are different.

[0060] In a possible implementation, the pixel electrode includes: a first slit group and a second slit group arranged along the first direction; the first slit group and the second slit group each include: a plurality of slits;

[0061] The multiple slits in the first slit group extend in the same direction; the multiple slits in the second slit group extend in the same direction; and the slits in the first slit group extend in a direction different from that in the second slit group.

[0062] In a possible implementation, the smaller of the angles formed between the slits of the first slit group and the slits of the second slit group is smaller than 90 degrees.

[0063] In a possible implementation, a larger angle between the angles formed by the slits of the first slit group and the angles formed by the slits of the second slit group is greater than 90 degrees.

[0064] In a possible implementation, the data line includes: a plurality of routing units; the plurality of routing units are arranged sequentially along the second direction;

[0065] The routing unit includes: a first sub-routing portion, a second sub-routing portion, a third sub-routing portion, and a fourth routing portion connected in sequence; the first sub-routing portion and the third sub-routing portion extend along the second direction; the second sub-routing portion and the fourth sub-routing portion extend along the first direction;

[0066] The orthographic projections of the first sub-routing portion and the third sub-routing portion on the substrate overlap with the orthographic projections of the gap between two adjacent pixel electrodes in the first direction on the substrate; the orthographic projections of the second sub-routing portion and the fourth sub-routing portion on the substrate overlap with the orthographic projections of the gap between adjacent pixel electrode rows on the substrate.

[0067] In a possible implementation manner, at least one of the first sub-routing portion and the third sub-routing portion further includes: a first sub-bending portion and a second sub-bending portion;

[0068] The first sub-bending portion and the second sub-bending portion extend in different directions.

[0069] In a possible implementation, at least part of the data lines are bent; and a distance between two adjacent data lines in the first direction is proportional to a width of the pixel electrode between the two data lines in the first direction.

[0070] In a possible implementation, the array substrate further includes: a common electrode layer; the common electrode layer includes: a plurality of common electrodes; the orthographic projection of the common electrodes on the substrate overlaps with the orthographic projection of the pixel electrodes on the substrate;

[0071] The length of the common electrode along the first direction is greater than the length of the common electrode along the second direction.

[0072] In one possible embodiment, the common electrode layer includes: a plurality of common electrode rows extending along the first direction and arranged along the second direction; the common electrode rows include: a plurality of common electrodes arranged along the first direction; the array substrate further includes: a first trace in the same layer as the gate line and extending along the first direction;

[0073] The first wiring portion is in direct contact with the common electrode, and the common electrodes in the same common electrode row are electrically connected via the first wiring.

[0074] In a possible implementation, the array substrate includes a plurality of transistors; the pixel electrode is electrically connected to the scan line and the data line through the transistor; the transistor includes a first electrode and a second electrode;

[0075] The common electrode has a first notch, and an orthographic projection of the first notch on the substrate overlaps with an orthographic projection of the second electrode on the substrate.

[0076] In a possible implementation manner, the scan line has a second gap; an orthographic projection of the second gap on the substrate overlaps with an orthographic projection of the second sub-routing portion or the third sub-routing portion on the substrate.

[0077] In a possible implementation manner, the scan line further has a third gap; an orthographic projection of the third gap on the substrate overlaps with an orthographic projection of the data line on the substrate;

[0078] A depth of the third notch in the second direction is greater than a depth of the second notch in the second direction.

[0079] The driving method described in the embodiment of the present disclosure is applied to the above-mentioned array substrate, and the display cycle includes a plurality of driving stages arranged in sequence; the driving method includes:

[0080] In the 2n-1 driving phase, the 2n-1 scanning line is turned on, and the sub-pixels located in the 2n-1 row receive data voltages provided by corresponding data lines.

[0081] In the 2nth driving phase, the 2nth scan line is turned on, and the sub-pixels located in the 2nth row receive data voltages provided by corresponding data lines.

[0082] n is a positive integer;

[0083] In the 2n-1 driving stage, the data voltage provided by the data line is the data voltage corresponding to the sub-pixels in the 2n-1 row; in the 2n driving stage, the data voltage provided by the data line is the data voltage corresponding to the sub-pixels in the 2n row.

[0084] The driving method described in the embodiment of the present disclosure is applied to the above-mentioned array substrate, and the driving method includes:

[0085] providing scan signals to the plurality of scan lines such that the 2n-1th scan signal provided by the 2n-1th scan line is the same as the 2nth scan signal provided by the 2nth scan line;

[0086] There is an overlapping period between the effective voltage period of the 2nth scan signal and the effective voltage period of the 2n+1th scan signal. During the overlapping period, the 2n-1th scan line, the 2nth scan line, the 2n+1th scan line, and the 2n+2th scan line are turned on, and the sub-pixels located in the 2n-1th row, the sub-pixels located in the 2nth row, the sub-pixels located in the 2n+1th row, and the sub-pixels located in the 2n+2th row receive data voltages provided by corresponding data lines.

[0087] n is a positive integer.

[0088] The driving method described in the embodiment of the present disclosure is applied to the above-mentioned array substrate, and the driving method includes:

[0089] providing scanning signals to the plurality of scanning lines to control the plurality of scanning lines to be turned on in sequence during a display period;

[0090] In the display period, there are overlapping time periods and non-overlapping time periods between the effective time periods of the scan signals provided by at least two adjacent scan lines among the plurality of scan lines turned on in sequence;

[0091] The data voltage received by the data line during at least a portion of the overlapping time period is the same as the data voltage received by the data line during at least a portion of the non-overlapping time period.

[0092] The display device described in the embodiment of the present disclosure includes the above-mentioned array substrate.

[0093] The array substrate, driving method, and display device described in the embodiments of the present disclosure can, in a frequency doubling mode, make adjacent sub-pixels on the same data line have the same color, thereby improving picture quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0094] Figure 1 is a structural diagram of at least one embodiment of a sub-pixel;

[0095] Figure 2A is a structural diagram of an array substrate according to at least one embodiment of the present disclosure;

[0096] Figure 2B For Figure 2A One of the corresponding schematic diagrams of the array substrate film layer;

[0097] Figure 2C for Figure 2B Schematic diagram of a single film layer of the common electrode layer;

[0098] Figure 2D for Figure 2B Schematic diagram of the stacking of the common electrode layer and the scan line;

[0099] Figure 2E for Figure 2B Schematic diagram of the stacking of the common electrode layer, scan lines, and data lines;

[0100] Figure 2F for Figure 2B Schematic diagram of a single film layer of the pixel electrode layer;

[0101] Figure 2G This is a schematic diagram of a manufacturing process of an array substrate provided in an embodiment of the present disclosure;

[0102] Figure 2H For Figure 2A The second schematic diagram of the corresponding array substrate film layer;

[0103] Figure 2I for Figure 2H Schematic diagram of a single film layer of the common electrode layer;

[0104] Figure 2J for Figure 2H Schematic diagram of the stacking of the common electrode layer and the scan line;

[0105] Figure 2K for Figure 2H Schematic diagram of the stacking of the common electrode layer, scan lines, and data lines;

[0106] Figure 2L for Figure 2H Schematic diagram of a single film layer of the pixel electrode layer;

[0107] Figure 2M A schematic cross-sectional view of another array substrate provided in an embodiment of the present disclosure;

[0108] Figure 3A is a structural diagram of an array substrate according to at least one embodiment of the present disclosure;

[0109] Figure 3B For Figure 3A One of the corresponding schematic diagrams of the array substrate film layer;

[0110] Figure 3C for Figure 3B Schematic diagram of a single film layer of the common electrode layer;

[0111] Figure 3D for Figure 3B Schematic diagram of the stacking of the common electrode layer and the scan line;

[0112] Figure 3E for Figure 3B Schematic diagram of the stacking of the common electrode layer, scan lines, and data lines;

[0113] Figure 3F for Figure 3B Schematic diagram of a single film layer of the pixel electrode layer;

[0114] Figure 3G For Figure 3A The second schematic diagram of the corresponding array substrate film layer;

[0115] Figure 3H for Figure 3H Schematic diagram of a single film layer of the common electrode layer;

[0116] Figure 3I for Figure 3H Schematic diagram of the stacking of the common electrode layer and the scan line;

[0117] Figure 3J for Figure 3H Schematic diagram of the stacking of the common electrode layer, scan lines, and data lines;

[0118] Figure 3K for Figure 3H Schematic diagram of a single film layer of the pixel electrode layer;

[0119] Figure 4A is a structural diagram of an array substrate according to at least one embodiment of the present disclosure;

[0120] Figure 4B is a structural diagram of an array substrate according to at least one embodiment of the present disclosure;

[0121] Figure 5 is a structural diagram of an array substrate according to at least one embodiment of the present disclosure;

[0122] Figure 6 is a structural diagram of an array substrate according to at least one embodiment of the present disclosure;

[0123] Figure 7 is a structural diagram of an array substrate according to at least one embodiment of the present disclosure;

[0124] Figure 8 is a structural diagram of an array substrate according to at least one embodiment of the present disclosure;

[0125] Figure 9 is a structural diagram of an array substrate according to at least one embodiment of the present disclosure;

[0126] Figure 10 is a structural diagram of an array substrate according to at least one embodiment of the present disclosure;

[0127] Figure 11is a structural diagram of an array substrate according to at least one embodiment of the present disclosure;

[0128] Figure 12 is a waveform diagram of a scanning signal corresponding to the driving method described in at least one embodiment of the present disclosure;

[0129] Figure 13 is a waveform diagram of a scanning signal corresponding to the driving method described in at least one embodiment of the present disclosure;

[0130] Figure 14 is a waveform diagram of a scanning signal corresponding to the driving method described in at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0131] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present disclosure without making any creative efforts shall fall within the scope of protection of the present disclosure.

[0132] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0133] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0134] The array substrate according to the embodiment of the present disclosure includes a plurality of pixels, each pixel including at least three sub-pixels with different colors;

[0135] The sub-pixel is provided with data lines on both sides in the first direction, and the sub-pixel is provided with scan lines on both sides in the second direction;

[0136] In two adjacent rows of sub-pixels, two sub-pixels electrically connected to the same data line have the same color, and the two sub-pixels are electrically connected to different scan lines respectively;

[0137] The sub-pixel includes a pixel electrode;

[0138] A length of the pixel electrode along the first direction is greater than a length of the pixel electrode along the second direction.

[0139] In the relevant array substrate, multiple sub-pixels within a pixel are arranged in a row. Two scan lines are located between two adjacent rows of pixels, and one data line is located between two adjacent columns of sub-pixels. Each data line connects sub-pixels with a color range of two or more. The relevant design does not support the frequency doubling method. In frequency doubling mode, adjacent sub-pixels on the same data line have different colors, resulting in a mixed display of the adjacent sub-pixels' colors rather than the expected single color, causing image distortion.

[0140] Based on this, embodiments of the present disclosure provide an array substrate in which two sub-pixels electrically connected to the same data line have the same color and are electrically connected to different scan lines. The length of the pixel electrode along the first direction is greater than the length of the pixel electrode along the second direction. In frequency doubling mode, embodiments of the present disclosure ensure that adjacent sub-pixels on the same data line have the same color, thereby improving image quality.

[0141] In at least one embodiment of the present disclosure, Figure 1 As shown, the sub-pixel may include a pixel electrode PE and a thin film transistor T0;

[0142] The gate of the thin film transistor T0 is electrically connected to a row of the scan lines GT, the first electrode of the thin film transistor T0 is electrically connected to the pixel electrode PE, and the second electrode of the thin film transistor T0 is electrically connected to a column of the data lines DT. When the thin film transistor T0 is turned on under the control of the scan signal provided by the scan line GT, the data line DT provides a data voltage to the pixel electrode PE.

[0143] In the relevant array substrate, the ratio between the length of the pixel electrode along the first direction and the length of the pixel electrode along the second direction can be about 1 / 3, and in the embodiment of the present disclosure, the length of the pixel electrode along the first direction can be greater than the length of the pixel electrode along the second direction.

[0144] Optional, see Figure 3A 、 Figure 4A 、 Figure 4B 、 Figure 5-Figure 8 As shown, multiple sub-pixels can be distributed in an array of multiple rows and columns, multiple scan lines can extend along the first direction, and multiple data lines can extend along the second direction; a scan line is set between two adjacent rows of sub-pixels, and a data line is set between two adjacent columns of sub-pixels.

[0145] Optionally, a ratio of a length of the pixel electrode extending along the first direction to a length of the pixel electrode extending along the second direction is greater than 1 and less than or equal to 2.

[0146] For example, a ratio between a length of the pixel electrode extending along the first direction and a length of the pixel electrode extending along the second direction may be 4 / 3, but is not limited thereto.

[0147] In at least one embodiment of the present disclosure, a ratio of a length of two adjacent rows and two columns of pixel electrodes along the first direction to a length of the two adjacent rows and two columns of pixel electrodes along the second direction is greater than or equal to 1.2 and less than or equal to 1.8.

[0148] In a specific implementation, the ratio of the length of two adjacent rows and two columns of pixel electrodes along the first direction to the length of the two adjacent rows and two columns of pixel electrodes along the second direction may be approximately 1.5, but is not limited thereto.

[0149] Optionally, the lengths of pixel electrodes in at least two sub-pixels included in the same pixel along the first direction are different, so as to improve the display contrast of sub-pixels with different colors.

[0150] Optionally, the pixel electrodes of at least two sub-pixels included in the same pixel have the same length along the first direction, so as to achieve regular arrangement of the sub-pixels and reduce wiring complexity.

[0151] In at least one embodiment of the present disclosure, the lengths of pixel electrodes in sub-pixels with the same color in different pixels along the first direction are the same, and the lengths of pixel electrodes in sub-pixels with the same color in different pixels along the second direction are the same, so as to improve the display uniformity of sub-pixels with the same color.

[0152] In at least one embodiment of the present disclosure, the pixel includes three sub-pixels with different colors;

[0153] The two sub-pixels included in the pixel are located in the 2n-1th row, and the pixels included in the pixel other than the two sub-pixels are located in the 2nth row;

[0154] n is a positive integer.

[0155] In a specific implementation, the length of the pixel electrode in the subpixel along the first direction can be twice the length of the related pixel electrode along the first direction, and the length of the pixel electrode in the subpixel along the second direction is 1 / 2 of the length of the related pixel electrode along the second direction. When the pixel includes three subpixels, the two subpixels included in the pixel are located in the 2n-1th row, and the subpixels included in the pixel other than the two subpixels are located in the 2nth row. The subpixels in two adjacent rows and two columns of pixels are combined to form a rectangle, and the size of the rectangle is the same as the size of the adjacent two rows and two columns of pixels in the related art. Therefore, in at least one embodiment of the present disclosure, the pixel resolution is the same as the pixel resolution in the related art. Without sacrificing resolution, in the frequency doubling mode, the colors of adjacent subpixels on the same data line can be made the same, thereby improving the picture quality.

[0156] In at least one embodiment of the present disclosure, a row of scan lines is provided between two adjacent rows of sub-pixels, and a row of pixels includes two rows of sub-pixels. Therefore, a row of pixels is electrically connected to the two rows of scan lines. The pixel structure in the array substrate described in at least one embodiment of the present disclosure is a dual gate pixel structure.

[0157] In at least one embodiment of the present disclosure, a column of data lines is provided between two adjacent columns of sub-pixels. The two columns of pixels occupy the length of three columns of sub-pixels along the second direction, and thus the two columns of pixels are electrically connected to the three columns of data lines. In the related art, every two columns of sub-pixels include a column of data lines. Since two columns of pixels include six columns of sub-pixels, the two columns of pixels also include three data lines.

[0158] Optionally, the first direction may be a horizontal direction, and the second direction may be a vertical direction.

[0159] In at least one embodiment of the present disclosure, see Figure 2B 、 Figure 3A As shown, the array substrate includes: a plurality of pixel rows; the pixel rows include: a plurality of first pixels P100 and a plurality of second pixels P200; the first pixels P100 and the second pixels P200 are alternately arranged along the first direction X;

[0160] The first pixel P100 includes: a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3; wherein, the first sub-pixel P1 and the second sub-pixel P2 are located in the 2n-1 row; the third sub-pixel P3 is located in the 2n row; the second pixel P200 includes: a fourth sub-pixel P4, a fifth sub-pixel P5, and a sixth sub-pixel P6; wherein, the fourth sub-pixel P4 is located in the 2n-1 row; the fifth sub-pixel P5 and the sixth sub-pixel P6 are located in the 2n row.

[0161] In at least one embodiment of the present disclosure, see Figure 2FAs shown, the pixel electrode of the first subpixel P1 has a first axis k1, which extends along the second direction Y and passes through the central area O1 of the pixel electrode of the first subpixel P1; the pixel electrode of the second subpixel P2 has a second axis K2, which extends along the second direction Y and passes through the central area O2 of the pixel electrode of the second subpixel P2; the pixel electrode of the third subpixel P3 has a third axis k3, which extends along the second direction Y and passes through the central area O3 of the pixel electrode of the third subpixel P3;

[0162] The pixel electrode of the fourth subpixel P4 has a fourth axis k4, which extends along the second direction Y and passes through the central area O4 of the pixel electrode of the fourth subpixel P4; the pixel electrode of the fifth subpixel P5 has a fifth axis k5, which extends along the second direction Y and passes through the central area O5 of the pixel electrode of the fifth subpixel P5; the pixel electrode of the sixth subpixel P6 has a sixth axis k6, which extends along the second direction Y and passes through the central area O6 of the pixel electrode of the sixth subpixel P6;

[0163] The orthographic projection of the third axis k3 on the substrate 1 is located between the orthographic projection of the first axis k1 and the orthographic projection of the second axis k2 on the substrate 1. The orthographic projection of the fourth axis k4 on the substrate 1 is located between the orthographic projection of the fifth axis k5 and the orthographic projection of the sixth axis k6 on the substrate 1. In an embodiment of the present invention, two adjacent rows of sub-pixels may be offset from each other. For example, the sub-pixels in the next row may be shifted by half the width of the pixel electrode relative to the sub-pixels in the previous row. The three sub-pixels in a pixel form a "P" shape or an inverted "P" shape.

[0164] In at least one embodiment of the present disclosure, see Figure 2F As shown, the distance between the first axis k1 and the third axis k3 is d1, and the distance between the fourth axis k4 and the fifth axis k5 is d2. d1 and d2 satisfy the following relationship:

[0165] 0≤d1≤w / 2;

[0166] 0≤d2≤w2; where w represents the width of the pixel electrode.

[0167] In at least one embodiment of the present disclosure, see Figure 2F As shown, the pixel electrode center O1 of the first sub-pixel P2, the pixel electrode center O2 of the second sub-pixel P2, the pixel electrode center O3 of the third sub-pixel P3, and the pixel electrode center O5 of the fifth sub-pixel P5 form a parallelogram;

[0168] The pixel electrode center O2 of the second sub-pixel P2, the pixel electrode center O4 of the fourth sub-pixel P4, the pixel electrode center O5 of the fifth sub-pixel P5, and the pixel electrode center O6 of the sixth sub-pixel P6 form a parallelogram.

[0169] In at least one embodiment of the present disclosure, see Figure 3F As shown, the pixel electrode of the first subpixel P1 has a first axis k1, which extends along the second direction Y and passes through the central area O1 of the pixel electrode of the first subpixel P1; the pixel electrode of the second subpixel P2 has a second axis K2, which extends along the second direction Y and passes through the central area O2 of the pixel electrode of the second subpixel P2; the pixel electrode of the third subpixel P3 has a third axis k3, which extends along the second direction Y and passes through the central area O3 of the pixel electrode of the third subpixel P3;

[0170] The pixel electrode of the fourth subpixel P4 has a fourth axis k4, which extends along the second direction Y and passes through the central area O4 of the pixel electrode of the fourth subpixel P4; the pixel electrode of the fifth subpixel P5 has a fifth axis k5, which extends along the second direction Y and passes through the central area O5 of the pixel electrode of the fifth subpixel P5; the pixel electrode of the sixth subpixel P6 has a sixth axis k6, which extends along the second direction Y and passes through the central area O6 of the pixel electrode of the sixth subpixel P6;

[0171] The orthographic projection of the third axis k3 on substrate 1 coincides with the orthographic projection of the first axis k1 on substrate 1; the orthographic projection of the fifth axis k5 on substrate 1 coincides with the orthographic projection of the second axis k2 on substrate 1; and the orthographic projection of the fourth axis k4 on substrate 1 coincides with the orthographic projection of the sixth axis k6 on substrate 1. In other words, the sub-pixels in two adjacent rows are arranged so that their left and right edges are roughly aligned.

[0172] In at least one embodiment of the present disclosure, see Figure 3A 、 Figure 4A 、 Figure 4B As shown, multiple sub-pixels are distributed in an array; the first sub-pixel P1 is located at the 2n-1th row and the 3m-2th column, the second sub-pixel P2 is located at the 2n-1th row and the 3m-1th column, and the third sub-pixel P3 is located at the 2nth row and the 3m-2th column;

[0173] The fourth subpixel P4 is located at the 2n-1th row and the 3mth column, the fifth subpixel P5 is located at the 2nth row and the 3m-1th column, and the sixth subpixel P6 is located at the 2nth row and the 3mth column, where m is a positive integer.

[0174] In at least one embodiment of the present disclosure, see Figure 2A 、 3A 、 Figure 4A 、 Figure 4B As shown, the first sub-pixel P1 is electrically connected to the 2n-1th scan line GT and the 3m-1th data line DT, the second sub-pixel P2 is electrically connected to the 2n-1th scan line GT and the 3mth data line DT, and the third sub-pixel P3 is electrically connected to the 2nth scan line GT and the 3m-2nd data line DT.

[0175] The fourth subpixel P4 is electrically connected to the 2n-1th scan line GT and the 3m+1th data line DT, respectively. The fifth subpixel P5 is electrically connected to the 2nth scan line GT and the 3m-1th data line DT, respectively. The sixth subpixel P6 is electrically connected to the 2nth scan line GT and the 3mth data line DT, respectively.

[0176] In at least one embodiment of the present disclosure, see Figure 2A 、 Figure 4B As shown, the first sub-pixel P1 is a red sub-pixel, the second sub-pixel P2 is a green sub-pixel, and the third sub-pixel P3 is a blue sub-pixel;

[0177] The fourth sub-pixel P4 is a blue sub-pixel, the fifth sub-pixel P5 is a red sub-pixel, and the sixth sub-pixel P6 is a green sub-pixel.

[0178] In at least one embodiment of the present disclosure, see Figure 4A As shown, the first sub-pixel P1 is a red sub-pixel, the second sub-pixel P2 is a blue sub-pixel, and the third sub-pixel P3 is a green sub-pixel;

[0179] The fourth sub-pixel P4 is a green sub-pixel, the fifth sub-pixel P5 is a red sub-pixel, and the sixth sub-pixel P6 is a blue sub-pixel.

[0180] In at least one embodiment of the present disclosure, see Figure 4B As shown, the first sub-pixel P1 is a blue sub-pixel, the second sub-pixel P2 is a red sub-pixel, and the third sub-pixel P3 is a green sub-pixel;

[0181] The fourth sub-pixel P4 is a green sub-pixel, the fifth sub-pixel P5 is a blue sub-pixel, and the sixth sub-pixel P6 is a red sub-pixel.

[0182] In at least one embodiment of the present disclosure, the sub-pixel in the 2n-1th row and the 3m-2th column, the sub-pixel in the 2n-1th row and the 3m-1th column, and the sub-pixel in the 2nth row and the 3m-2th column constitute a pixel;

[0183] The sub-pixel in the 2n-1th row and the 3mth column, the sub-pixel in the 2nth row and the 3m-1th column, and the sub-pixel in the 2nth row and the 3mth column constitute a pixel;

[0184] The sub-pixel in the 2n-1th row and the 3m-2th column is electrically connected to the 2n-1th scan line and the 3m-1th data line respectively, the sub-pixel in the 2n-1th row and the 3m-1th column is electrically connected to the 2n-1th scan line and the 3mth data line respectively, and the sub-pixel in the 2nth row and the 3m-2th column is electrically connected to the 2nth scan line and the 3m-2th data line respectively;

[0185] The sub-pixel in the 2n-1th row and the 3mth column is electrically connected to the 2n-1th scan line and the 3m+1th data line, respectively; the sub-pixel in the 2nth row and the 3m-1th column is electrically connected to the 2nth scan line and the 3m-1th data line, respectively; and the sub-pixel in the 2nth row and the 3mth column is electrically connected to the 2nth scan line and the 3mth data line, respectively.

[0186] m is a positive integer.

[0187] Optionally, the sub-pixel in the 2n-1th row and the 3m-2th column is a red sub-pixel, the sub-pixel in the 2n-1th row and the 3m-1th column is a green sub-pixel, and the sub-pixel in the 2nth row and the 3m-2th column is a blue sub-pixel;

[0188] The sub-pixel in the 2n-1th row and the 3mth column is a blue sub-pixel, the sub-pixel in the 2nth row and the 3m-1th column is a red sub-pixel, and the sub-pixel in the 2nth row and the 3mth column is a green sub-pixel.

[0189] Optionally, the sub-pixel in the 2n-1th row and the 3m-2th column is a red sub-pixel, the sub-pixel in the 2n-1th row and the 3m-1th column is a blue sub-pixel, and the sub-pixel in the 2nth row and the 3m-2th column is a green sub-pixel;

[0190] The sub-pixel in the 2n-1th row and the 3mth column is a green sub-pixel, the sub-pixel in the 2nth row and the 3m-1th column is a red sub-pixel, and the sub-pixel in the 2nth row and the 3mth column is a blue sub-pixel.

[0191] Optionally, the sub-pixel in the 2n-1th row and the 3m-2th column is a blue sub-pixel, the sub-pixel in the 2n-1th row and the 3m-1th column is a red sub-pixel, and the sub-pixel in the 2nth row and the 3m-2th column is a green sub-pixel;

[0192] The sub-pixel in the 2n-1th row and the 3mth column is a green sub-pixel, the sub-pixel in the 2nth row and the 3m-1th column is a blue sub-pixel, and the sub-pixel in the 2nth row and the 3mth column is a red sub-pixel.

[0193] like Figure 3A As shown, the red sub-pixel R11 in the first row and first column, the green sub-pixel G12 in the first row and second column, and the blue sub-pixel B21 in the second row and first column form a pixel;

[0194] The blue sub-pixel B13 in the first row and third column, the red sub-pixel R22 in the second row and second column, and the green sub-pixel G23 in the second row and third column form a pixel;

[0195] The red sub-pixel R31 in the third row and first column, the green sub-pixel G32 in the third row and second column, and the blue sub-pixel B41 in the fourth row and first column form a pixel;

[0196] The blue sub-pixel B33 in the third row and third column, the red sub-pixel R42 in the fourth row and second column, and the green sub-pixel G43 in the fourth row and third column form a pixel;

[0197] B21 and B41 are both electrically connected to the first column data line DT1, R11 and R31 are both electrically connected to the second column data line DT2, G12 and G32 are both electrically connected to the third column data line DT3, B31 and B33 are both electrically connected to the fourth column data line DT4,

[0198] R11, G12 and B13 are all electrically connected to the first row scan line GT1, B21, R22 and G23 are all electrically connected to the second row scan line GT2, R31, G32 and B33 are all electrically connected to the third row scan line GT3, and B41, R42 and G43 are all electrically connected to the fourth row scan line GT4.

[0199] exist Figure 3A In at least one embodiment shown, all sub-pixels electrically connected to the first column data line DT1 are blue sub-pixels, all sub-pixels electrically connected to the second column data line DT2 are red sub-pixels, all sub-pixels electrically connected to the third column data line DT3 are green sub-pixels, and all sub-pixels electrically connected to the fourth column data line DT4 are blue sub-pixels.

[0200] exist Figure 3A In at least one embodiment shown, the length of the pixel electrode in each sub-pixel along the horizontal direction is twice the length of the related pixel electrode along the horizontal direction, and the length of the pixel electrode in each sub-pixel along the vertical direction is 1 / 2 of the length of the related pixel electrode along the vertical direction. Optionally, the ratio of the length of the pixel electrode extending along the first direction to the length of the pixel electrode extending along the second direction may be 4 / 3. It should be noted that, in this case, the length of the pixel electrode may refer to: when the pixel electrode is a plate-shaped electrode, the length of the pixel electrode refers to the outline length of the plate-shaped electrode; when the pixel electrode includes a slit and the pixel electrode still includes a closed outer circle outline, the length of the pixel electrode refers to the closed outline length of the pixel electrode; when the pixel electrode includes multiple branch electrodes and there is no closed outline around the pixel electrode, the length of the pixel electrode refers to the length of the connecting line of the branch electrode close to the outer end of the pixel electrode. The same is true for the width of the pixel electrode, which will not be repeated here.

[0201] exist Figure 3A In at least one embodiment shown, the lengths of the pixel electrodes in each sub-pixel along the horizontal direction are equal, and the lengths of the pixel electrodes in each sub-pixel along the vertical direction are equal, so as to improve display uniformity.

[0202] like Figure 4A As shown, the red sub-pixel R11 in the first row and first column, the blue sub-pixel B12 in the first row and second column, and the green sub-pixel G21 in the second row and first column form a pixel;

[0203] The green sub-pixel G13 in the first row and third column, the red sub-pixel R22 in the second row and second column, and the blue sub-pixel B23 in the second row and third column form a pixel;

[0204] The red sub-pixel R31 in the third row and first column, the blue sub-pixel B32 in the third row and second column, and the green sub-pixel G41 in the fourth row and first column form a pixel;

[0205] The green sub-pixel G33 in the third row and third column, the red sub-pixel R42 in the fourth row and second column, and the blue sub-pixel B43 in the fourth row and third column form a pixel;

[0206] G21 and G41 are both electrically connected to the first column data line DT1, R11 and R31 are both electrically connected to the second column data line DT2, B12 and B32 are both electrically connected to the third column data line DT3, G31 and G33 are both electrically connected to the fourth column data line DT4,

[0207] R11, B12 and G13 are all electrically connected to the first row scan line GT1, G21, R22 and B23 are all electrically connected to the second row scan line GT2, R31, B32 and G33 are all electrically connected to the third row scan line GT3, and G41, R42 and B43 are all electrically connected to the fourth row scan line GT4.

[0208] exist Figure 4A In at least one embodiment shown, the length of the pixel electrode in each sub-pixel along the horizontal direction is twice the length of the related pixel electrode along the horizontal direction, and the length of the pixel electrode in each sub-pixel along the vertical direction is 1 / 2 of the length of the related pixel electrode along the vertical direction. Optionally, the ratio between the length of the pixel electrode extending along the first direction and the length of the pixel electrode extending along the second direction can be 4 / 3.

[0209] exist Figure 4A In at least one embodiment shown, the lengths of the pixel electrodes in each sub-pixel along the horizontal direction are equal, and the lengths of the pixel electrodes in each sub-pixel along the vertical direction are equal, so as to improve display uniformity.

[0210] like Figure 4B As shown, the blue sub-pixel B11 in the first row and first column, the red sub-pixel R12 in the first row and second column, and the green sub-pixel G21 in the second row and first column form a pixel;

[0211] The green sub-pixel G13 in the first row and third column, the blue sub-pixel B22 in the second row and second column, and the red sub-pixel R23 in the second row and third column form a pixel;

[0212] The blue sub-pixel B31 in the third row and first column, the red sub-pixel R32 in the third row and second column, and the green sub-pixel G41 in the fourth row and first column form a pixel;

[0213] The green sub-pixel G33 in the third row and third column, the blue sub-pixel B42 in the fourth row and second column, and the red sub-pixel R43 in the fourth row and third column form a pixel;

[0214] G21 and G41 are both electrically connected to the first column data line DT1, B11 and B31 are both electrically connected to the second column data line DT2, R12 and R32 are both electrically connected to the third column data line DT3, G31 and G33 are both electrically connected to the fourth column data line DT4,

[0215] B11, R12 and G13 are all electrically connected to the first row scan line GT1, G21, B22 and R23 are all electrically connected to the second row scan line GT2, B31, R32 and G33 are all electrically connected to the third row scan line GT3, and G41, B42 and R43 are all electrically connected to the fourth row scan line GT4.

[0216] In at least one embodiment of the present disclosure, three sub-pixels of different colors constitute one pixel based on:

[0217] After the corresponding data voltages are respectively provided to the three sub-pixels of different colors, the light emitted by the three sub-pixels of different colors may have a brightness corresponding to a predetermined grayscale, and the light emitted by the three sub-pixels of different colors may be synthesized into white light. Figure 4B ,for Figure 4B The division of a pixel is controlled by two rows of gate lines. When a pixel needs to be lit, the controlled two rows of gate lines are turned on and data voltages are given to three sub-pixels of different colors.

[0218] exist Figure 4B In at least one embodiment shown, the length of the pixel electrode in each sub-pixel along the horizontal direction is twice the length of the related pixel electrode along the horizontal direction, and the length of the pixel electrode in each sub-pixel along the vertical direction is 1 / 2 of the length of the related pixel electrode along the vertical direction. Optionally, the ratio between the length of the pixel electrode extending along the first direction and the length of the pixel electrode extending along the second direction can be 4 / 3.

[0219] exist Figure 4B In at least one embodiment shown, the lengths of the pixel electrodes in each sub-pixel along the horizontal direction are equal, and the lengths of the pixel electrodes in each sub-pixel along the vertical direction are equal, so as to improve display uniformity.

[0220] In at least one embodiment of the present disclosure, the at least three sub-pixels with different colors included in the pixel are located in the same row.

[0221] In a specific implementation, the at least three sub-pixels with different colors included in the pixel may be located in the same row, and at the same time,

[0222] The two pixels are horizontally offset by the width of one sub-pixel; or, the two pixels are horizontally offset by the width of two sub-pixels.

[0223] In at least one embodiment of the present disclosure, the pixel includes three sub-pixels with different colors;

[0224] The sub-pixel in the 2n-1th row and the 3m-2th column, the sub-pixel in the 2n-1th row and the 3m-1th column, and the sub-pixel in the 2n-1th row and the 3mth column constitute a pixel;

[0225] The sub-pixel in the 3m-1 column of the 2nth row, the sub-pixel in the 3mth column of the 2nth row, and the sub-pixel in the 3m-1th column of the 2nth row constitute a pixel;

[0226] The sub-pixel in the 2n-1th row and the 3m-2th column is electrically connected to the 2n-1th scan line and the 3m-1th data line respectively, the sub-pixel in the 2n-1th row and the 3m-1th column is electrically connected to the 2n-1th scan line and the 3mth data line respectively, and the sub-pixel in the 2n-1th row and the 3mth column is electrically connected to the 2n-1th scan line and the 3m+1th data line respectively;

[0227] The sub-pixel in the 2nth row and the 3m-1th column is electrically connected to the 2nth scan line and the 3m-1th data line respectively, the sub-pixel in the 2nth row and the 3mth column is electrically connected to the 2nth scan line and the 3mth data line respectively, and the sub-pixel in the 2nth row and the 3m+1th column is electrically connected to the 2nth scan line and the 3m+1th data line respectively;

[0228] n and m are positive integers.

[0229] Optionally, the color of the sub-pixel in the 2n-1th row and the 3m-2th column is the same as the color of the sub-pixel in the 2nth row and the 3m-1th column;

[0230] The color of the sub-pixel in the 2n-1th row and the 3m-1th column is the same as the color of the sub-pixel in the 2nth row and the 3mth column;

[0231] The color of the sub-pixel in the 2n-1th row and the 3mth column is the same as the color of the sub-pixel in the 2nth row and the 3m+1th column.

[0232] like Figure 5 As shown, the red sub-pixel R11 in the first row and first column, the green sub-pixel G12 in the first row and second column, and the blue sub-pixel B13 in the first row and third column form a pixel;

[0233] The red sub-pixel R22 in the second row and second column, the green sub-pixel G23 in the second row and third column, and the blue sub-pixel B24 in the second row and fourth column form a pixel;

[0234] The red sub-pixel R31 in the third row and first column, the green sub-pixel G32 in the third row and second column, and the blue sub-pixel B33 in the third row and third column form a pixel;

[0235] The red sub-pixel R34 in the third row and fourth column, the green sub-pixel G35 in the third row and fifth column, and the blue sub-pixel B36 in the third row and sixth column form a pixel;

[0236] The red sub-pixel R42 in the fourth row and second column, the green sub-pixel G43 in the fourth row and third column, and the blue sub-pixel B44 in the fourth row and fourth column form one pixel;

[0237] B21 and B41 are electrically connected to the first column data line DT1;

[0238] R11, R22, R31 and R42 are all electrically connected to the second column data line DT2;

[0239] G12, G23, G32 and G43 are all electrically connected to the third column data line DT3;

[0240] B13, B24, B33 and B44 are all electrically connected to the fourth column data line DT4;

[0241] R14, R25, R34 and R45 are all electrically connected to the fifth column data line DT5;

[0242] G15, G26, G35 and G46 are all electrically connected to the sixth column data line DT6;

[0243] B16 and B36 are both electrically connected to the seventh column data line DT7;

[0244] The red sub-pixel labeled R14 is in the first row and fourth column, the green sub-pixel labeled G15 is in the first row and fifth column, and the blue sub-pixel labeled B16 is in the first row and sixth column.

[0245] The blue sub-pixel labeled B21 is in the second row and first column, the red sub-pixel labeled R25 is in the second row and fifth column, and the green sub-pixel labeled G26 is in the second row and sixth column.

[0246] The blue sub-pixel labeled B41 is in the fourth row and first column, the red sub-pixel labeled R45 is in the fourth row and fifth column, and the green sub-pixel labeled G46 is in the fourth row and sixth column.

[0247] exist Figure 5In at least one embodiment shown, the length of the pixel electrode in each sub-pixel along the horizontal direction is twice the length of the related pixel electrode along the horizontal direction, and the length of the pixel electrode in each sub-pixel along the vertical direction is 1 / 2 of the length of the related pixel electrode along the vertical direction.

[0248] exist Figure 5 In at least one embodiment shown, the lengths of the pixel electrodes in each sub-pixel along the horizontal direction are equal, and the lengths of the pixel electrodes in each sub-pixel along the vertical direction are equal, so as to improve display uniformity.

[0249] like Figure 6 As shown, the red sub-pixel R11 in the first row and first column, the blue sub-pixel B12 in the first row and second column, and the green sub-pixel G13 in the first row and third column form a pixel;

[0250] The red sub-pixel R22 in the second row and second column, the blue sub-pixel B23 in the second row and third column, and the green sub-pixel G24 in the second row and fourth column form a pixel;

[0251] The red sub-pixel R31 in the third row and first column, the blue sub-pixel B32 in the third row and second column, and the green sub-pixel G33 in the third row and third column form a pixel;

[0252] The red sub-pixel R42 in the fourth row and second column, the blue sub-pixel B43 in the fourth row and third column, and the green sub-pixel G44 in the fourth row and fourth column form a pixel;

[0253] G21 and G41 are electrically connected to the first column data line DT1;

[0254] R11, R22, R31 and R42 are all electrically connected to the second column data line DT2;

[0255] B12, B23, B32 and B43 are all electrically connected to the third column data line DT3;

[0256] G13, G24, G33 and G44 are all electrically connected to the fourth column data line DT4;

[0257] R14, R25, R34 and R45 are all electrically connected to the fifth column data line DT5;

[0258] B15, B26, B35 and B46 are all electrically connected to the sixth column data line DT6;

[0259] G16 and G36 are both electrically connected to the seventh column data line DT7;

[0260] The red sub-pixel labeled R14 is in the first row and fourth column, the blue sub-pixel labeled B15 is in the first row and fifth column, and the green sub-pixel labeled G16 is in the first row and sixth column.

[0261] The green sub-pixel labeled G21 is in the second row and first column, the red sub-pixel labeled R25 is in the second row and fifth column, and the blue sub-pixel labeled B26 is in the second row and sixth column.

[0262] The red sub-pixel labeled R34 is in the third row and fourth column, the blue sub-pixel labeled B35 is in the third row and fifth column, and the green sub-pixel labeled G36 is in the third row and sixth column.

[0263] The green sub-pixel labeled G41 is in the fourth row and first column, the red sub-pixel labeled R45 is in the fourth row and fifth column, and the blue sub-pixel labeled B46 is in the fourth row and sixth column.

[0264] exist Figure 6 In at least one embodiment shown, the length of the pixel electrode in each sub-pixel along the horizontal direction is twice the length of the related pixel electrode along the horizontal direction, and the length of the pixel electrode in each sub-pixel along the vertical direction is 1 / 2 of the length of the related pixel electrode along the vertical direction.

[0265] exist Figure 6 In at least one embodiment shown, the lengths of the pixel electrodes in each sub-pixel along the horizontal direction are equal, and the lengths of the pixel electrodes in each sub-pixel along the vertical direction are equal, so as to improve display uniformity.

[0266] like Figure 7 As shown, the blue sub-pixel B11 in the first row and first column, the red sub-pixel R12 in the first row and second column, and the green sub-pixel G13 in the first row and third column form a pixel;

[0267] The blue sub-pixel B22 in the second row and second column, the red sub-pixel R23 in the second row and third column, and the green sub-pixel G24 in the second row and fourth column form a pixel;

[0268] The blue sub-pixel B31 in the third row and first column, the red sub-pixel R32 in the third row and second column, and the green sub-pixel G33 in the third row and third column form a pixel;

[0269] The blue sub-pixel B42 in the fourth row and second column, the red sub-pixel R43 in the fourth row and third column, and the green sub-pixel G44 in the fourth row and fourth column form a pixel;

[0270] G21 and G41 are electrically connected to the first column data line DT1;

[0271] B11, B22, B31 and B42 are all electrically connected to the second column data line DT2;

[0272] R12, R23, R32 and R43 are all electrically connected to the third column data line DT3;

[0273] G13, G24, G33 and G44 are all electrically connected to the fourth column data line DT4;

[0274] B14, B25, B34 and B45 are all electrically connected to the fifth column data line DT5;

[0275] R15, R26, R35 and R46 are all electrically connected to the sixth column data line DT6;

[0276] G16 and G36 are both electrically connected to the seventh column data line DT7;

[0277] The sub-pixels in the first row are electrically connected to the first scan line GT1, the sub-pixels in the second row are electrically connected to the second scan line GT2, the sub-pixels in the third row are electrically connected to the third scan line GT3, and the sub-pixels in the fourth row are electrically connected to the fourth scan line GT4;

[0278] The blue sub-pixel labeled B14 is in the first row and fourth column, the blue sub-pixel labeled R15 is in the first row and fifth column, and the green sub-pixel labeled G16 is in the first row and sixth column.

[0279] The green sub-pixel labeled G21 is in the second row and first column, the red sub-pixel labeled B25 is in the second row and fifth column, and the blue sub-pixel labeled R26 is in the second row and sixth column.

[0280] The red sub-pixel labeled B34 is in the third row and fourth column, the blue sub-pixel labeled R35 is in the third row and fifth column, and the blue sub-pixel labeled B36 is in the third row and sixth column.

[0281] The green sub-pixel labeled G41 is in the fourth row and first column, the red sub-pixel labeled B45 is in the fourth row and fifth column, and the red sub-pixel labeled R46 is in the fourth row and sixth column.

[0282] exist Figure 7 In at least one embodiment shown, the length of the pixel electrode in each sub-pixel along the horizontal direction is twice the length of the related pixel electrode along the horizontal direction, and the length of the pixel electrode in each sub-pixel along the vertical direction is 1 / 2 of the length of the related pixel electrode along the vertical direction.

[0283] exist Figure 7 In at least one embodiment shown, the lengths of the pixel electrodes in each sub-pixel along the horizontal direction are equal, and the lengths of the pixel electrodes in each sub-pixel along the vertical direction are equal, so as to improve display uniformity.

[0284] In at least one embodiment of the present disclosure, the pixel includes three sub-pixels with different colors;

[0285] The sub-pixel in the 2n-1th row and the 3m-2th column, the sub-pixel in the 2n-1th row and the 3m-1th column, and the sub-pixel in the 2n-1th row and the 3mth column constitute a pixel;

[0286] The sub-pixel in the 2nth row and 3mth column, the sub-pixel in the 2nth row and 3m+1th column, and the sub-pixel in the 2nth row and 3m+2th column constitute a pixel;

[0287] The sub-pixel in the 2n-1th row and the 3m-2th column is electrically connected to the 2n-1th scan line and the 3m-1th data line respectively, the sub-pixel in the 2n-1th row and the 3m-1th column is electrically connected to the 2n-1th scan line and the 3mth data line respectively, and the sub-pixel in the 2n-1th row and the 3mth column is electrically connected to the 2n-1th scan line and the 3m+1th data line respectively;

[0288] The sub-pixel in the 2nth row and the 3mth column is electrically connected to the 2nth scan line and the 3mth data line respectively, the sub-pixel in the 2nth row and the 3m+1th column is electrically connected to the 2nth scan line and the 3m+1th data line respectively, and the sub-pixel in the 2nth row and the 3m+2th column is electrically connected to the 2nth scan line and the 3m+2th data line respectively;

[0289] n and m are positive integers.

[0290] Optionally, the color of the sub-pixel in the 2n-1th row and the 3m-2th column is the same as the color of the sub-pixel in the 2nth row and the 3mth column;

[0291] The color of the sub-pixel in the 2n-1th row and the 3m-1th column is the same as the color of the sub-pixel in the 2nth row and the 3m+1th column;

[0292] The color of the sub-pixel in the 2n-1th row and the 3mth column is the same as the color of the sub-pixel in the 2nth row and the 3m+2nd column.

[0293] In a specific implementation, the at least three sub-pixels with different colors included in the pixel may be located in the same row, and at the same time, two pixels are laterally offset by the width of two sub-pixels.

[0294] like Figure 8 As shown, the red sub-pixel R11 in the first row and first column, the green sub-pixel G12 in the first row and second column, and the blue sub-pixel B13 in the first row and third column form a pixel;

[0295] The green sub-pixel G23 in the second row and third column, the blue sub-pixel B24 in the second row and fourth column, and the red sub-pixel R25 in the second row and fifth column form a pixel;

[0296] The red sub-pixel R3 in the third row and first column, the green sub-pixel G3 in the third row and second column, and the blue sub-pixel B3 in the third row and third column form a pixel;

[0297] The green sub-pixel G43 in the fourth row and third column, the blue sub-pixel B44 in the fourth row and fourth column, and the red sub-pixel R45 in the fourth row and fifth column form a pixel;

[0298] B21 and B41 are electrically connected to the first column data line DT1;

[0299] R11, R22, R31 and R42 are all electrically connected to the second column data line DT2;

[0300] G12, G23, G32 and G43 are all electrically connected to the third column data line DT3;

[0301] B13, B24, B33 and B44 are all electrically connected to the fourth column data line DT4;

[0302] R14, R25, R34 and R45 are all electrically connected to the fifth column data line DT5;

[0303] G15, G26, G35 and G46 are all electrically connected to the sixth column data line DT6;

[0304] B16 and B36 are both electrically connected to the seventh column data line DT7;

[0305] The sub-pixels in the first row are electrically connected to the first row scan line GT1, the sub-pixels in the second row are electrically connected to the second row scan line GT2, the sub-pixels in the third row are electrically connected to the third row scan line GT3, and the sub-pixels in the fourth row are electrically connected to the fourth row scan line GT4.

[0306] exist Figure 8 In at least one embodiment shown, the red sub-pixel labeled R14 is in the first row and fourth column, the green sub-pixel labeled G15 is in the first row and fifth column, and the blue sub-pixel labeled B16 is in the first row and sixth column.

[0307] The blue sub-pixel labeled B21 is in the second row and first column, the red sub-pixel labeled R22 is in the second row and second column, and the green sub-pixel labeled G26 is in the second row and sixth column.

[0308] The red sub-pixel labeled R34 is in the third row and fourth column, the green sub-pixel labeled G35 is in the third row and fifth column, and the blue sub-pixel labeled B36 is in the third row and sixth column.

[0309] The blue sub-pixel labeled B41 is in the fourth row and first column, the red sub-pixel labeled R42 is in the fourth row and second column, and the green sub-pixel labeled G46 is in the fourth row and sixth column.

[0310] exist Figure 8In at least one embodiment shown, the length of the pixel electrode in each sub-pixel along the horizontal direction is twice the length of the related pixel electrode along the horizontal direction, and the length of the pixel electrode in each sub-pixel along the vertical direction is 1 / 2 of the length of the related pixel electrode along the vertical direction.

[0311] exist Figure 8 In at least one embodiment shown, the lengths of the pixel electrodes in each sub-pixel along the horizontal direction are equal, and the lengths of the pixel electrodes in each sub-pixel along the vertical direction are equal, so as to improve display uniformity.

[0312] like Figure 9 As shown, the red sub-pixel R11 in the first row and first column, the blue sub-pixel B12 in the first row and second column, and the green sub-pixel G21 in the second row and first column form a pixel;

[0313] The green sub-pixel G13 in the first row and third column, the red sub-pixel R22 in the second row and second column, and the blue sub-pixel B23 in the second row and third column form a pixel;

[0314] The red sub-pixel R31 in the third row and first column, the blue sub-pixel B32 in the third row and second column, and the green sub-pixel G41 in the fourth row and first column form a pixel;

[0315] The green sub-pixel G33 in the third row and third column, the red sub-pixel R42 in the fourth row and second column, and the blue sub-pixel B43 in the fourth row and third column form a pixel;

[0316] G21 and G41 are both electrically connected to the first column data line DT1, R11 and R31 are both electrically connected to the second column data line DT2, B12 and B32 are both electrically connected to the third column data line DT3, G31 and G33 are both electrically connected to the fourth column data line DT4,

[0317] R11, B12 and G13 are all electrically connected to the first row scan line GT1, G21, R22 and B23 are all electrically connected to the second row scan line GT2, R31, B32 and G33 are all electrically connected to the third row scan line GT3, and G41, R42 and B43 are all electrically connected to the fourth row scan line GT4.

[0318] exist Figure 9 In at least one embodiment shown, the horizontal length of the pixel electrode in each green sub-pixel is greater than the horizontal length of the pixel electrode in each red sub-pixel, and the horizontal length of the pixel electrode in each red sub-pixel is greater than the horizontal length of the pixel electrode in each blue sub-pixel.

[0319] In each pixel, the pixel electrodes in the red sub-pixels have the same length along the horizontal direction, the pixel electrodes in the green sub-pixels have the same length along the horizontal direction, the pixel electrodes in the blue sub-pixels have the same length along the horizontal direction, the pixel electrodes in the red sub-pixels have the same length along the vertical direction, the pixel electrodes in the green sub-pixels have the same length along the vertical direction, and the pixel electrodes in the blue sub-pixels have the same length along the vertical direction, so as to improve the display uniformity of sub-pixels of the same color.

[0320] exist Figure 9 In at least one embodiment shown, the first length W1 is the length of the pixel electrode in R11 along the horizontal direction, the second length W2 is the length of the pixel electrode in B12 along the horizontal direction, and the third length W3 is the length of the pixel electrode in G13 along the horizontal direction.

[0321] exist Figure 9 In at least one embodiment shown, W3 is greater than W1 , and W1 is greater than W2 , but the present invention is not limited thereto.

[0322] like Figure 10 As shown, the red sub-pixel R11 in the first row and first column, the green sub-pixel G12 in the first row and second column, and the blue sub-pixel B21 in the second row and first column form a pixel;

[0323] The blue sub-pixel B13 in the first row and third column, the red sub-pixel R22 in the second row and second column, and the green sub-pixel G23 in the second row and third column form a pixel;

[0324] The red sub-pixel R31 in the third row and first column, the green sub-pixel G32 in the third row and second column, and the blue sub-pixel B41 in the fourth row and first column form a pixel;

[0325] The blue sub-pixel B33 in the third row and third column, the red sub-pixel R42 in the fourth row and second column, and the green sub-pixel G43 in the fourth row and third column form a pixel;

[0326] B21 and B41 are electrically connected to the first column data line DT1, R11, R22, R31 and R42 are electrically connected to the second column data line DT2, G12, G23, G32 and G43 are electrically connected to the third column data line DT3, and B31 and B33 are electrically connected to the fourth column data line DT4;

[0327] R11, G12 and B13 are all electrically connected to the first row scan line GT1, B21, R22 and G23 are all electrically connected to the second row scan line GT2, R31, G32 and B33 are all electrically connected to the third row scan line GT3, and B41, R42 and G43 are all electrically connected to the fourth row scan line GT4.

[0328] exist Figure 10In at least one embodiment shown, the horizontal length of the pixel electrode in each blue sub-pixel is greater than the horizontal length of the pixel electrode in each red sub-pixel, and the horizontal length of the pixel electrode in each red sub-pixel is greater than the horizontal length of the pixel electrode in each green sub-pixel.

[0329] In each pixel, the pixel electrodes in the red sub-pixels have the same length along the horizontal direction, the pixel electrodes in the green sub-pixels have the same length along the horizontal direction, the pixel electrodes in the blue sub-pixels have the same length along the horizontal direction, the pixel electrodes in the red sub-pixels have the same length along the vertical direction, the pixel electrodes in the green sub-pixels have the same length along the vertical direction, and the pixel electrodes in the blue sub-pixels have the same length along the vertical direction, so as to improve the display uniformity of sub-pixels of the same color.

[0330] exist Figure 10 In at least one embodiment shown, the first length W1 is the length of the pixel electrode in R11 along the horizontal direction, the fourth length W4 is the length of the pixel electrode in G12 along the horizontal direction, and the fifth length W5 is the length of the pixel electrode in B13 along the horizontal direction.

[0331] exist Figure 10 In at least one embodiment shown, W5 is greater than W1, and W1 is greater than W4, but the present invention is not limited thereto.

[0332] like Figure 11 As shown, the blue sub-pixel B11 in the first row and first column, the green sub-pixel G12 in the first row and second column, and the red sub-pixel R21 in the second row and first column form a pixel;

[0333] The red sub-pixel R13 in the first row and third column, the blue sub-pixel B22 in the second row and second column, and the green sub-pixel G23 in the second row and third column form a pixel;

[0334] The blue sub-pixel B31 in the third row and first column, the green sub-pixel G32 in the third row and second column, and the red sub-pixel R41 in the fourth row and first column form a pixel;

[0335] The red sub-pixel R33 in the third row and third column, the blue sub-pixel B42 in the fourth row and second column, and the green sub-pixel G43 in the fourth row and third column form a pixel;

[0336] R21 and R41 are both electrically connected to the first column data line DT1, B11 and B31 are both electrically connected to the second column data line DT2, G12 and G32 are both electrically connected to the third column data line DT3, and R31 and R33 are both electrically connected to the fourth column data line DT4;

[0337] The sub-pixels in the first row are electrically connected to the first row scan line GT1, the sub-pixels in the second row are electrically connected to the second row scan line GT2, the sub-pixels in the third row are electrically connected to the third row scan line GT3, and the sub-pixels in the fourth row are electrically connected to the fourth row scan line GT4.

[0338] exist Figure 11 In at least one embodiment shown, the horizontal length of the pixel electrode in each red sub-pixel is greater than the horizontal length of the pixel electrode in each blue sub-pixel, and the horizontal length of the pixel electrode in each blue sub-pixel is greater than the horizontal length of the pixel electrode in each green sub-pixel.

[0339] In each pixel, the pixel electrodes in the red sub-pixels have the same length along the horizontal direction, the pixel electrodes in the green sub-pixels have the same length along the horizontal direction, the pixel electrodes in the blue sub-pixels have the same length along the horizontal direction, the pixel electrodes in the red sub-pixels have the same length along the vertical direction, the pixel electrodes in the green sub-pixels have the same length along the vertical direction, and the pixel electrodes in the blue sub-pixels have the same length along the vertical direction, so as to improve the display uniformity of sub-pixels of the same color.

[0340] exist Figure 11 In at least one embodiment shown, the sixth length W6 is the length of the pixel electrode in B11 along the horizontal direction, the fourth length W4 is the length of the pixel electrode in G12 along the horizontal direction, and the seventh length W7 is the length of the pixel electrode in R13 along the horizontal direction.

[0341] exist Figure 11 In at least one embodiment shown, W7 is greater than W6, and W6 is greater than W4, but the present invention is not limited thereto.

[0342] In at least one embodiment of the present disclosure, see Figure 11 As shown, at least part of the data line DT is bent; the distance between two adjacent data lines DT in the first direction X is proportional to the width of the pixel electrode P between the two data lines DT in the first direction X. In this way, different pixel electrode widths can be adapted. In other words, the distance between two adjacent data lines at different positions is related to the pixel electrode width of the two adjacent data lines in the region. For example, Figure 11 , the width W6 of the pixel electrode of the first sub-pixel from the left in the first row of sub-pixels is smaller than the width W7 of the pixel electrode of the first sub-pixel from the left in the second row of sub-pixels. Accordingly, the spacing d3 between the data lines on both sides of the first sub-pixel from the left in the first row of sub-pixels is smaller than the spacing d4 between the data lines on both sides of the first sub-pixel from the left in the second row of sub-pixels. For another example, Figure 11In the second row of sub-pixels, the width W7 of the pixel electrode of the first sub-pixel from the left is greater than the width W6 of the pixel electrode of the second sub-pixel from the left. Correspondingly, in the second row of sub-pixels, the spacing d4 between the data lines on both sides of the first sub-pixel from the left is greater than the spacing d3 between the data lines on both sides of the second sub-pixel from the left.

[0343] In at least one embodiment of the present disclosure, see Figure 2B 、 Figure 2F 、 Figure 2H 、 Figure 2L 、 Figure 3B 、 Figure 3F 、 Figure 3G 、 Figure 3K As shown, the pixel electrode P includes a first slit group F1 and a second slit group F2 arranged along a first direction. Both the first slit group F1 and the second slit group F2 include multiple slits F. The multiple slits F1 in the first slit group F1 extend in the same direction, and the multiple slits F in the second slit group F2 extend in the same direction. The slits F in the first slit group F1 extend in a different direction than the slits F in the second slit group F2. In the disclosed embodiment, the pixel electrode P includes both the first and second slit groups F2, enabling dual-domain display.

[0344] In at least one embodiment of the present disclosure, see Figure 2F 、 Figure 3F As shown, the smaller angle between the slits F of the first slit group F1 and the slits F of the second slit group F2 is greater than 90°. Figure 2F As shown, the slits F of the first slit group F1 and the slits F of the second slit group F2 form a first angle β1 with the opening facing the left side, and a second angle α1 with the opening facing the right side, wherein the angle of the first angle β1 is greater than the angle of the second angle α1, that is, the second angle α1 is the smaller of the angles formed by the slits F of the first slit group F1 and the slits F of the second slit group F2, wherein the second angle α1 is greater than 90°.

[0345] Optional, see Figure 2F 、 Figure 3F As shown, the outer edge of the pixel electrode P in the first direction X can be straight, and the outer edge in the second direction Y can be folded line. The bending shape can be consistent with the bending shape of the slit. Optionally, the folded line shape is consistent with the shape of the data line.

[0346] In at least one embodiment of the present disclosure, see Figure 2L 、 Figure 3K As shown, the larger of the angles formed by the slits of the first slit group and the slits of the second slit group is less than 90°. Figure 3EAs shown, the slits F of the first slit group F1 and the slits F of the second slit group F2 form a third angle β2 with the opening facing the left side, and a fourth angle α2 with the opening facing the right side, wherein the angle of the third angle β2 is greater than the angle of the fourth angle α2, that is, the fourth angle α2 is the smaller of the angles formed by the slits F of the first slit group F1 and the slits F of the second slit group F2, wherein the fourth angle α2 is less than 90°.

[0347] Optional, see Figure 2L 、 Figure 3K As shown, the outer edge of the pixel electrode P in the first direction X can be a straight line, and the outer edge in the second direction Y can also be a straight line.

[0348] In at least one embodiment of the present disclosure, see Figure 2B 、 Figure 2E 、 Figure 2H 、 Figure 2K As shown, the data line DT includes: a plurality of routing units DT0; the plurality of routing units DT0 are arranged in sequence along the second direction Y;

[0349] The routing unit DT0 includes: a first sub-routing portion DT1, a second sub-routing portion DT2, a third sub-routing portion DT3, and a fourth routing portion DT4 connected in sequence; the first sub-routing portion DT1 and the third sub-routing portion DT3 extend along the second direction Y; the second sub-routing portion DT2 and the fourth sub-routing portion DT4 extend along the first direction X; the orthographic projections of the first sub-routing portion DT1 and the third sub-routing portion DT3 on the substrate 1 overlap with the orthographic projections of the gap between two adjacent pixel electrodes P in the first direction X on the substrate 1; the orthographic projections of the second sub-routing portion DT2 and the fourth sub-routing portion DT4 on the substrate 1 overlap with the orthographic projections of the gap between adjacent pixel electrode rows on the substrate 1.

[0350] Optional, combined Figure 2E As shown, the first sub-tracing portion DT1 and the third sub-tracing portion DT3 extend along the second direction Y, and may be a structure that extends along the second direction Y as a whole and may be partially bent.

[0351] Optional, combined Figure 2E As shown, at least one of the first sub-tracing portion DT1 and the third sub-tracing portion DT3 further includes a first sub-bend portion DT11 and a second sub-bend portion DT12; the first sub-bend portion DT11 and the second sub-bend portion DT2 extend in different directions. In embodiments of the present invention, the first sub-tracing portion DT1 and the third sub-tracing portion DT3 further include a first sub-bend portion DT11 and a second sub-bend portion DT12 to align with the curved outer edge of the pixel electrode P along the second direction Y.

[0352] Optional, combined Figure 2KAs shown, the first sub-routing portion DT1 and the third sub-routing portion DT3 may also be linear, so as to match the linear outer edge of the pixel electrode P along the second direction Y.

[0353] In at least one embodiment of the present disclosure, see Figure 3B 、 Figure 3E 、 Figure 3G 、 Figure 3J As shown, the data line DT may extend along the second direction Y as a whole, may be located between two adjacent columns of sub-pixels, and may be in a straight line, such as Figure 3J As shown; it can also be partially bent, such as Figure 3E As shown, when bending occurs, it can be consistent with the bending shape of the outer edge of the pixel electrode P along the second direction Y.

[0354] In at least one embodiment of the present disclosure, see Figure 2B-2K 、 Figure 3A-3J As shown, the array substrate further includes a common electrode layer; the common electrode layer includes a plurality of common electrodes C; the orthographic projection of the common electrodes C on the substrate 1 overlaps with the orthographic projection of the pixel electrodes P on the substrate; and the length of the common electrodes C along the first direction X is greater than the length of the common electrodes C along the second direction Y. In the disclosed embodiment, the length of the common electrodes C along the first direction X is greater than the length of the common electrodes C along the second direction Y to adapt to the shape of the pixel electrodes P, thereby forming an electric field between the two.

[0355] Optionally, the orthographic projection of the common electrode C on the substrate 1 roughly coincides with the orthographic projection of the pixel electrode P on the substrate; optionally, the orthographic projection of the outer edge of the common electrode C on the substrate 1 roughly coincides with the orthographic projection of the outer edge of the pixel electrode P on the substrate.

[0356] Optionally, the material of the common electrode C may be the same as that of the pixel electrode P.

[0357] In at least one embodiment of the present disclosure, see Figure 2B-2K 、 Figure 3A-3J As shown, the common electrode layer includes: a plurality of common electrode rows extending along a first direction X and arranged along a second direction Y; the common electrode rows include: a plurality of common electrodes C arranged along the first direction X; the array substrate further includes: a first trace C0 on the same layer as the gate line GT and extending along the first direction X; a portion of the first trace C0 is in direct contact with the common electrodes C, and the common electrodes C in the same common electrode row are electrically connected via the first trace C0, so that the common electrodes C in the same row are connected as a whole.

[0358] In at least one embodiment of the present disclosure, see Figure 2MAs shown, the common electrode layer includes: auxiliary scanning line C00, the orthographic projection of auxiliary scanning line C00 on substrate 1 can overlap with the orthographic projection of scanning line GT on substrate 1, and the patterns of the two can be the same. Optionally, auxiliary scanning line C00 and scanning line GT can be made by sharing a mask.

[0359] In at least one embodiment of the present disclosure, Figure 2B 、 Figure 2G As shown, the transistor may include: a gate (a portion that may reuse the scan line GT), a first electrode TA, a second electrode TB, and an active pattern G; a gate insulating layer 91 may be provided between the gate and the active pattern G, and a passivation layer 92 may be provided between the second electrode TB and the pixel electrode P, wherein the passivation layer 92 may have a via K, and the pixel electrode P may be connected to the second electrode TB through the via K.

[0360] Optional, combined Figure 2B-2F As shown, the common electrode C further has a first notch C2 at a position corresponding to the second electrode TB. Optionally, the orthographic projection of the second electrode TB on the substrate 1 overlaps with the orthographic projection of the first notch C2 on the substrate 1 to reduce the overlapping capacitance between the two and reduce the impact on the display panel.

[0361] Optional, combined Figure 2B-2F As shown, the scan line GT has a second gap GT1 at a position corresponding to the second sub-routing portion DT2, and the scan line GT has a third gap GT2 at a position corresponding to the data line DT; optionally, the orthographic projection of the second gap GT1 on the substrate 1 does not overlap with the orthographic projection of the second sub-routing portion DT2 on the substrate 1, and the orthographic projection of the third gap GT2 on the substrate 1 overlaps with the orthographic projection of the data line DT on the substrate 1; the depth a2 of the third gap GT2 in the second direction Y is greater than the depth a1 of the second gap GT1 in the second direction Y.

[0362] In at least one embodiment of the present disclosure, see Figure 2G As shown, when manufacturing the array substrate, a common electrode layer (including a common electrode C and a first trace C0) can be formed on the surface of the substrate 1 in sequence, and then a gate insulating layer 91 is formed, and then an active pattern G, a first pole TA, and a second pole TB are formed, and then a passivation layer 92 is formed, and a via K is etched to form, and then a pixel electrode layer (including a pixel electrode P) is formed.

[0363] The driving method described in the embodiment of the present disclosure is applied to the above-mentioned pixel structure, and the display cycle includes a plurality of driving phases arranged in sequence; the driving method includes:

[0364] In the 2n-1 driving phase, the 2n-1 scanning line is turned on, and the sub-pixels located in the 2n-1 row receive data voltages provided by corresponding data lines.

[0365] In the 2nth driving phase, the 2nth scan line is turned on, and the sub-pixels located in the 2nth row receive data voltages provided by corresponding data lines.

[0366] n is a positive integer;

[0367] In the 2n-1 driving stage, the data voltage provided by the data line is the data voltage corresponding to the sub-pixels in the 2n-1 row; in the 2n driving stage, the data voltage provided by the data line is the data voltage corresponding to the sub-pixels in the 2n row.

[0368] like Figure 12 As shown, when the array substrate according to at least one embodiment of the present disclosure includes M rows of sub-pixels and M rows of scan lines, and the sub-pixels located in the mth row are electrically connected to the mth row of scan lines (M is an integer greater than 1, and m is a positive integer less than or equal to M),

[0369] The display cycle includes a plurality of driving stages arranged in sequence; the first driving stage is labeled S1, the second driving stage is labeled S2, the third driving stage is labeled S3, and the Mth driving stage is labeled SM;

[0370] In the first driving phase S1, the first row scan line GT1 provides a high voltage signal (taking the transistors provided in the display area and electrically connected to the pixel electrodes as an N-type transistor as an example, when the transistors provided in the display area and electrically connected to the pixel electrodes are P-type transistors, a low voltage signal is provided as the transistor turn-on voltage), the data line DT provides a first data voltage D1, and the sub-pixels in the first row receive the first data voltage D1;

[0371] In the second driving phase S2, the second row scan line GT2 provides a high voltage signal, the data line DT provides a second data voltage D2, and the sub-pixels in the second row receive the second data voltage D2;

[0372] In the third driving phase S3, the third row scan line GT3 provides a high voltage signal, the data line DT provides a third data voltage D3, and the sub-pixels in the third row receive the third data voltage D3;

[0373] In the Mth driving phase SM, the Mth scan line GTM provides a high voltage signal, the data line DT provides an Mth data voltage DM, and the sub-pixels located in the Mth row receive the Mth data voltage DM.

[0374] exist Figure 12 In at least one embodiment shown, each driving phase may last for 1 hour (one row charging time);

[0375] S1 is the last 1H time included in the high-voltage time period of the first scan signal provided by GT1, S2 is the non-overlapping time period of the high-voltage time period of the first scan signal provided by GT1 and the high-voltage time period of the second scan signal provided by GT2, S3 is the non-overlapping time period between the high-voltage time period of the second scan signal provided by GT2 and the high-voltage time period of the third scan signal provided by GT3, SM is the non-overlapping time period between the high-voltage time period of the M-1th scan signal provided by the M-1th scan line and the high-voltage time period of the Mth scan signal provided by GTM.

[0376] In at least one embodiment of the present disclosure, during a high voltage period of each scan signal, the potential of each scan signal is a high voltage.

[0377] The driving method described in the embodiment of the present disclosure is applied to the above-mentioned pixel structure, and the driving method includes:

[0378] providing scan signals to the plurality of scan lines such that the 2n-1th scan signal provided by the 2n-1th scan line is the same as the 2nth scan signal provided by the 2nth scan line;

[0379] There is an overlapping period between the effective voltage period of the 2nth scan signal and the effective voltage period of the 2n+1th scan signal. During the overlapping period, the 2n-1th scan line, the 2nth scan line, the 2n+1th scan line, and the 2n+2th scan line are turned on, and the sub-pixels located in the 2n-1th row, the sub-pixels located in the 2nth row, the sub-pixels located in the 2n+1th row, and the sub-pixels located in the 2n+2th row receive data voltages provided by corresponding data lines.

[0380] n is a positive integer.

[0381] In the embodiment of the present disclosure, when the pixel structure in the array substrate operates in the DLG (dual-line gate) mode, since the sub-pixels electrically connected to the same data line have the same color, it can be achieved in the frequency doubling mode without any abnormal color problems in the display screen, and the charging time of at least some sub-pixels can be improved, the charging rate and refresh rate can be improved, and the display quality can be improved.

[0382] like Figure 13 As shown, when the array substrate according to at least one embodiment of the present disclosure includes M rows of sub-pixels and M rows of scan lines, and the sub-pixels located in the mth row are electrically connected to the mth row of scan lines (M is an integer greater than 1, and m is a positive integer less than or equal to M),

[0383] The first scan signal provided by the first scan line GT1 is the same as the second scan signal provided by the second scan line GT2, the third scan signal provided by the third scan line GT3 is the same as the fourth scan signal provided by the fourth scan line GT4, and the M-1th scan signal provided by the M-1th scan line GTM-1 is the same as the M-th scan signal provided by the M-th scan line GTM;

[0384] The display cycle includes a plurality of driving stages arranged in sequence; the first driving stage is labeled S1, the second driving stage is labeled S2, and the Mth driving stage is labeled SM;

[0385] The first driving stage S1 is an overlapping period between a high voltage period of the second scanning signal and a high voltage period of the third scanning signal;

[0386] The second driving stage S2 is an overlapping period of the high voltage period of the fourth scanning signal and the high voltage period of the fifth scanning signal provided by the fifth row of scanning lines;

[0387] The a-th driving stage Sa is the last 2H time included in the M-th scanning signal (a is a positive integer);

[0388] In the first driving phase S1, the data line DT provides the first data voltage D1, GT1, GT2, GT3 and GT4 are turned on, and the sub-pixels in the first row, the second row, the third row and the fourth row are turned on and receive the first data voltage D1;

[0389] In the second driving phase S2, the data line DT provides the third data voltage D3, GT3, GT4, the fifth scan line, and the sixth scan line are turned on, and the sub-pixels in the third row, the fourth row, the fifth row, and the sixth row are turned on to receive the third data voltage D3.

[0390] In the a-th driving phase Sa, the data line DT provides the M-1th data voltage DM-1, GTM-1 and GTM are turned on, and the sub-pixels in the M-1th row and the M-th row are turned on and receive the M-1th data voltage DM-1.

[0391] exist Figure 13 In at least one embodiment shown, each driving phase lasts for 2 hours;

[0392] The data voltage received by the sub-pixels in the 2n-1th row and the sub-pixels in the 2nth row is the same. The data voltage received by the sub-pixels in the 2n-1th row and the sub-pixels in the 2nth row can be the 2n-1th data voltage or the 2nth data voltage, or the average value of the 2n-1th data voltage and the 2nth data voltage.

[0393] The driving method described in the embodiment of the present disclosure is applied to the above-mentioned array substrate, and the driving method includes:

[0394] providing scanning signals to the plurality of scanning lines to control the plurality of scanning lines to be turned on in sequence during a display period;

[0395] In the display period, there are overlapping time periods and non-overlapping time periods between the effective time periods of the scan signals provided by at least two adjacent scan lines among the plurality of scan lines turned on in sequence;

[0396] The data voltage received by the data line during at least a portion of the overlapping time period is the same as the data voltage received by the data line during at least a portion of the non-overlapping time period.

[0397] In the embodiment of the present disclosure, when the pixel structure in the array substrate operates in the HSR (super-resolution frequency doubling) mode, since the sub-pixels electrically connected to the same data line have the same color, it can be achieved that in the frequency doubling mode, there will be no problem of abnormal color of the display screen, and the charging time of at least some sub-pixels can be improved, and the charging rate and refresh rate can be improved, thereby improving the display quality.

[0398] like Figure 14 As shown, when the array substrate according to at least one embodiment of the present disclosure includes M rows of sub-pixels and M rows of scan lines, and the sub-pixels located in the mth row are electrically connected to the mth row of scan lines (M is an integer greater than 1, and m is a positive integer less than or equal to M),

[0399] The display cycle may include a first overlapping time period J1 (optionally 1H), a first non-overlapping time period B1 (optionally 1H), a second overlapping time period J2 (optionally 1H), a second non-overlapping time period B2 (optionally 1H), an a-th overlapping time period Ja and an a-th non-overlapping time period Ba (a is a positive integer), where the first overlapping time period refers to a portion of time when adjacent rows of gate lines are simultaneously turned on, and the non-overlapping time period refers to a time period when, among the gate lines opened in sequence in adjacent rows, the first gate line turned on is closed and the later gate line turned on;

[0400] In the first overlapping period J1, the data line DT provides the first data voltage D1, GT1 and GT2 are turned on, and the first row of sub-pixels and the second row of sub-pixels receive the first data voltage D1;

[0401] In the first non-overlapping period B1, the data line DT provides the first data voltage D1, GT2 is turned on, and the sub-pixels in the second row receive the first data voltage D1, that is, in the first overlapping period and the first non-overlapping period, the sub-pixels in adjacent rows receive the same data voltage;

[0402] In the second overlapping period J2, the data line DT provides the third data voltage D3, GT3 and GT4 are turned on, and the sub-pixels in the third row and the fourth row receive the third data voltage D3;

[0403] In the second non-overlapping period B2, the data line DT provides the third data voltage D3, GT4 is turned on, and the sub-pixels in the fourth row receive the third data voltage D3;

[0404] In the ath overlapping period Ja, the data line DT provides the M-1th data voltage DM-1; GTM-1 and GTM are turned on, the M-1th row sub-pixels and the M-th row sub-pixels are turned on, and the M-1th row sub-pixels and the M-th row sub-pixels receive the M-1th data voltage DM-1;

[0405] In the ath non-overlapping period Ba, the data line DT provides the M-1th data voltage DM; the GTM is turned on, the Mth row of sub-pixels is turned on, and the Mth row of sub-pixels receives the M-1th data voltage DM-1.

[0406] exist Figure 14 In at least one embodiment shown, J1 is a partially overlapping period between a high voltage period of the first scan signal and a high voltage period of the second scan signal;

[0407] B1 is a non-overlapping period between the high voltage period of the first scanning signal and the high voltage period of the second scanning signal;

[0408] J2 is a partially overlapping period between the high voltage period of the third scan signal and the high voltage period of the fourth scan signal;

[0409] B2 is a non-overlapping period between the high voltage period of the third scan signal and the high voltage period of the fourth scan signal;

[0410] Ja is a partially overlapping period between the high voltage period of the M-1th scan signal and the high voltage period of the Mth scan signal;

[0411] Ba is a non-overlapping period between the high voltage period of the M-1th scan signal and the high voltage period of the Mth scan signal.

[0412] The pixel architecture in the embodiments of the present disclosure is applicable to display pixel modes such as TN (Twisted Nematic), IPS (In-Plane Switching), ADS (Advanced Super Dimension Switch) / FFS (Fringe Field Switching), and VA (Vertical Alignment).

[0413] The pixel architecture in the disclosed embodiment is applicable to backplane process technologies such as a-Si (amorphous silicon), Oxide (oxide), LTPS (low-temperature polycrystalline silicon), and LTPO (low-temperature polycrystalline oxide).

[0414] The display device described in the embodiment of the present disclosure includes the above-mentioned array substrate.

[0415] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. An array substrate, wherein: The method comprises a substrate, a plurality of pixels located on one side of the substrate, the pixels comprising at least three sub-pixels having different colors; The sub-pixel is provided with data lines on both sides in the first direction, and the sub-pixel is provided with scan lines on both sides in the second direction; In two adjacent rows of sub-pixels, two sub-pixels electrically connected to the same data line have the same color, and the two sub-pixels are electrically connected to different scan lines respectively; The sub-pixel includes a pixel electrode; The length of the pixel electrode along the first direction is greater than the length of the pixel electrode along the second direction; the spacing between two adjacent data lines in the first direction is proportional to the width of the pixel electrode between the two data lines in the first direction; The data line includes: a plurality of routing units; the plurality of routing units are arranged in sequence along the second direction; the routing unit includes: a first sub-routing portion, a second sub-routing portion, a third sub-routing portion, and a fourth sub-routing portion connected in sequence; the first sub-routing portion and the third sub-routing portion extend along the second direction; the second sub-routing portion and the fourth sub-routing portion extend along the first direction; The array substrate includes: a common electrode layer and a plurality of transistors; the common electrode layer includes: a plurality of common electrodes; the pixel electrodes are electrically connected to the scan lines and the data lines through transistors; the transistors include a first electrode and a second electrode; The common electrode has a first notch, and the orthographic projection of the first notch on the substrate overlaps with the orthographic projection of the second electrode on the substrate; the scan line has a second notch, and the orthographic projection of the second notch on the substrate overlaps with the orthographic projection of the second sub-routing portion or the third sub-routing portion on the substrate; the scan line also has a third notch, and the orthographic projection of the third notch on the substrate overlaps with the orthographic projection of the data line on the substrate, and the depth of the third notch in the second direction is greater than the depth of the second notch in the second direction.

2. The array substrate according to claim 1, wherein: The pixel includes three sub-pixels having different colors; The two sub-pixels included in the pixel are located in the 2n-1th row, and the sub-pixels included in the pixel other than the two sub-pixels are located in the 2nth row; wherein n is a positive integer.

3. The array substrate according to claim 2, wherein: The array substrate includes: a plurality of pixel rows; the pixel rows include: a plurality of first pixels and a plurality of second pixels; the first pixels and the second pixels are alternately arranged along the first direction; The first pixel includes: a first sub-pixel, a second sub-pixel, and a third sub-pixel; wherein the first sub-pixel and the second sub-pixel are located in the 2n-1th row; and the third sub-pixel is located in the 2nth row; The second pixel includes: a fourth sub-pixel, a fifth sub-pixel, and a sixth sub-pixel; wherein the fourth sub-pixel is located in the 2n-1th row; the fifth sub-pixel and the sixth sub-pixel are located in the 2nth row.

4. The array substrate according to claim 3, wherein: The pixel electrode of the first subpixel has a first axis, which extends along the second direction and passes through a central area of ​​the pixel electrode of the first subpixel; the pixel electrode of the second subpixel has a second axis, which extends along the second direction and passes through a central area of ​​the pixel electrode of the second subpixel; the pixel electrode of the third subpixel has a third axis, which extends along the second direction and passes through a central area of ​​the pixel electrode of the third subpixel; The pixel electrode of the fourth subpixel has a fourth axis, which extends along the second direction and passes through a central area of ​​the pixel electrode of the fourth subpixel; the pixel electrode of the fifth subpixel has a fifth axis, which extends along the second direction and passes through a central area of ​​the pixel electrode of the fifth subpixel; and the pixel electrode of the sixth subpixel has a sixth axis, which extends along the second direction and passes through a central area of ​​the pixel electrode of the sixth subpixel. The orthographic projection of the third axis on the substrate is located between the orthographic projection of the first axis on the substrate and the orthographic projection of the second axis on the substrate; The orthographic projection of the fourth axis on the substrate is located between the orthographic projection of the fifth axis on the substrate and the orthographic projection of the sixth axis on the substrate.

5. The array substrate according to claim 4, wherein: The distance between the first axis and the third axis is d1, and the distance between the fourth axis and the fifth axis is d2. d1 and d2 satisfy the following relationship: 0≤d1≤w / 2; 0≤d2≤w2; wherein w represents the width of the pixel electrode.

6. The array substrate according to claim 4 or 5, wherein: The center of the pixel electrode of the first sub-pixel, the center of the pixel electrode of the second sub-pixel, the center of the pixel electrode of the third sub-pixel, and the center of the pixel electrode of the fifth sub-pixel form a parallelogram; The center of the pixel electrode of the second sub-pixel, the center of the pixel electrode of the fourth sub-pixel, the center of the pixel electrode of the fifth sub-pixel, and the center of the pixel electrode of the sixth sub-pixel form a parallelogram.

7. The array substrate according to claim 3, wherein: The pixel electrode of the first subpixel has a first axis, which extends along the second direction and passes through a central area of ​​the pixel electrode of the first subpixel; the pixel electrode of the second subpixel has a second axis, which extends along the second direction and passes through a central area of ​​the pixel electrode of the second subpixel; the pixel electrode of the third subpixel has a third axis, which extends along the second direction and passes through a central area of ​​the pixel electrode of the third subpixel; The pixel electrode of the fourth subpixel has a fourth axis, which extends along the second direction and passes through a central area of ​​the pixel electrode of the fourth subpixel; the pixel electrode of the fifth subpixel has a fifth axis, which extends along the second direction and passes through a central area of ​​the pixel electrode of the fifth subpixel; and the pixel electrode of the sixth subpixel has a sixth axis, which extends along the second direction and passes through a central area of ​​the pixel electrode of the sixth subpixel. The orthographic projection of the third axis on the substrate coincides with the orthographic projection of the first axis on the substrate; The orthographic projection of the fifth axis on the substrate coincides with the orthographic projection of the second axis on the substrate; The orthographic projection of the fourth axis on the substrate coincides with the orthographic projection of the sixth axis on the substrate.

8. The array substrate according to claim 7, wherein: The plurality of sub-pixels are distributed in an array; the first sub-pixel is located at the 2n-1th row and the 3m-2th column, the second sub-pixel is located at the 2n-1th row and the 3m-1th column, and the third sub-pixel is located at the 2nth row and the 3m-2th column; The fourth sub-pixel is located at the 2n-1th row and the 3mth column, the fifth sub-pixel is located at the 2nth row and the 3m-1th column, and the sixth sub-pixel is located at the 2nth row and the 3mth column; wherein m is a positive integer.

9. The array substrate according to claim 3, wherein: The first sub-pixel is electrically connected to the 2n-1th scan line and the 3m-1th data line, respectively; the second sub-pixel is electrically connected to the 2n-1th scan line and the 3mth data line, respectively; and the third sub-pixel is electrically connected to the 2nth scan line and the 3m-2th data line, respectively; The fourth sub-pixel is electrically connected to the 2n-1th scan line and the 3m+1th data line respectively, the fifth sub-pixel is electrically connected to the 2nth scan line and the 3m-1th data line respectively, and the sixth sub-pixel is electrically connected to the 2nth scan line and the 3mth data line respectively.

10. The array substrate according to claim 3, wherein: The first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel; The fourth sub-pixel is a blue sub-pixel, the fifth sub-pixel is a red sub-pixel, and the sixth sub-pixel is a green sub-pixel.

11. The array substrate according to claim 3, wherein: The first sub-pixel is a red sub-pixel, the second sub-pixel is a blue sub-pixel, and the third sub-pixel is a green sub-pixel; The fourth sub-pixel is a green sub-pixel, the fifth sub-pixel is a red sub-pixel, and the sixth sub-pixel is a blue sub-pixel.

12. The array substrate according to claim 3, wherein: The first sub-pixel is a blue sub-pixel, the second sub-pixel is a red sub-pixel, and the third sub-pixel is a green sub-pixel; The fourth sub-pixel is a green sub-pixel, the fifth sub-pixel is a blue sub-pixel, and the sixth sub-pixel is a red sub-pixel.

13. The array substrate according to claim 1, wherein: The pixel includes at least three sub-pixels with different colors located in the same row.

14. The array substrate according to claim 13, wherein: The plurality of sub-pixels are distributed in an array; the pixel includes three sub-pixels with different colors; The sub-pixel in the 2n-1th row and the 3m-2th column, the sub-pixel in the 2n-1th row and the 3m-1th column, and the sub-pixel in the 2n-1th row and the 3mth column constitute a pixel; The sub-pixel in the 3m-1 column of the 2nth row, the sub-pixel in the 3mth column of the 2nth row, and the sub-pixel in the 3m-1th column of the 2nth row constitute a pixel; The sub-pixel in the 2n-1th row and the 3m-2th column is electrically connected to the 2n-1th scan line and the 3m-1th data line respectively, the sub-pixel in the 2n-1th row and the 3m-1th column is electrically connected to the 2n-1th scan line and the 3mth data line respectively, and the sub-pixel in the 2n-1th row and the 3mth column is electrically connected to the 2n-1th scan line and the 3m+1th data line respectively; The sub-pixel in the 2nth row and the 3m-1th column is electrically connected to the 2nth scan line and the 3m-1th data line respectively, the sub-pixel in the 2nth row and the 3mth column is electrically connected to the 2nth scan line and the 3mth data line respectively, and the sub-pixel in the 2nth row and the 3m+1th column is electrically connected to the 2nth scan line and the 3m+1th data line respectively; wherein n and m are positive integers.

15. The array substrate according to claim 14, wherein: The color of the sub-pixel in the 2n-1th row and the 3m-2th column is the same as the color of the sub-pixel in the 2nth row and the 3m-1th column; The color of the sub-pixel in the 2n-1th row and the 3m-1th column is the same as the color of the sub-pixel in the 2nth row and the 3mth column; The color of the sub-pixel in the 2n-1th row and the 3mth column is the same as the color of the sub-pixel in the 2nth row and the 3m+1th column.

16. The array substrate according to claim 15, wherein: The pixel includes three sub-pixels having different colors; The sub-pixel in the 2n-1th row and the 3m-2th column, the sub-pixel in the 2n-1th row and the 3m-1th column, and the sub-pixel in the 2n-1th row and the 3mth column constitute a pixel; The sub-pixel in the 2nth row and 3mth column, the sub-pixel in the 2nth row and 3m+1th column, and the sub-pixel in the 2nth row and 3m+2th column constitute a pixel; The sub-pixel in the 2n-1th row and the 3m-2th column is electrically connected to the 2n-1th scan line and the 3m-1th data line respectively, the sub-pixel in the 2n-1th row and the 3m-1th column is electrically connected to the 2n-1th scan line and the 3mth data line respectively, and the sub-pixel in the 2n-1th row and the 3mth column is electrically connected to the 2n-1th scan line and the 3m+1th data line respectively; The sub-pixel in the 2nth row and 3mth column is electrically connected to the 2nth scan line and the 3mth data line respectively, the sub-pixel in the 2nth row and 3m+1th column is electrically connected to the 2nth scan line and the 3m+1th data line respectively, and the sub-pixel in the 2nth row and 3m+2th column is electrically connected to the 2nth scan line and the 3m+2th data line respectively; wherein n and m are positive integers.

17. The array substrate according to claim 16, wherein: The color of the sub-pixel in the 2n-1th row and the 3m-2th column is the same as the color of the sub-pixel in the 2nth row and the 3mth column; The color of the sub-pixel in the 2n-1th row and the 3m-1th column is the same as the color of the sub-pixel in the 2nth row and the 3m+1th column; The color of the sub-pixel in the 2n-1th row and the 3mth column is the same as the color of the sub-pixel in the 2nth row and the 3m+2nd column.

18. The array substrate according to claim 1, wherein: A ratio of a length of the pixel electrode along the first direction to a length of the pixel electrode along the second direction is greater than 1 and less than or equal to 2.

19. The array substrate according to claim 1, wherein: A ratio of a length of two adjacent rows and two columns of pixel electrodes along the first direction to a length of two adjacent rows and two columns of pixel electrodes along the second direction is greater than or equal to 1.2 and less than or equal to 1.

8.

20. The array substrate according to claim 1, wherein: The lengths of the pixel electrodes in sub-pixels with the same color in different pixels along the first direction are the same; The lengths of the pixel electrodes in sub-pixels of the same color in different pixels along the second direction are the same.

21. The array substrate according to claim 1, wherein: The pixel electrodes of at least two sub-pixels included in the same pixel have the same length along the first direction.

22. The array substrate according to claim 1, wherein: The lengths of the pixel electrodes in at least two sub-pixels included in the same pixel are different along the first direction.

23. The array substrate according to claim 1, wherein: The pixel electrode includes: a first slit group and a second slit group arranged along the first direction; the first slit group and the second slit group each include: a plurality of slits; The multiple slits in the first slit group extend in the same direction; the multiple slits in the second slit group extend in the same direction; and the slits in the first slit group extend in a direction different from that in the second slit group.

24. The array substrate according to claim 23, wherein: The smaller of the angles formed by the slits of the first slit group and the slits of the second slit group is less than 90 o .

25. The array substrate according to claim 23, wherein: The larger of the angles formed by the slits of the first slit group and the slits of the second slit group is greater than 90 o .

26. The array substrate according to claim 4, wherein: The orthographic projections of the first sub-routing portion and the third sub-routing portion on the substrate overlap with the orthographic projections of the gap between two adjacent pixel electrodes in the first direction on the substrate; the orthographic projections of the second sub-routing portion and the fourth sub-routing portion on the substrate overlap with the orthographic projections of the gap between adjacent pixel electrode rows on the substrate.

27. The array substrate according to claim 26, wherein: At least one of the first sub-routing portion and the third sub-routing portion further includes: a first sub-bending portion and a second sub-bending portion; The first sub-bending portion and the second sub-bending portion extend in different directions.

28. The array substrate according to claim 22, wherein: At least part of the data lines is bent; and a distance between two adjacent data lines in the first direction is proportional to a width of the pixel electrode between the two data lines in the first direction.

29. The array substrate according to claim 1, wherein: The orthographic projection of the common electrode on the substrate overlaps with the orthographic projection of the pixel electrode on the substrate; The length of the common electrode along the first direction is greater than the length of the common electrode along the second direction.

30. The array substrate according to claim 29, wherein: The common electrode layer includes: a plurality of common electrode rows extending along the first direction and arranged along the second direction; the common electrode rows include: a plurality of common electrodes arranged along the first direction; the array substrate further includes: a first trace in the same layer as the gate line and extending along the first direction; The first wiring portion is in direct contact with the common electrode, and the common electrodes in the same common electrode row are electrically connected via the first wiring.

31. A driving method, applied to the array substrate according to any one of claims 1 to 30, wherein a display cycle includes a plurality of driving phases arranged in sequence; the driving method comprising: In the 2n-1 driving phase, the 2n-1 scanning line is turned on, and the sub-pixels located in the 2n-1 row receive data voltages provided by corresponding data lines. In the 2nth driving phase, the 2nth scan line is turned on, and the sub-pixels located in the 2nth row receive data voltages provided by corresponding data lines; n is a positive integer; In the 2n-1 driving stage, the data voltage provided by the data line is the data voltage corresponding to the sub-pixels in the 2n-1 row; in the 2n driving stage, the data voltage provided by the data line is the data voltage corresponding to the sub-pixels in the 2n row.

32. A driving method, applied to the array substrate according to any one of claims 1 to 30, the driving method comprising: providing scan signals to the plurality of scan lines such that the 2n-1th scan signal provided by the 2n-1th scan line is the same as the 2nth scan signal provided by the 2nth scan line; There is an overlapping period between the effective voltage period of the 2nth scan signal and the effective voltage period of the 2n+1th scan signal. During the overlapping period, the 2n-1th scan line, the 2nth scan line, the 2n+1th scan line, and the 2n+2th scan line are turned on, and the sub-pixels located in the 2n-1th row, the sub-pixels located in the 2nth row, the sub-pixels located in the 2n+1th row, and the sub-pixels located in the 2n+2th row receive data voltages provided by corresponding data lines. n is a positive integer.

33. A driving method, applied to the array substrate according to any one of claims 1 to 30, the driving method comprising: providing scanning signals to the plurality of scanning lines to control the plurality of scanning lines to be turned on in sequence during a display period; In the display period, there are overlapping time periods and non-overlapping time periods between the effective time periods of the scan signals provided by at least two adjacent scan lines among the plurality of scan lines turned on in sequence; The data voltage received by the data line during at least a portion of the overlapping time period is the same as the data voltage received by the data line during at least a portion of the non-overlapping time period.

34. A display device comprising the array substrate according to any one of claims 1 to 30.

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