Method for forming low resistance contact

Abstract

A method for reducing contact resistance includes performing a selective titanium silicide (TiSi) deposition process on an intermediate process (MOL) contact structure including a cavity in a substrate of dielectric material. The contact structure also includes a silicon-based connection portion at the bottom of the cavity. The selective TiSi deposition process is selective for silicon-based materials relative to dielectric materials. The method also includes performing a selective deposition process of a metal material on the MOL contact structure. The selective deposition process is selective for the TiSi material relative to the dielectric material and forms a silicide capping layer on the silicon-based connection portion. The method further includes performing a seed layer deposition process of a metallic material on the contact structure.

Description

Technical Field

[0001] Embodiments of the present principles generally relate to semiconductor chambers used in semiconductor processing. Background Art

[0002] Middle of the line (MOL) contacts allow connections to be made between front end of the line (FEOL) semiconductor structures and back end of the line (BEOL) interconnects. When MOL contacts have high resistance, these contacts create poor connections between FEOL structures and BEOL packaging interconnects, thereby reducing the performance of the packaged semiconductor structure. In conventional MOL contact formation, titanium silicide (TiSi) is formed as a capping layer on silicon or silicon germanium connections, and then the titanium silicide is nitrided to form titanium silicon nitride (TiSiN) to prevent TiSi oxidation. The final silicide capping layer is a double layer of TiSi and TiSiN. However, the inventors have found that the TiSiN layer has a high resistivity (approximately 300 μΩ / cm for a thickness of approximately 6 nm).

[0003] Therefore, the inventors have provided improved methods to reduce MOL contact resistance by forming contacts without using high resistance TiSiN or TiN layers. Summary of the invention

[0004] Methods for reducing inter-process contact resistance are provided herein.

[0005] In some embodiments, a method for reducing contact resistance may include: performing a selective titanium silicide (TiSi) deposition process on a middle-of-line (MOL) contact structure, the middle-of-line (MOL) contact structure including a cavity in a substrate of a dielectric material and a silicon-based connection portion at the bottom of the cavity, wherein the selective TiSi deposition process is selective to the silicon-based material relative to the dielectric material, and a TiSi layer of approximately 3 nm to approximately 6 nm is formed on the silicon-based connection portion; performing a selective deposition process of a metal material on the MOL contact structure, wherein the selective deposition process is selective to the TiSi material relative to the dielectric material and forms a silicide capping layer on the silicon-based connection portion; and performing a seed layer deposition process of the metal material on the contact structure, wherein the thickness of the metal material deposited on the contact structure is approximately 2 nm to approximately 3 nm.

[0006] In some embodiments, the method may further include: the dielectric material is silicon dioxide or silicon nitride, wherein the silicon-based connecting portion is silicon or silicon germanium, and wherein the silicon-based material is silicon or silicon germanium; wherein the selective TiSi deposition process is a chemical vapor deposition (CVD) process having a selectivity of at least 30:1 between the silicon-based material and the dielectric material; wherein the selective deposition process is a fluorine-free metal deposition process for the metal material; wherein the fluorine-free metal deposition process is a halide-based atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process using a metal chloride gas together with hydrogen or a process using a metal organic precursor; wherein the seed layer deposition process is a plasma vapor deposition (PVD) process. The invention relates to a method of manufacturing a MOL contact structure according to the present invention, wherein the metal material is tungsten or molybdenum, and wherein the metal material is tungsten or molybdenum. The method comprises the following steps: performing a pre-cleaning process on the MOL contact structure before performing a selective TiSi deposition process; performing a selective etching process to remove a portion of the metal material deposited on the sidewall of the cavity of the MOL contact structure by the seed layer deposition process, while maintaining the metal material on the bottom of the contact structure and on the silicon-based connecting portion; and depositing a metal gap filling material in a bottom-up selective deposition process to fill the MOL contact structure, wherein the selective etching process is a dry etching process or a wet etching process, wherein the bottom-up selective deposition process is a selective chemical vapor deposition (CVD) process; depositing the metal gap filling material in the cavity of the MOL contact structure using a conformal deposition process; and / or wherein the method uses a mixture of a tungsten material and a molybdenum material in the method.

[0007] In some embodiments, a method for reducing contact resistance may include: performing a selective titanium silicide (TiSi) deposition process on a middle-of-line (MOL) contact structure, the middle-of-line (MOL) contact structure including a cavity in a substrate of a dielectric material together with a silicon-based connection portion at the bottom of the cavity, wherein the selective TiSi deposition process is selective to the silicon-based material relative to the dielectric material, and a TiSi layer of approximately 3 nm to approximately 6 nm is formed on the silicon-based connection portion; performing an in-situ selective deposition process of fluorine-free tungsten on the MOL contact structure, wherein the selective deposition process is selective to the TiSi material relative to the dielectric material and forms a silicide capping layer on the silicon-based connection portion; performing a tungsten seed layer deposition process on the contact structure, wherein the thickness of the tungsten deposited on the contact structure is approximately 2 nm. nm to about 3 nm; performing a selective etching process to remove a portion of the tungsten deposited on the sidewalls of the cavity of the MOL contact structure by the seed layer deposition process while maintaining the tungsten on the bottom of the contact structure and on the silicon-based connecting portion; and depositing a tungsten gap-fill material in a bottom-up selective deposition process to fill the MOL contact structure.

[0008] In some embodiments, the method may further include: the dielectric material is silicon oxide or silicon nitride, wherein the silicon-based connecting portion is silicon or silicon germanium, and wherein the silicon-based material is silicon or silicon germanium; wherein the selective TiSi deposition process is a chemical vapor deposition (CVD) process having a selectivity of at least 30:1 between silicon-based material and dielectric material; wherein the selective deposition process is a halide-based atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process using tungsten chloride gas together with hydrogen gas or a process using a metal organic precursor; wherein the seed layer deposition process is a plasma vapor deposition (PVD) process that anneals the tungsten deposited by the selective deposition process; and / or wherein the bottom-up selective deposition process is a selective chemical vapor deposition (CVD) process.

[0009] In some embodiments, a non-transitory computer readable medium having instructions stored thereon is provided, the instructions, when executed, causing a method for reducing contact resistance to be performed, the method comprising performing a selective titanium silicide (TiSi) deposition process on a middle-of-line (MOL) contact structure, the middle-of-line (MOL) contact structure comprising a cavity in a substrate of a dielectric material together with a silicon or silicon germanium connection portion at a bottom of the cavity, wherein the selective TiSi deposition process is selective to the silicon or silicon germanium material relative to the dielectric material, and a TiSi layer of about 3 nm to about 6 nm is formed on the silicon or silicon germanium connection portion; performing an in-situ selective deposition process of fluorine-free tungsten on the MOL contact structure, wherein the selective deposition process is selective to the TiSi material relative to the dielectric material and forms a silicide capping layer on the silicon or silicon germanium connection portion; performing a tungsten seed layer deposition process on the contact structure, wherein the thickness of the tungsten deposited on the contact structure is about 2 nm to about 3 nm. nm; performing a selective etching process to remove a portion of the tungsten deposited on the sidewalls of the cavity of the MOL contact structure by the seed layer deposition process, while maintaining the tungsten on the bottom of the contact structure and on the silicon or silicon germanium connecting portion; and depositing a tungsten gap fill material in a bottom-up selective deposition process to fill the MOL contact structure.

[0010] Other and further embodiments are disclosed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Embodiments of the present invention principles briefly summarized above and discussed in more detail below can be understood by reference to the illustrative embodiments of the present invention principles depicted in the accompanying drawings. However, the accompanying drawings depict only typical embodiments of the present invention principles and therefore should not be considered limiting of the scope, as the present invention principles may admit to other equally effective embodiments.

[0012] Figure 1 Methods for reducing contact resistance according to some embodiments of the present invention are provided.

[0013] Figure 2 A cross-sectional diagram depicting a contact resistance reduction process according to some embodiments of the present principles.

[0014] Figure 3 An integrated tool according to some embodiments of the present principles is described.

[0015] For ease of understanding, the same reference numerals have been used, where possible, to represent the same elements common to the figures. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated into other embodiments without repetition. DETAILED DESCRIPTION

[0016] These methods provide middle of the line (MOL) contacts with reduced resistivity. The innovative integrated flow integrates multiple MOL processes on the same integrated tool, thereby eliminating high resistivity materials in the integrated stack to achieve low contact resistance (Rc). The titanium silicide (TiSi) capping layer is capped with a selective tungsten (W) followed by a plasma vapor deposition (PVD) tungsten seed layer to eliminate the need for high resistivity titanium silicon nitride (TiSiN) and titanium nitride (TiN) from the contact film stack to achieve low contact Rc. The MOL contact integration flow advantageously completely removes the need for TiSiN and TiN film layers. Selective tungsten deposition is then used to achieve bottom-up tungsten fill in some embodiments to further reduce Rc. The method of the present principles also utilizes a highly selective chemical vapor deposition (CVD) TiSi deposition process together with an in-situ TiSi / W integration flow, which eliminates the high resistivity TiSiN film layer and reduces the thickness of the high cost fluorine free tungsten (FFW) deposition process.

[0017] In short, the integrated flow provides several key integration benefits for the MOL contact structure. Highly selective CVD TiSi deposition on Si eliminates TiSiN capping layer (which reduces contact Rc), FFW+PVD W metal capping (which reduces thickness requirements of FFW and PVD W as oxide and F barriers), simple and low-cost dry process for TiSi / W pull-back (etch), integrated bottom-up fill W flow to reduce overall Rc and cost, integrated conformal W fill, and W can be replaced by Mo capping layer and gap fill. In some embodiments, for example, in accordance with the method of the present principles, in the presence of a capping layer, removing the TiSiN layer in the process reduces the resistivity of the silicide cap layer from about 300 μΩ / cm (for a TiSiN layer thickness of about 6nm) to about less than 20 μΩ / cm.

[0018] The methods disclosed herein are generally effective for metal gapfill processes and can be used with other metal gapfill materials besides tungsten, such as but not limited to molybdenum and the like. For simplicity, the examples discussed use tungsten but are not meant to be limited to use with only tungsten. Figure 1 In method 100, highly selective CVD TiSi deposition and in-situ TiSi / W integration processes eliminate the highly resistive TiSiN layer and reduce the costly fluorine-free metal thickness (metal cap thickness). In the discussion of method 100, reference will be made to Figure 2 In block 102, as in Figure 2As depicted in view 200A of FIG. 1 , a pre-cleaning process is performed to remove any contaminants and / or oxides from the surface of the contact structure. The contact structure has a silicon-based portion 204 exposed in a cavity 210 of a substrate 202 formed of a dielectric material (e.g., silicon dioxide, silicon nitride, etc.). In some embodiments, the silicon-based portion 204 may be a silicon material or a silicon germanium (SiGe) material.

[0019] In block 104, as in Figure 2 200B, a selective TiSi deposition process is performed to produce a TiSi layer 206 on the silicon-based portion 204. The process is selective to the silicon-based portion 204 relative to the dielectric material of the substrate 202, but a thin TiSi layer 208 may also be formed on the surface of the field 222 of the substrate 202 and on the sidewalls 224 in the cavity 210, including the bottom surface 226 of the cavity 210. In some embodiments, the selective TiSi deposition process is a CVD TiSi process having a selectivity of greater than about 30:1 for silicon (Si) or silicon germanium (SiGe) to oxide / SiN. With a TiSi deposition thickness of about 3 nm to about 6 nm on the silicon-based portion 204, the selectivity loss on the sidewalls 224 and bottom surface 226 of the field 222 or cavity 210 is generally less than about 1 angstrom to about 3 angstroms. Therefore, the CVD TiSi process provides a good basis for in-situ selective FFW growth.

[0020] In block 106, as in Figure 2 As depicted in view 200C of , a selective metal cap 212 is deposited on the TiSi layer 206 on the silicon base portion 204. The selective metal cap 212 may be deposited using a selective deposition process that is a fluorine-free metal deposition process for forming the metal material of the selective metal cap 212. In some embodiments, the selective metal cap 212 may be formed of tungsten. In some embodiments, the selective metal cap 212 may be formed of molybdenum. For example, in some embodiments, an in-situ selective FFW material is deposited on the TiSi layer as a silicide capping layer. In doing so, because the in-situ deposition process eliminates exposure of the TiSi layer to oxygen prior to deposition of the selective metal cap 212, a highly resistive TiSiN layer is eliminated from the process flow. In some embodiments, the selective FFW process may be from a halide-based atomic layer deposition (ALD) process. In some embodiments, the selective FFW process may be from a metal chloride process, such as from a CVD (WCl5+H2) process or from a CVD (WCl6+H2) process. In some embodiments, the selective FFW process may be from a process using metal organic precursors.

[0021] In block 108, as in Figure 2As depicted in view 200D of FIG. 2 , a thin metal seed layer 214 is deposited in cavity 210 and on field 222. In some embodiments, the selective metal cap 212 may be formed of tungsten. In some embodiments, the selective metal cap 212 may be formed of molybdenum. In some embodiments, for example, a thin PVD W layer provides W seed on the bottom of cavity 210 (e.g., SiO2 or SiN surface where selective FFW cannot grow). The PVD process may be biased to produce anisotropic deposition (field and deposition on the bottom of the cavity more than on the sidewalls of the cavity, etc.). PVD plasma bombardment of the selective ALD or CVD FFW may anneal the FFW film and improve the oxidation and F barrier properties of the FFW film, which in turn reduces the FFW thickness requirements. The PVD W no longer acts as a TiSi protective layer (as in conventional processes), but only serves to provide a seed layer on the bottom oxide surface for the selective CVD W. Therefore, the bottom thickness requirement of the thin metal seed layer 214 is reduced from about 4 nm to about 5 nm to about 2 nm to about 3 nm. The thin PVD W layer also simplifies the W pull-back (etch) process (for bottom-up gapfill process), especially for the selective dry pull-back process.

[0022] After deposition of the thin metal seed layer 214, a process may be used to perform bottom-up gap filling (blocks 110, 112, Figure 2 218 in FIG. 1 ) or performing a conformal gap fill process (block 114 , Figure 2 For a bottom-up gap fill process, in block 110, as in Figure 2 As depicted in view 200E of FIG. 200A , a selective etching process is performed. For example, a simple and low-cost in-situ dry etching or wet etching process can remove about 3 nm to about 4 nm of a thin metal seed layer 214 (e.g., PVD W, etc.) on the sidewalls 224 of the field 222 and the cavity 210, leaving a bottom surface 226 having a portion of the thin metal seed layer 214 (see FIG. 200B ). Figure 2 200E). The tungsten pullback need not be performed in situ (in the same integrated tool as the above process). In block 112, as in Figure 2 As depicted in view 200F of FIG. 2 , a metal gap fill material 228 is deposited in a bottom-up selective process (e.g., a tungsten hexafluoride (WF6) based selective process (tungsten on top of dielectric material of sidewalls 224 of cavity 210, etc.). After wet / dry pull-back (etching), only the FFW+PVD W seed layer is left at the bottom of the structure and on the silicon base portion, which (e.g.) provides a seed layer for the selective CVD W bottom-up gap fill. In some embodiments, a portion of the thin metal seed layer 214 on the selective metal cap 212 protects the selective metal cap 212 during the etching process.

[0023] In some embodiments, after depositing a thin metal seed layer 214 (block 108 ) (see Figure 2 In block 114, a conformal deposition process is used to deposit a metal gap filler, as depicted in views 200G to 200I. In some embodiments, for example, cavity 210 may be filled by conformal CVD using tungsten or molybdenum and the like. In some embodiments, conformal molybdenum filling may be performed by using a MoO2Cl2 or MoOCl4+H2 process or a mixture of MoCl5 and the two precursors. View 200G depicts a first layer 216A of the conformal filling process. View 200H depicts an additional layer 216B of the conformal filling process. View 200I depicts a filled cavity 216C.

[0024] As previously mentioned, in addition to using tungsten as the TiSi capping layer, the selective Mo process can also use molybdenum (Mo) as the capping material. The thin metal seed layer 214 can also be a thin PVD Mo seed layer. Similarly, structural filling can be performed by selective Mo filling or conformal Mo filling. In some embodiments, Mo and W materials can be interchanged or a mixture of Mo and W can be used.

[0025] The methods described herein may be performed in individual process chambers that may be provided as part of a cluster tool, such as described below with respect to Figure 3 An integrated tool 300 (i.e., a cluster tool) is described. An advantage of using the integrated tool 300 is that there is no vacuum break between chambers, and therefore, there is no need to degas and pre-clean the substrate prior to processing in the chamber. For example, in some embodiments, the inventive method discussed above may be advantageously performed in an integrated tool such that there is limited or no vacuum break between processes, thereby limiting or preventing contamination of the substrate, such as oxidation and the like. The integrated tool 300 includes a vacuum sealed processing platform 301, a factory interface 304, and a system controller 302. The processing platform 301 includes a plurality of processing chambers, such as 314A, 313B, 314C, 314D, 314E, and 314F, operatively coupled to a vacuum substrate transfer chamber (transfer chambers 303A, 303B). The factory interface 304 interfaces with one or more load lock chambers (two load lock chambers, such as, Figure 3 306A and 306B) are operatively coupled to the transfer chamber 303A.

[0026] In some embodiments, the factory interface 304 includes at least one docking station 307 and at least one factory interface robot 338 to facilitate the transfer of semiconductor substrates. The docking station 307 is configured to receive one or more front opening unified pods (FOUPs). Figure 3 In the embodiment of FIG. 3 , four FOUPs are shown, such as 305A, 305B, 305C, and 305D. The factory interface robot 338 is configured to transfer substrates from the factory interface 304 to the processing platform 301 via load lock chambers, such as 306A and 306B. Each of the load lock chambers 306A and 306B has a first port coupled to the factory interface 304 and a second port coupled to the transfer chamber 303A. The load lock chambers 306A and 306B are coupled to a pressure control system (not shown) that pumps and evacuates the load lock chambers 306A and 306B to facilitate the transfer of substrates between the vacuum environment of the transfer chamber 303A and the substantially ambient (e.g., atmospheric pressure) environment of the factory interface 304. The transfer chambers 303A, 303B have vacuum robots 342A, 342B disposed in the respective transfer chambers 303A, 303B. The vacuum robot 342A can transfer the substrate 321 between the load lock chambers 306A, 306B, the processing chambers 314A and 314F, and the cooling station 340 or the pre-cleaning station 342. The vacuum robot 342B can transfer the substrate 321 between the cooling station 340 or the pre-cleaning station 342 and the processing chambers 341B, 314C, 314D, and 314E.

[0027] In some embodiments, processing chambers 314A, 314B, 314C, 314D, 314E, and 314F are coupled to transfer chambers 303A, 303B. Processing chambers 314A, 314B, 314C, 314D, 314E, and 314F may include, for example, pre-clean chambers, ALD process chambers, PVD process chambers, remote plasma chambers, CVD chambers, or the like. These chambers may include any chamber suitable for performing all or part of the methods described herein (as discussed above), such as, for example, PVD W or PVD Mo chambers, CVD chambers, ALD chambers, and the like. In some embodiments, one or more optional service chambers (shown as 316A and 316B) may be coupled to transfer chamber 303A. Service chambers 316A and 316B may be configured to perform other substrate processes, such as, degassing, orientation, substrate metrology, cooling, and the like.

[0028] The system controller 302 controls the operation of the tool 300 using direct control of the process chambers 314A, 314B, 314C, 314D, 314E, and 314F or by controlling a computer (or controller) associated with the process chambers 314A, 314B, 314C, 314D, 314E, and 314F and the tool 300. In operation, the system controller 302 enables data collection and feedback from the corresponding chambers and systems to optimize the performance of the tool 300. The system controller 302 generally includes a central processing unit (CPU) 330, a memory 334, and support circuits 332. The CPU 330 can be any type of general-purpose computer processor that can be used in an industrial environment. The support circuits 332 are conventionally coupled to the CPU 330 and can include cache memory, clock circuits, input / output subsystems, power supplies, and the like. Software routines (such as the methods described above) may be stored in memory 334 and when executed by CPU 330 transform CPU 330 into a special purpose computer (system controller) 302. Software routines may also be stored and / or executed by a second controller (not shown) remote from tool 300.

[0029] Embodiments according to the principles of the present invention may be implemented in hardware, firmware, software, or any combination thereof. Embodiments may also be implemented as instructions stored using one or more computer-readable media, which instructions may be read and executed by one or more processors. Computer-readable media may include any mechanism for storing or transmitting data in a form that can be read by a machine (e.g., a computing platform or a "virtual machine" running on one or more computing platforms). For example, computer-readable media may include any suitable form of volatile or non-volatile memory. In some embodiments, computer-readable media may include non-temporary computer-readable media.

[0030] While the foregoing is directed to embodiments of the present principles, other and further embodiments of the present principles may be devised without departing from the basic scope of the present principles.

Claims

1. A method for reducing contact resistance, comprising the following steps: performing a selective titanium silicide (TiSi) deposition process on a middle-of-line (MOL) contact structure comprising a cavity in a substrate of a dielectric material and having a silicon-based connection portion at a bottom of the cavity, wherein the selective TiSi deposition process is selective to the silicon-based material relative to the dielectric material and a TiSi layer of about 3 nm to about 6 nm is formed on the silicon-based connection portion; performing a selective deposition process of a metal material on the MOL contact structure, wherein the selective deposition process is selective to a TiSi material relative to a dielectric material and forms a silicide capping layer on the silicon-based connection portion; as well as A seed layer deposition process of the metal material is performed on the contact structure, wherein a thickness of the metal material deposited on the contact structure is about 2 nm to about 3 nm.

2. The method of claim 1, wherein the dielectric material is silicon dioxide or silicon nitride, wherein the silicon-based connecting portion is silicon or silicon germanium, and wherein the silicon-based material is silicon or silicon germanium.

3. The method of claim 1, wherein the selective TiSi deposition process is a chemical vapor deposition (CVD) process having a selectivity of at least 30:1 between silicon-based materials and dielectric materials. The method of claim 1 , wherein the selective deposition process is a fluorine-free metal deposition process of the metal material. 5 . The method of claim 4 , wherein the fluorine-free metal deposition process is a halide-based atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process using a metal chloride gas together with hydrogen gas or a process using a metal organic precursor. 6 . The method of claim 4 , wherein the seed layer deposition process is a plasma vapor deposition (PVD) process, and the PVD process anneals the metal material deposited by the fluorine-free metal deposition process. The method according to claim 1 , wherein the metal material is tungsten or molybdenum.

8. The method of claim 1, further comprising the steps of: Before performing the selective TiSi deposition process, a pre-cleaning process is performed on the MOL contact structure.

9. The method of claim 1, further comprising the steps of: performing a selective etching process to remove a portion of the metal material deposited on the sidewalls of the cavity of the MOL contact structure by the seed layer deposition process while maintaining the metal material on the bottom of the contact structure and on the silicon-based connection portion; as well as A metal gap-fill material is deposited in a bottom-up selective deposition process to fill the MOL contact structure. 10 . The method of claim 9 , wherein the selective etching process is a dry etching process or a wet etching process.

11. The method of claim 9, wherein the bottom-up selective deposition process is a selective chemical vapor deposition (CVD) process.

12. The method of claim 1, further comprising the steps of: A metal gapfill material is deposited in the cavity of the MOL contact structure using a conformal deposition process.

13. The method of claim 1, wherein the method uses a mixture of tungsten material and molybdenum material in the method.

14. A method for reducing contact resistance, comprising the steps of: performing a selective titanium silicide (TiSi) deposition process on a middle-of-line (MOL) contact structure comprising a cavity in a substrate of a dielectric material and having a silicon-based connection portion at a bottom of the cavity, wherein the selective TiSi deposition process is selective to the silicon-based material relative to the dielectric material and a TiSi layer of about 3 nm to about 6 nm is formed on the silicon-based connection portion; performing an in-situ fluorine-free tungsten selective deposition process on the MOL contact structure, wherein the selective deposition process is selective to TiSi material relative to dielectric material and forms a silicide capping layer on the silicon-based connection portion; performing a tungsten seed layer deposition process on the contact structure, wherein the thickness of the tungsten deposited on the contact structure is about 2 nm to about 3 nm; performing a selective etching process to remove a portion of the tungsten deposited on the sidewalls of the cavity of the MOL contact structure by the seed layer deposition process while maintaining the tungsten on the bottom of the contact structure and on the silicon-based connection portion; as well as A tungsten gap-fill material is deposited in a bottom-up selective deposition process to fill the MOL contact structure.

15. The method of claim 14, wherein the dielectric material is silicon oxide or silicon nitride, wherein the silicon-based connecting portion is silicon or silicon germanium, and wherein the silicon-based material is silicon or silicon germanium.

16. The method of claim 14, wherein the selective TiSi deposition process is a chemical vapor deposition (CVD) process having a selectivity of at least 30:1 between silicon-based materials and dielectric materials.

17. The method of claim 14, wherein the selective deposition process is a halide-based atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process using tungsten chloride gas together with hydrogen gas or a process using a metal organic precursor.

18. The method of claim 14, wherein the seed layer deposition process is a plasma vapor deposition (PVD) process, the PVD process anneals the tungsten deposited by the selective deposition process.

19. The method of claim 14, wherein the bottom-up selective deposition process is a selective chemical vapor deposition (CVD) process.

20. A non-transitory computer readable medium having stored thereon instructions which, when executed, cause a method for reducing contact resistance to be performed, the method comprising the steps of: performing a selective titanium silicide (TiSi) deposition process on a middle-of-line (MOL) contact structure comprising a cavity in a substrate of a dielectric material and having a silicon or silicon germanium connection portion at a bottom of the cavity, wherein the selective TiSi deposition process is selective to the silicon or silicon germanium material relative to the dielectric material and a TiSi layer of about 3 nm to about 6 nm is formed on the silicon or silicon germanium connection portion; performing an in-situ fluorine-free tungsten selective deposition process on the MOL contact structure, wherein the selective deposition process is selective to TiSi material relative to dielectric material and forms a silicide capping layer on the silicon or silicon germanium connection portion; performing a tungsten seed layer deposition process on the contact structure, wherein the thickness of the tungsten deposited on the contact structure is about 2 nm to about 3 nm; performing a selective etching process to remove a portion of the tungsten deposited on the sidewalls of the cavity of the MOL contact structure by the seed layer deposition process while maintaining the tungsten on the bottom of the contact structure and on the silicon or silicon germanium connecting portion; as well as A tungsten gap-fill material is deposited in a bottom-up selective deposition process to fill the MOL contact structure.

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