Quasi-monolithic die architecture

Abstract

Microelectronic assemblies, related devices and methods are disclosed herein. In some embodiments, a microelectronic component may include a first die and a through dielectric via (TDV) surrounded by a dielectric material in a first layer, where the TDV has a larger width at a first surface of the first layer and a smaller width at an opposite second surface of the first layer; a second die surrounded by a dielectric material in a second layer on the first layer, where the first die is coupled to the second die by interconnects less than 10 microns in pitch, and the dielectric material around the second die has an interfacial seam extending from a second surface of the second layer toward an opposing first surface of the second layer, the angle of the interface joint relative to the second surface is less than 90 degrees; and a substrate on and coupled to the second layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of the entire contents of U.S. Non-Provisional Application No. 17 / 821,001, filed on August 19, 2022, entitled “QUASI-MONOLITHIC DIE ARCHITECTURES” and is hereby incorporated by reference herein for all purposes. Technical Field

[0003] The present disclosure relates to techniques, methods, and apparatus for a quasi-monolithic die architecture in semiconductor integrated circuit (IC) packaging. Background Art

[0004] When electronic circuits are typically manufactured on a wafer of a semiconductor material such as silicon, the electronic circuit is referred to as an IC. Wafers with such ICs are typically cut into many individual dies. The dies may be packaged into an IC package, which contains one or more dies and other electronic components such as resistors, capacitors, and inductors. The IC package may be integrated into an electronic system such as a consumer electronic system. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The embodiments will be easily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, similar reference numerals represent similar structural elements. The embodiments are illustrated in the figures of the accompanying drawings by way of example and not limitation.

[0006] Figure 1A is a schematic cross-sectional view of an example microelectronic assembly according to some embodiments of the present disclosure.

[0007] Figure 1B yes Figure 1A Schematic cross-sectional view of a portion of an example microelectronic assembly.

[0008] Figure 1C yes Figure 1A Schematic cross-sectional view of a portion of an example microelectronic assembly.

[0009] Figure 2 is a schematic cross-sectional view of another example microelectronic assembly according to some embodiments of the present disclosure.

[0010] Figure 3 is a schematic cross-sectional view of yet another example microelectronic assembly according to some embodiments of the present disclosure.

[0011] Figure 4 is a schematic cross-sectional view of yet another example microelectronic assembly according to some embodiments of the present disclosure.

[0012] Figure 5 is a schematic cross-sectional view of yet another example microelectronic assembly according to some embodiments of the present disclosure.

[0013] 6A to 6H According to some embodiments of the present disclosure, Figure 1A Schematic cross-sectional views of different stages of an example process of microelectronic assembly.

[0014] Figure 7 is a schematic flow chart listing example operations that may be associated with fabricating a microelectronic assembly according to some embodiments of the present disclosure.

[0015] Figure 8 is a cross-sectional view of a device package including one or more microelectronic assemblies according to any embodiment disclosed herein.

[0016] Fig. 9 is a cross-sectional side view of a device assembly including one or more microelectronic assemblies according to any embodiment disclosed herein.

[0017] Fig.10 is a block diagram of an example computing device including one or more microelectronic assemblies according to any embodiment disclosed herein. DETAILED DESCRIPTION

[0018] For the purpose of illustrating the IC packaging described herein, it is important to understand the phenomena that may play a role during the assembly and packaging of the IC. The following basic information can be considered as the basis upon which the present disclosure can be properly interpreted. This information is provided for explanation purposes only and therefore should not be interpreted in any way to limit the broad scope of the present disclosure and its potential applications.

[0019] Advances in semiconductor processing and logic design have allowed the number of logic circuits that can be included in processors and other IC devices to increase. As a result, many processors now have multiple cores monolithically integrated on a single die. Typically, these types of monolithic ICs are also described as planar because they take the form of a flat surface and are typically built on a single silicon wafer made from a single crystal silicon boule. The typical manufacturing process for such monolithic ICs is known as a planar process, which allows photolithography, etching, thermal diffusion, oxidation, and other such processes to be performed on the surface of the wafer so that active circuit elements (e.g., transistors and diodes) are formed on the planar surface of the silicon wafer.

[0020] Current technology allows hundreds and thousands of such active circuit elements to be formed on a single die, so that multiple logic circuits can be implemented thereon. In such a monolithic die, the manufacturing process must be optimized equally for all circuits, resulting in tradeoffs between different circuits. In addition, due to the constraint that the circuits must be placed on a planar surface, some circuits are further away from some other circuits, resulting in reduced performance, such as longer delays. Manufacturing yields may also be severely affected, because if even one circuit fails, the entire die may have to be discarded.

[0021] One solution to overcome such negative effects of a monolithic die is to decompose the circuit into smaller dies (e.g., core particles, modules (tiles)) electrically coupled by interconnection bridges. These smaller dies are part of a component of interconnected dies that together form a complete IC in terms of application and / or function (such as a memory chip, a microprocessor, a microcontroller, a commercial IC (e.g., a chip for repetitive processing routines, simple tasks, special ICs, etc.) and a system on a chip (SoC)). In other words, the individual dies are connected to realize the function of a monolithic IC. By using multiple separate dies, each individual die can be optimally designed and manufactured for a specific function. For example, a processor core containing logic circuits may be intended for performance, and therefore may require a layout that is very optimized in speed. This has different manufacturing requirements compared to a USB controller, which is built to meet a specific universal serial bus (USB) standard, rather than processing speed. Therefore, by dividing different parts of the overall design into different dies (each die is optimized in design and manufacturing), the total yield and cost of the combined die solution can be improved.

[0022] The connection between these tube cores can be realized in many ways.For example, in 2.5D packaging solutions, silicon interposers and through-silicon vias (TSVs) connect tube cores with silicon interconnect speeds with minimum occupied area.In another example, a silicon bridge embedded below the edge of two interconnected tube cores promotes electrical coupling between them.In a three-dimensional (3D) architecture, tube cores are stacked vertically to each other, thereby generally producing a smaller occupied area.Usually, electrical connections and mechanical couplings in such 3D architectures are realized using TSVs and high-pitch solder-based bumps (e.g., C2 interconnects).Bridges and 3D stacking architectures can also be combined to allow the top packaged chip to communicate horizontally with other chips using bridges and vertically communicate with other chips using through-mold vias (Through-Mold Via, TMV) that are generally larger than TSVs.However, these current interconnect technologies use solder or its equivalent to connect, and thus have low vertical and horizontal interconnect density.

[0023] One way to mitigate low vertical interconnect density is to use an interposer, which increases vertical interconnect density but suffers from low lateral interconnect density when the base wafer of the interposer is passive. In a general sense, "interposer" is often used to refer to the silicon substrate that interconnects two dies. By including active circuit elements in the interposer, lateral speed can be increased, but it requires a more expensive manufacturing process, especially when a large base die is used to interconnect smaller dies. In addition, not all interfaces require fine pitch connections, which may result in additional manufacturing and processing overhead without the benefits of fine pitch.

[0024] In one aspect of the present disclosure, an example of a quasi-monolithic die architecture includes recursively coupling multiple IC dies to form a microelectronic assembly of a processing system. Multiple IC dies may include active dies and / or passive dies, and at least a portion of the multiple dies are coupled using high-density interconnects. As used herein, "high-density interconnects" include die-to-die (DTD) interconnects with a spacing of less than 10 microns. As used herein, spacing is measured center-to-center (e.g., from the center of an interconnect to the center of an adjacent interconnect). In some embodiments, two interconnects may form a single interconnect (e.g., a dual interconnect).

[0025] Thus, microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, the microelectronic assembly may include a first die surrounded by dielectric material in a first layer and a through-dielectric via (TDV), wherein the TDV has a larger width at a first surface of the first layer and a smaller width at an opposite second surface of the first layer; a second die, the second die surrounded by dielectric material in a second layer on the first layer, wherein the first die is coupled to the second die by an interconnect having a pitch of less than 10 microns, and the dielectric material around the second die has an interface seam extending from a second surface of the second layer toward an opposite first surface of the second layer at an angle less than 90 degrees relative to the second surface; and a substrate, the substrate being on the second layer and coupled to the second layer.

[0026] Each of the structures, components, packaging, methods, devices, and systems disclosed herein may have several innovative aspects, no single aspect of which is solely responsible for all of the desirable properties disclosed herein. The details of one or more implementations of the subject matter described in this specification are set forth in the following description and the accompanying drawings.

[0027] In the following detailed description, various aspects of the illustrative embodiments may be described using terms commonly used by those skilled in the art to convey the substance of their work to others skilled in the art.

[0028] The terms "circuit" and "electronic circuit" refer to one or more passive and / or active electrical and / or electronic components that are arranged to cooperate with each other to provide a desired function. These terms also refer to analog circuits, digital circuits, hard-wired circuits, programmable circuits, microcontroller circuits, and / or any other type of physical hardware electrical and / or electronic components.

[0029] The term "integrated circuit" refers to an electrical circuit integrated into a single piece of semiconductor or similar material.

[0030] In some embodiments, the IC die disclosed herein may include a substantially single-crystal semiconductor, such as silicon or germanium, as a base material (e.g., substrate, body) on which an integrated circuit is manufactured using conventional semiconductor processing methods. The semiconductor base material may include, for example, an N-type or P-type material. The die may include, for example, a crystalline base material formed using bulk silicon (or other bulk semiconductor material) or a silicon-on-insulator (SOI) structure. In some other embodiments, the base material of one or more IC dies may include an alternative material, which may or may not be combined with silicon, the alternative material including, but not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of III-N, III-V, II-VI, or IV materials. In further other embodiments, the base material may include a compound semiconductor, for example, a first sub-lattice having at least one element from Group III of the periodic table (e.g., Al, Ga, In) and a second sub-lattice having at least one element from Group V of the periodic table (e.g., P, As, Sb). In further other embodiments, the base material may include an intrinsic IV or III-V semiconductor material or alloy that has not been intentionally doped with any electrically active impurities; in alternative embodiments, a nominal impurity dopant level may be present. In still further other embodiments, the die may include an amorphous material such as a polymer; for example, the base material may include a silica-filled epoxy. In other embodiments, the base material may include a high-mobility oxide semiconductor material such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. Typically, the base material may include one or more of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, N-type or P-type amorphous or polycrystalline silicon, germanium, indium gallium arsenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphide, and black phosphorus, each of which may be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium, etc. Although a few examples of materials for the die are described herein, any material or structure that can be used as a base (e.g., base material) on which IC circuits and structures as described herein are built falls within the spirit and scope of the present disclosure.

[0031] Unless otherwise described, IC dies described herein include one or more IC structures (or simply "ICs") that implement (i.e., are configured to perform) a particular function. In one such example, the term "memory die" may be used to describe a die that includes one or more ICs that implement memory circuits (e.g., ICs that implement one or more of a memory device, a memory array, control logic configured to control the memory device and array, etc.). In another such example, the term "compute die" may be used to describe a die that includes one or more ICs that implement logic / compute circuits (e.g., ICs that implement one or more of I / O functions, arithmetic operations, pipelining of data, etc.).

[0032] In another example, the terms "package" and "IC package" are synonymous, as are the terms "die" and "IC die." Note that the terms "chip," "die," and "IC die" are used interchangeably herein.

[0033] Unless otherwise specified, the term "insulation" means "electrical insulation" and the term "conduction" means "electrical conduction." For optical signals and / or devices, components and elements that operate on or use optical signals, the term "conduction" may also mean "optical conduction."

[0034] The terms "oxide," "carbide," "nitride," and the like refer to compounds containing oxygen, carbon, nitrogen, and the like, respectively.

[0035] The term "high-k dielectric" refers to a material having a higher dielectric constant than silicon oxide, while the term "low-k dielectric" refers to a material having a lower dielectric constant than silicon oxide.

[0036] The term "insulating material" or "insulator" (also referred to herein as "dielectric material" or "dielectric") refers to a solid material (and / or a liquid material that solidifies after treatment as described herein) that is substantially non-conductive. By way of example and not limitation, they may include organic polymers and plastics, as well as inorganic materials such as ionic crystals, porcelain, glass, silicon, silicon oxide, silicon carbide, silicon carbonitride, silicon nitride, and aluminum oxide, or combinations thereof. They may include dielectric materials, highly polarizable materials, and / or piezoelectric materials. The dielectric material may include any suitable dielectric material commonly used in semiconductor manufacturing, such as silicon, and one or more of oxygen, nitrogen, hydrogen, and carbon (e.g., in the form of silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride); polyimide materials; or low-k or ultra-low-k dielectrics (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, organic polymer dielectrics, photoimageable dielectrics, and / or benzocyclobutene-based polymers). They may be transparent or opaque without departing from the scope of the present disclosure. Other examples of insulating materials are underfills and molding or molding-like materials used in packaging applications, including, for example, materials used for organic interposers, package standoffs, and other such components.

[0037] In various embodiments, elements associated with an IC may include, for example, transistors, diodes, power supplies, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. In various embodiments, elements associated with an IC may include those elements monolithically integrated within the IC, those elements mounted on the IC, or those elements connected to the IC. Depending on the components associated with the IC, the IC described herein may be analog or digital and may be used in a variety of applications, such as microprocessors, optoelectronic devices, logic blocks, audio amplifiers, etc. The IC described herein may be used in a single IC die or as part of a chipset to perform one or more related functions in a computer.

[0038] In various embodiments of the present disclosure, the transistors described herein may be field effect transistors (FETs), such as MOSFETs. In a number of embodiments, the FET is a four-terminal device. In silicon-on-insulator or nanoribbon or all-around gate (GAA) FETs, the FET is a three-terminal device that includes source, drain, and gate terminals, and uses an electric field to control the current flowing through the device. A FET typically includes: a channel material; a source region and a drain region disposed in and / or on the channel material; and a gate stack, the gate stack including a gate electrode material disposed on a portion of the channel material located between the source region and the drain region ("channel portion"), or referred to as a "work function" material, and optionally, the gate stack also includes a gate dielectric material between the gate electrode material and the channel material.

[0039] In a general sense, an "interconnect" refers to any element that provides a physical connection between two other elements. For example, an electrical interconnect provides an electrical connection between two electrical components to facilitate the transmission of electrical signals between them; an optical interconnect provides an optical connection between two optical components to facilitate the transmission of optical signals between them. As used herein, both electrical and optical interconnects are included in the term "interconnect". The nature of the interconnect being described will be understood herein with reference to the signal medium associated with the interconnect being described. Therefore, when used with respect to an electronic device (such as an IC that operates using electrical signals), the term "interconnect" describes any element formed of a conductive material for providing an electrical connection to one or more elements associated with the IC or / and providing an electrical connection between various such elements. In such cases, the term "interconnect" can refer to both electrical traces (sometimes also referred to as "wires", "wiring", "metal wires" or "trench") and conductive vias (sometimes also referred to as "vias" or "metal vias"). Sometimes, conductive traces and vias may be referred to as "conductive traces" and "conductive vias", respectively, to highlight the fact that these elements include conductive materials such as metals. Likewise, when used with respect to a device that also operates on optical signals, such as a photonic IC (PIC), "interconnect" may also describe any element formed of light-conducting material for providing an optical connection to one or more elements associated with the PIC. In such cases, the term "interconnect" may refer to optical waveguides, including optical fibers, optical splitters, optical combiners, optical couplers, and optical vias.

[0040] The term "waveguide" refers to any structure used to guide light to propagate from one location to another, typically through a substrate material such as silicon or glass. In various examples, the waveguide can be formed from silicon, doped silicon, silicon nitride, glass (such as silica (e.g., silicon dioxide or SiO2), borosilicate (e.g., 70-80wt% SiO2, 7-13wt% B2O3, 4-8wt% Na2O or K2O, and 2-8wt% Al2O3), etc. The waveguide can be formed using various techniques, including but not limited to in-situ waveguide formation. For example, in some embodiments, the waveguide can be formed in-situ in the glass using low temperature glass-to-glass bonding or by laser direct writing. The waveguide formed in-situ can have lower loss characteristics.

[0041] The term "conductive trace" may be used to describe conductive elements that are separated by insulating materials. Within an IC die, such insulating materials include interlayer low-k dielectrics disposed within the IC die. Within package substrates and printed circuit boards (PCBs), such insulating materials include organic materials such as Ajinomoto Buildup Film (ABF), polyimide, or epoxy. Such conductors are typically arranged in several levels or layers of a metallization stack.

[0042] The term "conductive via" may be used to describe a conductive element that interconnects two or more conductors at different levels of a metallization stack. To this end, the via may be disposed substantially perpendicular to the plane of the IC die / chip or a support structure on which the IC structure is disposed, and may interconnect two conductors in adjacent levels or two conductors in non-adjacent levels.

[0043] The term "package substrate" may be used to describe any substrate material that facilitates packaging together any collection of semiconductor die and / or other electrical components (e.g., passive electrical components). As used herein, a package substrate may be formed of any material, including but not limited to insulating materials such as resin-impregnated fiberglass (e.g., PCB or printed wiring board (PWB)), glass, ceramic, silicon, silicon carbide, etc. In addition, as used herein, a package substrate may refer to a substrate including a buildup layer (e.g., ABF layer).

[0044] The term "metallization stack" may be used to refer to a stack of one or more interconnects used to provide connections to different circuit components of a package substrate and / or an IC die / chip.

[0045] As used herein, the term "pitch" of interconnects refers to the center-to-center distance between adjacent interconnects.

[0046] In the context of a stack of dies coupled to each other or in the context of a die coupled to a package substrate, the term "interconnect" may also refer to a die-to-die (DTD) interconnect and a die-to-package substrate (DTPS) interconnect, respectively. A DTD interconnect may also be referred to as a first-level interconnect (FLI). A DTPS interconnect may also be referred to as a second-level interconnect (SLI).

[0047] Although not specifically shown in all current illustrations in order not to clutter the figures, when describing a DTD or DTPS interconnect, the surface of the first die may include a first set of conductive contacts, and the surface of the package substrate or the second die may include a second set of conductive contacts. One or more conductive contacts in the first set may then be electrically and mechanically coupled to some conductive contacts in the second set via the DTD or DTPS interconnect.

[0048] In some embodiments, the pitch of the DTD interconnects may be different than the pitch of the DTPS interconnects, although in other embodiments, these pitches may be substantially the same.

[0049] The DTPS interconnect disclosed herein can take any suitable form. In some embodiments, a group of DTPS interconnects can include solder (e.g., solder bumps or solder balls that undergo thermal reflow to form DTPS interconnects). DTPS interconnects including solder can include any appropriate solder material, such as lead / tin, tin / bismuth, eutectic tin / silver, ternary tin / silver / copper, eutectic tin / copper, tin / nickel / copper, tin / bismuth / copper, tin / indium / copper, tin / zinc / indium / bismuth, or other alloys. In some embodiments, a group of DTPS interconnects can include anisotropic conductive materials, such as anisotropic conductive films or anisotropic conductive pastes. Anisotropic conductive materials can include conductive materials dispersed in non-conductive materials. In some embodiments, anisotropic conductive materials can include microscopic conductive particles embedded in a binder or a thermosetting adhesive film (e.g., a thermosetting biphenyl epoxy resin or an acrylic-based material). In some embodiments, the conductive particles can include polymers and / or one or more metals (e.g., nickel or gold). For example, the conductive particles can include gold coated with nickel or copper coated with silver, which are in turn coated with polymers. In another example, the conductive particles may include nickel. When the anisotropic conductive material is not compressed, there may be no conductive path from one side of the material to the other side. However, when the anisotropic conductive material is sufficiently compressed (e.g., by conductive contacts on both sides of the anisotropic conductive material), the conductive materials near the compressed area may contact each other, thereby forming a conductive path from one side of the film to the other side in the compressed area.

[0050] The DTD interconnects disclosed herein may take any suitable form. In some embodiments, some or all of the DTD interconnects in the microelectronic assembly or IC package as described herein may be metal-to-metal interconnects (e.g., copper-to-copper interconnects, or plated interconnects). In such embodiments, the conductive contacts on both sides of the DTD interconnects may be bonded together (e.g., under elevated pressure and / or temperature) without using an intermediate solder or anisotropic conductive material. In some metal-to-metal interconnects, dielectric materials (e.g., silicon oxide, silicon nitride, silicon carbide) may be present between the metals bonded together (e.g., between copper pads or pillars providing associated conductive contacts). In some embodiments, one side of the DTD interconnect may include a metal pillar (e.g., a copper pillar), and the other side of the DTD interconnect may include a metal contact (e.g., a copper contact) recessed in the dielectric. In some embodiments, a metal-to-metal interconnect (e.g., a copper-to-copper interconnect) may include a noble metal (e.g., gold) or a metal (e.g., silver) whose oxide is conductive. In some embodiments, a metal-to-metal interconnect may include a metal nanostructure (e.g., a nanorod) that may have a reduced melting point. Metal-to-metal interconnects may be able to reliably conduct higher currents than other types of interconnects; for example, some solder interconnects may form brittle intermetallic compounds when current flows, and the maximum current provided through such interconnects may be constrained to mitigate mechanical failure.

[0051] In some embodiments, the dies on both sides of a set of DTD interconnects may be bare (eg, unpackaged) dies.

[0052] In some embodiments, the DTD interconnect may include solder. For example, the DTD interconnect may include a conductive bump or column (e.g., a copper bump or column) attached to a corresponding conductive contact by solder. In some embodiments, a thin solder cap may be used in a metal-to-metal interconnect to provide flatness, and the solder may become an intermetallic compound during processing. In some embodiments, the solder used in some or all of the DTD interconnects may have a higher melting point than the solder included in some or all of the DTPS interconnects. For example, when the DTD interconnect in an IC package is formed before the DTPS interconnect is formed, the solder-based DTD interconnect may use a higher temperature solder (e.g., having a melting point greater than 200 degrees Celsius), while the DTPS interconnect may use a lower temperature solder (e.g., having a melting point less than 200 degrees Celsius). In some embodiments, the higher temperature solder may include tin; tin and gold; or tin, silver and copper (e.g., 96.5% tin, 3% silver and 0.5% copper). In some embodiments, the lower temperature solder may include tin and bismuth (eg, eutectic tin-bismuth), tin, silver, bismuth, indium, indium and tin, or gallium.

[0053] In some embodiments, a set of DTD interconnects may include anisotropic conductive materials, such as any of the materials discussed above for DTPS interconnects. In some embodiments, DTD interconnects may be used as data transmission channels, while DTPS interconnects may be used for power and ground lines, etc.

[0054] In a microelectronic assembly or IC package as described herein, some or all DTD interconnections may have a finer spacing than DTPS interconnections. In some embodiments, the DTPS interconnections disclosed herein may have a spacing between about 80 microns and 300 microns, while the DTD interconnections disclosed herein may have a spacing between about 0.5 microns and 100 microns, depending on the type of DTD interconnections. An example of silicon-level interconnection density is provided by the density of some DTD interconnections. In some embodiments, the DTD interconnections may have a spacing that is too fine to be directly coupled to a package substrate (e.g., too fine to be used as a DTPS interconnection). Since the similarity of materials in different tube cores on both sides of a group of DTD interconnections is greater than the similarity of materials between the tube core and the package substrate on both sides of a group of DTPS interconnections, the DTD interconnections may have a smaller spacing than the DTPS interconnections. In particular, the difference in the material composition of the tube core and the package substrate may cause the tube core and the package substrate to produce differential expansion and contraction due to the heat generated during operation (and the heat applied during each manufacturing operation). To mitigate damage (e.g., cracking, solder bridging, etc.) caused by such differential expansion and contraction, the DTPS interconnects in any microelectronic assembly or IC package as described herein can be formed to be larger and farther apart than the DTD interconnects, which can experience less thermal stress due to the greater material similarity of the die pairs on both sides of the DTD interconnects.

[0055] It should be appreciated that one or more levels of bottom filler (e.g., organic polymer material such as benzotriazole, imidazole, polyimide, or epoxy) may be provided in the IC package described herein and may not be labeled to avoid cluttering the drawings. In various embodiments, the various levels of bottom filler may include the same or different insulating materials. In some embodiments, the levels of bottom filler may include a thermosetting epoxy with silicon oxide particles; in some embodiments, the levels of bottom filler may include any suitable material capable of performing bottom fill functions, such as supporting the die and reducing thermal stress on the interconnect. In some embodiments, the selection of bottom fill material may be based on design considerations, such as form factor, size, stress, operating conditions, etc.; in other embodiments, the selection of bottom fill material may be based on material properties and processing conditions, such as factors such as curing temperature, glass transition temperature, viscosity, and chemical resistance; in some embodiments, the selection of bottom fill material may be based on both design and processing considerations.

[0056] In some embodiments, one or more levels of solder resist (e.g., epoxy liquid, liquid photoimageable polymer, dry film photoimageable polymer, acrylic, solvent) may be provided in the IC packages described herein and may not be labeled or shown to avoid cluttering the drawings. The solder resist may be a liquid or dry film material, including a photoimageable polymer. In some embodiments, the solder resist may be non-photoimageable.

[0057] The terms "substantially," "close," "approximately," "near," and "approximately" generally mean within + / - 20% of a target value (e.g., within + / - 5 or 10% of a target value), based on the context of a particular value as described herein or as known in the art.

[0058] Terms indicating the orientation of various elements (e.g., "coplanar," "perpendicular," "orthogonal," "parallel," or any other angle between elements) generally refer to within + / - 5%-20% of the target value, based on the context of specific values ​​as described herein or as known in the art.

[0059] The term "connected" means a direct connection between the things being connected (which may be one or more of a mechanical, electrical and / or thermal connection) without any intermediary devices, while the term "coupled" means a direct connection between the things being connected, or an indirect connection through one or more passive or active intermediary devices.

[0060] This specification uses the phrases "in one embodiment" or "in an embodiment," which may each refer to one or more of the same or different embodiments.

[0061] Furthermore, as used with respect to embodiments of the present disclosure, the terms "comprising," "including," "having," and the like are synonymous.

[0062] The present disclosure may use perspective-based descriptions, such as “above,” “below,” “top,” “bottom,” and “side”; such descriptions are used to facilitate discussion and are not intended to limit the application of the disclosed embodiments.

[0063] As used herein, the terms "above," "below," "between," and "on" refer to the relative position of one material layer or component with respect to other layers or components. For example, a layer disposed above or below another layer may be in direct contact with the other layer or may have one or more intervening layers. Additionally, a layer disposed between two layers may be in direct contact with one or both of the two layers or may have one or more intervening layers. Conversely, a first layer described as being "on" a second layer refers to the layer that is in direct contact with the second layer. Similarly, unless expressly stated otherwise, a feature disposed between two features may be in direct contact with the adjacent feature or may have one or more intervening layers.

[0064] As used herein, the term "disposed" refers to placing, positioning, placing, and / or arranging, rather than to any particular method of formation.

[0065] When the term "between" is used with respect to a measuring range, the term "between" includes the ends of the measuring range.

[0066] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). When used herein, the notation "A / B / C" means (A), (B), and / or (C).

[0067] Although certain elements may be referred to in the singular herein, such elements may include multiple sub-elements. For example, a "conductive material" may include one or more conductive materials. In another example, a "dielectric material" may include one or more dielectric materials.

[0068] Unless otherwise indicated, the use of the ordinal adjectives "first," "second," and "third," etc., used to describe common objects simply indicates that different instances of similar objects are mentioned and is not intended to imply that the objects so described must be in a given order, whether temporally, spatially, in ranking, or in any other manner.

[0069] In the following detailed description, reference is made to the accompanying drawings which form a part of the detailed description, and in which embodiments that can be practiced are shown by way of illustration. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be understood in a limiting sense.

[0070] The drawings are not necessarily drawn to scale.

[0071] In the figures, the same reference numerals refer to the same or similar elements / materials being shown, so that, unless otherwise stated, the explanation of the elements / materials with a given reference numeral provided in the context of one of the figures applies to the other figures where the elements / materials with the same reference numerals are shown. In addition, singular and plural forms of the reference numerals may be used with the reference numerals to refer to a single or multiple elements of the same or similar type, kind or class of elements, respectively.

[0072] In addition, in the figures, some schematic diagrams of example structures of various devices and components described herein may be shown with exact right angles and straight lines, but it should be understood that such schematic diagrams may not reflect real-world process limitations, which may cause features to appear less than "ideal" when any structure described herein is examined using, for example, images of suitable characterization tools, such as scanning electron microscope (SEM) images, transmission electron microscope (TEM) images, or non-contact profilometers. In such images of actual structures, possible processing and / or surface defects may also be visible, for example, surface roughness, curvature or profile deviations, pits or scratches, imperfectly straight edges of materials, tapered vias or other openings, unintentional rounding of corners or thickness variations of different material layers, occasional screw dislocations, edge dislocations, or combined dislocations within one or more crystal regions, and / or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but common in the field of device manufacturing and / or packaging.

[0073] Note that in the accompanying drawings, various components (e.g., interconnects) are shown as aligned (e.g., at corresponding interfaces) for ease of illustration only; in fact, some or all of them may be misaligned. In addition, there may be other components in the assembly that are not shown in the drawings, such as bonding pads, landing pads, metallizations, etc., to prevent confusion. In addition, the drawings are intended to show the relative arrangement of the components within their assemblies, and generally speaking, such assemblies may include other components that are not shown (e.g., various interface layers or various other components related to optical functions, electrical connections, or thermal relief). For example, in some additional embodiments, the assembly as shown may include more dies and other electrical components. In addition, although some components of the assembly are shown as flat rectangles or formed by rectangular solid lines in the drawings, this is only for ease of illustration, and embodiments of these assemblies may be curved, rounded, or otherwise irregularly shaped, as indicated by the manufacturing process used to manufacture the various components and sometimes unavoidable.

[0074] In the figures, specific numbers and arrangements of structures and components are described for illustrative purposes, and any desired number or arrangement of such structures and components may be present in various embodiments.

[0075] Furthermore, unless otherwise stated, the structures shown in the figures may take any suitable form or shape depending on material properties, manufacturing processes, and operating conditions.

[0076] For convenience, if there are graph collections named with different letters (e.g. Figures 1A-1C), such a set may be referred to herein without a letter (e.g., as “FIG. 1”). Similarly, if there is a set of reference numerals named with different numbers or letters (e.g., 104-1, 104-2, 104-3), such a set may be referred to herein without a number or letter (e.g., as “104”).

[0077] The various operations may be described in order as a plurality of discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be interpreted as implying that the operations must be dependent on the order. In particular, the operations may not be performed in the order of introduction. The described operations may be performed in an order different from the described embodiments. Various additional operations may be performed, and / or the described operations may be omitted in additional embodiments.

[0078] Figure 1A is a schematic cross-sectional view of an example microelectronic assembly 100 according to some embodiments of the present disclosure. The microelectronic assembly 100 includes a plurality of layers 102 (e.g., 102-1 and 102-2) of an IC die 104 (e.g., 104-1, 104-2, 104-3), each layer 102 being coupled to an adjacent layer 102 via an interconnect 106. In various embodiments, the interconnect 106 may be a FLI, wherein the spacing between adjacent interconnects is less than 10 microns. In some embodiments, an example of the interconnect 106 is a hybrid bond, including metal-metal bonding and dielectric-dielectric bonding. In the example shown in the figure, the number of layers 102 is two: a first layer 102-1 and a second layer 102-2. In various other embodiments, the microelectronic assembly 100 may include two or more numbers of layers 102. In some embodiments, each layer 102 may include an interface layer (not shown, for ease of illustration and so as not to clutter the drawings) on either side, the interface layer including the metal material and the dielectric material of the interconnect 106. The plurality of layers 102 may have a first surface 170 - 1 (eg, a bottom surface) and an opposing second surface 170 - 2 (eg, a top surface).

[0079] In various embodiments, one or more of the plurality of layers 102 can include a dielectric material 108 around (e.g., between, around, etc.) the IC die 104. In the example shown, layer 102-1 includes a first dielectric material 108-1 around the die 104-1, and a second layer 102-2 has a second dielectric material 108-2 around the IC dies 104-2, 104-3. The dielectric material 108-2 around the die 104-2 can include an interface seam 125 extending from the second die 104-2 toward the first surface 172-1 of the layer 102-2 at the second surface 172-2 of the layer 102-2, the interface seam 125 having an angle (θ) of less than 90 degrees relative to the second surface of the layer 102-2. In some embodiments, the interface seam 125 can have an angle between 25 degrees and 65 degrees (e.g., between 35 degrees and 55 degrees) relative to the second surface of the layer. As Figure 1A As shown, the dielectric material 108-2 may include more than one interface seam 125 extending from the IC die 104-2, 104-3 toward the first surface 172-1 of the layer 102-2 at the second surface 172-2 of the layer 102-2, which has an angle of less than 90 degrees relative to the second surface of the layer 102-2. In other embodiments where there are a greater number of layers 102, the dielectric material 108 in the other layers may include an interface seam 125 extending from the IC die 104 toward the first surface of the layer 102 at the second surface of the layer 102, and the interface seam 125 has an angle of less than 90 degrees relative to the second surface of the corresponding layer. The interface seam 125 may be formed as described below with reference to FIG. 6. In other embodiments where there are a greater number of layers 102, the dielectric material 108 may not be present around the IC die 104 in one or more such layers 102. One or more through dielectric vias (TDVs) 110 may be present in the dielectric material 108 in the layer 102. In various embodiments, the dielectric material 108 includes an inorganic material, such as silicon, and one or more of oxygen, nitrogen, hydrogen, and carbon (e.g., in the form of silicon oxide, silicon nitride, or silicon carbide), and / or other forms of inorganic dielectric materials that are commonly used as interlayer dielectrics (ILDs) in semiconductor devices.

[0080] The substrate 112 can be coupled to the second surface 170-2 of the plurality of layers 102. In some embodiments, the substrate 112 can include a structurally rigid and thermally conductive base portion, such as silicon, which can provide mechanical support and stability for the plurality of layers 102. In various embodiments, the substrate 112 can include a silicon wafer cut into a suitable size to fit over the layer 102. The substrate 112 can be coupled to the second surface 170-2 of the layer 102-2 by fusion bonding (i.e., having a dielectric-to-dielectric bond at the interface without a metal-to-metal bond). In some embodiments, as Figure 1A As shown, substrate 112 may not include devices and / or metal traces. In other embodiments (e.g., Figure 3 As shown, the substrate 112 may include devices and / or metal traces such that the substrate 112 is electrically coupled to the second surface 170-2 of the second layer 102-2 through an interconnect (eg, the interconnect 106).

[0081] In some embodiments (as shown), one or more IC dies 104 (e.g., 104-1) in some layers 102 (e.g., 102-1) may include through-substrate vias (TSVs) 122. TSVs 122 may be configured to carry power, signal, and / or ground connections between package substrate 118 and IC dies 104 in multiple layers 102. In various embodiments, one or more IC dies 104 in microelectronic assembly 100 may include different kinds of conductive traces having different sizes, such as conductive traces configured to carry power and conductive traces configured to carry signals (e.g., conductive traces configured to carry power may generally be larger (e.g., thicker, wider) than conductive traces configured to carry signals). The conductive traces may be present in a metallization stack 116 having multiple metal layers through an insulator fabricated using known semiconductor fabrication processes. In some embodiments, the insulator material in the metallization stack may be the same as the insulator material of the dielectric material 108 surrounding the IC die 104 ; in other embodiments, the insulator material in the metallization stack may be different from the insulator material of the dielectric material 108 surrounding the IC die 104 .

[0082] In the example embodiment shown in the figure, the metallization stacks 116 of the IC die 104 are face-to-face (e.g., the metallization stack 116 of the IC die 104-1 faces the metallization stacks 116 of the IC die 104-2, 104-3 and is coupled to the metallization stacks 116 of the IC die 104-2, 104-3). In other embodiments, the metallization stacks 116 of the IC die 104 are face-to-back (not shown) (e.g., the metallization stack 116 of the IC die 104-1 can face away from the metallization stacks 116 of the IC die 104-2, 104-3, so that the IC die 104-2, 104-3 is coupled to the TSV 122 of the IC die 104-1).

[0083] Figure 1B 6 is a schematic cross-sectional view of a detail of a particular one of the interconnects 106 in the microelectronic assembly 100. Note that although only the interconnect 106 is shown, the same structure and description may apply to any other such interconnects including hybrid bonding in the microelectronic assembly 100, where applicable. In a general sense, the interconnect 106 may include metal-metal bonding between a bonding pad 132 of the layer 102-1 and a bonding pad 134 of the layer 102-2 at the interface 130 between the layers 102-1 and 102-2, and dielectric-dielectric bonding (e.g., oxide-oxide bonding) in the dielectric materials 109 of the layers 102-1 and 102-2. In some embodiments, the structure as shown may be present in an interface layer (e.g., bonding layer 124 in FIG. 6 ) between the layers 102-1 and 102-2. In other embodiments, the structure as shown may be present in the IC die 104 of the corresponding layer. In yet other embodiments, some structures as shown may be present in the IC die 104 of one layer, and other structures may be present outside / around the IC die 104 of another layer. The bonding pad 132 of layer 102-1 may be bonded to the bonding pad 134 of layer 102-2. The dielectric materials 109 (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.) in layers 102-1 and 102-2 may be bonded to each other. In some embodiments, dielectric material 109 may be the same material as dielectric material 108. The bonded metal and dielectric materials form interconnect 106, including hybrid bonding, thereby providing electrical and mechanical coupling between layers 102-1 and 102-2. In various embodiments, interconnect 106 may have a linear dimension of less than 5 microns and a spacing of less than 10 microns between adjacent interconnects.

[0084] Figure 1C 1 is a schematic cross-sectional view of a detail of a particular TDV 110 in the microelectronic assembly 100. Figure 1AAs shown, TDV 110 may be included in layer 102-1 and adjacent to IC die 104-1. Layer 102-1 may include a first surface 171-1 and an opposing second surface 171-2. TDV 110 may extend through dielectric material 108 from first surface 171-1 to second surface 171-2 of layer 102-1. TDV 110 may have a tapered or conical shape. TDV 110 may have a larger width 191-1 (e.g., y-dimension) at first surface 171-1 and a smaller width 191-2 at second surface of layer 102-1. Although Figure 1A The TDV 110 is shown to be included only in the layer 102 - 1 , but any layer 102 (eg, the layer 102 - 2 ) may include a TDV 110 having a width 191 - 1 toward the first surface 171 - 1 greater than a width 191 - 2 toward the second surface 171 - 2 .

[0085] Back to Figure 1A , the package substrate 118 may include a conductive path (not shown) passing through the organic dielectric material. The conductive path may include a conductive trace coupled through a conductive via. The package substrate 118 may also include bonding pads, redistribution layers, substrate cores, passive components, and other elements, which are not shown only for ease of illustration and not as a limitation. The package substrate 118 may be coupled to the first surface 170-1 of the plurality of layers 102 via an SLI 142 (e.g., a DTPS interconnect, such as a flip chip solder bond). In various embodiments, the SLI 142 may have a spacing greater than 10 microns between adjacent interconnects. An underfill material 127 may be disposed around the SLI 142. The underfill process may include dispensing the underfill material in liquid form, allowing the material to flow and fill the interstitial gap around the SLI 142, and subjecting the assembly to a curing process (such as baking) to cure the material.

[0086] Figure 2 is a schematic cross-sectional view of another example microelectronic assembly according to some embodiments of the present disclosure. Except for the differences as further described, the configuration of the embodiment shown in this figure is similar to Figure 1A The configuration of the microelectronic assembly 100 as described herein is a quasi-monolithic packaging architecture. The substrate 112 in a conventional quasi-monolithic packaging architecture typically includes a silicon substrate without devices or metal traces, and the interface of the structural silicon is fusion bonded (i.e., at the interface, there is a dielectric-dielectric bond, but no metal-metal bond, such as Figure 1A In contrast, in embodiments as described herein, substrate 112 may be electrically coupled to second surface 170-2 of plurality of layers 102 via interconnect 107. Interface 130 between substrate 112 and second surface 170-2 of plurality of layers 102 may include, for example, Figure 1B The metal-to-metal bonding and dielectric-to-dielectric bonding described above. In some embodiments, a conductive trace (not shown) can be disposed on substrate 112, proximate to second surface 170-2 of layer 102, and electrically coupled to second surface 170-2 of multiple layers 102 through interconnect 107. Interconnect 107 can improve thermal performance of microelectronic assembly 100 by dissipating heat through interconnect 107. In some embodiments, interconnect 107 can have the same type and spacing as interconnect 106. In other embodiments, interconnect 107 can have a different size and spacing than interconnect 106. In other embodiments, top substrate 112 can include active devices such as memory or processing logic.

[0087] Figure 3 is a schematic cross-sectional view of another example microelectronic assembly according to some embodiments of the present disclosure. Except for the differences as further described, the configuration of the embodiment shown in this figure is similar to Figure 2 The substrate 112 may also include a metallization stack 116 having a plurality of metal layers through an insulator (e.g., a conductive path formed by conductive vias and conductive traces) electrically coupled to the second surface 170-2 of the plurality of layers 102 through the interconnect 107. The interface 130 between the substrate 112 and the second surface 170-2 of the plurality of layers 102 may include, for example, Figure 1B The metal-metal bonding and dielectric-dielectric bonding described above. In some embodiments, substrate 112 may also include devices such as capacitors. In some embodiments, IC die 104-2, 104-3 may be double-sided dies (e.g., similar to IC die 104-1, with metallization stacks or TSVs 122 on opposite sides), and substrate 112 may be electrically coupled to transmit signals between IC die 104-2, 104-3.

[0088] Figure 4 is a schematic cross-sectional view of another example microelectronic assembly according to some embodiments of the present disclosure. Except for the differences as further described, the configuration of the embodiment shown in this figure is similar to Figure 1A The IC die 104 in layer 102-2 may include multiple IC dies 104 stacked vertically and electrically coupled via interconnects 106. Figure 4 As shown, IC die 104-4, 104-5 may include TSV 122 and may be electrically coupled to IC die 104-1 on the bottom surface via interconnect 106-1 and to IC die 104-6, 104-7, respectively, on the top surface via interconnect 106-2. Stacked IC dies (e.g., IC die 104-4, 104-6 and IC die 104-5, 104-7) may be pre-assembled before being integrated into microelectronic assembly 100.

[0089] Figure 5 is a schematic cross-sectional view of another example microelectronic assembly according to some embodiments of the present disclosure. Except for the differences as further described, the configuration of the embodiment shown in this figure is similar to Figure 1A The configuration is the same. The microelectronic assembly 100 includes multiple layers 102 (e.g., 102-1, 102-2, 102-3) of an IC die 104 (e.g., 104-1, 104-2, 104-3, 104-8, 104-9), each layer 102 coupled to an adjacent layer 102 by an interconnect 106. In the example shown in the figure, the number of layers 102 is three: a first layer 102-1 having a first surface 171-1 and an opposite second face 171-2, a second layer 102-2 at the second surface 171-2 of the first layer 102-1, and a third layer 102-3 at the first surface 171-1 of the first layer 102-1. In some embodiments, each layer 102 may include an interface layer on either side, the interface layer including a metal material and a dielectric material of the interconnect 106. In various embodiments, one or more of the plurality of layers 102 may include dielectric material 108 around (e.g., between, around, etc.) the IC die 104. In the example shown, layer 102-1 includes dielectric material 108 around die 104-1, layer 102-2 has dielectric material 108 around IC die 104-2, 104-3, and layer 102-3 has dielectric material 108 around IC die 104-8, 104-9. The dielectric material 108 around die 104-8, 104-9 may include an interface seam 125 extending from die 104-8, 104-9 toward first surface 173-1 of layer 102-3 at second surface 173-2 of layer 102-3, the interface seam 125 having an angle of less than 90 degrees relative to the second surface of layer 102-3. The interface seam 125 may have an angle between 25 and 65 degrees (e.g., between 35 and 55 degrees) relative to the second surface of the layer. Figure 5 As shown in , the dielectric material 108 may include more than one interface seam 125 extending from the die 104-8, 104-9 toward the first surface 173-1 of the layer 102-3 at the second surface 173-2 of the layer 102-3, which has an angle of less than 90 degrees relative to the second surface of the layer 102-3. The interface seam 125 may be formed as described below with reference to FIG. 6. In some embodiments, all layers 102 of the IC die 104 may include the interface seam 125. In some embodiments, only one layer 102 of the IC die 104 may include the interface seam 125.

[0090] Any suitable technique may be used to manufacture the microelectronic assembly 100 disclosed herein. For example, Figure 6A-6HAccording to various embodiments, Figure 1A The microelectronic assembly 100 is a side cross-sectional view of various stages in the process of the example. Although the following reference Figure 6A-6H The operations discussed in the present disclosure (and other figures showing the manufacturing process) are shown in a particular order, but these operations can be performed in any suitable order. In addition, additional operations not shown can also be performed without departing from the scope of the present disclosure. In addition, the present disclosure can be modified according to the present disclosure. Figure 6A-6H Various operations are discussed to fabricate other of the microelectronic assemblies 100 disclosed herein.

[0091] Fig. 6A The assembly is shown after mounting the IC die 104-2, 104-3 on the substrate 112, with the metallization stack 116 facing away from the substrate 112. The IC die 104-2, 104-3 may be placed using any suitable method, such as automated pick and place. The substrate 112 may include any suitable material for providing mechanical stability during manufacturing operations and use, and in some embodiments, may include silicon. In some embodiments, the IC die 104-2, 104-3 may be coupled to the substrate 112 by fusion bonding. In some embodiments, the IC die 104-2, 104-3 may be bonded to the substrate 112 by a metallization stack 116 such as Figure 2 An interconnect such as interconnect 107 in is electrically coupled to substrate 112 .

[0092] Figure 6B The assembly is shown during deposition of dielectric material 108 on the top surface of the assembly (e.g., on the top and side surfaces of IC die 104-2, 104-3, and on the top surface of substrate 112). Interface seam 125 may be formed by depositing dielectric material 108 on the surfaces of die 104-2, 104-3 and on the surface of substrate 112. Dielectric material 108 may be deposited using any suitable technique, such as chemical vapor deposition, physical vapor deposition, plasma enhanced chemical vapor deposition, etc. In some embodiments, dielectric material 108 may be dispensed in liquid form to flow around and conform to various shapes of components and metallization, and may then be subjected to a process, such as curing, to solidify dielectric material 108. In other embodiments, the dielectric may be deposited and then reflowed to improve its planarity for subsequent processing.

[0093] Figure 6CThe assembly is shown after depositing dielectric material 108 all around and between IC dies 104-2, 104-3 and on substrate 112 and planarizing the top surface of the assembly to remove the dielectric material over the IC dies. The top surface of the assembly may be planarized to remove dielectric 108 using any suitable technique such as grinding or etching and then chemical mechanical polishing (CMP).

[0094] Fig.6D Shown in Figure 6C The assembly after forming a bonding layer 124 on the top surface of the assembly. The bonding layer 124 may include a bonding pad 134 in the dielectric material 109, which corresponds to the bonding pad 132, as described above with reference to Figure 1B As described, in order to form a hybrid direct bond (e.g., Fig. 6E Interconnect 106 shown).

[0095] Fig. 6E The assembly is shown after attaching the IC die 104 - 1 , which may include TSVs 122 , to the bonding layer 124 and forming the interconnects 106 . Fig. 6E The components may be subjected to an appropriate bonding process to form the interconnect 106. For example, the bonding process may include applying appropriate pressure and heating to an appropriate temperature (e.g., heating to a moderately high temperature, e.g., between about 50 and 400 degrees Celsius) for a period of time. In some embodiments, a bonding material may be applied at the interface between the IC die 104-1 and the bonding layer 124. In some embodiments, the bonding material may be an adhesive that ensures that the IC die 104-1 is attached to the bonding layer 124. In other embodiments, the bonding material may be an etch stop material. In yet other embodiments, the bonding material may be an etch stop material and also have suitable adhesive properties to ensure that the IC die 104-1 is attached to the bonding layer 124. In further other embodiments, no bonding material may be used.

[0096] Fig. 6F Shown in Fig. 6E The assembly after dielectric material 108 is disposed on the top surface of the assembly (e.g., on and around IC die 104-1 and on the top surface of bonding layer 124). In some embodiments, dielectric material 108 around IC die 104-1 can be the same material as dielectric material 108 around IC die 104-2, 104-3. In some embodiments, dielectric material 108 around IC die 104-1 can be a different material than dielectric material 108 around IC die 104-2, 104-3. Dielectric material 108 can be deposited using any suitable technique, such as the dielectric material 108 described above with reference to FIG. Figure 6B and Figure 6CThe operations described include forming an interface seam 125 .

[0097] Figure 6G The assembly is shown after forming a via opening through the dielectric material 108, depositing a conductive material such as a metal in the opening to form the TDV 110, and planarizing the top surface of the assembly to remove the dielectric material 108 and expose the TDV 110 and the top surface of the TSV 122 in the IC die 104-1 to form the layer 102-1. The TDV 110 can be electrically coupled to the bonding pad 134 in the bonding layer 124. The top surface of the assembly can be planarized using any suitable technique, such as grinding or chemical mechanical polishing (CMP). The via opening can be formed using any suitable technique, such as laser drilling, wherein the via opening has a tapered or conical shape. Figure 6A-6F The processes described in and portions thereof may be repeated any number of times as desired to fabricate a microelectronic assembly 100 that includes any number of layers 102 and any number of IC dies 104 within a single layer 102 .

[0098] Figure 6H Shows the flip Figure 6G The component after the components are formed and finishing operations are performed on the bottom surface of the component (e.g., forming conductive contacts 144, depositing solder resist (not shown), and depositing solder 145 on the bottom surface of conductive contacts 144). If multiple components are manufactured together, component singulation can be performed. Figure 6H The component itself can be a microelectronic component 100, as shown. Figure 6H The microelectronic assembly 100 is subjected to further manufacturing operations to form other microelectronic assemblies 100; for example, the solder 145 can be used to Figure 6H The microelectronic assembly 100 is coupled to a package substrate 118, similar to Figure 1A A microelectronic assembly 100 is provided.

[0099] Figure 7 is a flow chart of an example method of manufacturing an example microelectronic assembly according to various embodiments. At 702, a second layer of IC dies 104-2, 104-3 may be attached to a substrate 112. The IC dies 104-2, 104-3 may include a metallization stack 116 facing away from the substrate 112. The IC dies 104-2, 104-3 may be coupled to the substrate 112 using any suitable technique, including by fusion bonding or by forming a hybrid direct bond.

[0100] At 704, a dielectric material 108 is deposited on and around the second layer IC dies 104-2, 104-3 and on the substrate 112. The dielectric material 108 may be deposited using any technique and may be formed to have an interface seam 125. The top surface of the dielectric material 108 may be planarized using CMP or any other suitable process to expose the bond pads 134 on the IC dies 104-2, 104-3.

[0101] At 706, a bonding layer 124 can be formed on the top surface of the IC dies 104-2, 104-3 and the dielectric layer 108. The bonding layer 124 can include a bonding pad 134 surrounded by a dielectric material 109.

[0102] At 708, the first IC die 104-1 may be attached to the top surface of the bonding layer 124. Interconnects 106 are formed to electrically couple the IC die 104-1 to the IC dies 104-2, 104-3. The interconnects 106 may be formed using any suitable bonding process, such as applying suitable pressure and heating to a suitable temperature for a period of time.

[0103] At 710, dielectric material 108 may be disposed on and around IC die 104-1 and on the top surface of bonding layer 124, and TDV 110 may be formed. Dielectric material 108 may be deposited using any technique and may be formed to have an interface seam 125. The top surface of dielectric material 108 and / or TDV 110 may be planarized using CMP or any other suitable process.

[0104] At 712, component singulation, component flipping, and surface finishing operations may be performed. In some embodiments, surface finishing operations may be performed before singulation. Surface finishing operations may include, for example, forming conductive contacts 144, dispensing solder resist, and attaching solder balls 145 at the bottom surface.

[0105] The packages disclosed herein (eg, any microelectronic assembly 100 or any further embodiments described herein) can be included in any suitable electronic component. Figure 8-Figure 10 Various examples of packages, components, and devices are shown that may be used with or include any of the IC packages as disclosed herein.

[0106] Figure 8 is a side cross-sectional view of an example IC package 2200, which may include an IC package according to any embodiment disclosed herein. In some embodiments, the IC package 2200 may be a SiP.

[0107] As shown, the package substrate 2252 may be formed of an insulator (e.g., ceramic, a built-up film, an epoxy film with filler particles therein, etc.), and may have conductive pathways extending through the insulator between the first side 2272 and the second side 2274, or extending between different locations on the first side 2272, and / or extending between different locations on the second side 2274. These conductive pathways may take the form of any of the interconnect structures including wires and / or vias.

[0108] The packaging substrate 2252 may include conductive contacts 2263, which are coupled to conductive paths 2262 passing through the packaging substrate 2252, thereby allowing the circuits within the tube core 2256 and / or the interposer 2257 to be electrically coupled to individual conductive contacts in the conductive contacts 2264 (or to other devices not shown included in the packaging substrate 2252).

[0109] IC package 2200 may include an interposer 2257 coupled to a package substrate 2252 via conductive contacts 2261 of the interposer 2257, first level interconnects 2265, and conductive contacts 2263 of the package substrate 2252. The first level interconnects 2265 shown in the figure are solder bumps, but any suitable first level interconnects 2265 may be used, such as solder bumps, solder pillars, or bond wires.

[0110] The IC package 2200 may include one or more dies 2256, which are coupled to the interposer 2257 via the conductive contacts 2254 of the dies 2256, the first-level interconnects 2258, and the conductive contacts 2260 of the interposer 2257. The conductive contacts 2260 may be coupled to conductive pathways (not shown) that pass through the interposer 2257, thereby allowing the circuits within the dies 2256 to be electrically coupled to the respective conductive contacts in the conductive contacts 2261 (or to other devices not shown included in the interposer 2257). The first-level interconnects 2258 shown in the figure are solder bumps, but any suitable first-level interconnects 2258 may be used, such as solder bumps, solder pillars, or bond wires. As used herein, "conductive contacts" may refer to a portion of a conductive material (e.g., metal) that serves as an interface between different components; the conductive contacts may be recessed into the surface of the component, flush with the surface of the component, or extend away from the surface of the component, and may take any suitable form (e.g., a conductive pad or a socket).

[0111] In some embodiments, an underfill material 2266 may be disposed around the first level interconnect 2265 between the package substrate 2252 and the interposer 2257, and a molding 2268 may be disposed around the die 2256 and the interposer 2257 and in contact with the package substrate 2252. In some embodiments, the underfill material 2266 may be the same as the molding 2268. An example material that may be used for the underfill material 2266 and the molding 2268 is a suitable epoxy. A second level interconnect 2270 may be coupled to the conductive contacts 2264. The second level interconnect 2270 shown in the figure is a solder ball (e.g., for a ball grid array (BGA) arrangement), but any suitable second level interconnect 2270 may be used (e.g., a pin in a pin grid array arrangement or a land in a land grid array arrangement). The second level interconnect 2270 may be used to couple the IC package 2200 to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as is known in the art and as described below with reference Fig. 9 discussed.

[0112] In various embodiments, any of the dies 2256 may be a microelectronic assembly 100 as described herein. In embodiments where the IC package 2200 includes a plurality of dies 2256, the IC package 2200 may be referred to as a multi-chip package (MCP). The dies 2256 may include circuits that perform any desired functions. For example, in addition to one or more of the dies 2256 being a microelectronic assembly 100 as described herein, one or more of the dies 2256 may be a logic die (e.g., a silicon-based die), one or more of the dies 2256 may be a memory die (e.g., an HBM), etc. In some embodiments, any of the dies 2256 may be implemented as discussed with reference to any of the previous figures. In some embodiments, at least some of the dies 2256 may not include an implementation as described herein.

[0113] Although the IC package 2200 shown in the figure is a flip chip package, other packaging architectures can be used. For example, the IC package 2200 can be a BGA package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package 2200 can be a wafer-level chip scale package (WLCSP) or a panel fan-out (FO) package. Although two dies 2256 are shown in the IC package 2200, the IC package 2200 can include any desired number of dies 2256. The IC package 2200 may include additional passive components, such as surface mount resistors, capacitors, and inductors disposed on the first side 2272 or the second side 2274 of the package substrate 2252 or on either side of the interposer 2257. More generally, the IC package 2200 may include any other active or passive components known in the art.

[0114] In some embodiments, interposer 2257 may not be included in IC package 2200 ; instead, die 2256 may be coupled directly to conductive contacts 2263 at first side 2272 via first level interconnects 2265 .

[0115] Fig. 9 is a cross-sectional side view of an IC device assembly 2300, which may include components having one or more microelectronic assemblies 100 according to any of the embodiments disclosed herein. The IC device assembly 2300 includes a plurality of components disposed on a circuit board 2302 (which may be, for example, a motherboard). The IC device assembly 2300 includes components disposed on a first side 2340 of the circuit board 2302 and an opposing second side 2342 of the circuit board 2302; typically, the components may be disposed on one or both of the sides 2340 and 2342. In particular, any suitable component among the components of the IC device assembly 2300 may include any of the one or more microelectronic assemblies 100 according to any of the embodiments disclosed herein; for example, any of the IC packages discussed below with reference to the IC device assembly 2300 may employ the IC packages discussed above with reference to the IC device assembly 2300. Figure 8 The IC package 2200 may be in the form of any of the embodiments discussed.

[0116] In some embodiments, circuit board 2302 may be a PCB including multiple metal layers separated from each other by insulator layers and interconnected by conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to transmit electrical signals between components coupled to circuit board 2302 (optionally in combination with other metal layers). In other embodiments, circuit board 2302 may be a non-PCB packaging substrate.

[0117] As shown, in some embodiments, the IC device assembly 2300 can include a package-on-interposer structure 2336 coupled to a first side 2340 of a circuit board 2302 via a coupling feature 2316. The coupling feature 2316 can electrically and mechanically couple the package-on-interposer structure 2336 to the circuit board 2302 and can include solder balls (as shown), protrusions and recesses of a socket, an adhesive, an underfill material, and / or any other suitable electrical and / or mechanical coupling structure.

[0118] Package structure 2336 on interposer may include IC package 2320 coupled to interposer 2304 via coupling component 2318. Coupling component 2318 may take any suitable form depending on the desired functionality, such as the forms discussed above with reference to coupling component 2316. In some embodiments, IC package 2320 may be or include, for example, as described above with reference to Figure 8 IC package 2200 is described. In some embodiments, IC package 2320 may include at least one microelectronic assembly 100 as described herein. In order not to clutter the drawings, microelectronic assembly 100 is not shown in detail.

[0119] Although a single IC package 2320 is shown, multiple IC packages can be coupled to the interposer 2304; indeed, additional interposers can be coupled to the interposer 2304. The interposer 2304 can provide an intermediate package substrate for bridging the circuit board 2302 and the IC package 2320. In general, the interposer 2304 can redistribute connections to a wider pitch or reroute connections to different connections. For example, the interposer 2304 can couple the IC package 2320 to the BGA of the coupling component 2316 to facilitate coupling to the circuit board 2302.

[0120] In the embodiment shown in the figure, IC package 2320 and circuit board 2302 are attached to opposite sides of interposer 2304. In other embodiments, IC package 2320 and circuit board 2302 can be attached to the same side of interposer 2304. In some embodiments, three or more components can be interconnected through interposer 2304.

[0121] Interposer 2304 may be formed of epoxy, glass fiber reinforced epoxy, ceramic material, or polymer material such as polyimide. In some embodiments, interposer 2304 may be formed of alternative rigid or flexible materials, which may include the same materials as those used in semiconductor substrates described above, such as silicon, germanium, and other III-V and IV materials. Interposer 2304 may include metal interconnects 2308 and vias 2310, including but not limited to TSVs 2306. Interposer 2304 may also include embedded devices 2314, including both passive devices and active devices. Such devices may include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, ESD devices, and memory devices. More complex devices, such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices, may also be formed on interposer 2304. Interposer-on-package structure 2336 may take the form of any interposer-on-package structure known in the art.

[0122] In some embodiments, IC device assembly 2300 may include an IC package 2324 coupled to first side 2340 of circuit board 2302 via coupling component 2322. Coupling component 2322 may take the form of any of the embodiments discussed above with reference to coupling component 2316, and IC package 2324 may take the form of any of the embodiments discussed above with reference to IC package 2320.

[0123] In some embodiments, the IC device assembly 2300 may include a package-on-package structure 2334 coupled to the second side 2342 of the circuit board 2302 via a coupling component 2328. The package-on-package structure 2334 may include an IC package 2326 and an IC package 2332, which are coupled together via a coupling component 2330, such that the IC package 2326 is disposed between the circuit board 2302 and the IC package 2332. The coupling components 2328 and 2330 may take the form of any of the embodiments of the coupling component 2316 discussed above, and the IC packages 2326 and / or 2332 may take the form of any of the embodiments of the IC package 2320 discussed above. The package-on-package structure 2334 may be configured according to any of the package-on-package structures known in the art.

[0124] Fig.10 2400, which may include one or more components having one or more IC packages according to any of the embodiments disclosed herein. For example, any suitable component in the components of computing device 2400 may include a microelectronic assembly (e.g., 100) according to any of the embodiments disclosed herein. In another example, any one or more of the components of computing device 2400 may include IC package 2200 (e.g., as Figure 8 In yet another example, any one or more of the components of the computing device 2400 may include the IC device assembly 2300 (e.g., as shown in Fig. 9 shown).

[0125] The figure shows that multiple components are included in the computing device 2400, but any one or more of these components can be omitted or duplicated to suit the application. In some embodiments, some or all of the components included in the computing device 2400 can be attached to one or more motherboards. In some embodiments, some or all of these components are manufactured onto a single SoC die.

[0126] Additionally, in various embodiments, computing device 2400 may not include one or more of the components shown in the figures, but computing device 2400 may include interface circuitry for coupling to the one or more components. For example, computing device 2400 may not include display device 2406, but may include display device interface circuitry (e.g., connectors and driver circuitry) to which display device 2406 may be coupled. In another set of examples, computing device 2400 may not include audio input device 2418 or audio output device 2408, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which audio input device 2418 or audio output device 2408 may be coupled.

[0127] The computing device 2400 may include a processing device 2402 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to convert the electronic data into other electronic data that can be stored in registers and / or memory. The processing device 2402 may include one or more DSPs, ASICs, CPUs, GPUs, cryptographic processors (special processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing devices. The computing device 2400 may include a memory 2404, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard drive. In some embodiments, the memory 2404 may include a memory that shares a die with the processing device 2402. The memory may be used as a cache memory and may include an embedded dynamic random access memory (eDRAM) or a spin transfer torque magnetic random access memory (STT-MRAM).

[0128] In some embodiments, computing device 2400 may include a communication chip 2412 (e.g., one or more communication chips). For example, communication chip 2412 may be configured to manage wireless communications to transmit data to and from computing device 2400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that may communicate data using modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wiring, although in some embodiments they may not.

[0129] The communication chip 2412 can implement any of a plurality of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE802.16-2005 amendment), LTE project and any amendments, updates and / or revisions (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). Broadband wireless access (BWA) networks compatible with IEEE 802.16 are generally referred to as WiMAX networks, which is an abbreviation standing for Worldwide Interoperability for Microwave Access and is a certification mark for products that have passed conformance and interoperability testing of the IEEE802.16 standard. The communication chip 2412 can operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2412 may operate according to GSM Evolution Enhanced Data (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2412 may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO) and its derivatives, and any other wireless protocols named 3G, 4G, 5G and higher. In other embodiments, the communication chip 2412 may operate according to other wireless protocols. The computing device 2400 may include an antenna 2422 to facilitate wireless communications and / or receive other wireless communications (such as AM or FM radio transmissions).

[0130] In some embodiments, the communication chip 2412 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, the communication chip 2412 can include multiple communication chips. For example, the first communication chip 2412 can be dedicated to short-range wireless communications such as Wi-Fi or Bluetooth, while the second communication chip 2412 can be dedicated to long-range wireless communications such as global positioning systems (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communication chip 2412 can be dedicated to wireless communications, while the second communication chip 2412 can be dedicated to wired communications.

[0131] Computing device 2400 may include battery / power circuitry 2414. Battery / power circuitry 2414 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of computing device 2400 to an energy source separate from computing device 2400 (e.g., AC line power).

[0132] Computing device 2400 may include a display device 2406 (or corresponding interface circuitry as discussed above). For example, display device 2406 may include any visual indicator, such as a heads-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0133] Computing device 2400 may include audio output device 2408 (or corresponding interface circuitry as discussed above). Audio output device 2408 may include any device that generates an audible indicator, such as a speaker, headphones, or earbuds, for example.

[0134] The computing device 2400 may include an audio input device 2418 (or corresponding interface circuitry as discussed above). The audio input device 2418 may include any device that generates a signal representative of sound, such as a microphone, a microphone array, or a digital instrument (e.g., an instrument with a Musical Instrument Digital Interface (MIDI) output).

[0135] Computing device 2400 may include a GPS device 2416 (or corresponding interface circuitry as discussed above). GPS device 2416 may communicate with a satellite-based system and may receive the location of computing device 2400, as is known in the art.

[0136] Computing device 2400 may include other output devices 2410 (or corresponding interface circuitry as discussed above). Examples of other output devices 2410 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or additional storage.

[0137] The computing device 2400 may include other input devices 2420 (or corresponding interface circuitry as discussed above). Examples of other input devices 2420 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0138] The computing device 2400 may have any desired form factor, such as a handheld or mobile computing device (e.g., a cellular phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device 2400 may be any other electronic device that processes data.

[0139] The above description of the illustrated embodiments of the present disclosure (including what is described in the Abstract) is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. Although specific embodiments and examples of the present disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the present disclosure as will be appreciated by those skilled in the relevant art.

[0140] Example 1 is a microelectronic assembly comprising: a first die in a first layer, the first layer having a first surface and an opposite second surface, the first die being surrounded by a dielectric material; a through-dielectric via (TDV) in the first layer, wherein the TDV has a larger width toward the first surface of the first layer and a smaller width toward the second surface of the first layer; a second die in a second layer, the second layer having a first surface and an opposite second surface, wherein the first surface of the second layer is at the second surface of the first layer, wherein the first die is electrically coupled to the second die by interconnects, the interconnects having a pitch of less than 10 microns between adjacent interconnects, and wherein the second die is surrounded by a dielectric material and includes an interface seam extending from the second die toward the first surface of the second layer at the second surface of the second layer, and the interface seam has an angle of less than 90 degrees relative to the second surface of the second layer; and a substrate coupled to the second surface of the second layer.

[0141] Example 2 may include the subject matter of Example 1, and may further specify that the dielectric material includes silicon, and one or more of nitrogen, oxygen, hydrogen, and carbon; a polyimide material; or a low-k or ultra-low-k dielectric.

[0142] Example 3 may include the subject matter of Example 1 or 2, and may further specify that the dielectric material in the first layer is a first dielectric material, and the dielectric in the second layer is a second dielectric material different from the first dielectric material.

[0143] Example 4 may include the subject matter of any of Examples 1-3, and may further specify that the angle of the interface seam relative to the second surface of the second layer is between 35 degrees and 55 degrees.

[0144] Example 5 may include the subject matter of any of Examples 1-4, and may further specify that the interface seam is a first interface seam, and wherein the dielectric material in the second layer also includes a second interface seam extending from the second die toward the first surface of the second layer at the second surface of the second layer, and the second interface seam has an angle less than 90 degrees relative to the second surface of the second layer.

[0145] Example 6 may include the subject matter of Example 5, and may further specify that the angle of the second interface seam relative to the second surface of the second layer is between 35 degrees and 55 degrees.

[0146] Example 7A may include the subject matter of any of Examples 1-6, and may further specify that the TDV is electrically coupled to the second die.

[0147] Example 7B may include the subject matter of any of Examples 1-6, and may further specify that the TDV is one of a plurality of TDVs.

[0148] Example 8 may include the subject matter of any of Examples 1-7, and may further include a package substrate electrically coupled to the first surface of the first layer by a solder interconnect.

[0149] Example 9 may include the subject matter of Example 8, and may further specify that the TDV is electrically coupled to the package substrate at a first end and to the second die at an opposing second end.

[0150] Example 10 may include the subject matter of any of Examples 1-9, and may further specify that the material of the substrate includes silicon.

[0151] Example 11 is a microelectronic component comprising: a first layer having a first surface and an opposite second surface, the first layer comprising a first die, a dielectric material around the first die, and a through-dielectric via (TDV), wherein the TDV has a larger width toward the first surface of the first layer and a smaller width toward the second surface of the first layer; and a second layer having a first surface and an opposite second surface, the first surface of the second layer being at the second surface of the first layer, the second layer comprising a second die, a third die, and dielectric material around the second die and the third die and between the second die and the third die, wherein the first die is electrically coupled to the second die and the third die via interconnects, the interconnects having a pitch of less than 10 microns between adjacent interconnects, wherein the TDV is electrically coupled to the second die, and wherein the dielectric material between the second die and the third die comprises an interface seam, the interface seam extending from the second die at the second surface of the second layer toward the third die at the first surface of the second layer, and the interface seam has an angle of less than 90 degrees relative to the second surface of the second layer.

[0152] Example 12 may include the subject matter of Example 11, and may further specify that the dielectric material includes silicon, and one or more of nitrogen, oxygen, hydrogen, and carbon; a polyimide material; or a low-k or ultra-low-k dielectric.

[0153] Example 13 may include the subject matter of Example 11 or 12, and may further specify that the dielectric material in the first layer is a first dielectric material, and the dielectric in the second layer is a second dielectric material different from the first dielectric material.

[0154] Example 14 may include the subject matter of any of Examples 11-13, and may further specify that the angle of the interface seam relative to the second surface of the second layer is between 35 degrees and 55 degrees.

[0155] Example 15 may include the subject matter of any of Examples 11-14, and may further specify that the interface seam is a first interface seam, and wherein the dielectric material between the second die and the third die also includes a second interface seam extending from the third die at the second surface of the second layer toward the second die at the first surface of the second layer, and the second interface seam has an angle less than 90 degrees relative to the second surface of the second layer.

[0156] Example 16 may include the subject matter of Example 15, and may further specify that the angle of the second interface seam relative to the second surface of the second layer is between 35 degrees and 55 degrees.

[0157] Example 17 may include the subject matter of any of Examples 11-16, and may further specify that the TDV is one of a plurality of TDVs.

[0158] Example 18 may include the subject matter of any of Examples 11-17, and may further include a package substrate electrically coupled to the first surface of the first layer by a solder interconnect.

[0159] Example 19 may include the subject matter of any of Examples 11-18, and may further include a substrate coupled to the second surface of the second layer.

[0160] Example 20 may include the subject matter of Example 19, and may further specify that the material of the substrate includes silicon.

[0161] Example 21 may include the subject matter of Example 19, and may further specify that the substrate is bonded to the second surface of the second layer.

[0162] Example 22 may include the subject matter of Example 19, and may further specify that the substrate is coupled to the second die via second interconnects, the second interconnects having a pitch of less than 10 microns between adjacent second interconnects.

[0163] Example 23 may include the subject matter of Example 22, and may further specify that the substrate further includes a conductive via, and the conductive via is electrically coupled to the second die through a second interconnect.

[0164] Example 24 may include the subject matter of Example 23, and may further specify that the conductive via in the substrate is further electrically coupled to the third die through a third interconnect, the third interconnect having a pitch of less than 10 microns between adjacent third interconnects.

[0165] Example 25 is a microelectronic component comprising: a first die in a first layer, the first layer having a first surface and an opposite second surface, the first die being surrounded by a dielectric material; a through-dielectric via (TDV) in the first layer, wherein the TDV has a larger width toward the first surface of the first layer and a smaller width toward the second surface of the first layer; a second die in a second layer, the second layer having a first surface and an opposite second surface, wherein the first surface of the second layer is at the second surface of the first layer, wherein the first die is electrically coupled to the second die via a first interconnect, the first interconnect having a pitch of less than 10 microns between adjacent first interconnects, and wherein the second die is surrounded by a dielectric material and includes an interface seam extending from the second die toward the first surface of the second layer at the second surface of the second layer, and the interface seam has an angle of less than 90 degrees relative to the second surface of the second layer; a substrate coupled to the second surface of the second layer; and a packaging substrate electrically coupled to the first surface of the first layer via a second interconnect.

[0166] Example 26 may include the subject matter of Example 25, and may further specify that the material of the substrate includes silicon.

[0167] Example 27 may include the subject matter of Example 25 or 26, and may further specify that the substrate is bonded to the second surface of the second layer.

[0168] Example 28 may include the subject matter of Example 25 or 26, and may further specify that the substrate is coupled to the second die via second interconnects, the second interconnects having a pitch of less than 10 microns between adjacent second interconnects.

[0169] Example 29 may include the subject matter of Example 28, and may further specify that the substrate further includes a conductive via, and the conductive via is electrically coupled to the second die through a second interconnect.

[0170] Example 30 is a method for manufacturing a microelectronic assembly, comprising: bonding a second die and a third die to a substrate, wherein the second die and the third die include a first surface having conductive contacts and an opposing second surface, and wherein the first surfaces of the second die and the third die face away from the substrate; depositing a dielectric material around the second die and the third die and between the second die and the third die and exposing the conductive contacts, wherein depositing the dielectric material around the second die and the third die and between the second die and the third die includes forming an interface seam between the second die and the third die, wherein the interface seam extends from the second surface of the second die toward the first surface of the third die, and wherein the interface seam has an angle of less than 90 degrees relative to the substrate; attaching the first die to the second die and the third die by forming interconnects to electrically couple the conductive contacts of the first die to the conductive contacts of the second die and the third die, wherein the interconnects have a spacing of less than 10 microns between adjacent interconnects; and depositing the dielectric material around the first die.

[0171] Example 31 may include the subject matter of Example 30, and may further specify that forming the interconnect further includes forming an interface layer having bonding pads and a dielectric material on the second die and the third die, and forming metal-metal bonds and dielectric-dielectric bonds with the interface layer.

[0172] Example 32 may include the subject matter of Example 30 or 31, and may further specify that depositing dielectric material around the second die and the third die and between the second die and the third die also includes forming a second interface seam between the second die and the third die, wherein the second interface seam extends from the second surface of the third die toward the first surface of the second die, and wherein the second interface seam has an angle less than 90 degrees relative to the substrate.

[0173] Example 33 may include the subject matter of any of Examples 30 to 32, and may further include forming a through-dielectric via (TDV) in the dielectric material adjacent to the first die, wherein the TDV is electrically coupled to the first surface of the second die, and wherein the TDV has a smaller width toward the first surface of the second die.

[0174] Example 34 may include the subject matter of any of Examples 30 to 33, and may further specify that the dielectric material includes silicon, and one or more of nitrogen, oxygen, hydrogen, and carbon; a polyimide material; or a low-k or ultra-low-k dielectric.

[0175] Example 35 may include the subject matter of Example 33, and may further include electrically coupling a packaging substrate to the first die and the TDV.

Claims

1. A microelectronic assembly comprising: a first die in a first layer, the first layer having a first surface and an opposing second surface, the first die being surrounded by a dielectric material; a through dielectric via (TDV) in the first layer, wherein the TDV has a larger width toward the first surface of the first layer and a smaller width toward the second surface of the first layer; a second die in a second layer, the second layer having a first surface and an opposing second surface, wherein the first surface of the second layer is at the second surface of the first layer, wherein the first die is electrically coupled to the second die by interconnects having a pitch between adjacent interconnects of less than 10 microns, and wherein the second die is surrounded by a dielectric material and includes an interface seam extending from the second die at the second surface of the second layer toward the first surface of the second layer, and the interface seam has an angle of less than 90 degrees relative to the second surface of the second layer; and A substrate is coupled to the second surface of the second layer.

2. The microelectronic assembly according to claim 1, wherein: The dielectric material comprises: one or more of nitrogen, oxygen and carbon, and silicon; Polyimide material; or Low-k or ultra-low-k dielectrics.

3. The microelectronic assembly according to claim 1 or 2, wherein: The dielectric material in the first layer is a first dielectric material, and the dielectric material in the second layer is a second dielectric material different from the first dielectric material.

4. The microelectronic assembly according to any one of claims 1 to 3, wherein: The interface seam is at an angle between 35 degrees and 55 degrees relative to the second surface of the second layer.

5. The microelectronic assembly according to any one of claims 1 to 4, wherein: The interface seam is a first interface seam, and wherein the dielectric material in the second layer further comprises a second interface seam extending from the second die toward the first surface of the second layer at the second surface of the second layer, and the second interface seam has an angle less than 90 degrees relative to the second surface of the second layer.

6. The microelectronic assembly according to claim 5, wherein: The second interface seam is at an angle between 35 degrees and 55 degrees relative to the second surface of the second layer.

7. A microelectronic assembly according to any one of claims 1 to 6, wherein: The TDV is electrically coupled to the second die.

8. The microelectronic assembly according to any one of claims 1 to 7, further comprising: A package substrate is electrically coupled to the first surface of the first layer through a solder interconnect.

9. The microelectronic assembly of claim 8, wherein: The TDV is electrically coupled to the package substrate at a first end and to the second die at an opposing second end.

10. The microelectronic assembly according to any one of claims 1 to 9, wherein: The material of the substrate includes silicon.

11. A microelectronic assembly comprising: a first layer having a first surface and an opposing second surface, the first layer comprising a first die, a dielectric material around the first die, and a through-dielectric via (TDV), wherein the TDV has a larger width toward the first surface of the first layer and a smaller width toward the second surface of the first layer; and A second layer having a first surface and an opposing second surface, the first surface of the second layer being at the second surface of the first layer, the second layer comprising a second die, a third die, and dielectric material on and between the second die and the third die, wherein the first die is electrically coupled to the second die and the third die via interconnects having a pitch of less than 10 microns between adjacent interconnects, wherein the TDV is electrically coupled to the second die, and wherein the dielectric material between the second die and the third die comprises an interface seam extending from the second die at the second surface of the second layer toward the third die at the first surface of the second layer, and the interface seam has an angle of less than 90 degrees relative to the second surface of the second layer.

12. The microelectronic assembly of claim 11, wherein: The interface seam is at an angle between 35 degrees and 55 degrees relative to the second surface of the second layer.

13. A microelectronic assembly according to claim 11 or 12, wherein: The interface seam is a first interface seam, and wherein the dielectric material between the second tube core and the third tube core also includes a second interface seam, the second interface seam extending from the third tube core at the second surface of the second layer toward the second tube core at the first surface of the second layer, and the second interface seam has an angle less than 90 degrees relative to the second surface of the second layer.

14. The microelectronic assembly of claim 13, wherein: The second interface seam is at an angle between 35 degrees and 55 degrees relative to the second surface of the second layer.

15. The microelectronic assembly according to any one of claims 11 to 14, further comprising: A substrate is coupled to the second surface of the second layer through second interconnects, the second interconnects having a pitch of less than 10 microns between adjacent second interconnects.

16. The microelectronic assembly of claim 15, wherein: The substrate also includes a conductive via, and the conductive via is electrically coupled to the second die through the second interconnect.

17. A microelectronic assembly comprising: a first die in a first layer, the first layer having a first surface and an opposing second surface, the first die being surrounded by a dielectric material; a through dielectric via (TDV) in the first layer, wherein the TDV has a larger width toward the first surface of the first layer and a smaller width toward the second surface of the first layer; a second die in a second layer, the second layer having a first surface and an opposing second surface, wherein the first surface of the second layer is at the second surface of the first layer, wherein the first die is electrically coupled to the second die by first interconnects, the first interconnects having a pitch between adjacent first interconnects of less than 10 microns, and wherein the second die is surrounded by a dielectric material and includes an interface seam extending from the second die at the second surface of the second layer toward the first surface of the second layer, and the interface seam has an angle of less than 90 degrees relative to the second surface of the second layer; a substrate coupled to the second surface of the second layer; and A package substrate is electrically coupled to the first surface of the first layer through a second interconnect.

18. The microelectronic assembly of claim 17, wherein: The material of the substrate includes silicon.

19. A microelectronic assembly according to claim 17 or 18, wherein: The substrate is coupled to the second die through second interconnects having a pitch of less than 10 microns between adjacent second interconnects.

20. The microelectronic assembly of claim 19, wherein: The substrate also includes a conductive via, and the conductive via is electrically coupled to the second die through the second interconnect.

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