Voltage regulation circuit

Abstract

The invention provides a voltage regulating circuit which comprises a first current source and at least two first voltage stabilizing devices, the first current source and the at least two first voltage stabilizing devices are connected between a power supply voltage end and a grounding end in series, a first current provided by the first current source flows through each first voltage stabilizing device, and each first voltage stabilizing device has a first preset voltage drop; the second current source, the MOS transistor M4 and the MOS transistor M5 are connected between the power supply voltage end and the grounding end in series, second current provided by the second current source flows through the MOS transistor M4 and the MOS transistor M5, the grid electrode of the MOS transistor M4 is coupled to one connecting end of a corresponding first voltage stabilizing device, and the grid electrode of the MOS transistor M5 is coupled to the other connecting end of the corresponding second voltage stabilizing device. The grid electrode of the MOS transistor M5 is coupled to one connecting end of the other corresponding first voltage stabilizing device; the MOS transistor M6 is coupled between the power supply voltage end and a voltage output end, a grid electrode of the MOS transistor M6 is coupled to the second current source and an intermediate node A of the MOS transistor M4, and the voltage output end is coupled to an intermediate node B of the MOS transistor M4 and the MOS transistor M5. Therefore, the voltage regulation circuit can have a simple structure and very low power consumption.

Description

[Technical field]

[0001] The present invention relates to the field of circuit design, and in particular to a voltage regulating circuit. [Background technology]

[0002] The Chinese patent application with application number 201510187845.0 discloses a low-dropout voltage regulator (LDO), which includes a power output tube MP5, an error amplifier EA and a voltage divider circuit. The error amplifier EA controls the gate voltage of the power output tube MP5 according to the feedback voltage VB provided by the voltage divider circuit, thereby controlling the output voltage VO. However, due to the use of the error amplifier EA and the voltage divider circuit, the low-dropout voltage regulator has the problems of complex structure, high power consumption and large occupied area.

[0003] Therefore, it is necessary to propose an improved technical solution to overcome the above problems. [Summary of the invention]

[0004] One of the purposes of the present invention is to provide a voltage regulating circuit with a simple structure and low power consumption.

[0005] According to one aspect of the present invention, the present invention provides a voltage regulating circuit, which includes: a first current source connected in series between a power supply voltage terminal and a ground terminal and at least two first voltage stabilizing devices, wherein a first current provided by the first current source flows through each first voltage stabilizing device, and each first voltage stabilizing device has a first predetermined voltage drop; a second current source, a MOS transistor M4 and a MOS transistor M5 connected in series between the power supply voltage terminal and the ground terminal, wherein a second current provided by the second current source flows through the MOS transistor M4 and the MOS transistor M5, a gate of the MOS transistor M4 is coupled to a connection terminal of a corresponding first voltage stabilizing device, and a gate of the MOS transistor M5 is coupled to a connection terminal of another corresponding first voltage stabilizing device; a MOS transistor M6 coupled between the power supply voltage terminal and a voltage output terminal, a gate of which is coupled to an intermediate node A between the second current source and the MOS transistor M4, wherein the voltage output terminal is coupled to an intermediate node B between the MOS transistor M4 and the MOS transistor M5.

[0006] Compared with the prior art, the present invention does not need to use an error amplifier EA and a voltage divider circuit. The voltage regulation circuit has a simple structure and low power consumption, and can provide a power supply voltage when the system is in sleep mode, thereby reducing costs.

Brief Description of the Drawings

[0007] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor. Among them:

[0008] Figure 1 is a circuit diagram of a voltage regulating circuit in a first embodiment of the present invention;

[0009] Figure 2 FIG. 4 is a circuit diagram of a voltage regulating circuit in a second embodiment of the present invention. [Specific implementation method]

[0010] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0011] The term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The term "in one embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor does it refer to a separate or selective embodiment that is mutually exclusive with other embodiments.

[0012] The present invention provides a voltage regulating circuit which does not need to use an error amplifier EA and a voltage divider circuit, has the advantages of simple structure and low power consumption, can provide a power supply voltage when the system is dormant, and reduces the cost.

[0013] Figure 1 FIG. 1 is a circuit diagram of a voltage regulating circuit in a first embodiment of the present invention. Figure 1 As shown, the voltage regulation circuit includes: a first current source I20 and three first voltage stabilizing devices 110a, 110b and 110c connected in series between the power supply voltage terminal AVDD and the ground terminal AGND; a second current source I21, a MOS transistor M4 and a MOS transistor M5 connected in series between the power supply voltage terminal AVDD and the ground terminal AGND; a MOS transistor M6 and a resistor R0 coupled between the power supply voltage terminal AVDD and the voltage output terminal VREG.

[0014] The first current provided by the first current source I20 flows through each of the first voltage stabilizing devices 110a, 110b and 110c, and each of the first voltage stabilizing devices has a first predetermined voltage drop. The second current provided by the second current source I21 flows through the MOS transistor M4 and the MOS transistor M5. The gate of the MOS transistor M4 is coupled to a connection terminal of a corresponding first voltage stabilizing device 110a, and the gate of the MOS transistor M5 is coupled to a connection terminal of another corresponding first voltage stabilizing device 110b. The gate of the MOS transistor M6 is coupled to the intermediate node A between the second current source I21 and the MOS transistor M4, wherein the voltage output terminal VREG is coupled to the intermediate node B between the MOS transistor M4 and the MOS transistor M5 through the second voltage stabilizing device 120a. The second voltage stabilizing device 120a has a second predetermined voltage drop.

[0015] exist Figure 1 In the illustrated embodiment, the MOS transistors M4 and M5 are NMOS transistors, and the MOS transistor M6 is a PMOS transistor. The source of the MOS transistor M4 is coupled to the middle node B, and the drain of the MOS transistor M4 is coupled to the middle node A. The drain of the MOS transistor M5 is coupled to the middle node B, and the source of the MOS transistor M5 is coupled to the ground terminal. The source of the MOS transistor M6 is coupled to the power supply voltage terminal, and the drain of the MOS transistor M6 is coupled to the voltage output terminal.

[0016] The first voltage stabilizing device 110a-110c can be a diode-connected PMOS (positive channel Metal Oxide Semiconductor) transistor, a diode-connected NMOS (negative channel Metal Oxide Semiconductor) transistor, a diode, or a diode-connected bipolar transistor. The second voltage stabilizing device 120a is a diode-connected PMOS transistor, a diode-connected NMOS transistor, a diode, or a diode-connected bipolar transistor. Specifically, the diode connection of the NMOS transistor is: the gate and drain of the NMOS transistor are interconnected as the positive electrode, and the source of the NMOS transistor is the negative electrode; the diode connection of the PMOS transistor is: the gate and drain of the PMOS transistor are interconnected as the negative electrode, and the source of the PMOS transistor is the positive electrode.

[0017] exist Figure 1In the illustrated embodiment, the first voltage stabilizing devices 110a-110c are diode-connected NMOS transistors. The first voltage stabilizing device corresponding to the MOS transistor M5 is the MOS transistor M3, the gate of the MOS transistor M3 is coupled to the gate of the MOS transistor M5, the gate and drain of the MOS transistor M3 are interconnected and coupled to the negative electrode of the other first voltage stabilizing devices, and the source of the MOS transistor M3 is coupled to the ground terminal. The MOS transistor M5 and the MOS transistor M3 form a current mirror, and the first voltage stabilizing device corresponding to the MOS transistor M4 is the MOS transistor M1, the gate of the MOS transistor M1 is coupled to the gate of the MOS transistor M4, the gate and drain of the MOS transistor M1 are interconnected and coupled to the output end of the first current source, and the source of the MOS transistor M1 is coupled to the positive electrode of the other first voltage stabilizing device.

[0018] according to Figure 1 From the circuit connection relationship shown in the figure, VREG=V gsM1 +V gsM2 +V gsM3 -V gsM4 +V gsM7 =3*Vgs, where VREG is the voltage at the voltage output terminal, V gsM1 is the gate-source voltage of the MOS transistor M1, that is, the first predetermined voltage drop of the first voltage stabilizing device 110a, V gsM2 is the gate-source voltage of the MOS transistor M2, that is, the first predetermined voltage drop of the first voltage stabilizing device 110c, V gsM3 is the gate-source voltage of the MOS transistor M3, that is, the first predetermined voltage drop of the first voltage stabilizing device 110b, V gsM4 is the gate-source voltage of MOS transistor M4, V gsM7 is the gate-source voltage of the MOS transistor M7, ie, the second predetermined voltage drop of the second voltage stabilizing device 120a, wherein the first predetermined voltage drop of the first voltage stabilizing device can be set to be the same as the second predetermined voltage drop of the second voltage stabilizing device 120a.

[0019] In some embodiments, the first predetermined voltage drop of the first voltage stabilizing device 120 b may also be set to be different from the second predetermined voltage drop of the second voltage stabilizing device 120 b .

[0020] In some embodiments, the MOS transistor M2 may be omitted, and the MOS transistor M7 may also be omitted, so that VREG=V gsM1 +V gsM3 -V gsM4 =1*Vgs.

[0021] Figure 2 FIG. 4 is a circuit diagram of a voltage regulating circuit in a second embodiment of the present invention. Figure 2 The voltage regulation circuit in Figure 1The voltage regulation circuit in is different in that: Figure 2 The number of first voltage stabilizing devices between the MOS transistors M1 and M3 in the embodiment is different. Figure 2 More first voltage stabilizing devices, namely MOS transistors M2 and M8, etc. are shown; Figure 2 The number of second voltage stabilizing devices between the voltage output terminal VREG and the intermediate node B is different. Figure 2 More second voltage stabilizing devices are shown, namely, MOS transistors M9, M10 and M7, etc. By adjusting the number of first voltage stabilizing devices and the number of second voltage stabilizing devices, the value of the output voltage VREG can be adjusted.

[0022] As described above, the first voltage stabilizing device and the second voltage stabilizing device may also be in other forms, such as a diode-connected PMOS transistor, a diode, or a diode-connected bipolar transistor, etc., which will not be described again here.

[0023] Please refer to Figure 1 As shown, the working principle of the present invention is illustrated below. If the voltage VA of the middle node A decreases, the Vsg (gate-source voltage) of the MOS transistor M6 increases, the current flowing through the MOS transistor M6 increases, the output voltage VREG increases, and the voltage VB of the middle node B also increases accordingly. Correspondingly, when the voltage VB increases, the Vgs of the MOS transistor M4 decreases, which eventually causes the voltage VA to increase, thereby performing negative feedback and causing VREG to have a stable voltage output. On the contrary, when the voltage VA increases, the negative feedback loop in the circuit causes the voltage VA to decrease, and finally the output voltage VREG will have a stable voltage output after the circuit stabilizes.

[0024] In one embodiment, the first current provided by the first power source I20 may be 200nA, the second current provided by the second current source I21 may be 100nA, and the current on the MOS transistor M7 is 100nA, so that the power consumption of the entire voltage regulation circuit will be very low. The operational amplifier in the existing low-dropout voltage regulator LDO has a large power consumption, and the static current is at the uA level, which is much higher than the power consumption of the present invention. In addition, the circuit structure in the present invention is simpler than the prior art and occupies a smaller area.

[0025] When the voltage of the middle node A is very low, the current of the MOS transistor M6 may be very large, and the resistor R0 can be used for current limiting at this time. Of course, in some embodiments, the resistor R0 may not be provided, and the voltage regulating circuit of the present invention can also operate. In addition, the resistor R0 may also be provided between the MOS transistor M6 and the voltage output terminal VREG.

[0026] In another embodiment, the MOS transistors M4 and M5 may also be PMOS transistors, and the MOS transistor M6 may also be an NMOS transistor.

[0027] In the present invention, words such as "connect", "connected", "connect", "coupled", "interconnected" and the like indicating electrical connection, unless otherwise specified, indicate direct or indirect electrical connection. The direct electrical connection indicates a direct connection between two or more objects without any intervening objects, and the indirect electrical connection indicates an electrical connection between two or more objects with one or more objects (such as electrical components or electrical units such as resistors, capacitors, inductors, switches, filters, etc.) intervening.

[0028] It should be noted that any changes made by those skilled in the art to the specific embodiments of the present invention do not deviate from the scope of the claims of the present invention. Accordingly, the scope of the claims of the present invention is not limited to the above specific embodiments.

Claims

1. A voltage regulating circuit, characterized in that: It includes: A first current source and at least two first voltage stabilizing devices are connected in series between a power supply voltage terminal and a ground terminal, wherein a first current provided by the first current source flows through each first voltage stabilizing device, and each first voltage stabilizing device has a first predetermined voltage drop; A second current source, a MOS transistor M4 and a MOS transistor M5 are connected in series between the power supply voltage terminal and the ground terminal, wherein a second current provided by the second current source flows through the MOS transistor M4 and the MOS transistor M5, a gate of the MOS transistor M4 is coupled to a connection terminal of a corresponding first voltage stabilizing device, and a gate of the MOS transistor M5 is coupled to a connection terminal of another corresponding first voltage stabilizing device; The MOS transistor M6 coupled between the power supply voltage terminal and the voltage output terminal has a gate coupled to the second current source and the intermediate node A of the MOS transistor M4, wherein the voltage output terminal is coupled to the intermediate node B of the MOS transistor M4 and the MOS transistor M5.

2. The voltage regulating circuit according to claim 1, characterized in that: The source of the MOS transistor M4 is coupled to the middle node B, and the drain of the MOS transistor M4 is coupled to the middle node A. A drain of the MOS transistor M5 is coupled to the middle node B, and a source of the MOS transistor M5 is coupled to the ground.

3. The voltage regulating circuit according to claim 2, characterized in that: A source of the MOS transistor M6 is coupled to the power voltage terminal, and a drain of the MOS transistor M6 is coupled to the voltage output terminal.

4. The voltage regulating circuit according to claim 3, characterized in that: The MOS transistors M4 and M5 are NMOS transistors The MOS transistor M6 is a PMOS transistor.

5. The voltage regulating circuit according to claim 1, characterized in that: It also includes: One or more second voltage stabilizing devices are coupled between the voltage output terminal and the intermediate node B, each of the second voltage stabilizing devices having a second predetermined voltage drop.

6. The voltage regulating circuit according to claim 5, characterized in that: The first voltage stabilizing device is a diode-connected PMOS transistor, a diode-connected NMOS transistor, a diode, or a diode-connected bipolar transistor; The second voltage stabilizing device is a diode-connected PMOS transistor, a diode-connected NMOS transistor, a diode, or a diode-connected bipolar transistor.

7. The voltage regulating circuit according to claim 6, characterized in that: The diode connection of the NMOS transistor is as follows: the gate and drain of the NMOS transistor are interconnected as the positive electrode, and the source of the NMOS transistor is used as the negative electrode; The diode connection of the PMOS transistor is as follows: the gate and drain of the PMOS transistor are interconnected as the negative electrode, and the source of the PMOS transistor is the positive electrode.

8. The voltage regulating circuit according to claim 6, characterized in that: The first voltage stabilizing device is a diode-connected NMOS transistor. The first voltage stabilizing device corresponding to the MOS transistor M5 is a MOS transistor M3, the gate of the MOS transistor M3 is coupled to the gate of the MOS transistor M5, the gate and drain of the MOS transistor M3 are interconnected and coupled to the negative electrode of the other first voltage stabilizing device, and the source of the MOS transistor M3 is coupled to the ground terminal. MOS transistor M5 and MOS transistor M3 form a current mirror. The first voltage stabilizing device corresponding to the MOS transistor M4 is a MOS transistor M1, the gate of the MOS transistor M1 is coupled to the gate of the MOS transistor M4, the gate and drain of the MOS transistor M1 are interconnected and coupled to the output end of the first current source, and the source of the MOS transistor M1 is coupled to the positive electrode of the other first voltage stabilizing device.

9. The voltage regulating circuit according to claim 1, characterized in that: It also includes: A resistor R0 is coupled between the power voltage terminal and the voltage output terminal and connected in series with the MOS transistor M6.

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