A test method and device applied to cache reading of a Nand Flash controller and a medium

Abstract

The present application relates to the field of storage, and in particular to a test method and device for cache reading of a Nand Flash controller and a medium. The present application sets a cache reading time standard, constructs a test scene, returns results, and checks the results. In the stage of setting the cache reading time standard, the same lun is read multiple times to obtain a time reference for reading data from the cache. In the stage of constructing the test scene, different read and write operations are sent according to the actual application scene. In the stage of returning the results, the data returned by the NFC is processed for the next step of analysis. In the stage of checking the results, it is judged whether the returned data is read from the cache, and a visual report is generated. The present application can verify whether the flash controller can effectively read data from the cache, and improve the read performance and data access speed of the NAND Flash storage system.

Description

Technical Field

[0001] The present invention relates to the field of storage, and in particular to a test method, device and medium for Nand Flash controller cache reading. Background Art

[0002] NAND Flash is a non-volatile memory based on NAND technology. It offers advantages such as high storage density and fast rewrite speed, making it widely used in various solid-state drives. To improve data access speed in NAND Flash memory, cache read technology has been introduced. When the controller receives a read request, it first checks whether the requested data is already stored in the cache. If the data is already in the cache (a cache hit), the controller directly reads the data from the cache and returns it to the requester. This effectively reduces the number of data reads from the NAND Flash chip, thereby improving system performance and responsiveness.

[0003] Existing cache read test methods directly read data from Nand flash, such as reading data from a specified address to test cache read. This method is difficult to cover complex actual application scenarios, such as multi-plan random read and write concurrency, and testing across different luns and pages, and lacks flexibility. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a test method, device and medium for Nand Flash controller cache reading, perform special tests on cache read operations, and verify the cache read function inside the NAND Flash controller in detail, covering a variety of practical application scenarios.

[0005] In order to solve the above technical problem, the present invention adopts a technical solution: a test method for Nand Flash controller cache reading, comprising the following steps:

[0006] S01) Set the cache read time standard. The cache read time standard includes the single plane read time standard and the multi-plane read time standard. First, initialize the NAND storage organization structure PBA information to be operated, including channel, chip, lun, block, set the transmission data size and transmission mode, and then send multiple single-plane read operations to NFC to determine the time to read data from the single plane in the cache, recorded as sp_cache_level, and then send multiple multi-plane read operations to determine the time to read data from the multi-plane in the cache, recorded as mp_cache_level;

[0007] S02) Construct a test scenario and send different read and write operations according to the actual application scenario, including mixed read and write of different flash memory types on the same lun, read of different luns, read of different planes, and read of different pages;

[0008] S03) Result return: process the data returned by NFC;

[0009] S04) Result verification: perform result verification based on the data returned by NFC, and compare the verification result with the expected result. If they are consistent, the cache read function is correct, otherwise it is incorrect.

[0010] Furthermore, step S04 specifically includes the following steps: first, determining whether the status bit is 9c. If not, the test fails. If so, the read data is then determined to be correct. If not, the test fails. If so, the read performance is then determined to be improved. The performance data is compared with the sp_cache_level and mp_cache_level set in step S02. For a single-plane read operation, if the read time is less than the sp_cache_level, the performance is considered improved and the test passes. Otherwise, the test fails. For a multi-plane read operation, if the read time is less than the mp_cache_level, the performance is considered improved and the test passes. Otherwise, the test fails.

[0011] Further, the test process of mixed read and write of same lun and different flash types is as follows: under the same lun, read and write operations are performed through single plane and multi-plane, including first write and then read, first read and then write, read and write concurrent scenarios. For cached data reading, first determine whether the state bit is 9c. If not, the test fails. If yes, continue to determine whether the read data is correct. If not, the test fails. If yes, continue to determine whether the read performance is improved. Compare the performance data with sp_cache_level and mp_cache_level set in step S02. For single plane read operation, if the read time is less than sp_cache_level, it is considered that the performance is improved, the test passes, otherwise the test fails. For multi-plane, if the read time is less than mp_cache_level, it is considered that the performance is improved, the test passes, otherwise the test fails.

[0012] Further, the test process of mixed read and write of same lun and different flash types is as follows: under the same lun, read and write operations are performed through single plane and multi-plane, including first write and then read, first read and then write, read and write concurrent scenarios. For cached data reading, first determine whether the state bit is 9c. If not, the test fails. If yes, continue to determine whether the read data is correct. If not, the test fails. If yes, continue to determine whether the read performance is improved. Compare the performance data with sp_cache_level and mp_cache_level set in step S02. For single plane read operation, if the read time is less than sp_cache_level, it is considered that the performance is improved, the test passes, otherwise the test fails. For multi-plane, if the read time is less than mp_cache_level, it is considered that the performance is improved, the test passes, otherwise the test fails.

[0013] For each read operation, set the expected value, compare the test result with the expected result, if it meets the expectation, the test passes, otherwise, the test fails.

[0014] The expected result is that the state bit returned by the second reading is not 0x9c, the slot done time of the second reading is greater than sp_cache_level, and the state bit returned by the third reading is 0x9c, and the read slot done time is not greater than sp_cache_level.

[0015] Further, the test process of mixed read and write of same lun and different flash types is as follows: under the same lun, read and write operations are performed through single plane and multi-plane, including first write and then read, first read and then write, read and write concurrent scenarios. For cached data reading, first determine whether the state bit is 9c. If not, the test fails. If yes, continue to determine whether the read data is correct. If not, the test fails. If yes, continue to determine whether the read performance is improved. Compare the performance data with sp_cache_level and mp_cache_level set in step S02. For single plane read operation, if the read time is less than sp_cache_level, it is considered that the performance is improved, the test passes, otherwise the test fails. For multi-plane, if the read time is less than mp_cache_level, it is considered that the performance is improved, the test passes, otherwise the test fails.

[0016] For each read operation, set the expected value, compare the test result with the expected result, if it meets the expectation, the test passes, otherwise, the test fails.

[0017] The expected result is that the state bit returned by the second reading is not 0x9c, the slot done time of the second reading is greater than sp_cache_level, and the state bit returned by the third reading is 0x9c, and the read slot done time is not greater than sp_cache_level.

[0018] Furthermore, the test process for reading different pages is as follows: first send a single plane read operation of lun0 plane0 page0 to NFC, and then send a single plane read operation of lun0 plane0 page1;

[0019] For each read operation, an expected value is set and the test result is compared with the expected result. If it meets the expectation, the test passes; otherwise, the test fails.

[0020] The expected result is: the status bit returned by the second read is not 0x9c, the read data is correct, and the slot done time is greater than sp_cache_level.

[0021] Furthermore, a result verification interface is encapsulated to read data from the cache and obtain data from NFC, and the result verification is performed through the result verification interface.

[0022] Furthermore, all operations, data and test result information during the operation process are recorded to generate a test report.

[0023] The present invention also discloses a test device for Nand Flash controller cache reading, comprising a processor and a memory storing program instructions, characterized in that the processor is configured to execute the above-mentioned test method for Nand Flash controller cache reading when running the program instructions.

[0024] A storage medium stores program instructions, wherein the program instructions, when running, execute the above-mentioned test method applied to Nand Flash controller cache reading.

[0025] Beneficial effects of the present invention:

[0026] 1) Enhanced Test Accuracy: This method specifically tests cache read operations, covering both cache hit and miss scenarios and validating the read data to ensure the NAND Flash controller operates correctly in both cache hit and miss scenarios. This helps identify potential cache coherence issues or read errors, improving test accuracy and reliability.

[0027] 2) High Flexibility: This method can be customized for testing different NAND Flash controllers and cache strategies, adapting to diverse hardware and software environments. Furthermore, the test scenario design is highly flexible and can be expanded and adjusted based on actual needs.

[0028] 3) The test results are clear, which helps in statistical analysis and improves test efficiency and quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is a flow chart of the test method described in Example 1;

[0030] Figure 2 Flowchart for result verification. DETAILED DESCRIPTION

[0031] The present invention will be further described below with reference to the accompanying drawings and specific implementations.

[0032] Example 1

[0033] This embodiment discloses a test method for Nand Flash controller cache reading, such as Figure 1 As shown, the following steps are included:

[0034] S01) Set the cache read time standard. The cache read time standard includes the single plane read time standard and the multi-plane read time standard. First, initialize the NAND storage organization structure PBA information to be operated, including channel, chip, lun, block, set the transmission data size and transmission mode, and then send multiple single-plane read operations to NFC to determine the time to read data from the single plane in the cache, recorded as sp_cache_level, and then send multiple multi-plane read operations to determine the time to read data from the multi-plane in the cache, recorded as mp_cache_level.

[0035] S02) Construct a test scenario and send different read and write operations according to the actual application scenario, including mixed read and write of the same lun and different flash memory types, read of different luns, read of different planes, and read of different pages.

[0036] S03) The result is returned, and the data returned by NFC is processed for further analysis.

[0037] S04) Result verification: perform result verification based on the data returned by NFC, and compare the verification result with the expected result. If they are consistent, the cache read function is correct, otherwise it is incorrect.

[0038] like Figure 2As shown, step S04 specifically includes: first, determining whether the status bit is 9c (in NAND Flash, if the command sent is to return data from the cache, the corresponding bit in the status register will be set to 9c, indicating that the operation of reading data from the cache has been successfully completed). If not, the test fails. If so, the process continues to determine whether the read data is correct. If not, the test fails. If so, the process continues to determine whether the read performance is improved. The performance data is compared with the sp_cache_level and mp_cache_level set in step S02. For a single-plane read operation, if the read time is less than the sp_cache_level, the performance is considered to be improved and the test passes. Otherwise, the test fails. For a multi-plane read operation, if the read time is less than the mp_cache_level, the performance is considered to be improved and the test passes. Otherwise, the test fails.

[0039] In this embodiment, different read and write operations are sent according to actual application scenarios, including mixed read and write of the same lun and different flash memory types, read of different luns, read of different planes, and read of different pages. The test process of various read and write operations is as follows:

[0040] The test process for mixed read and write operations with different flash memory types in the same LUN is as follows: under the same LUN, read and write operations are performed through single-plane and multi-plane, including write-first-read-later, read-first-write-later, and concurrent read and write scenarios. For cached data reads, the test first determines whether the status bit is 9c. If not, the test fails. If so, the test continues to determine whether the read data is correct. If not, the test fails. If so, the test continues to determine whether the read performance has improved. The performance data is compared with the sp_cache_level and mp_cache_level set in step S02. For single-plane read operations, if the read time is less than the sp_cache_level, the performance is considered to have improved and the test passes; otherwise, the test fails. For multi-plane read operations, if the read time is less than the mp_cache_level, the performance is considered to have improved and the test passes; otherwise, the test fails.

[0041] The test process of different lun read is as follows: first, continuously sending lun0 single plane read operation to NFC, then sending a lun1 single plane read operation, and finally sending a single plane read of lun0; for each read operation, the expected value is set, the test result is compared with the expected result, if it meets the expectation, the test passes, otherwise, the test fails; the expected result is that the status bit returned by the second read is not 0x9c, the slot done time of read is greater than sp_cache_level, and the status bit returned by the third read is 0x9c, and the slot done time of read is not greater than sp_cache_level.

[0042] The test process of different plane read is as follows: first, continuously sending lun0 plane0 and lun0 plane1 single plane read operation to NFC, and then repeating the above operation; for each read operation, the expected value is set, the test result is compared with the expected result, if it meets the expectation, the test passes, otherwise, the test fails; the expected result is that the status bit returned by the second read is not 0x9c, the status bit returned by the third and fourth read is 0x9c, the slot done time of the second read is greater than sp_cache_level, and the read time of the third and fourth read is not greater than sp_cache_level.

[0043] The test process of different page read is as follows: first, sending a single plane read of lun0 plane0 page0 to NFC, and then sending a single plane read of lun0 plane0 page1; for each read operation, the expected value is set, the test result is compared with the expected result, if it meets the expectation, the test passes, otherwise, the test fails; the expected result is that the status bit returned by the second read is not 0x9c, the data of read is correct, and the slot done time is greater than sp_cache_level.

[0044] In this embodiment, a result verification interface for reading data from cache and verifying the result of data obtained from NFC is packaged, and the result verification is performed through the result verification interface.

[0045] The method records all operations, data and test result information in the operation process, and generates a test report, so as to facilitate subsequent analysis and problem positioning.

[0046] The above test scenarios are designed and executed to comprehensively verify the cache read module of the NAND Flash controller.

[0047] Embodiment 2

[0048] This embodiment discloses a test device for Nand Flash controller cache reads, comprising a processor and memory. Optionally, the device may also include a communication interface and a bus. The processor, communication interface, and memory may communicate with each other via the bus. The communication interface may be used for information transmission. The processor may invoke logic instructions in the memory to execute the Nand Flash controller cache read test method of the above embodiment.

[0049] In addition, the logic instructions in the above-mentioned memory can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.

[0050] Memory, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as the program instructions / modules corresponding to the methods in the embodiments of the present disclosure. The processor executes the program instructions / modules stored in the memory to perform functional applications and data processing, thereby implementing the test method for Nand Flash controller cache reads in the above-mentioned embodiments.

[0051] The memory may include a program storage area and a data storage area. The program storage area may store an operating system and at least one application required for a function; the data storage area may store data generated based on the use of the terminal device. Furthermore, the memory may include high-speed random access memory and non-volatile memory.

[0052] Example 3

[0053] An embodiment of the present disclosure provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are configured to execute the above-mentioned test method applied to Nand Flash controller cache reading.

[0054] The aforementioned computer-readable storage medium may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

[0055] The technical solutions of the embodiments of the present disclosure may be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for causing a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in the embodiments of the present disclosure. The aforementioned storage medium may be a non-transitory storage medium, including: a USB flash drive, a mobile hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, an optical disk, and other media that can store program code, or a transient storage medium.

[0056] The above description and the accompanying drawings sufficiently illustrate the embodiments of the present disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent only possible variations. Unless expressly required, individual components and functions are optional, and the order of operations may vary. Portions and features of some embodiments may be included in or replace portions and features of other embodiments. Moreover, the terms used in this application are only used to describe the embodiments and are not used to limit the claims. As used in the description of the embodiments and claims, the singular forms "a", "an" and "the" are intended to also include the plural forms unless the context clearly indicates otherwise. Similarly, the term "and / or" as used in this application means any and all possible combinations of one or more of the associated listings. In addition, when used in this application, the term "comprise" and its variations "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, an element defined by the sentence "comprising a..." does not exclude the presence of other identical elements in the process, method or device that includes the element. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments can be referenced to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can be referred to the description of the method part.

[0057] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. The technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of the present disclosure. The technicians will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

Claims

1. A test method for Nand Flash controller cache read, characterized by: The following steps are involved: S01) Set the cache read time standard, which includes single plane read time standard and multi-plane read time standard. First, initialize the NAND storage organization structure PBA information to be operated, including channel, chip, lun, block, set the transmission data size and transmission mode, and then send multiple single plane read operations to NFC to determine the time to read data from the single plane in the cache, recorded as sp_cache_level, and then send multiple multi-plane read operations to determine the time to read data from the multi-plane in the cache, recorded as mp_cache_level; S02) Construct a test scenario and send different read and write operations according to the actual application scenario, including mixed read and write of different flash memory types on the same lun, read of different luns, read of different planes, and read of different pages; S03) Result return: process the data returned by NFC; S04) Result verification: perform result verification based on the data returned by NFC, and compare the verification result with the expected result. If they are consistent, the cache read function is correct, otherwise it is incorrect; Step S04 specifically involves first determining whether the status bit is 9c. If not, the test fails. If so, the read data is then determined to be correct. If not, the test fails. If so, the read performance is then determined to be improved. The performance data is then compared with the sp_cache_level and mp_cache_level set in step S02. For a single-plane read operation, if the read time is less than the sp_cache_level, the performance is considered improved and the test passes. Otherwise, the test fails. For a multi-plane read operation, if the read time is less than the mp_cache_level, the performance is considered improved and the test passes. Otherwise, the test fails.

2. The test method for Nand Flash controller cache read according to claim 1, characterized in that: The test process for mixed read and write operations with different flash memory types in the same LUN is as follows: under the same LUN, read and write operations are performed through single-plane and multi-plane, including write-first-read-later, read-first-write-later, and concurrent read and write scenarios. For cached data reads, the test first determines whether the status bit is 9c. If not, the test fails. If so, the test continues to determine whether the read data is correct. If not, the test fails. If so, the test continues to determine whether the read performance has improved. The performance data is compared with the sp_cache_level and mp_cache_level set in step S02. For single-plane read operations, if the read time is less than the sp_cache_level, the performance is considered to have improved and the test passes; otherwise, the test fails. For multi-plane read operations, if the read time is less than the mp_cache_level, the performance is considered to have improved and the test passes; otherwise, the test fails.

3. The test method for Nand Flash controller cache read according to claim 1, characterized in that: The test process for reading different luns is as follows: first send lun0 single plane read operations to NFC continuously, then send a lun1 single plane read operation, and finally send a lun0 single plane read operation; For each read operation, an expected value is set and the test result is compared with the expected result. If it meets the expectation, the test passes; otherwise, the test fails. The expected result is: the status bit returned by the second read is not 0x9c, the slot done time is greater than sp_cache_level, and the status bit returned by the third read is 0x9c, and the slot done time is no greater than sp_cache_level.

4. The test method for Nand Flash controller cache read according to claim 1, characterized in that: The test process for reading different planes is as follows: first send single-plane read operations of lun0 plane0 and lun0 plane1 to NFC in succession, and then repeat the above operations; For each read operation, an expected value is set and the test result is compared with the expected result. If it meets the expectation, the test passes; otherwise, the test fails. The expected results are: the status bit returned by the second read is not 0x9c, the status bit returned by the third and fourth reads is 0x9c, the slot done time of the second read is greater than sp_cache_level, and the time of the third and fourth reads is not greater than sp_cache_level.

5. The test method for Nand Flash controller cache read according to claim 1, characterized in that: The test process for reading different pages is as follows: first send a single plane read operation of lun0 plane0 page0 to NFC, and then send a single plane read operation of lun0 plane0 page1; For each read operation, an expected value is set and the test result is compared with the expected result. If it meets the expectation, the test passes; otherwise, the test fails. The expected result is: the status bit returned by the second read is not 0x9c, the read data is correct, and the slot done time is greater than sp_cache_level.

6. The test method for Nand Flash controller cache read according to claim 1, characterized in that: Encapsulates a result verification interface that reads data from the cache and obtains data from NFC, and performs result verification through the result verification interface.

7. The test method for Nand Flash controller cache read according to claim 1, characterized in that: Record all operations, data and test results during the operation process and generate a test report.

8. A test device for Nand Flash controller cache reading, comprising a processor and a memory storing program instructions, characterized in that: The processor is configured to execute the test method for Nand Flash controller cache reading according to any one of claims 1 to 7 when running the program instructions.

9. A storage medium storing program instructions, characterized in that: When the program instructions are executed, the test method for Nand Flash controller cache reading according to any one of claims 1 to 7 is executed.

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