A PCIe device and a testing method of the PCIe device

Abstract

The application provides a PCIe device and a testing method of the PCIe device, the PCIe device comprising: a PCIe controller and a loopback test enabling selector; the PCIe controller comprising a TX channel module and a RX channel module; the output of the TX channel module being connected to the first input of the loopback test enabling selector through a set type output link; when a loopback test enabling signal is enabled, the loopback test enabling selector selects to send the output of the TX channel module into the RX channel module through a set type input link. The technical scheme of the application can effectively exclude the influence of link signal quality and the behavior of the opposite end device, quickly define the problem boundary of the PCIe device unable to build a link, and test the correctness of the receiving and sending logic of the physical layer module of the local PCIe controller.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of chips, and particularly relates to a PCIe device and a testing method of the PCIe device. BACKGROUND

[0002] With the development of PCIe technology, especially after entering the PCIe 5.0 era, the improvement of PCIe performance makes it more and more difficult to meet the demand for the integrity, stability and reliability of signal transmission. The link establishment process involves not only the physical layer module of the local PCIe controller, but also the PCS (Physical Coding Sublayer) and PMA (Physical Medium Attachment) of the local PHY (Physical Layer Interface), and also involves the behavior of the opposite end device and the link signal quality. Locating the link establishment problem itself is complex, and if the test environment cannot meet the test conditions of the test tool (protocol analyzer, etc.), a way is needed to quickly define the problem side that causes the current link establishment problem. In this way, efforts can be quickly and accurately invested to efficiently solve the problem. SUMMARY

[0003] The purpose of the present application is to provide a PCIe device and a testing method of the PCIe device, aiming to solve the problem that when the local PHY is abnormal or the link signal quality is poor in the related art, the PCIe controller may not enter the loopback test state, thereby causing the expected test to be unable to be performed.

[0004] According to a first aspect of the present application, a PCIe device is provided, comprising: a PCIe controller and a loopback test enable selector;

[0005] The PCIe controller comprises a TX channel module and an RX channel module;

[0006] The output of the TX channel module is connected to the first input of the loopback test enable selector through a set type output link, and the output of the loopback test enable selector is connected to the RX channel module through a set type input link;

[0007] When the loopback test enable signal is enabled, the loopback test enable selector selects to send the output of the TX channel module to the RX channel module through the set type input link.

[0008] In an optional embodiment, the PCIe device further comprises: a link training module, a loopback test training signal enable module and a loopback test training signal selector;

[0009] The link training module is configured to generate a first link training signal and a second link training signal;

[0010] The first link training signal is a default link training signal which can make the link state machine of the PCIe device normally jump from a current state to a next state when the PCIe device is in a configuration stage as a DP device;

[0011] The second link training signal is a modified link training signal which can make the link state machine of the PCIe device jump from a current state to a next state when the PCIe device is in a configuration stage as a UP device;

[0012] The loopback test training signal enabling module enables the training enabling signal when the loopback test enabling signal is enabled when the PCIe device is in a configuration stage as a UP device.

[0013] The loopback test training signal selector selects the second link training signal to be sent to the TX channel module when the training enabling signal is enabled.

[0014] In an optional embodiment, the output of the TX channel module is also connected to a sending link to a peer device, and the second input of the loopback test enabling selector is connected to a receiving link from the peer device.

[0015] In an optional embodiment, the set type output link comprises a PIPE output interface of the PCIe controller, and the set type input link comprises a PIPE input interface of the PCIe controller.

[0016] In an optional embodiment, the PCIe device further comprises a PHY device, and the PHY device comprises a PCS module; the set type output link comprises a PIPE output interface of the PCIe controller, an output interface of the PCS module on a sending channel, and the PCS module; and the set type input link comprises a PIPE input interface of the PCIe controller, an input interface of the PCS module on a receiving channel, and the PCS module.

[0017] In an optional embodiment, the PCIe device further comprises a PHY device, and the PHY device comprises a PMA module; the set type output link comprises a PIPE output interface of the PCIe controller, the PCS module, an output interface of the PCS module on a sending channel, the PMA module, and a SerDes TX interface of the PMA module on the sending channel; and the set type input link comprises a PIPE input interface of the PCIe controller, the PCS module, an input interface of the PCS module on a receiving channel, the PMA module, and a SerDes RX interface of the PMA module on the receiving channel.

[0018] According to a first aspect of the present application, a testing method of a PCIe device is provided, the PCIe device comprising a PCIe controller and a loopback test enable selector, the PCIe controller comprising a TX channel module and a RX channel module; the method comprising:

[0019] In the configuration phase, the TX channel module receives a first link training signal or a second link training signal, and processes the received first link training signal or second link training signal, and sends the output obtained to the first input of the loopback test enable selector through the set type output link;

[0020] If the loopback test enable signal is enabled, the loopback test enable selector sends the output of the TX channel module received by the first input to the RX channel module through the set type input link.

[0021] In an optional embodiment, if the PCIe device is a UP device, the PCIe device further comprises a link training module, a loopback test training signal enable module and a loopback test training signal selector; the method further comprises:

[0022] In the configuration phase, the link training module generates a first link training signal and a second link training signal; wherein the first link training signal is a default link training signal that can make the link state machine of the PCIe device normally jump from the current state to the next state in the configuration phase when the PCIe device is a DP device; the second link training signal is a modified link training signal that can make the link state machine of the PCIe device jump from the current state to the next state in the configuration phase when the PCIe device is a UP device;

[0023] The loopback test training signal enable module detects the enable state of the loopback test enable signal;

[0024] If the loopback test enable signal is enabled, the loopback test training signal enable module enables a training enable signal;

[0025] The loopback test enable selector outputs the second link training signal to the TX channel module under the control of the training enable signal.

[0026] In an optional embodiment, the method further comprises:

[0027] The TX channel module further sends the output obtained by processing the first link training signal or the second link training signal to a transmission link to a peer device;

[0028] When the loopback test enable signal is not enabled, the loopback test enable selector selects to output the second input, data received from a receiving link of a peer device, to the RX channel module.

[0029] In an optional implementation, the set type output link includes a PIPE output interface of the PCIe controller, and the set type input link includes a PIPE input interface of the PCIe controller.

[0030] In an optional implementation, the test method of the PCIe device further includes a PHY device; the PHY device includes a PCS module; the set type output link includes a PIPE output interface of the PCIe controller, the PCS module, and an output interface of the PCS module on a sending channel; and the set type input link includes a PIPE input interface of the PCIe controller, the PCS module, and an input interface of the PCS module on a receiving channel.

[0031] In an optional implementation, the test method of the PCIe device further includes a PHY device; the PHY device includes a PMA module; the set type output link includes a PIPE output interface of the PCIe controller, the PCS module, an output interface of the PCS module on a sending channel, the PMA module, and a SerDes TX interface of the PMA module on the sending channel; and the set type input link includes a PIPE input interface of the PCIe controller, the PCS module, an input interface of the PCS module on a sending channel, the PMA module, and a SerDes RX interface of the PMA module on a receiving channel.

[0032] Compared with the related art, the technical solution of the present application has at least the following advantages:

[0033] The loopback self-built chain test solution provided in the present application can independently and flexibly perform loopback self-test without relying on the working condition of a peer device under the condition that chain building detection conforms to the PCIe protocol, can effectively exclude the influence of link signal quality and peer device behavior, quickly define the problem boundary of the PCIe device unable to build a chain, and test the correctness of the receiving and sending logic of the physical layer module of the local PCIe controller.

[0034] The application can also cooperate with the loopback mode (PCS loopback test and SerDes loopback test) inside the PHY device, and through the self-built chain mode, the reason for not building a chain is checked one by one whether it is related to PCS or PMA. The application can be applied in the FPGA stage and the sample test link stage, and quickly determine whether the current chain building exception is a PCIe device problem, which is conducive to concentrating on positioning the link quality problem: at the same time, it can also be applied in the screening and factory test, and efficiently give the conclusion whether the PCIe device sending and receiving exists problem.

[0035] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent from the description, or can be learned by practice of the present application. The objects and other advantages of the present application can be realized and achieved by the structures and processes indicated in the description and drawings. BRIEF DESCRIPTION OF DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the following will briefly introduce the drawings needed to be used in the embodiment or related art description. Obviously, the drawings described below are some embodiments of the present application, and those skilled in the art can obtain other drawings according to these drawings without creative labor.

[0037] Figure 1 It is a chain building structure schematic diagram of PCIe device according to the related art.

[0038] Figure 2 It is a chain building structure schematic diagram of PCIe device according to the present application.

[0039] Figure 3 It is another chain building structure schematic diagram of PCIe device according to the present application.

[0040] Figure 4 It is still another chain building structure schematic diagram of PCIe device according to the present application.

[0041] Figure 5 It is still another chain building structure schematic diagram of PCIe device according to the present application.

[0042] Figure 6 It is a flowchart of a test method of PCIe device according to the present application. DETAILED DESCRIPTION

[0043] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts should fall into the scope of the present application.

[0044] The process of state machine link establishment is a process of negotiation between two sides of a PCIe device. Please refer to Figure 1 , the two sides of a PCIe link are DP (Downstream port, downstream data device, i.e. the device whose data flow is away from the RP) and UP (Upstream port, upstream data device, i.e. the device whose data flow is toward the RP). In the link establishment process, the DP device and the UP device cooperate with each other to complete the negotiation of link width and supported rate. However, in the negotiation process, the DP device is the active party (actively initiates the negotiation process and sends the supported link width and supported rate), and the UP device is the passive party (receives the TS information sent by the DP, and then sends TS containing the supported link width and supported rate of the current device). The link establishment process needs to distinguish between UP and DP modes, and the main differences are reflected in the following states:

[0045] 1. CFG_LINKWIDTH_START stage

[0046] As a DP device, it needs to receive two consecutive TS1s and the LINKNUM in the received TS1 is non-PAD and the LANENUM is PAD, and it needs to send TS1 and the LINKNUM in the sent TS1 is a specific value (non-PAD) and the LANENUM is PAD;

[0047] As a UP device, it needs to receive two consecutive TS1s and the LINKNUM in the received TS1 is non-PAD and the LANENUM is PAD, and it needs to send TS1 and the LINKNUM and the LANENUM in the sent TS1 are both non-PAD.

[0048] 2. CFG_LINKWIDTH_ACCEPT stage

[0049] As a DP device, it needs to receive two consecutive TS1s and the LINKNUM in the received TS1 is non-PAD (which is consistent with the sent LINKNUM) and the LANENUM is not concerned, and it needs to send TS1 from all LANE (channels) and the LINKNUM and the LANENUM in the TS1 are both non-PAD (each LANE has a unique LANENUM);

[0050] As UP device, it needs to receive two consecutive TS1s and LINKNUM and LANENUM in the received TS1s are not PAD, and it needs to send TS1 and LINKNUM and LANENUM in the sent TS1s are the values sent by the received DP.

[0051] 3, CFG_LANENUM_WAIT stage

[0052] All LANE receives two consecutive TSs, and LINKNUM and LANENUM in the received TSs are consistent with those in the sent TSs; wherein the DP device sends TS2 and receives TS1, and the UP device sends TS1 and receives TS2.

[0053] 4, CFG_LANENUM_ACCEPT stage

[0054] All LANE receives two consecutive TSs and LINKNUM and LANENUM in the received TSs are not PAD, and LINKNUM and LANENUM are consistent with those in the sent TSs; wherein the DP device sends TS2 and receives TS1, and the UP device sends TS1 and receives TS2.

[0055] According to the PCIe protocol, LOOPBACK can meet the requirement of returning the data of the MASTER (the active party in the LOOPBACK mode) to the MASTER, and the data returned by the MASTER is checked and compared, so as to verify the stability and correctness of the link. However, the application of the LOOPBACK state described in the protocol has a defect, and the cooperation of the devices on both sides of the link is required to complete the test function. If the signal quality of the link is poor or the opposite device is abnormal or the local PHY is abnormal, the link cannot enter the LOOPBACK, which will lead to the fact that the LOOPBACK test cannot be realized. In order to exclude the influence of the signal quality of the link and the PHY, it is required to limit the LOOPBACK to one side of the local PCIe controller.

[0056] According to the above knowledge, when the PIPE interface is looped back, due to the particularity of the link establishment, the interface loopback of the DP device can meet the requirement of the link establishment, but the UP device cannot meet the link establishment condition. The application provides a loopback self-link establishment method, so that the LOOPBACK test is more flexible, and can be independently tested without relying on the opposite device and the link condition. In the case that the LOOPBACK self-link establishment is enabled, the TS code stream sent by the UP device for testing is modified, and the data of the TX channel is looped back to the RX channel, the self-link establishment of the local device is tested, so as to determine whether the behavior of the current local device is consistent with the expectation.

[0057] The LOOPBACK scheme described in the current PCIe protocol, when the controller is in the Configuration phase or the Recovery phase, the LOOPBACK MASTER sends TS1 to the LOOPBACK SLAVE, and sets the LOOPBACK bit in the TS1 Training Control field. When the LOOPBACK SLAVE continuously receives two TS1 sequences with the LOOPBACK bit set, it enters the LOOPBACK state, and then re-sends any subsequent received content to the MASTER. The MASTER checks the received content and compares it with the previously sent content. If the content is consistent after encoding (decoding) by both sides, it means that the link can pass the loopback verification and the integrity is not a problem. However, as described above, this scheme has a defect that requires the cooperation of both sides of the link to enter the LOOPBACK state. If there is a problem with the signal quality of the link, it cannot correctly transmit the complete data back to the MASTER, and at this time the result of this scheme cannot satisfy the verification of the correctness of the MASTER.

[0058] In some related technologies, the main implementation and protocol are similar, which proposes a special way of sending TLP (Transaction Layer Packet) and comparing TLP. But this scheme also has known defects: 1. It needs to rely on the cooperation of both sides of the link to enter the LOOPBACK state, which may not be met in actual scenarios, resulting in the test cannot continue.

[0059] In some other related technologies, the state machine is modified for general state machine chain building. By modifying the state machine and trigger conditions, the data sent by the sending end and the received data complete the handshake. In these related technologies, a flexible configuration state machine trigger condition and a configuration state machine state method are proposed, which can complete the handshake under normal conditions of the two sides of the PHY. However, this scheme has the following defects: 1. The chain building condition can be configured, resulting in a non-actual working state machine and a non-actual required condition trigger condition, which cannot verify the correctness of the trigger condition and the state machine jump in the actual scenario. 2. The chain building process relies on the negotiation of both sides of the link, and if the signal quality of the link is poor or the PHY is abnormal, the handshake cannot be completed, so the physical layer verification cannot continue.

[0060] The core idea of the technical solution of the present application is as follows: through the analysis of the above related technology, it can be known that the related scheme mainly relies on the LOOPBACK state specified by the protocol to realize loopback test, and the scheme has a precondition: the controller can complete negotiation with the opposite end and enter the LOOPBACK state. However, in actual situation, if the local PHY is abnormal or the link signal quality is poor, the controller may not be able to enter the LOOPBACK state, resulting in that the expected test cannot be performed.

[0061] Referring to Figure 2 As shown in the figure, the present application exemplarily proposes a PCIe device, which comprises a PCIe controller and a loopback test enabling selector;

[0062] The PCIe controller comprises a TX channel module and an RX channel module;

[0063] The output of the TX channel module is connected to the first input of the loopback test enabling selector through a set type output link;

[0064] When the loopback test enabling signal is enabled, the loopback test enabling selector selects to send the output of the TX channel module into the RX channel module through a set type input link.

[0065] The loopback self-building link mode proposed by the present application has the following optimization: the present application loops back the TX channel to the RX channel through the set type output link and the set type input interface on the PCIe device, and simultaneously relies on the existing state machine and physical layer channel to perform state machine training. The purpose of doing so is to verify the correctness of the state machine and the physical layer logic.

[0066] Exemplarily, the PCIe device is as a DP device, as a downlink data device (DP device), sends data to a peer device on a PCIe link (i.e. as an uplink data device of a UP device, i.e. a UP device). In a configuration phase of a link establishment process with the peer device, the PCIe device negotiates with the peer device through sending TSs the respective supported PCIe link width, rate, etc. In order to implement loopback test, the output of the TX channel module PL_TX_DATA of the PCIe controller of the present application is connected to a first input of a loopback test enable selector through setting a type output link, and the output of the loopback test enable selector is connected to the input of the RX channel module PL_RX_DATA of the PCIe controller, so that under the control of a loopback test enable signal cfg_dfx_lpbk_en, the TX channel of the PCIe device is looped back to the RX channel of the PCIe device, so that the TS sent out by the TX channel module PL_TX_DATA is also received by the PCIe device as the input of the RX channel module PL_RX_DATA, so that the LTSSM state machine judges whether the looped back TS meets the expectation to complete the verification, to test the abnormal state of each module of the PCIe and the link signal quality, etc. through which the TS code stream passes. The loopback test enable signal can be configured by software, i.e. in the loopback test mode, the loopback test enable signal can be configured to be in an enabled state by software, so that the loopback test enable selector can be enabled by the loopback test enable signal to select the output of the TX channel module to be sent to the RX channel module.

[0067] Exemplarily, Figure 2 A feasible implementation structure of the PCIe device proposed in the present application is shown, in which the TS code stream is looped back from the TX channel to the RX channel at the PIPE interface, and there are two cases:

[0068] The DP device (i.e. the PCIe device as a DP device) can establish link normally, because the DP device as an initiator can actively send the required TS code stream, return the default value, and meet the link establishment condition.

[0069] The UP device (i.e. the PCIe device as a UP device) cannot establish link, because the UP device is a passive party and needs to return the required TS according to the TS sent by the DP device. If the PIPE interface loopback is simply used, the TS received by the current controller is the TS data sent by the device, and the UP state machine waits for the required TS in the CFG phase until the timeout.

[0070] Therefore, in order to loopback self-build link when the PCIe device is a UP device, in some optional embodiments, the PCIe device further comprises a link training module, a loopback test training signal enabling module and a loopback test training signal selector;

[0071] The link training module is configured to generate a first link training signal and a second link training signal;

[0072] The first link training signal is a default link training signal that can make the link state machine of the PCIe device normally jump from a current state to a next state when the PCIe device is in a configuration stage as a DP device;

[0073] The second link training signal is a modified link training signal that can make the link state machine of the PCIe device jump from a current state to a next state when the PCIe device is in a configuration stage as a UP device;

[0074] The loopback test training signal enabling module enables a training enabling signal when a loopback test enabling signal is enabled in the configuration stage as the UP device;

[0075] The loopback test training signal selector selects the second link training signal to be sent to the TX channel module when the training enabling signal is enabled.

[0076] Exemplarily, the application enables the UP device to send TS that can meet link building in the PIPE interface loopback mode by modifying the sent TS stream (non-protocol TS), so that the controller can normally build link when the data output by the TX channel is looped back to the RX channel.

[0077] Exemplarily, the link training signal TS of the application is generated by the link training module. In the related art, the PCIe device generates a default link training signal. Referring to Figure 3 As shown, exemplarily, the application generates a modified link training signal LPBK_TS and a default link training signal TS, and selects the modified link training signal to be output to the TX channel module of the PCIe controller in the configuration stage as the UP device through the loopback test training signal selector, so as to achieve the modification of the TS stream sent by the UP device, so that the TS stream to be sent is sent to the PIPE output interface of the physical layer of the PCIe controller after data coding, scrambling and data reorganization of the TX channel module, and is received by the RX channel module after loopback through the PIPE input interface of the physical layer of the PCIe controller, and is sent to the state machine module LTSSMSTATE after data reorganization, descrambling and decoding of the TX channel module, so as to complete the link self-building, and thus verify the physical layer logic correctness of the controller when the PCIe device is a UP device.

[0078] Exemplarily, the configuration phase of the PCIe device as a UP device, the TS code stream LPBK TS (i.e. the second link training signal) modified for implementing the loopback test is as follows:

[0079] 1. At CFG_LINKWIDTH_START, LINKNUM in LPBK_TS can be non-PAD.

[0080] 2. At CFG_LINKWIDTH_ACCEPT, LANENUM in LPBK_TS can be non-PAD.

[0081] 3. At CFG_LANENUM_WAIT, LPBK_TS is TS2 specified by the PCIe protocol.

[0082] 4. At CFG_LANENUM_ACCEPT, LPBK_TS is TS2 specified by the PCIe protocol.

[0083] It should be noted that the first link training signal is a default link training signal that can make the link state machine of the PCIe device normally jump from the current state to the next state during the configuration phase of the PCIe device as a DP device, i.e. the default link training signal specified by the PCIe protocol, which is as follows:

[0084] 1. CFG_LINKWIDTH_START phase

[0085] As a DP device, 2 consecutive TS1 need to be received, and LINKNUM in the received TS1 is non-PAD and LANENUM is PAD, TS1 needs to be sent, and LINKNUM in the sent TS1 is a specific value (non-PAD) selected and LANENUM is PAD;

[0086] 2. CFG_LINKWIDTH_ACCEPT phase

[0087] As a DP device, 2 consecutive TS1 need to be received, and LINKNUM in the received TS1 is non-PAD (which is consistent with the sent LINKNUM) and LANENUM is not concerned, all LANE (channels) need to send TS1, and LINKNUM and LANENUM in TS1 are both non-PAD (each LANE has a unique LANENUM).

[0088] 3. CFG_LANENUM_WAIT phase

[0089] All LANE receives 2 consecutive TSs, and LINKNUM and LANENUM in the received TSs are consistent with the sent ones; wherein the DP device sends TS2 and receives TS1.

[0090] 4. CFG_LANENUM_ACCEPT stage

[0091] All LANE receives 2 consecutive TSs, and LINKNUM and LANENUM in the received TSs are non-PAD, and LINKNUM and LANENUM are consistent with the sent ones; wherein the DP device sends TS2 and receives TS1.

[0092] In some optional embodiments, the output of the TX channel module is also connected to a sending link to a peer device, and the second input of the loopback test enabling selector is connected to a receiving link from the peer device.

[0093] Exemplarily, referring to Figure 2 and Figure 3 , in the non-loopback test mode, the output of the TX channel module is connected to the sending link of the peer device, so that data such as TS stream is sent out to the peer device through the sending link when the loopback test enabling signal is not enabled; meanwhile, the second input of the loopback test enabling selector is connected to the receiving link from the peer device, so that data received from the peer device is received from the receiving link when the loopback test enabling signal is not enabled, and the received data is selected to be output to the RX channel module, so that normal data transmission with the peer device is realized. Therefore, in the non-loopback test mode, the loopback test enabling signal is configured by software to be in the non-enabled state, so that when the loopback test enabling signal is not enabled, the loopback test enabling selector selects to send the data received from the peer device to the RX channel module, and the output of the TX channel module is sent to the peer device through the sending link.

[0094] In some optional embodiments, the set type output link includes a PIPE output interface of a PCIe controller, and the set type input link includes a PIPE input interface of the PCIe controller.

[0095] Exemplarily, referring to Figure 2 and Figure 3As shown, the set type output link is the PIPE interface of the PCIe controller, that is, after the TS stream output by the TX channel module (when the PCIe device is in DP mode, it can be the first link training signal, and when the PCIe device is in UP mode, it can be the second link training signal) is output to the loopback test enable selector at the output interface PIPE of the PCIe controller, the loopback test enable selector selects the TS stream to be sent to the RX channel module through the PIPE input interface of the PCIe controller under the control of the loopback test enable signal, so that the loopback test of the PCIe controller can be realized.

[0096] In some optional embodiments, the PCIe device further comprises a PHY device; the PHY device comprises a PCS module; the set type output link comprises a PIPE output interface of the PCIe controller, the PCS module, and an output interface of the PCS module on a sending channel; and the set type input link comprises a PIPE input interface of the PCIe controller, the PCS module, and an input interface of the PCS module on a receiving channel.

[0097] Exemplarily, referring to Figure 4 As shown, the PCIe controller is connected with the PCS module of the PHY device, and the loopback test mode proposed in the application is also applicable to the loopback test of the PCS module at the local end. In order to realize the loopback test of the PCS at the local end, the output of the TX channel module can be connected to the input interface of the PCS module through the loopback test enable selector at the output interface of the PCS module, so that the output of the TX channel module is output at the output interface of the PCS module, is processed by the output of the PCS module, and is processed by the input of the PCS module and then looped back to the RX channel module. Of course, for the PCIe device as a UP device, the modified LPBK_TS, that is, the second link training signal, can be sent in the configuration stage, so that the link building requirement can be met. In this way, whether the PCIe controller and the PCS module are abnormal can be quickly confirmed.

[0098] In some optional embodiments, the PCIe device further comprises a PHY device; the PHY device comprises a PMA module, the set type output link comprises a PIPE output interface of the PCIe controller, the PCS module, an output interface of the PCS module on a sending channel, the PMA module, and a SerDes TX interface of the PMA module on the sending channel; and the set type input link comprises a PIPE input interface of the PCIe controller, the PCS module, an input interface of the PCS module on a receiving channel, the PMA module, and a SerDes RX interface of the PMA module on the receiving channel.

[0099] Exemplarily, referring to Figure 5As shown, the loopback test mode proposed in the application is also applicable to the loopback test of the local SerDes interface, wherein the PCS module is connected to the PMA module. In order to realize the loopback test of the local SerDes interface, the output of the TX channel module can be connected to the input of the PMA module through the loopback test enable selector at the output interface of the PMA module of the PHY device, that is, the SerDes output interface, so that the output of the TX channel module is processed through the output of the PCS module and the output of the PMA module, and then is looped back to the RX channel module after being processed through the input of the PMA module and the input of the PCS module. Of course, for the PCIe device as the UP device, the modified LPBK_TS, that is, the second link training signal, can be sent in the configuration stage, so that the link building requirement can be met. In this way, it can be quickly determined whether the PCI controller and the PHY device are abnormal.

[0100] The loopback self-link building test scheme proposed in the application can independently and flexibly perform self-test under the condition that the link building detection meets the PCIe protocol, without depending on the working condition of the peer device, can effectively exclude the influence of the link signal quality and the behavior of the peer device, quickly define the problem boundary of the PCIe device that cannot build a link, and test the correctness of the receiving and transmitting logic of the physical layer module of the PCIe controller.

[0101] The application can also cooperate with the loopback mode (PCS loopback test and SerDes loopback test) inside the PHY device, and through the self-link building mode, it can check whether the link building failure is related to the PCS or the PMA. The application can be applied in the FPGA test and the sample test link stage, can quickly define whether the current link building failure is a PCIe device problem, is conducive to concentrating on positioning the link quality problem, and can also be applied in the screening and factory test, and can efficiently give a conclusion whether the PCIe device sending and receiving exist problems.

[0102] Correspondingly, referring to Figure 6 As shown, the application exemplarily proposes a test method of a PCIe device, the PCIe device comprising a PCIe controller and a loopback test enable selector, the PCIe controller comprising a TX channel module and an RX channel module; the method comprises:

[0103] In step S601, in the configuration stage, the TX channel module receives a first link training signal or a second link training signal, processes the received first link training signal or second link training signal, and sends the obtained output to the first input of the loopback test enable selector through a set type output link;

[0104] In step S602, if the loopback test enable signal is enabled, the loopback test enable selector sends the output of the TX channel module received by the first input to the RX channel module through the set type input link.

[0105] In some optional embodiments, if the PCIe device is a UP device, the PCIe device further comprises a link training module, a loopback test training signal enable module and a loopback test training signal selector; the method further comprises:

[0106] In the configuration phase, the link training module generates a first link training signal and a second link training signal; wherein the first link training signal is a default link training signal which can make the link state machine of the PCIe device normally jump from the current state to the next state in the configuration phase when the PCIe device is a DP device; the second link training signal is a modified link training signal which can make the link state machine of the PCIe device jump from the current state to the next state in the configuration phase when the PCIe device is a UP device;

[0107] The loopback test training signal enable module detects the enabled state of the loopback test enable signal;

[0108] If the loopback test enable signal is enabled, the loopback test training signal enable module enables the training enable signal;

[0109] The loopback test enable selector outputs the second link training signal to the TX channel module under the control of the training enable signal.

[0110] In some optional embodiments, the method further comprises:

[0111] The TX channel module further sends the output obtained by processing the first link training signal or the second link training signal to the sending link to the peer device;

[0112] When the loopback test enable signal is not enabled, the loopback test enable selector selects to output the data received by the second input from the receiving link of the peer device to the RX channel module.

[0113] In some optional embodiments, the set type output link comprises a PIPE output interface of the PCIe controller; the set type input link comprises a PIPE input interface of the PCIe controller.

[0114] In some optional embodiments, the test method of the PCIe device further comprises a PHY device; the PHY device comprises a PCS module; the set type output link comprises a PIPE output interface of the PCIe controller, the PCS module, and an output interface of the PCS module on a sending channel; and the set type input link comprises a PIPE input interface of the PCIe controller, the PCS module, and an input interface of the PCS module on a receiving channel.

[0115] In some optional embodiments, the test method of the PCIe device further comprises a PHY device; the PHY device comprises a PMA module; the set type output link comprises a PIPE output interface of the PCIe controller, the PCS module, an output interface of the PCS module on a sending channel, the PMA module, and a SerDes TX interface of the PMA module on the sending channel; and the set type input link comprises a PIPE input interface of the PCIe controller, the PCS module, an input interface of the PCS module on a sending channel, the PMA module, and a SerDes RX interface of the PMA module on the receiving channel.

[0116] The above method can be implemented by the PCIe device provided in the above embodiments, and the specific implementation manner can refer to the description of the PCIe device in the above embodiments, which will not be described here again.

[0117] It can be understood that the circuit structure, name, and parameter described in the above embodiments are only examples. Those skilled in the art can also combine and adjust the structural features of the above multiple embodiments according to the use needs, and the concept of the present application should not be limited to the specific details of the above examples.

[0118] Although the present application is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A PCIe device, characterized in that, Comprising: a PCIe controller and a loopback test enable selector; the PCIe controller comprises a TX channel module and a RX channel module; an output of the TX channel module is connected to a first input of the loopback test enable selector through a set type output link; when the loopback test enable signal is enabled, the loopback test enable selector selects to send the output of the TX channel module to the RX channel module through a set type input link; the PCIe device further comprises a link training module, a loopback test training signal enable module and a loopback test training signal selector; the link training module is used to generate a first link training signal and a second link training signal; the first link training signal is a default link training signal which can make the link state machine of the PCIe device normally jump from a current state to a next state when the PCIe device is in a configuration stage as a DP device; the second link training signal is a modified link training signal which can make the link state machine of the PCIe device jump from a current state to a next state when the PCIe device is in a configuration stage as a UP device; the loopback test training signal enable module enables a training enable signal when the loopback test enable signal is enabled when the PCIe device is in a configuration stage as a UP device; the loopback test training signal selector selects to send the second link training signal to the TX channel module when the training enable signal is enabled.

2. The PCIe device of claim 1, wherein, an output of the TX channel module is further connected to a sending link to a peer device, and a second input of the loopback test enable selector is connected to a receiving link from the peer device.

3. The PCIe device of claim 1, wherein, the set type output link comprises a PIPE output interface of the PCIe controller; and the set type input link comprises a PIPE input interface of the PCIe controller.

4. The PCIe device of claim 1, wherein, the PCIe device further comprises a PHY device; the PHY device comprises a PCS module; the set type output link comprises a PIPE output interface of the PCIe controller, the PCS module and an output interface of the PCS module on a sending channel; and the set type input link comprises a PIPE input interface of the PCIe controller, the PCS module and an input interface of the PCS module on a receiving channel.

5. The PCIe device of claim 1, wherein, the PCIe device further comprises a PHY device; the PHY device comprises a PMA module; the set type output link comprises a PIPE output interface of the PCIe controller, a PCS module, an output interface of the PCS module on a sending channel, the PMA module and a SerDes TX interface of the PMA module on the sending channel; and the set type input link comprises a PIPE input interface of the PCIe controller, the PCS module, an input interface of the PCS module on a receiving channel, the PMA module and a SerDes RX interface of the PMA module on the receiving channel.

6. A test method of a PCIe device, characterized by, The PCIe device comprises a PCIe controller and a loopback test enabling selector, the PCIe controller comprises a TX channel module and a RX channel module; the method comprises: In the configuration phase, the TX channel module receives a first link training signal or a second link training signal, processes the received first link training signal or second link training signal, and sends the output obtained to a first input of the loopback test enabling selector through a set type output link; If the loopback test enabling signal is enabled, the loopback test enabling selector sends the output of the TX channel module received by the first input to the RX channel module through a set type input link; If the PCIe device is a UP device, the PCIe device further comprises a link training module, a loopback test training signal enabling module and a loopback test training signal selector; the method further comprises: In the configuration phase, the link training module generates a first link training signal and a second link training signal; wherein the first link training signal is a default link training signal which can make the link state machine of the PCIe device normally jump from the current state to the next state in the configuration phase when the PCIe device is a DP device; the second link training signal is a modified link training signal which can make the link state machine of the PCIe device jump from the current state to the next state in the configuration phase when the PCIe device is a UP device; The loopback test training signal enabling module detects the enabling state of the loopback test enabling signal; If the loopback test enabling signal is enabled, the loopback test training signal enabling module enables a training enabling signal; The loopback test enabling selector outputs the second link training signal to the TX channel module under the control of the training enabling signal.

7. The method of testing a PCIe device of claim 6, wherein, The method further comprises: The TX channel module further sends the output obtained by processing the first link training signal or second link training signal to a sending link to a peer device; When the loopback test enabling signal is not enabled, the loopback test enabling selector selects to output data received by the second input from a receiving link of a peer device to the RX channel module.

8. The method of testing a PCIe device of claim 6, wherein, The set type output link comprises a PIPE output interface of the PCIe controller; the set type input link comprises a PIPE input interface of the PCIe controller.

9. The method of testing a PCIe device of claim 6, wherein, The test method of the PCIe device further comprises a PHY device; the PHY device comprises a PCS module; the set type output link comprises a PIPE output interface of the PCIe controller, the PCS module and an output interface of the PCS module on a sending channel; the set type input link comprises a PIPE input interface of the PCIe controller, the PCS module and an input interface of the PCS module on a receiving channel.

10. The method of testing a PCIe device of claim 6, wherein, The test method of the PCIe device further includes a PHY device; the PHY device includes a PMA module; the set type output link includes a PIPE output interface of the PCIe controller, a PCS module, an output interface of the PCS module on a sending channel, the PMA module and a SerDes TX interface of the PMA module on the sending channel; and the set type input link includes a PIPE input interface of the PCIe controller, the PCS module, an input interface of the PCS module on a sending channel, the PMA module and a SerDes RX interface of the PMA module on a receiving channel.

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