Data processing method, system, device and readable storage medium

Abstract

The embodiment of the present invention provides a data processing method, system, device and readable storage medium, the method comprising: receiving target data sent by a lower-level storage controller, storing the target data in a temporary storage queue; the lower-level storage controller is used to search for the target data indicated by an access request in the lower-level storage; the access request is stored in a missing queue by an upper-level storage controller and sent to the lower-level storage controller; the target data in the temporary storage queue is sent to the upper-level storage controller; the upper-level storage controller is used to send a write-back request to the lower-level storage controller when the target data is stored and data replacement occurs; the lower-level storage controller is used to perform the write-back operation indicated by the write-back request, and return write-back confirmation information to the upper-level storage controller; the upper-level storage controller is used to store the write-back confirmation information in the write-back queue. The present invention can decouple the missing queue and the write-back queue through the temporary storage queue, thereby improving the flexibility of queue configuration.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a data processing method, system, electronic device and readable storage medium. Background Art

[0002] TileLink is a network on chip (NoC) protocol used to communicate between different components in a chip. TileLink defines multiple channels to implement communication, including AcquireChannel, Data Channel, and other channels. The Data Channel is used to return data to the data requester and also to return write-back confirmation information to the write-back requester.

[0003] In the related technology, access requests can be stored in the missing queue (MissQueue) in the upper-level storage. When the return data corresponding to the access request is obtained through the data channel, the upper-level storage may generate data replacement when storing the returned data. The writeback queue (WritebackQueue) in the upper-level storage needs to store all the data to be replaced, and then write these data back to the lower-level storage. The lower-level storage returns a write-back confirmation message through the data channel.

[0004] However, in the related art, since both the return data and the write-back confirmation message are transmitted through the data channel, there is a data channel dependency. Therefore, the depth of the write-back queue needs to be greater than or equal to the depth of the missing queue, otherwise there will be a deadlock. In order to avoid deadlock, the depth of the write-back queue must be greater than or equal to the missing queue, which leads to greater configuration limitations on the write-back queue and the missing queue. Summary of the invention

[0005] The embodiments of the present invention provide a data processing method, system, electronic device and readable storage medium, which can solve the problem that the configuration of write-back queues and missing queues in related technologies is relatively limited.

[0006] In order to solve the above problems, an embodiment of the present invention discloses a data processing method, which is applied to an intermediate storage controller; the method comprises:

[0007] receiving target data sent by a lower-level storage controller, and storing the target data in a temporary storage queue; the lower-level storage controller is used to search the lower-level storage for the target data indicated by the access request; the access request is stored in a missing queue by the upper-level storage controller, and sent to the lower-level storage controller;

[0008] The target data in the temporary queue is sent to the upper-level storage controller; the upper-level storage controller is used to send a write-back request to the lower-level storage controller when the target data is stored and data replacement occurs; the lower-level storage controller is used to execute the write-back operation indicated by the write-back request and return write-back confirmation information to the upper-level storage controller; the upper-level storage controller is used to store the write-back confirmation information in the write-back queue.

[0009] On the other hand, an embodiment of the present invention discloses a data processing method, which is applied to a lower-level storage controller; the method comprises:

[0010] Receive an access request sent by an upper-level storage controller, and search for target data indicated by the access request in a lower-level storage; the access request is stored in a missing queue by the upper-level storage controller and sent to the lower-level storage controller;

[0011] The target data is sent to an intermediate storage controller; the intermediate storage controller is used to receive the target data and store the target data in a temporary storage queue; the intermediate storage controller is also used to send the target data in the temporary storage queue to the upper storage controller; the upper storage controller is used to send a write-back request to the lower storage controller when storing the target data and data replacement occurs;

[0012] Receive a write-back request sent by the upper-level storage controller, execute the write-back operation indicated by the write-back request, and return write-back confirmation information to the upper-level storage controller; the upper-level storage controller is used to store the write-back confirmation information in a write-back queue.

[0013] In another aspect, an embodiment of the present invention further discloses a data processing system, the system comprising: an upper-level storage controller, an intermediate storage controller and a lower-level storage controller;

[0014] The upper storage controller is used to store the access request in the missing queue and send the access request in the missing queue to the lower storage controller;

[0015] The lower-level storage controller is used to search the target data indicated by the access request in the lower-level storage according to the access request sent by the upper-level storage controller, and send the target data to the intermediate storage controller;

[0016] The intermediate storage controller is used to receive the target data sent by the lower-level storage controller, store the target data in a temporary storage queue, and send the target data in the temporary storage queue to the upper-level storage controller;

[0017] The upper storage controller is used to send a write-back request to the lower storage controller when storing the target data and data replacement occurs;

[0018] The lower-level storage controller is used to receive the write-back request, perform the write-back operation indicated by the write-back request, and return write-back confirmation information to the upper-level storage controller;

[0019] The upper-level storage controller is used to store the write-back confirmation information in a write-back queue.

[0020] An embodiment of the present invention also discloses an electronic device, which includes a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other via the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the aforementioned data processing method.

[0021] An embodiment of the present invention further discloses a readable storage medium. When instructions in the readable storage medium are executed by a processor of an electronic device, the electronic device can execute the aforementioned data processing method.

[0022] The embodiment of the present invention includes the following advantages: the upper storage controller stores the access request to the missing queue, and sends the access request in the missing queue to the lower storage controller, the lower storage controller searches for the target data indicated by the access request in the lower cache, sends the target data to the intermediate storage controller, the intermediate storage controller receives the target data, stores the target data in the temporary storage queue, and then sends the target data in the temporary storage queue to the upper storage controller, the upper storage controller sends a write-back request to the lower storage controller when storing the target data and data replacement occurs, the lower storage controller performs the write-back operation, returns the write-back confirmation information to the upper storage controller, and the upper storage controller stores the write-back confirmation information in the write-back queue. The target data can be stored in the temporary storage queue first, the data channel can complete the return of the target data, and the write-back confirmation message can also be normally transmitted based on the data channel, thereby completing the write-back, so there is no coupling problem that the depth of the write-back queue must be greater than or equal to the missing queue, and there is no need to have a specific size relationship between the depth of the write-back queue and the missing queue, so that the queue depth can be flexibly configured, and the flexibility of queue configuration is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0024] Figure 1 is a step diagram of a data processing method of the present invention;

[0025] Figure 2 It is a schematic diagram of the existing data processing process of the present invention;

[0026] Figure 3 is a step diagram of another data processing method of the present invention;

[0027] Figure 4 is a step diagram of another data processing method of the present invention;

[0028] Figure 5 is a schematic diagram of a data processing system of the present invention;

[0029] Figure 6 is a structural block diagram of a data processing device of the present invention;

[0030] Figure 7 is a structural block diagram of another data processing device of the present invention;

[0031] Figure 8 It is a structural block diagram of an electronic device for data processing of the present invention. DETAILED DESCRIPTION

[0032] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0033] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable when appropriate, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In the embodiments of the present invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0034] Method Embodiment

[0035] Reference Figure 1 , shows a flow chart of steps of an embodiment of a data processing method of the present invention, which is applied to an intermediate storage controller; the method may specifically include the following steps:

[0036] Step 101, receiving target data sent by a lower-level storage controller, and storing the target data in a temporary queue; the lower-level storage controller is used to search for the target data indicated by the access request in the lower-level storage; the access request is stored in the missing queue by the upper-level storage controller and sent to the lower-level storage controller.

[0037] There are mainly two approaches in the related technology. One is that the missing queue stores all data sent by the lower-level storage controller, and there is no requirement for the depth of the write-back queue. The other is that the missing queue does not store the data sent by the lower-level storage controller, and the data is stored by the write-back queue, but the depth of the write-back queue needs to be greater than or equal to the sum of the depths of the missing queue and the detection queue. The disadvantage of the first approach is that each item of the missing queue and the write-back queue needs to store data, and the disadvantage of the second approach is that the depth of the write-back queue is greater than or equal to the depth of the missing queue, resulting in a depth that is too large, and the processor usually only needs to configure a very small depth for the write-back queue. The large depth configuration is to avoid deadlock. In addition, whether it is a write-back queue or a missing queue, registers are used to store data, and the extensive use of registers usually leads to greater area occupancy and power consumption.

[0038] Because when returning the data indicated by the access request, it is done through the data channel, and after obtaining the returned data, if other data is already stored in the location where the data needs to be stored, the other data needs to be replaced, and the other data needs to be stored in the write-back queue first (the second approach), and then the other data needs to be written back to the lower-level storage, such as the next-level cache. When the lower-level storage completes the write-back operation and returns the write-back confirmation information, it is also through the data channel. Based on the write-back confirmation information, the upper-level storage can release the corresponding data to be replaced, so that other data can continue to be stored.

[0039] The depth of the write-back queue indicates the amount of data that can be stored. The depth can also be understood as the number of items in the queue. Each item can correspond to a data buffer (Databuffer). Each item in the write-back queue can store data, and each item in the missing queue can store an access request. Different access requests correspond to their own return data. In extreme cases, the missing queue is full, that is, the maximum number of access requests that can be stored in the missing queue has been reached, and the corresponding number of return data will also be obtained. In extreme cases, storing these return data will cause data replacement. In order to write back the corresponding data to be replaced, the write-back queue needs to store the corresponding number of data to be replaced. The depth must be greater than or equal to the depth of the missing queue to store the corresponding number of data to be replaced. In some cases, the depth of the write-back queue can be greater, for example, the depth of the write-back queue must be greater than or equal to the sum of the depth of the missing queue and the depth of the probe queue (ProbeQueue), which is not restricted here.

[0040] If the depth of the write-back queue is less than the depth of the missing queue, in the extreme case that the maximum number of access requests is stored in the missing queue, the lower-level storage will return the corresponding amount of data, and the write-back queue will be unable to store the corresponding amount of data to be replaced, then a deadlock occurs and data processing cannot continue.

[0041] Figure 2 It is a schematic diagram of the existing data processing process provided by an embodiment of the present invention; the upper-level storage 21 can be a data cache (Data Cache) close to the processor core, and the upper-level storage 21 can include a missing queue 211 and a write-back queue 212; the lower-level storage 22 can be a lower-level cache, and the lower-level storage 22 can include a data channel response queue 221, and the target data and write-back confirmation message that the lower-level storage 22 needs to return can be first stored in the data channel response queue 221, and then returned to the upper-level storage 21 respectively.

[0042] In the embodiment of the present invention, the application scenario may be a multi-level cache system, such as a three-level cache (L1, L2, L3) system. In the cache system, an intermediate storage (memory) located outside the upper storage and lower storage may be added, and the temporary storage queue is located in the intermediate storage.

[0043] In the cache system, the upper-level storage controller is used to read and write the upper-level storage, which includes a miss queue and a write-back queue. The intermediate storage controller is used to read and write the intermediate storage, which includes a temporary storage queue. The lower-level storage controller is used to read and write the lower-level storage, which may include a data channel response queue.

[0044] If the target data is not hit in the current cache, that is, a cache miss occurs, the upper-level storage controller sends the access request to the lower-level storage controller. In order to avoid confusion of missed access requests, the upper-level storage controller can first store the access request in the miss queue, and then send the access request in the miss queue to the lower-level storage controller.

[0045] The lower-level storage controller searches for target data according to the received access request, and returns the target data to the intermediate storage controller in the read-write intermediate storage area, and the intermediate storage controller stores the target data in the temporary storage queue.

[0046] Step 102, sending the target data in the temporary queue to the upper-level storage controller; the upper-level storage controller is used to send a write-back request to the lower-level storage controller when storing the target data and data replacement occurs; the lower-level storage controller is used to execute the write-back operation indicated by the write-back request and return write-back confirmation information to the upper-level storage controller; the upper-level storage controller is used to store the write-back confirmation information in the write-back queue.

[0047] The intermediate storage controller stores the target data in the temporary storage queue, and then sends the target data in the temporary storage queue to the upper storage controller, avoiding the problem that the upper storage directly obtains a large amount of target data and generates a large amount of data to be replaced in extreme cases. The temporary storage queue can store a large amount of target data, and the target data provided by the lower storage can all be stored, without the D channel always responding to access requests and being in the state of returning data because the write-back queue cannot store a large amount of data to be replaced.

[0048] The upper storage controller can generate a write-back request based on the data to be replaced in the write-back queue and send it to the lower storage controller. The lower storage controller performs a write-back operation according to the write-back request, that is, writes the data to be replaced in the write-back queue back to the lower storage, such as the lower cache. And because the D channel will not be in a state of responding to access requests and returning data all the time, a write-back confirmation message can be returned through the D channel.

[0049] The upper storage controller stores the write-back confirmation information in the write-back queue, and can release the to-be-replaced data corresponding to the write-back confirmation message, so that the write-back queue can continue to process other to-be-replaced data. Therefore, even if the depth of the write-back queue is less than the missing queue, deadlock will not occur because the temporary storage queue temporarily stores data.

[0050] In summary, in the implementation of the embodiment of the present invention, the upper storage controller stores the access request to the missing queue and sends the access request in the missing queue to the lower storage controller, the lower storage controller searches for the target data indicated by the access request in the lower cache, sends the target data to the intermediate storage controller, the intermediate storage controller receives the target data, stores the target data in the temporary storage queue, and then sends the target data in the temporary storage queue to the upper storage controller, the upper storage controller stores the target data and replaces the data, sends a write-back request to the lower storage controller, the lower storage controller performs the write-back operation, returns the write-back confirmation information to the upper storage controller, and the upper storage controller stores the write-back confirmation information in the write-back queue. The target data can be stored in the temporary storage queue first, the data channel can complete the return of the target data, and the write-back confirmation message can also be normally transmitted based on the data channel to complete the write-back, so there is no coupling problem that the depth of the write-back queue must be greater than or equal to the missing queue, and there is no need to have a specific size relationship between the depth of the write-back queue and the missing queue, so that the queue depth can be flexibly configured, and the flexibility of queue configuration is improved.

[0051] Figure 3 A step diagram of another data processing method of the present invention is shown, comprising the following steps:

[0052] Step 303, receiving target data sent by the lower-level storage controller, and storing the target data in a temporary storage queue; the lower-level storage controller is used to search the lower-level storage for the target data indicated by the access request; the access request is stored in the missing queue by the upper-level storage controller and sent to the lower-level storage controller;

[0053] Step 304, sending the target data in the temporary queue to the upper-level storage controller; the upper-level storage controller is used to send a write-back request to the lower-level storage controller when storing the target data and data replacement occurs; the lower-level storage controller is used to execute the write-back operation indicated by the write-back request and return write-back confirmation information to the upper-level storage controller; the upper-level storage controller is used to store the write-back confirmation information in the write-back queue.

[0054] The contents of the above steps 303-304 can refer to the above Figure 1 The embodiments are not described in detail here.

[0055] Optionally, the method further includes:

[0056] Step 301, determining a second number of storage areas in an intermediate memory other than an upper level storage and a lower level storage according to a preset queue depth and a preset first number of registers; the sum of the preset first number and the second number is equal to the value of the preset queue depth;

[0057] Step 302: construct a temporary queue of the preset queue depth according to the preset first number of registers and the second number of storage areas.

[0058] In the embodiment of the present invention, it is necessary to construct a temporary queue in the intermediate storage area in advance, and the preset queue depth of the temporary queue may be greater than or equal to the depth of the missing queue. It is understood that the queue depth can be used to represent the number of items in the queue, for example, if the queue depth is 16, the queue may include 16 items.

[0059] In order to improve the read and write speed of the temporary storage queue, data can be stored based on a preset first number of registers. The specific value of the preset first number is not limited here. Each register can be regarded as having a depth of 1, representing one item. However, the area of ​​the register is large and the power consumption is high. Therefore, a larger storage capacity can be provided based on other storage areas while occupying a smaller area.

[0060] Therefore, according to the preset queue depth and the preset first number of registers, in the intermediate memory outside the upper storage and the lower storage, the second number of storage areas can be determined by subtracting the value of the preset first number from the value of the preset queue depth. The storage area can be a storage area in the intermediate memory, such as a static random access memory (SRAM).

[0061] Among them, the SRAM can be a single-port SRAM, which has only one set of address lines, data lines and control lines, and can only perform one operation at a time, that is, a read operation or a write operation. The single-port SRAM has a high data read and write speed and can quickly respond to read or write requests.

[0062] A temporary queue with a preset queue depth is constructed according to a preset first number of registers and a preset second number of storage areas. The temporary queue may be a First Input First Output (FIFO) queue.

[0063] In the implementation of the embodiment of the present invention, the second number of storage areas is determined according to the preset queue depth and the preset first number of registers, and a temporary storage queue of the preset queue depth is constructed according to the preset first number of registers and the preset second number of storage areas. The temporary storage queue can be constructed in a mixed manner based on the first number of registers and the second number of storage areas, and the read and write speed, occupied area and power consumption can be balanced to construct a temporary storage queue with higher read and write speed, smaller occupied area and lower power consumption; and as the specifications of the upper storage (such as Dcache) increase, the area advantage of the temporary storage queue implemented using SRAM will become more obvious.

[0064] Optionally, the step 303 of receiving the target data sent by the lower-level storage controller and storing the target data in the temporary storage queue includes:

[0065] Sub-step 3031, receiving target data sent by the lower-level storage controller, and determining the state of the temporary storage queue and the state of the register; the state of the temporary storage queue includes empty and non-empty; the state of the register includes valid and invalid;

[0066] Sub-step 3032, when the temporary storage queue is empty and the register is invalid, writing the target data into the register and setting the state of the register to valid;

[0067] Sub-step 3033, when the temporary storage queue is not empty and the register is valid, write the target data into the storage area.

[0068] In an embodiment of the present invention, after receiving the target data sent by the lower-level storage controller, the state of the temporary storage queue and the state of the register can be determined first. The state of the temporary storage queue includes empty and non-empty, where empty means that there is no data in the temporary storage queue, and non-empty means that there is data in the temporary storage queue. The state of the register includes valid and invalid, where valid means that the register has stored data, and invalid means that the register has not stored data.

[0069] When the temporary storage queue is empty and the register is invalid, it means that there is no data in the temporary storage queue and there is no data in the register. Since the register has a fast read and write speed, the target data can be written to the register first. When the data is read later, the data in the register can be obtained at a faster reading speed. It can be understood that the invalid register here means that at least one register is invalid. When there is a register that does not store data, the target data can be written to the register.

[0070] When the temporary storage queue is not empty and the register is valid, it means that there is data in the temporary storage queue and the register has stored the data, so the target data can be written to the storage area. It can be understood that the register valid here means that all registers are valid, so the target data needs to be written to the storage area.

[0071] The embodiment of the present invention is implemented by receiving the target data sent by the lower-level storage controller, determining the state of the temporary storage queue and the state of the register, and when the temporary storage queue is empty and the register is invalid, writing the target data to the register and setting the state of the register to be valid, and when the temporary storage queue is not empty and the register is valid, writing the target data to the storage area. The respective data storage conditions can be determined based on the states of the temporary storage queue and the register, and then the data can be first stored in the register to increase the reading and writing speed, thereby improving the efficiency of data processing.

[0072] Optionally, the step 304 of sending the target data in the temporary storage queue to the upper-level storage controller includes:

[0073] Sub-step 3041, if the register is valid, sending the target data in the register to the upper storage controller, and setting the state of the register to invalid;

[0074] Sub-step 3042, when the register is invalid, sending the target data in the storage area to the upper-level storage controller.

[0075] In the embodiment of the present invention, when sending the data in the temporary storage queue to the upper-level storage controller, it can also be done based on the state of the register.

[0076] When the register is valid, it means that there is data in the register, so the target data in the register can be sent to the upper storage controller first, and the state of the register is set to invalid, so that the data can be written to the register later. It can be understood that when there are multiple registers, the valid register here means that at least one register is valid, even if only one register stores data, the data in the register can be sent first.

[0077] In the case where the registers are invalid, it may mean that all the registers are invalid and no data is stored in any register, and then the target data in the storage area needs to continue to be sent to the upper-level storage controller.

[0078] By implementing the embodiment of the present invention, when the register is valid, the target data in the register is sent to the upper storage controller, and the state of the register is set to invalid. When the register is invalid, the target data in the storage area is sent to the upper storage controller. The data in the register with a higher read / write speed can be sent first, and then the data in the storage area is sent to the upper storage controller, thereby improving the efficiency of data processing.

[0079] Optionally, the temporary storage queue corresponds to a write pointer; the write pointer is used to point to the next writable register or storage area;

[0080] The step 303 of receiving the target data sent by the lower-level storage controller and storing the target data in the temporary storage queue includes:

[0081] Sub-step 3034, receiving the target data sent by the lower-level storage controller, and storing the target data in the register or storage area pointed to by the write pointer in the temporary storage queue;

[0082] Sub-step 3035: based on the address of the next writable register or storage area, update the write pointer so that the write pointer points to the next writable register or storage area.

[0083] In an embodiment of the present invention, writing to the temporary storage queue can be performed based on a write pointer (sram_enq_ptr) or an enqueue pointer, which is used to point to a location in the data queue where an enqueue operation is performed, and data can be stored at the location pointed to by the write pointer.

[0084] The write pointer may include a storage address. In a temporary storage queue constructed based on SRAM or other storage media, the value of the write pointer corresponds to a specific storage unit address in the SRAM.

[0085] When data needs to be stored in the temporary storage queue, the target data can be stored in the register or storage area pointed to by the storage address of the write pointer in the temporary storage queue according to the instruction of the write pointer, thereby storing the data.

[0086] Furthermore, based on the address of the next writable register or storage area, the write pointer is updated to point to the next writable register or storage area, so that the corresponding storage location can be found when writing data to the temporary storage queue next time.

[0087] The way to update the write pointer to point to the next location where data can be stored can be adjusted according to the queue type. If it is a linear queue, you can usually simply increase the write pointer by 1; if it is a circular queue, you can perform a modulo operation sram_enq_ptr = (sram_enq_ptr + 1) % queue_size, and the write pointer can point to the location in the queue where the next data can be stored.

[0088] Optionally, the temporary storage queue corresponds to a read pointer; the read pointer is used to point to the next readable register or storage area;

[0089] The step 304 of sending the target data in the temporary storage queue to the upper storage controller includes:

[0090] Sub-step 3043, determining a readable register or storage area in the temporary storage queue and target data in the readable register or storage area based on the read pointer;

[0091] Sub-step 3044, sending the target data to the upper-level storage controller, and updating the read pointer based on the address of the next readable register or storage area, so that the read pointer points to the next readable register or storage area.

[0092] In the embodiment of the present invention, similarly, the temporary storage queue has a corresponding read pointer, which is used to point to the next readable register or storage area. When reading data in the temporary storage queue, the register or storage area corresponding to the read pointer can be determined, and then the target data in the register or storage area can be obtained, and then the data can be sent to the upper storage register.

[0093] Further, based on the address of the next readable register or storage area, the read pointer is updated so that the write pointer points to the next readable register or storage area. The method of updating the read pointer can be similar to the updating of the write pointer, which will not be repeated here.

[0094] Figure 4 is a step diagram of another data processing method provided by an embodiment of the present invention; applied to a lower-level storage controller, Figure 4 include:

[0095] Step 401, receiving an access request sent by an upper-level storage controller, and searching for target data indicated by the access request in a lower-level storage; the access request is stored in a missing queue by the upper-level storage controller, and sent to the lower-level storage controller;

[0096] Step 402, sending the target data to an intermediate storage controller; the intermediate storage controller is used to receive the target data and store the target data in a temporary storage queue; the intermediate storage controller is also used to send the target data in the temporary storage queue to the upper storage controller; the upper storage controller is used to send a write-back request to the lower storage controller when storing the target data and data replacement occurs;

[0097] Step 403, receiving a write-back request sent by the upper-level storage controller, executing the write-back operation indicated by the write-back request, and returning write-back confirmation information to the upper-level storage controller; the upper-level storage controller is used to store the write-back confirmation information in a write-back queue.

[0098] For details of steps 401 to 403, please refer to Figures 1 to 3 The contents of the embodiments are not described in detail.

[0099] Optionally, the method further includes:

[0100] Step 404: when at least part of the storage area in the missing queue is in an idle state, send the target data to the upper-level storage controller; the upper-level storage controller is used to store the target data in the missing queue.

[0101] In an embodiment of the present invention, the depth of the missing queue can be flexibly configured, so the missing queue still has a certain storage capacity. Therefore, if at least part of the storage area of ​​the missing queue is in an idle state, the target data can also be sent to the upper-level storage controller, and the upper-level storage controller is used to store the target data in the missing queue.

[0102] In the case where the missing queue is full, Figure 3 In an embodiment, the target data is sent to an intermediate storage controller.

[0103] Similarly, whether the upper-level storage controller obtains the target data indirectly based on the intermediate storage or directly from the lower-level storage controller, it needs to store the target data. If data replacement occurs, it also needs to send a write-back request to the lower-level storage controller, which will not be repeated here.

[0104] By implementing the embodiment of the present invention, when at least part of the storage area in the missing queue is in an idle state, the target data is sent to the upper storage controller, and the upper storage controller stores the target data in the missing queue. The storage capacity of the missing queue can be fully utilized to store the target data, and the storage in the temporary storage queue is not required, so that the stream mode support is realized and the delay and performance of data processing are optimized. Thus, the storage capacity and data processing capacity of the whole system are improved.

[0105] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0106] System Example

[0107] Figure 5 is a schematic diagram of a data processing system provided by an embodiment of the present invention, wherein the system 50 comprises: an upper-level storage controller 501, an intermediate storage controller 502, and a lower-level storage controller 503;

[0108] The upper storage controller 501 is used to store access requests into a missing queue, and send the access requests in the missing queue to the lower storage controller 503;

[0109] The lower-level storage controller 503 is used to search for target data indicated by the access request in the lower-level storage according to the access request sent by the upper-level storage controller 501, and send the target data to the intermediate storage controller 502;

[0110] The intermediate storage controller 502 is used to receive the target data sent by the lower-level storage controller 503, store the target data in a temporary storage queue, and send the target data in the temporary storage queue to the upper-level storage controller 501;

[0111] The upper storage controller 501 is used to send a write-back request to the lower storage controller 503 when storing the target data and data replacement occurs;

[0112] The lower-level storage controller 503 is used to receive the write-back request, perform the write-back operation indicated by the write-back request, and return write-back confirmation information to the upper-level storage controller 501;

[0113] The upper storage controller 501 is used to store the write-back confirmation information in a write-back queue.

[0114] In addition, the operations that can be performed by the upper storage controller 501, the intermediate storage controller 502 and the lower storage controller 503 can refer to Figures 1 to 3 The specific content of the embodiment will not be repeated here.

[0115] As for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0116] Device Embodiment

[0117] Figure 6 : is a structural block diagram of a data processing device of the present invention, the device is applied to an intermediate storage controller, and the device 60 includes:

[0118] The temporary storage module 601 is used to receive the target data sent by the lower storage controller and store the target data in the temporary storage queue; the lower storage controller is used to search the target data indicated by the access request in the lower storage; the access request is stored in the missing queue by the upper storage controller and sent to the lower storage controller;

[0119] The sending module 602 is used to send the target data in the temporary queue to the upper-level storage controller; the upper-level storage controller is used to send a write-back request to the lower-level storage controller when storing the target data and data replacement occurs; the lower-level storage controller is used to execute the write-back operation indicated by the write-back request and return write-back confirmation information to the upper-level storage controller; the upper-level storage controller is used to store the write-back confirmation information in the write-back queue.

[0120] Optionally, the device further comprises:

[0121] An intermediate storage module, configured to determine a second number of storage areas in an intermediate storage outside an upper storage and a lower storage according to a preset queue depth and a preset first number of registers; the sum of the preset first number and the second number being equal to a value of the preset queue depth;

[0122] The queue construction module is used to construct a temporary queue of the preset queue depth according to the preset first number of registers and the second number of storage areas.

[0123] Optional, staging module, including:

[0124] A working status submodule, used for receiving target data sent by a lower-level storage controller, and determining the status of the temporary storage queue and the status of the register; the status of the temporary storage queue includes empty and non-empty; the status of the register includes valid and invalid;

[0125] A register writing submodule, used for writing the target data into the register and setting the state of the register to be valid when the temporary storage queue is empty and the register is invalid;

[0126] The storage area writing module is used to write the target data into the storage area when the temporary storage queue is not empty and the register is valid.

[0127] Optional, sending module, including:

[0128] A register sending submodule, used for sending the target data in the register to the upper storage controller and setting the state of the register to invalid when the register is valid;

[0129] The storage area sending submodule is used to send the target data in the storage area to the upper storage controller when the register is invalid.

[0130] Optionally, the temporary storage queue corresponds to a write pointer; the write pointer is used to point to the next writable register or storage area; the temporary storage module includes:

[0131] A write pointer indicating submodule, used for receiving target data sent by a lower-level storage controller, and storing the target data in a register or storage area pointed to by the write pointer in a temporary storage queue;

[0132] The write pointer update submodule is used to update the write pointer based on the address of the next writable register or storage area so that the write pointer points to the next writable register or storage area.

[0133] Optionally, the temporary storage queue corresponds to a read pointer; the read pointer is used to point to the next readable register or storage area; the sending module includes:

[0134] a read pointer indicating submodule, configured to determine, based on the read pointer, a readable register or storage area in the temporary storage queue, and target data in the readable register or storage area;

[0135] The read pointer update submodule is used to send the target data to the upper storage controller and update the read pointer based on the address of the next readable register or storage area so that the read pointer points to the next readable register or storage area.

[0136] Figure 7 : is a structural block diagram of a data processing device of the present invention, the device is applied to a lower-level storage controller; the device 70 includes:

[0137] The request receiving module 701 is used to receive an access request sent by an upper-level storage controller, and search for target data indicated by the access request in the lower-level storage; the access request is stored in a missing queue by the upper-level storage controller, and sent to the lower-level storage controller;

[0138] The data return module 702 is used to send the target data to the intermediate storage controller; the intermediate storage controller is used to receive the target data and store the target data in a temporary storage queue; the intermediate storage controller is also used to send the target data in the temporary storage queue to the upper storage controller; the upper storage controller is used to send a write-back request to the lower storage controller when storing the target data and data replacement occurs;

[0139] The data write-back module 703 is used to receive a write-back request sent by the upper-level storage controller, execute the write-back operation indicated by the write-back request, and return write-back confirmation information to the upper-level storage controller; the upper-level storage controller is used to store the write-back confirmation information in a write-back queue.

[0140] Optionally, the device further comprises:

[0141] The supplementary sending module is used to send the target data to the upper-level storage controller when at least part of the storage area in the missing queue is in an idle state; the upper-level storage controller is used to store the target data in the missing queue.

[0142] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0143] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0144] Regarding the processor in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0145] Reference Figure 8 , is a structural block diagram of an electronic device for data processing provided by an embodiment of the present invention. Figure 8 As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the data processing method of the aforementioned embodiment.

[0146] The processor may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array) or other editable devices, transistor logic devices, hardware components or any combination thereof. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor.

[0147] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus. The communication bus may be divided into an address bus, a data bus, and a control bus. For ease of representation, Figure 4 The fact that only one line is used in the diagram does not mean that there is only one bus or only one type of bus.

[0148] The memory can be a ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or it can be an EEPROM (Electrically ErasableProgrammable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory), a magnetic tape, a floppy disk, and an optical data storage device.

[0149] The embodiment of the present invention further provides a non-temporary readable storage medium, when the instructions in the storage medium are executed by a processor of an electronic device (server or terminal), the processor is enabled to execute Figure 2 The data processing method shown.

[0150] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0151] It will be appreciated by those skilled in the art that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (which may include disk storage, CD-ROM, optical storage) containing computer-usable program code.

[0152] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0153] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0154] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 Functional steps of one or more boxes.

[0155] Although the preferred embodiments of the present invention are described, those skilled in the art will recognize the basic creative concept and may make other changes and modifications to these embodiments. The appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0156] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0157] The data processing method, device, electronic device and readable storage medium provided by the present invention are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A data processing method, characterized in that: Applied to intermediate storage controller; The intermediate storage controller is used to read and write intermediate storage outside each level of cache in the multi-level cache system; the method includes: Receive target data sent by a lower-level storage controller, and store the target data in a temporary storage queue in the intermediate storage; the lower-level storage controller is used to search for target data indicated by an access request in the lower-level storage; the access request is stored by the upper-level storage controller in a missing queue in the upper-level storage, and sent to the lower-level storage controller; the upper-level storage and the lower-level storage are two adjacent levels of cache in the multi-level cache system; the temporary storage queue is composed of a preset first number of registers and a second number of storage areas, the second number is determined by a preset queue depth and the preset first number; the sum of the preset first number and the second number is equal to the value of the preset queue depth; when the temporary storage queue is empty and the register is invalid, the register is used for data writing; when the temporary storage queue is not empty and the register is valid, the storage area is used for data writing; The target data in the temporary queue is sent to the upper-level storage controller; the upper-level storage controller is used to send a write-back request to the lower-level storage controller when the target data is stored and data replacement occurs; the lower-level storage controller is used to execute the write-back operation indicated by the write-back request and return write-back confirmation information to the upper-level storage controller; the upper-level storage controller is used to store the write-back confirmation information in the write-back queue.

2. The method according to claim 1, characterized in that The method further comprises: Determining a second number of storage areas in an intermediate memory outside of the upper level storage and the lower level storage according to a preset queue depth and a preset first number of registers; A temporary queue of the preset queue depth is constructed according to the preset first number of registers and the second number of storage areas.

3. The method according to claim 2, characterized in that The step of receiving target data sent by the lower-level storage controller and storing the target data in a temporary storage queue comprises: Receive target data sent by the lower-level storage controller, and determine the state of the temporary storage queue and the state of the register; the state of the temporary storage queue includes empty and non-empty; the state of the register includes valid and invalid; When the temporary storage queue is empty and the register is invalid, writing the target data into the register and setting the state of the register to be valid; When the temporary storage queue is not empty and the register is valid, the target data is written into the storage area.

4. The method according to claim 2, characterized in that: The step of sending the target data in the temporary storage queue to the upper-level storage controller includes: When the register is valid, the target data in the register is sent to the upper storage controller, and the state of the register is set to invalid; In a case where the register is invalid, target data in the storage area is sent to the upper storage controller.

5. The method according to claim 2, characterized in that: The temporary storage queue corresponds to a write pointer; the write pointer is used to point to the next writable register or storage area; The step of receiving target data sent by the lower-level storage controller and storing the target data in a temporary storage queue comprises: Receive target data sent by the lower-level storage controller, and store the target data in the register or storage area pointed to by the write pointer in the temporary storage queue; Based on the address of the next writable register or storage area, the write pointer is updated so that the write pointer points to the next writable register or storage area.

6. The method according to claim 2, characterized in that The temporary storage queue corresponds to a read pointer; the read pointer is used to point to the next readable register or storage area; The step of sending the target data in the temporary storage queue to the upper-level storage controller includes: Based on the read pointer, determining a readable register or storage area in the temporary storage queue, and target data in the readable register or storage area; The target data is sent to the upper storage controller, and based on the address of the next readable register or storage area, the read pointer is updated so that the read pointer points to the next readable register or storage area.

7. A data processing method, characterized in that: Applied to a lower-level storage controller; the method comprises: Receive an access request sent by an upper-level storage controller, and search for target data indicated by the access request in a lower-level storage; the access request is stored in a missing queue by the upper-level storage controller and sent to the lower-level storage controller; The target data is sent to an intermediate storage controller; the intermediate storage controller is used to receive the target data and store the target data in a temporary storage queue; the intermediate storage controller is also used to send the target data in the temporary storage queue to the upper-level storage controller; the upper-level storage controller is used to send a write-back request to the lower-level storage controller when the target data is stored and data replacement occurs; the temporary storage queue is composed of a preset first number of registers and a second number of storage areas, the second number is determined by a preset queue depth and the preset first number; the sum of the preset first number and the second number is equal to the value of the preset queue depth; when the temporary storage queue is empty and the register is invalid, the register is used for data writing; when the temporary storage queue is not empty and the register is valid, the storage area is used for data writing; Receive a write-back request sent by the upper-level storage controller, execute the write-back operation indicated by the write-back request, and return write-back confirmation information to the upper-level storage controller; the upper-level storage controller is used to store the write-back confirmation information in a write-back queue.

8. The method according to claim 7, characterized in that The method further comprises: In a case where at least part of the storage area in the missing queue is in an idle state, the target data is sent to the upper-level storage controller; and the upper-level storage controller is used to store the target data in the missing queue.

9. A data processing system, characterized in that: The system comprises: an upper-level storage controller, an intermediate storage controller and a lower-level storage controller; the intermediate storage controller is used to read and write intermediate storage outside each level of cache in the multi-level cache system; The upper storage controller is used to store the access request in the missing queue in the upper storage, and send the access request in the missing queue to the lower storage controller; The lower-level storage controller is used to search the target data indicated by the access request in the lower-level storage according to the access request sent by the upper-level storage controller, and send the target data to the intermediate storage controller; the upper-level storage and the lower-level storage are two adjacent levels of cache in the multi-level cache system; The intermediate storage controller is used to receive the target data sent by the lower storage controller, store the target data in the temporary storage queue in the intermediate storage, and send the target data in the temporary storage queue to the upper storage controller; the temporary storage queue is composed of a preset first number of registers and a second number of storage areas, the second number is determined by a preset queue depth and the preset first number; the sum of the preset first number and the second number is equal to the value of the preset queue depth; when the temporary storage queue is empty and the register is invalid, the register is used for data writing; when the temporary storage queue is not empty and the register is valid, the storage area is used for data writing; The upper storage controller is used to send a write-back request to the lower storage controller when storing the target data and data replacement occurs; The lower-level storage controller is used to receive the write-back request, perform the write-back operation indicated by the write-back request, and return write-back confirmation information to the upper-level storage controller; The upper-level storage controller is used to store the write-back confirmation information in a write-back queue.

10. An electronic device, characterized in that: The electronic device includes a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the data processing method as described in any one of claims 1 to 8.

11. A readable storage medium, characterized in that: When the instructions in the readable storage medium are executed by a processor of an electronic device, the processor is enabled to execute the data processing method as claimed in any one of claims 1 to 8.

Images