Devices and systems for superconducting quantum computing control, reading and feedback

Abstract

The present disclosure relates to the field of quantum computing technology, and more particularly to a device and system for superconducting quantum computing control, reading, and feedback, comprising a clock module and one or more acquisition modules. The clock module provides a clock synchronization signal to each acquisition module to achieve clock synchronization between the acquisition modules, thereby reducing the delay between the acquisition modules and achieving low-latency control of a quantum chip. Each acquisition module compares the read signal of each auxiliary quantum bit with a preset threshold value to obtain multiple quantum measurement results. The error type of the data quantum bit is then determined based on the measurement results, and a quantum error correction operation corresponding to the error type is determined. A drive signal is then output based on the quantum error correction operation to perform quantum error correction on the erroneous data quantum bit. The device has high feedback control efficiency, and the number of acquisition modules can be adjusted as needed, which has high scalability.

Description

Technical Field

[0001] The present disclosure relates to the field of quantum computing technology, and in particular to a device and system for superconducting quantum computing control, reading and feedback. Background Art

[0002] With the rapid development of technologies for superconducting quantum computing control, readout, and feedback, the number of qubits on quantum chips has exceeded 50. This increase in the number of qubits has also placed higher demands on the measurement and control systems of quantum chips. In the past, measurement and control systems for quantum chips primarily consisted of instruments such as commercial arbitrary waveform generators (AWGs) and data acquisition cards (DAQ-cards). As the number of bits increases, the scale of the measurement and control system also increases linearly. This poses additional challenges to experiments in terms of cost, convenience, and latency in real-time feedback. Furthermore, existing superconducting quantum systems are subject to errors caused by environmental noise and imperfect control mechanisms. Quantum error correction is crucial for addressing these errors. Some error correction methods for Bose qubits require real-time feedback technology, which requires the control system to rapidly process the readout data of the bits in real time, comprehensively analyze it, and immediately execute the corresponding control instructions. Summary of the Invention

[0003] According to one aspect of the present disclosure, a device for superconducting quantum computing control, reading, and feedback is provided, wherein the device for superconducting quantum computing control, reading, and feedback comprises a clock module and one or more acquisition modules, wherein:

[0004] The clock module is used to provide a clock synchronization signal to each acquisition module to achieve clock synchronization between the acquisition modules;

[0005] Each acquisition module is connected to the quantum chip and the clock module, and each acquisition module is used to:

[0006] receiving a measurement signal output by the quantum chip, wherein the measurement signal includes a plurality of auxiliary quantum bit states;

[0007] Comparing the measurement signal with a preset threshold combination to obtain a plurality of quantum measurement results, wherein the preset threshold combination includes a plurality of preset thresholds, each preset threshold corresponding to each auxiliary quantum bit state;

[0008] Determining an error type of a data qubit in the quantum chip based on each quantum measurement result, and determining a quantum error correction operation corresponding to the error type;

[0009] A driving signal is output according to the quantum error correction operation to perform quantum error correction on the erroneous data quantum bit.

[0010] In one possible implementation, the comparison of the preset threshold combination with the measurement signal to obtain multiple quantum measurement results includes:

[0011] Comparing the measurement signals of the auxiliary qubits using any number of preset threshold combinations in the preset threshold combination to obtain a comparison result;

[0012] The comparison result is used to determine the state of each auxiliary quantum bit to obtain the quantum measurement result.

[0013] In one possible implementation, determining an error type of a data qubit in the quantum chip according to each quantum measurement result, and determining a quantum error correction operation corresponding to the error type, includes:

[0014] Processing the quantum measurement result using a preset coding logic to obtain a logical operation result;

[0015] The error type of the data quantum bit is determined according to the logical operation result.

[0016] In a possible implementation, the acquisition module includes a radio frequency signal output module, a radio frequency signal input module, a pulse signal output module, a pulse signal input module, a logic control module, and a timing synchronization module, wherein:

[0017] The output end of the radio frequency signal output module is connected to the input end of the quantum chip, and is used to output the driving signal;

[0018] The input end of the radio frequency signal input module is connected to the output end of the quantum chip, and is used to receive the measurement signal of the auxiliary quantum bit;

[0019] The pulse signal output module is used to generate an output pulse signal;

[0020] The pulse signal input module is used to receive an input pulse signal, wherein the input pulse signal includes the state of the auxiliary quantum bit;

[0021] The timing synchronization module is used to receive a clock synchronization signal to achieve clock synchronization with other acquisition modules;

[0022] The logic control module is connected to the RF signal output module, the RF signal input module, the pulse signal output module, the pulse signal input module, and the timing synchronization module. The logic control module is used to use a preset threshold to compare with the read signal of each auxiliary quantum bit to obtain multiple quantum measurement results, determine the error type of the data quantum bit according to each quantum measurement result, and determine the quantum error correction operation corresponding to the error type, and then generate digital driving information according to the quantum error correction operation. The digital driving information is used to generate the driving signal.

[0023] In a possible implementation, the radio frequency signal output module includes a digital-to-analog converter, configured to perform digital-to-analog conversion on the received digital driving information and obtain the driving signal;

[0024] The RF signal input module includes an analog-to-digital converter and a comparison circuit. The analog-to-digital converter is used to perform analog-to-digital conversion on the received measurement signal of the auxiliary quantum bit to obtain a target digital signal; the comparison circuit is used to perform a comparison operation between the target digital signal and a preset threshold to determine the state of the auxiliary quantum bit based on the comparison result.

[0025] In a possible implementation, the clock module includes an atomic clock signal input module, a clock synchronization signal output module, a trigger signal input module, and a trigger signal output module, wherein:

[0026] The clock signal input end of the atomic clock signal input module is used to receive the atomic clock signal and configure the clock signal for the clock module;

[0027] The clock synchronization signal output module is used to output the clock synchronization signal;

[0028] The trigger signal input module is connected to the host computer or the external trigger device, and is used to receive the first trigger signal sent by the host computer or the second trigger signal sent by the external trigger device;

[0029] The trigger signal output module is used to output one or more third trigger signals.

[0030] In a possible implementation, the clock module further includes a rubidium atomic clock, the clock signal input end of the atomic clock signal input module is connected to the output end of the rubidium atomic clock, and the output end of the rubidium atomic clock is used to output the atomic clock signal.

[0031] In a possible implementation manner, the sampling rates of the RF signal output module and the RF signal input module are both greater than 1 Gsps.

[0032] In a possible implementation, the acquisition module and the clock module are both implemented based on a field programmable gate array (FPGA).

[0033] According to one aspect of the present disclosure, a system for superconducting quantum computing control, reading, and feedback is provided, wherein the system for superconducting quantum computing control, reading, and feedback comprises one or more of the devices for superconducting quantum computing control, reading, and feedback and a quantum chip.

[0034] The apparatus for superconducting quantum computing control, reading, and feedback in the disclosed embodiment includes a clock module and one or more acquisition modules. The clock module provides a clock synchronization signal to each acquisition module to achieve clock synchronization between the acquisition modules, which can reduce the delay between the acquisition modules and thus achieve low-latency control of the quantum chip. The measurement signal output by the quantum chip is received by each acquisition module, and a preset threshold is used to compare it with the measurement signal of each auxiliary quantum bit to obtain multiple quantum measurement results. The preset threshold is for multiple auxiliary quantum bits. The error type of the data quantum bit is determined based on these measurement results, and the quantum error correction operation corresponding to the error type is determined. Then, a drive signal is output based on the quantum error correction operation to perform quantum error correction on the data quantum bit that has an error. The apparatus for superconducting quantum computing control, reading, and feedback has high feedback control efficiency, and the number of acquisition modules can be set according to needs, which has high scalability.

[0035] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, rather than limiting the present disclosure. Other features and aspects of the present disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The accompanying drawings herein are incorporated into and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and, together with the specification, are used to explain the technical solutions of the present disclosure.

[0037] Figure 1 A block diagram of an apparatus for superconducting quantum computing control, reading, and feedback according to an embodiment of the present disclosure is shown.

[0038] Figure 2 A schematic diagram of execution feedback logic of a collection module according to an embodiment of the present disclosure is shown.

[0039] Figure 3a 、 Figure 3b A feedback logic diagram of feedback error correction control according to an embodiment of the present disclosure is shown.

[0040] Figure 4A block diagram of an acquisition module in a device for superconducting quantum computing control, reading, and feedback according to an embodiment of the present disclosure is shown.

[0041] Figure 5 A block diagram of a clock module in a device for superconducting quantum computing control, reading, and feedback according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0042] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0043] In the description of the present disclosure, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0044] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the present disclosure, "plurality" means two or more, unless otherwise specifically defined.

[0045] In this disclosure, unless otherwise expressly specified or limited, terms such as "mounted," "connected," "connect," and "fixed" should be understood broadly. For example, they may refer to fixed connections, detachable connections, or integration; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal connections between two components or interactions between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on specific circumstances.

[0046] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0047] The term "and / or" herein simply describes an association relationship between associated objects, indicating that three relationships can exist. For example, "A and / or B" can represent the existence of three situations: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" herein refers to any combination of at least two of any one or more of a plurality of items. For example, "at least one of A, B, and C" can represent any one or more elements selected from the set consisting of A, B, and C.

[0048] In addition, numerous specific details are provided in the following detailed description to better illustrate the present disclosure. Those skilled in the art will appreciate that the present disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art are not described in detail in order to highlight the main points of the present disclosure.

[0049] See also Figure 1 , Figure 1 A block diagram of an apparatus for superconducting quantum computing control, reading, and feedback according to an embodiment of the present disclosure is shown.

[0050] like Figure 1 As shown, the device for superconducting quantum computing control, reading and feedback includes a clock module 10 and one or more acquisition modules 20, wherein:

[0051] The clock module 10 is used to provide a clock synchronization signal to each acquisition module 20 to achieve clock synchronization between the acquisition modules 20;

[0052] Each acquisition module 20 is connected to the quantum chip 30 and the clock module 10, and each acquisition module 20 is used to:

[0053] receiving a measurement signal output by the quantum chip, wherein the measurement signal includes a plurality of auxiliary quantum bit states;

[0054] Comparing the measurement signal with a preset threshold combination to obtain a plurality of quantum measurement results, wherein the preset threshold combination includes a plurality of preset thresholds, each preset threshold corresponding to each auxiliary quantum bit state;

[0055] Determining an error type of a data qubit in the quantum chip based on each quantum measurement result, and determining a quantum error correction operation corresponding to the error type;

[0056] A driving signal is output according to the quantum error correction operation to perform quantum error correction on the erroneous data quantum bit.

[0057] The apparatus for superconducting quantum computing control, reading, and feedback in the disclosed embodiment includes a clock module 10 and one or more acquisition modules 20. The clock module 10 provides a clock synchronization signal to each acquisition module 20 to achieve clock synchronization between the acquisition modules 20, thereby reducing the delay between the acquisition modules 20 and achieving low-latency control of the quantum chip 30 using the acquisition modules. The measurement signals output by the quantum chip are received by each acquisition module 20, and compared with the measurement signals of each auxiliary qubit using a preset threshold value to obtain multiple quantum measurement results, wherein the preset threshold value is specific to multiple auxiliary qubits. The error type of the data qubit is determined based on these measurement results, and the quantum error correction operation corresponding to the error type is determined. Then, a drive signal is output based on the quantum error correction operation to perform quantum error correction on the erroneous data qubit. The apparatus for superconducting quantum computing control, reading, and feedback has high feedback control efficiency, and the number of acquisition modules can be set according to needs, which has high scalability.

[0058] The embodiments of the present disclosure do not limit the type of quantum chip 30, the specific implementation of the clock module 10, and one or more acquisition modules 20. Those skilled in the art can make settings according to actual conditions and needs. The quantum chip 30, the clock module 10, and the one or more acquisition modules 20 can all be implemented through hardware circuits. The quantum chip is the core structure for realizing quantum computing. A large number of quantum bit structures are provided on the quantum chip. Each quantum bit is composed of a specific hardware circuit provided on the quantum chip. Each quantum bit has at least two distinguishable logical states. Based on the quantum algorithm, the logical state of the quantum bit can undergo controllable changes, thereby realizing quantum computing.

[0059] The device for superconducting quantum computing control, reading and feedback in the embodiment of the present disclosure may also include a device body, such as a square chassis, and each module is arranged in the device body. Of course, the shape of the device body may also be other, which is not limited by the embodiment of the present disclosure. Those skilled in the art can set it according to actual conditions and needs.

[0060] Exemplarily, the device for superconducting quantum computing control, reading and feedback of the embodiment of the present disclosure can be connected to a quantum system. The core of the quantum system is a quantum chip 30 located in a refrigerator, which can realize quantum computing. The entire system includes external devices at room temperature and low temperature (below 4K). To control the quantum chip 30, it is necessary to provide a radio frequency electromagnetic drive signal. Exemplarily, an acquisition module 20 can emit a radio frequency signal of about 100 megahertz and some trigger signals (for example, which can be used to control other room temperature devices). After a series of microwave devices, it can control a channel of the quantum chip 30. Among them, multiple acquisition cards can be used in combination to control the entire quantum chip 30.

[0061] It's worth noting that in quantum computing, for clarity, we use the terms logical bit, physical bit (or data qubit), and auxiliary bit. Physical bits are the actual bits on the quantum chip, which are subject to interference from various noises. Generally, when discussing hardware and physical implementations, qubits refer to physical bits (in the context of this article). Logical bits, on the other hand, are typically formed by encoding multiple physical bits. They have a certain degree of redundancy against various errors. When an error occurs (in this case, an error in the physical bit encoding the logical bit), the logical state changes to the corresponding error state, while the stored information is not lost. Logical bits are the core component used to actually perform quantum computations.

[0062] The purpose of quantum error correction in the disclosed embodiments is to protect logical bits from being interfered with by environmental noise and thus causing errors.

[0063] Auxiliary bits are physical bits specifically used for error detection and correction. They don't carry actual computational information, but through interaction with logical bits, they can detect and identify errors in the physical bits that make up the logical bits, thereby guiding error correction in the logical bits. By measuring the auxiliary bits, we can determine which physical bit of the logical bit has experienced the error and what type of error, allowing us to provide appropriate feedback and error correction.

[0064] The embodiment of the present disclosure does not limit the specific implementation of each step performed by the acquisition module 20. Those skilled in the art can adopt relevant technologies to implement the steps according to actual conditions and needs.

[0065] The embodiments of the present disclosure do not limit the preset threshold values ​​in the preset threshold value combination and the specific number and state of the auxiliary qubit states in the measurement signal. Those skilled in the art can set them according to actual conditions and needs. Among them, the preset threshold values ​​in the preset threshold value combination can be obtained based on logical qubits. Logical qubits can be obtained, for example, based on the calculation results of the quantum chip (such as the results of the pre-calculation), or based on an important intermediate parameter or other type of parameter maintained as needed. The embodiments of the present disclosure do not limit this. In this case, the embodiments of the present disclosure can use the auxiliary qubit state to realize error detection and error correction of the data qubit to maintain the qubit state of the data qubit, so that the quantum chip can normally complete the quantum computing operation.

[0066] Exemplarily, the using of a preset threshold combination to compare with the measurement signal to obtain multiple quantum measurement results may include:

[0067] Comparing the measurement signals of the auxiliary qubits using any number of preset threshold combinations in the preset threshold combination to obtain a comparison result;

[0068] The comparison result is used to determine the state of each auxiliary quantum bit to obtain the quantum measurement result.

[0069] The embodiments of the present disclosure do not limit the specific implementation method of comparing the measurement signals of each auxiliary quantum bit using a combination of any number of preset thresholds in the preset threshold combination, and do not limit the setting method of the preset threshold size. Those skilled in the art can set it according to actual conditions and needs. For example, when the auxiliary quantum bit is at 1, the signal strength is large, and when it is at 0, the signal strength is small. In this case, the embodiments of the present disclosure can set the preset threshold at the signal strength corresponding to the intermediate value between 0 and 1, so as to automatically judge the state of the bit and obtain the comparison result.

[0070] Exemplarily, the measurement result may represent the state of the auxiliary qubit. After obtaining the measurement result, the error type of the data qubit in the quantum chip may be determined based on each quantum measurement result, and a quantum error correction operation corresponding to the error type may be determined. For example, the error correction operation may include:

[0071] Determining an error type of a data qubit in the quantum chip according to each quantum measurement result, and determining a quantum error correction operation corresponding to the error type, including:

[0072] Processing the quantum measurement result using a preset coding logic to obtain a logical operation result;

[0073] The error type of the data quantum bit is determined according to the logical operation result.

[0074] Specifically, this may include:

[0075] Performing quantum logic gate processing on the state (measurement result) of each auxiliary qubit using a qubit combination in a preset quantum signal, wherein the qubit combination includes a combination of any number of preset qubits;

[0076] Determining the quantum bit state of each auxiliary quantum bit to obtain the quantum measurement result;

[0077] Processing the quantum measurement result using a preset coding logic to obtain a logical operation result;

[0078] The error type of the data quantum bit is determined based on the result of the logical operation.

[0079] The embodiments of the present disclosure do not limit the type and implementation of quantum logic gates. Those skilled in the art may configure the gates according to actual conditions and needs. For example, the quantum logic gates may include at least one of a Pauli-X gate, a Hadamard gate, a Pauli-Y gate, a Pauli-Z gate, a swap gate, a phase-shift gate, and a Toffoli gate.

[0080] The embodiments of the present disclosure do not limit the specific combination of quantum bit combinations in the preset quantum signal. Those skilled in the art can set it according to actual conditions and needs. For example, if the preset quantum signal includes M preset quantum bits, each quantum bit combination can include any s preset quantum bits, where 0<s<M and s and M are both integers.

[0081] The following is an illustrative introduction using an example in which a preset quantum signal includes three preset quantum bits and a measurement signal includes two auxiliary quantum bit states.

[0082] See also Figure 2 , Figure 2 A schematic diagram of execution feedback logic of a collection module according to an embodiment of the present disclosure is shown.

[0083] For example, Figure 2 As shown, the embodiment of the present disclosure may first prepare a preset quantum signal α|000>+β|111>. Of course, the preset quantum signal α|000>+β|111> may also be prepared in advance, which is not limited in the embodiment of the present disclosure.

[0084] Assuming that the logical quantum bit is α|0>+β|1>, and the preset quantum signal includes three preset quantum bits, the embodiment of the present disclosure can use the logical quantum bit α|0>+β|1> to prepare the preset quantum signal α|000>+β|111>. Of course, the embodiment of the present disclosure does not limit the specific implementation method of using the logical quantum bit to prepare the preset quantum signal. Those skilled in the art can adopt relevant technologies to implement it according to actual conditions and needs. For example, the embodiment of the present disclosure can apply a drive to a physical bit α|0>+β|1> to make it become a logical quantum bit α|0>+β|1>, and then apply a CNOT gate to the second and third quantum bits to make them entangled with each other, thereby realizing the α|000>+β|111> state. Among them, the working principle of the CNOT gate is: assuming that the first quantum bit is used to perform a CNOT gate on the second quantum bit, when the first quantum bit is in state 0, the quantum state remains unchanged, and when the first quantum bit is in state 1, the quantum state of the second quantum bit is flipped, for example: CNOT|00>=|00>; CNOT|10>=|11>; CNOT(α|00>+β|11>=α|00>+β|10>; CNOT(α|0>+β|1>)|0>=α|00>+β|11>.

[0085] Then, the embodiment of the present disclosure can use the quantum bit combination in the preset quantum signal to perform quantum logic gate processing on each auxiliary quantum bit state corresponding to each measurement result, and the quantum bit combination includes a combination of any number of preset quantum bits, for example, using the first two quantum bits of the preset quantum signal α|000>+β|111> Perform CNOT gates on the first auxiliary bit in turn, and use the last two quantum bits of the preset quantum signal α|000>+β|111> The second auxiliary bits are sequentially subjected to CNOT gates to implement quantum logic gate processing on the states of the auxiliary quantum bits using the quantum bit combination in the preset quantum signal.

[0086] For example, Figure 2 As shown, the embodiment of the present disclosure can determine the quantum bit state of each auxiliary quantum bit based on the measurement result to obtain the quantum measurement result, determine the error type of the quantum bit based on each quantum measurement result, and determine the quantum error correction operation corresponding to the error type, output a driving signal based on the quantum error correction operation, and perform quantum error correction on the quantum bit in which the error occurs in the data quantum bit.

[0087] Of course, the embodiments of the present disclosure do not limit the specific implementation method for determining the quantum bit state of each auxiliary quantum bit. Those skilled in the art can adopt relevant technologies to implement it according to actual conditions and needs. For example, referring to the above introduction, the quantum bit state of each auxiliary quantum bit can be compared with a preset threshold (corresponding to a voltage signal) by using a comparison circuit. In this way, the quantum bit state of each auxiliary quantum bit can be determined, and the quantum operation result can be obtained by combining the quantum bit states of each auxiliary quantum bit. The embodiments of the present disclosure do not limit the specific implementation method for determining the error type of the quantum bit according to each quantum operation result and determining the quantum error correction operation corresponding to the error type. For example, there can be a mapping relationship between the quantum operation result, the error type of the quantum bit, and the quantum error correction operation. After the quantum operation result is determined, those skilled in the art can determine the quantum bit error type and quantum error correction operation corresponding to the quantum operation result according to the mapping relationship.

[0088] For example, assuming that the first auxiliary bit and the second auxiliary bit are measured and the measurement result |00> is obtained, it means that there is no error in the data qubit and no operation is performed;

[0089] For example, assuming that the first auxiliary bit and the second auxiliary bit are measured to obtain a measurement result |10>, indicating that an X error occurs in the first qubit in the data qubit, an X gate is applied to the first qubit in the data qubit;

[0090] For example, assuming that the first auxiliary bit and the second auxiliary bit are measured to obtain a measurement result |01>, indicating that an X error occurs in the second qubit of the data qubit, an X gate is applied to the first qubit of the data qubit;

[0091] For example, assuming that the first auxiliary bit and the second auxiliary bit are measured to obtain a measurement result |11>, it indicates that an X error occurs in the third qubit in the data qubit, and an X gate is applied to the first qubit in the data qubit.

[0092] The embodiments of the present disclosure are described by way of example using an X error and applying an X gate as the quantum error correction operation corresponding to the X error. However, this should not be considered as limiting the embodiments of the present disclosure. In other embodiments, other errors may occur in each bit of the data qubit. For different error types, those skilled in the art may configure corresponding quantum error correction operations (e.g., applying corresponding quantum logic gates) according to actual conditions and needs.

[0093] In the embodiments of the present disclosure, a quantum error correction operation can be implemented by the driving signal. That is, applying an X gate or other quantum logic gate to a corresponding qubit can generate a driving signal for the corresponding qubit to perform a quantum error correction operation on the corresponding qubit. Of course, those skilled in the art can use relevant technologies to generate corresponding driving signals to implement the X gate or other quantum logic gate according to actual conditions and needs, and the embodiments of the present disclosure are not limited to this.

[0094] In the disclosed embodiment, the goal of error correction is to maintain the prepared quantum state α|000>+β|111>. In some scenarios, this quantum state may be obtained as a result of a previous operation, so it is necessary to protect it from being affected by errors as much as possible (it can be understood that in actual quantum computing, these three bits as a whole encode a logical bit α|0>+β|1>).

[0095] The qubit error type in the embodiments of this disclosure may be caused by interaction with the environment. This error may refer to a qubit in α|000>+β|111> experiencing error X. In the above example, the auxiliary bits in the embodiments of this disclosure measure whether error X has occurred in these qubits.

[0096] When an error is confirmed, the disclosed embodiments can determine a corresponding quantum error correction operation based on the error type to restore the qubit with the error in the data qubit to its original quantum state. For example, in the above example, if it is determined that an error X has occurred in a qubit in α|000>+β|111>, an X gate is applied to the qubit to restore the qubit with the error to its original quantum state.

[0097] The measurement method described above produces consistent results for any quantum state (α|> and β|>), thus preserving the quantum states (α|> and β|>) unchanged. This, in turn, preserves the logical bits in the pre-set quantum signal of the disclosed embodiment. Furthermore, the error correction method of the disclosed embodiment summarizes the short duration of the error correction process, which can be repeated repeatedly. Overall, this system can overcome single-bit X errors, thereby improving the lifespan of the quantum bit.

[0098] Of course, the embodiments of the present disclosure are not limited to performing error correction once. For the entire process of quantum computing, a continuous feedback error correction control method can be adopted.

[0099] See also Figure 3a 、 Figure 3b , Figure 3a 、 Figure 3b A feedback logic diagram of feedback error correction control according to an embodiment of the present disclosure is shown.

[0100] The feedback logic diagram is an abstract description of the logic of a quantum feedback experiment. It consists of feedback nodes and feedback edges, primarily describing the read-feedback operation on a quantum chip. Feedback nodes represent the current state of the quantum system, while feedback edges represent the conditions for the system to transition between different feedback nodes. Feedback nodes are connected by directed feedback edges. Feedback nodes can contain information such as the qubit drive and measurement instructions for the current stage. The system selects which feedback edge to use by comprehensively determining the state of the quantum system at the end of the feedback node. For example, the system can select the appropriate feedback edge based on the qubit error type or measurement result determined after measuring the bit state, thereby enabling a transition to the next feedback node. This abstract structure can generate arbitrary quantum feedback logic, including but not limited to multi-level feedback and cyclic feedback.

[0101] For example, Figure 3a 、 Figure 3b The two feedback logic diagrams shown are Figure 3a The feedback logic diagram shown is a loop feedback. Figure 3b The feedback logic diagram shown is multi-level feedback. Of course, Figure 3a 、 Figure 3b The two feedback logics shown are exemplary and should not be considered as limitations on the embodiments of the present disclosure. In other embodiments, multi-level feedback and loop feedback may include other feedback nodes and feedback edges.

[0102] For example, Figure 3aFor example, if the error type of the quantum bit is determined to be error type 1 at the node measuring bit state 1, the feedback edge of error type 1 is selected to execute the feedback node corresponding to feedback drive 1. Taking the above example, if error type 1 is that the first quantum bit in the preset quantum signal has an X error, then the feedback drive 1 operation may include "applying an X gate to the first quantum bit in the preset quantum signal."

[0103] For example, Figure 3b For example, if the result of the quantum bit is determined to be result 1 at the node measuring the bit state, the feedback edge of result 1 is selected to perform feedback drive & the feedback node corresponding to measurement 1. Taking the above example, if result 1 is "measuring the first auxiliary bit and the second auxiliary bit to obtain the measurement result |10>", the feedback drive 1 operation can include "applying an X gate to the first quantum bit in the preset quantum signal", and then determining the result of the quantum bit again. If it is result 3, the corresponding feedback edge is selected.

[0104] The following is an exemplary introduction to the preferred implementation of the acquisition module 20 and the clock module 10.

[0105] See also Figure 4 , Figure 4 A block diagram of the acquisition module 20 in the apparatus for superconducting quantum computing control, reading, and feedback according to an embodiment of the present disclosure is shown.

[0106] In one possible implementation, Figure 4 As shown, the acquisition module 20 may include a radio frequency signal output module 220, a radio frequency signal input module 210, a pulse signal output module 230, a pulse signal input module 240, a logic control module 260, and a timing synchronization module 250, wherein:

[0107] The output end of the RF signal output module 220 is connected to the input end of the quantum chip 30 for outputting the driving signal;

[0108] The input end of the radio frequency signal input module 210 is connected to the output end of the quantum chip 30, and is used to receive the read signal (i.e., measurement signal) of the auxiliary quantum bit;

[0109] The pulse signal output module 230 is used to generate an output pulse signal;

[0110] The pulse signal input module 240 is used to receive an input pulse signal, wherein the input pulse signal includes the state of the auxiliary quantum bit;

[0111] The timing synchronization module 250 is used to receive a clock synchronization signal to achieve clock synchronization with other acquisition modules 20;

[0112] The logic control module 260 is connected to the RF signal output module 220, the RF signal input module 210, the pulse signal output module 230, the pulse signal input module 240, and the timing synchronization module 250. The logic control module 260 is used to compare the preset threshold with the read signal of each auxiliary quantum bit to obtain multiple quantum measurement results, determine the error type of the data quantum bit according to each quantum measurement result, and determine the quantum error correction operation corresponding to the error type, and then generate digital driving information according to the quantum error correction operation. The digital driving information is used to generate the driving signal.

[0113] The embodiments of the present disclosure do not limit the specific implementation methods of the RF signal output module 220, the RF signal input module 210, the pulse signal output module 230, the pulse signal input module 240, the logic control module 260, and the timing synchronization module 250. Those skilled in the art can set them according to actual conditions and needs. For example, the RF signal output module 220, the RF signal input module 210, the pulse signal output module 230, and the pulse signal input module 240 all include hardware interfaces. The embodiments of the present disclosure do not limit the types of the hardware interfaces and the protocols used. Those skilled in the art can set them according to actual conditions and needs.

[0114] In one possible implementation, the RF signal output module 220 may include a digital-to-analog converter (DAC) for performing digital-to-analog conversion on the received digital driving information and obtaining the driving signal. The embodiment of the present disclosure does not limit the specific implementation method of the digital-to-analog converter, nor does it limit the specific parameters (such as accuracy) of the digital-to-analog converter. Those skilled in the art may adopt a suitable digital-to-analog converter according to actual conditions and needs.

[0115] Exemplarily, the RF signal output module 220 can output a signal at a sampling rate of at least 1 Gsps, which can be used to drive a quantum chip in a quantum system, where Gsps (GigaSamples per Second) is the unit of sampling rate, indicating that the number of samples collected per second reaches the billion level.

[0116] In one possible implementation, the RF signal input module 210 may include an analog-to-digital converter (ADC) and a comparison circuit. The analog-to-digital converter is used to perform analog-to-digital conversion on the measurement signal of the auxiliary quantum bit received from the quantum chip to obtain a target digital signal; the comparison circuit is used to perform a comparison operation between the target digital signal and a preset threshold to determine the state of the quantum bit based on the comparison result. The embodiment of the present disclosure does not limit the specific implementation method of the analog-to-digital converter and the comparison circuit, and does not limit the specific parameters (such as accuracy) of the analog-to-digital converter. Those skilled in the art may adopt a suitable analog-to-digital converter according to actual conditions and needs. As an example, the comparison circuit may include a comparator and related peripheral circuits. Those skilled in the art may refer to relevant technical implementations for its specific implementation method.

[0117] Exemplarily, the RF signal input module 210 can collect RF input signals at a sampling rate of at least 1 GHz per second (Gsps), which can be used to obtain information output by the quantum system. The RF signal input module 210 has a demodulation and analysis function, capable of analyzing the state of the qubit from the collected data. The ADC chip used by the RF signal input module 210 can convert the analog signal (the received analog auxiliary qubit state) into a digital signal (the target digital signal). The RF signal input module 210 processes the obtained digital signal and compares it with a preset signal to determine the state of the qubit.

[0118] For example, the pulse signal output module 230 can output a pulse signal (such as a 0 / 2V signal), and the pulse signal input module 240 can input a pulse signal (such as a 0 / 2V signal), where 0V represents bit 0 and 2V represents bit 1. Of course, the output can also be performed according to other preset logic, which is not limited in the embodiment of the present disclosure. The logic control module 260 and the timing control module can be directly programmed and implemented on the FPGA. They both have dedicated logic circuits. Both the RF signal input and output and the pulse signal input and output have dedicated conversion chips.

[0119] Exemplarily, the pulse signal output module 230 can output a pulse signal of 0V or 2V. The pulse signal output module 230 outputs according to the logic preset by the experimenter (exemplarily, one acquisition module 20 can include multiple pulse signal output modules 230). This part of the logic can be output in time according to a preset instruction sequence (for example, 0V*20ns, 2V*100ns, 0V*40ns, etc.), or it can be the output of the logic control module 260. The pulse signal can be used to control other devices or send signals to other acquisition modules 20. When used to control other devices, it mainly serves as a trigger signal, similar to a switch. When sending related signals (such as bit status) to other acquisition modules 20, 0V can be used to represent bit 0 and 2V to represent bit 1, or it can be output according to other preset logic.

[0120] The apparatus for superconducting quantum computing control, reading, and feedback in the embodiment of the present disclosure may include multiple acquisition modules 20, wherein the auxiliary quantum bit state included in the measurement signal includes the measurement signal of the auxiliary quantum bit state directly received by the radio frequency signal input module 210 of the current acquisition module, and may also include the measurement signal of the auxiliary quantum bit state transmitted by other acquisition modules 20. For example, after receiving the measurement signal of the auxiliary quantum bit state through the radio frequency signal input module 210, the other acquisition module 20 may send the measurement signal of the auxiliary quantum bit state to the current acquisition module 20 through the pulse signal output module 230, so that the current acquisition module 20 performs a quantum error correction operation according to the measurement signal of the auxiliary quantum bit state received by its own radio frequency signal input module 210 and the measurement signal of the auxiliary quantum bit state received by the pulse signal output module 230.

[0121] In a possible implementation, the logic control module 260 is configured to:

[0122] The quantum bit state is converted into a pulse signal and outputted through the pulse signal output module 230 , for example, converted into a 0 / 2V signal as a pulse signal output.

[0123] Exemplarily, the pulse signal input module 240 is capable of receiving pulse signals. Specifically, it can receive the signal output by the pulse signal output module 230 in other acquisition modules 20 and send the result to the logic control module 260. Other acquisition modules 20 can send the measurement signal of the quantum bit obtained by the radio frequency signal input module 210 to the pulse signal input module 240 of this acquisition module 20 through the pulse signal output module 230, thereby transmitting the bit information of the quantum bit between the acquisition modules 20.

[0124] The embodiments of the present disclosure do not limit the specific implementation of the logic control module 260. Those skilled in the art can use relevant technologies to implement it according to actual conditions and needs. For example, the logic control module 260 may include a processing component. For example, the processing component includes but is not limited to a separate processor, or a discrete component, or a combination of a processor and a discrete component. The processor may include a controller with an execution instruction function in an electronic device. The processor may be implemented in any appropriate manner, for example, by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors or other electronic components. Inside the processor, the executable instructions can be executed by hardware circuits such as logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers and embedded microcontrollers.

[0125] Preferably, the logic control module 260 of the embodiment of the present disclosure is implemented using FPGA, so that the processing capability of the quantum chip 30 with an increased number of quantum bits can be improved, and the scale of the measurement and control system can be increased. The technical solution of the embodiment of the present disclosure is applied to the FPGA-based system, which can solve the problems of high cost and cumbersome control of traditional measurement and control systems, and can achieve quantum real-time feedback at the hundred-nanosecond level. In addition, the embodiment of the present disclosure can solve the problem of multi-chassis multi-nested real-time feedback.

[0126] In the embodiment of the present disclosure, the logic control module 260 processes the quantum measurement result using a preset quantum signal to obtain a quantum operation result; the error type of the data quantum bit is determined based on the quantum operation result, and a quantum error correction operation corresponding to the error type is determined. The specific implementation method of generating digital drive information based on the quantum error correction operation is not limited, and those skilled in the art can configure it according to actual conditions and needs.

[0127] Exemplarily, the digital driving information may correspond to a quantum error correction operation. For example, the digital driving information may be a driving parameter corresponding to a quantum logic gate. If the error type of the quantum bit is determined, the corresponding quantum logic gate may be determined according to the error type, thereby generating corresponding digital driving information to perform the quantum logic gate operation on the corresponding quantum bit. Of course, the specific implementation method of the logic control module 260 generating the corresponding digital driving information according to a specific quantum error correction operation is not limited in the embodiment of the present disclosure, and those skilled in the art may refer to relevant technical implementations according to actual conditions and needs.

[0128] Exemplarily, the logic control module 260 can use the auxiliary quantum bit state received by the RF signal input module 210 and the pulse signal (including the auxiliary quantum bit state) received by the pulse signal input module 240 to determine the current state of the quantum system (the quantum bit state) and the next required operation, thereby controlling the output waveform of the driving signal of the RF signal output module 220 to control the quantum system, and send the result (generally transmitting the quantum bit information obtained by the RF signal input module 210) to other acquisition modules 20 and / or other devices through the pulse signal output module 230.

[0129] Exemplarily, the RF signal input module 210 can analyze the collected waveform (computation result) to obtain information about the auxiliary qubit state of the current acquisition module 20, and the pulse signal input module 240 can obtain information about the qubits controlled by other acquisition modules 20 (for example, there is another acquisition module 20, which obtains the measurement signal of the qubit through its own RF signal input module 210, analyzes it to obtain the 01 state of the qubit, and then transmits it to the pulse signal input module 240 of the current acquisition module 20 through the pulse signal output module 230). The logic control module 260 can integrate the signals of the RF signal input module 210 and the pulse signal input module 240 to obtain the qubit state according to a preset logical operation. Of course, the embodiments of the present disclosure do not limit the specific type of the preset logical operation, and those skilled in the art can set it according to actual conditions and needs.

[0130] For example, the quantum bit state can be transmitted to other acquisition modules 20 by the pulse signal output module 230, thereby obtaining the state of the entire quantum chip 30 and performing the next feedback operation.

[0131] Of course, the above introduction to the functions of the logic control module 260 is exemplary and should not be regarded as a limitation on the embodiments of the present disclosure. Those skilled in the art can use the logic control module 260 to control other modules according to actual conditions and needs.

[0132] The embodiments of the present disclosure do not limit the specific implementation of the timing synchronization module 250. Those skilled in the art can set it according to actual conditions and needs. For example, the timing synchronization module 250 can cooperate with the subsequent control and trigger system to fine-tune the timing of the system. Specifically, in order to improve the measurement and control accuracy of the quantum chip 30, the embodiments of the present disclosure can align the measurement and control signals of the embodiments of the present disclosure at the level of hundreds of ps. Due to factors such as line length, the signals emitted from the room temperature equipment are not naturally aligned when they reach the superconducting chip. Therefore, the embodiments of the present disclosure need to fine-tune the time when different acquisition modules 20 start running. The timing synchronization module 250 can adjust the trigger time of different acquisition modules 20 at the level of hundreds of ps and ensure that they remain synchronized throughout the experiment, with no mutual delay, thereby improving the time accuracy of the experiment.

[0133] See also Figure 5 , Figure 5 FIG. 4 is a block diagram of a clock module 10 in a device for superconducting quantum computing control, reading, and feedback according to an embodiment of the present disclosure.

[0134] In one possible implementation, Figure 5 As shown, the clock module 10 may include an atomic clock signal input module 110, a clock synchronization signal output module 120, a trigger signal input module 130, and a trigger signal output module 140, wherein:

[0135] The clock signal input terminal of the atomic clock signal input module 110 is used to receive the atomic clock signal and configure the clock signal for the clock module 10;

[0136] The clock synchronization signal output module 120 is used to output the clock synchronization signal to achieve synchronization and calibration of different acquisition modules 20. Exemplarily, the clock module 10 may further include a synchronization signal generating circuit. When the atomic clock signal input module 110 receives the atomic seed signal (such as a 10 MHz signal), the synchronization signal generating circuit may generate a plurality of mutually synchronized clock synchronization signals (such as a 125 MHz signal) according to the atomic clock signal, and output them from different clock synchronization signal output modules 120 (clock synchronization signal output ports) to each acquisition module 20. Since each clock synchronization signal is synchronized, synchronization and calibration of different acquisition modules 20 can be achieved.

[0137] The trigger signal input module 130 is connected to a host computer or an external trigger device and is used to receive a first trigger signal sent by the host computer or a second trigger signal sent by the external trigger device. In this way, the trigger signal input module 130 of the embodiment of the present disclosure can select internal triggering or external triggering functions. Internal triggering means that the host computer program controls the triggering of the clock module 10 through the first trigger signal; external triggering means that the clock module 10 waits for the second trigger signal from the trigger input port to trigger other devices.

[0138] The trigger signal output module 140 is used to output one or more third trigger signals. In this way, through the trigger signal output module 140, the embodiment of the present disclosure can simultaneously trigger multiple clock modules 10 or acquisition modules 20. The clock module 10 triggering the clock module 10 can achieve multi-level triggering. For example, if the current clock module 10 receives the second trigger signal from other clock modules 10 or the first trigger signal sent by the host computer, it can immediately generate and output one or more third trigger signals to trigger the acquisition module 20 and other connected clock modules 10. Of course, the trigger delay (the duration between receiving the first trigger signal and the second trigger signal and generating and outputting one or more third trigger signals) can be adjusted (that is, it can be set to wait for a period of time (ns level) after receiving the trigger signal before triggering the next level). At the same time, which acquisition modules 20 and clock modules 10 are triggered can also be set, and this is not limited in the embodiment of the present disclosure.

[0139] The embodiments of the present disclosure do not limit the specific implementation methods of the atomic clock signal input module 110, the clock synchronization signal output module 120, the trigger signal input module 130, and the trigger signal output module 140. Those skilled in the art can configure them according to actual conditions and needs.

[0140] In one possible implementation, Figure 5 As shown, the clock module 10 may further include a rubidium atomic clock 100 , the clock signal input end of the atomic clock signal input module 110 is connected to the output end of the rubidium atomic clock 100 , and the output end of the rubidium atomic clock 100 is used to output the atomic clock signal.

[0141] The embodiment of the present disclosure can provide an accurate clock signal (the atomic clock signal) by providing the rubidium atomic clock 100 , thereby improving the clock output accuracy of the clock module 10 .

[0142] In a possible implementation, the sampling rates of the RF signal output module 220 and the RF signal input module 210 are both greater than 1 Gsps.

[0143] The apparatus for superconducting quantum computing control, reading, and feedback in the embodiments of the present disclosure may further include other modules, which are not limited in the embodiments of the present disclosure and can be configured by those skilled in the art according to actual circumstances and needs. For example, the apparatus for superconducting quantum computing control, reading, and feedback may further include a storage module for storing data. In one example, the storage module may include a computer-readable storage medium, which may be a tangible device that can retain and store instructions used by an instruction execution device. The computer-readable storage medium may be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples of computer-readable storage media (a non-exhaustive list) include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a programmable read-only memory (PROM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or raised structures in grooves having instructions stored thereon, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium is not to be construed as a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., light pulses through a fiber optic cable), or an electrical signal transmitted through an electrical wire.

[0144] In a possible implementation, the acquisition module 20 and the clock module 10 are both implemented based on a field programmable gate array (FPGA).

[0145] The device for superconducting quantum computing control, reading and feedback of the disclosed embodiment solves the shortcomings of the existing technology and provides an expandable multi-bit multi-level feedback system to solve the problems in the actual manipulation of quantum bits. The device for superconducting quantum computing control, reading and feedback of the disclosed embodiment uses a customized system based on FPGA, which can solve the problems of high cost and cumbersome control of traditional measurement and control systems, and can achieve quantum real-time feedback at the level of hundreds of nanoseconds. Compared with other systems using FPGA, the device for superconducting quantum computing control, reading and feedback of the disclosed embodiment solves the problem of multi-chassis multi-nested real-time feedback.

[0146] According to one aspect of the present disclosure, a system for superconducting quantum computing control, reading, and feedback is provided, wherein the system for superconducting quantum computing control, reading, and feedback comprises one or more of the aforementioned devices for superconducting quantum computing control, reading, and feedback and a quantum chip 30.

[0147] The device for superconducting quantum computing control, reading, and feedback according to the disclosed embodiment has the following advantages compared to the prior art:

[0148] 1. The disclosed embodiment realizes real-time feedback of multiple cards across chassis, has good scalability, and can be used to implement large-scale quantum bit feedback experiments.

[0149] 2. The disclosed embodiments implement a customized integrated system based on FPGA, which significantly improves cost, convenience and real-time feedback delay.

[0150] 3. The embodiments of the present disclosure implement a feedback logic diagram method for quantum feedback experiments and implement corresponding programs. Compared with existing feedback control methods such as binary trees, the control efficiency is higher, the applicable scenarios are more flexible, and it is easier for experimenters to understand.

[0151] While various embodiments of the present disclosure have been described above, the above descriptions are illustrative, non-exhaustive, and not intended to be limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or improvements to existing technologies, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A device for superconducting quantum computing control, reading and feedback, characterized in that: The device for superconducting quantum computing control, reading and feedback includes a clock module and one or more acquisition modules, wherein: The clock module is used to provide a clock synchronization signal to each acquisition module to achieve clock synchronization between the acquisition modules; Each acquisition module is connected to the quantum chip and the clock module, and each acquisition module is used to: receiving a measurement signal output by the quantum chip, wherein the measurement signal includes a plurality of auxiliary quantum bit states; Comparing the measurement signal with a preset threshold combination to obtain a plurality of quantum measurement results, wherein the preset threshold combination includes a plurality of preset thresholds, each preset threshold corresponding to each auxiliary quantum bit state; Determining an error type of a data qubit in the quantum chip based on each quantum measurement result, and determining a quantum error correction operation corresponding to the error type; Outputting a driving signal according to the quantum error correction operation to perform quantum error correction on the erroneous data quantum bits, The acquisition module includes a radio frequency signal output module, a radio frequency signal input module, a pulse signal output module, a pulse signal input module, a logic control module, and a timing synchronization module, wherein: The output end of the radio frequency signal output module is connected to the input end of the quantum chip, and is used to output the driving signal; The input end of the radio frequency signal input module is connected to the output end of the quantum chip, and is used to receive the measurement signal of the auxiliary quantum bit; The pulse signal output module is used to generate an output pulse signal; The pulse signal input module is used to receive an input pulse signal, wherein the input pulse signal includes the state of the auxiliary quantum bit; The timing synchronization module is used to receive a clock synchronization signal to achieve clock synchronization with other acquisition modules; The logic control module is connected to the RF signal output module, the RF signal input module, the pulse signal output module, the pulse signal input module, and the timing synchronization module. The logic control module is used to use a preset threshold to compare with the read signal of each auxiliary quantum bit to obtain multiple quantum measurement results, determine the error type of the data quantum bit according to each quantum measurement result, and determine the quantum error correction operation corresponding to the error type, and then generate digital driving information according to the quantum error correction operation. The digital driving information is used to generate the driving signal.

2. The device for superconducting quantum computing control, reading and feedback according to claim 1, characterized in that: The method of comparing the preset threshold combination with the measurement signal to obtain multiple quantum measurement results includes: Comparing the measurement signals of the auxiliary qubits using any number of preset threshold combinations in the preset threshold combination to obtain a comparison result; The comparison result is used to determine the state of each auxiliary quantum bit to obtain the quantum measurement result.

3. The device for superconducting quantum computing control, reading and feedback according to claim 2, characterized in that: Determining an error type of a data qubit in the quantum chip according to each quantum measurement result, and determining a quantum error correction operation corresponding to the error type, including: Processing the quantum measurement result using a preset coding logic to obtain a logical operation result; The error type of the data quantum bit is determined according to the logical operation result.

4. The device for superconducting quantum computing control, reading and feedback according to claim 1, characterized in that: The radio frequency signal output module includes a digital-to-analog converter for performing digital-to-analog conversion on the received digital driving information to obtain the driving signal; The RF signal input module includes an analog-to-digital converter and a comparison circuit. The analog-to-digital converter is used to perform analog-to-digital conversion on the received measurement signal of the auxiliary quantum bit to obtain a target digital signal; the comparison circuit is used to perform a comparison operation between the target digital signal and a preset threshold to determine the state of the auxiliary quantum bit based on the comparison result.

5. The device for superconducting quantum computing control, reading and feedback according to claim 1, characterized in that: The clock module includes an atomic clock signal input module, a clock synchronization signal output module, a trigger signal input module, and a trigger signal output module, wherein: The clock signal input end of the atomic clock signal input module is used to receive the atomic clock signal and configure the clock signal for the clock module; The clock synchronization signal output module is used to output the clock synchronization signal; The trigger signal input module is connected to the host computer or the external trigger device, and is used to receive the first trigger signal sent by the host computer or the second trigger signal sent by the external trigger device; The trigger signal output module is used to output one or more third trigger signals.

6. The device for superconducting quantum computing control, reading and feedback according to claim 5, characterized in that: The clock module also includes a rubidium atomic clock. The clock signal input end of the atomic clock signal input module is connected to the output end of the rubidium atomic clock. The output end of the rubidium atomic clock is used to output the atomic clock signal.

7. The device for superconducting quantum computing control, reading and feedback according to claim 1, characterized in that: The sampling rates of the radio frequency signal output module and the radio frequency signal input module are both greater than 1 Gsps.

8. The device for superconducting quantum computing control, reading and feedback according to claim 1, characterized in that: The acquisition module and the clock module are both implemented based on a field programmable gate array (FPGA).

9. A system for superconducting quantum computing control, reading and feedback, characterized in that: The system for superconducting quantum computing control, reading and feedback includes one or more devices for superconducting quantum computing control, reading and feedback and quantum chips as described in any one of claims 1 to 8.

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