Starting control circuit for power tube, line driving circuit and LED display device

Abstract

The present application provides a start-up control circuit for a power tube, a line driving circuit, and an LED display device. The start-up control circuit for the power tube includes: a first start-up branch that provides a first start-up signal to the power tube when turned on; a second start-up branch that provides a second start-up signal to the power tube when turned on; a first start-up control circuit that controls the first start-up branch to turn on at least in a first start-up stage within the valid period of the input signal, and the power tube starts to conduct when the driving voltage of the power tube reaches the turn-on threshold by the first start-up signal; a second start-up control circuit that receives the input signal and the driving voltage, and controls the second start-up branch to turn on in a second start-up stage within the valid period of the input signal, and the power tube is fully conducted by the second start-up signal. Therefore, the power tube is in a weak turn-on state in the first start-up stage to discharge the charge of the parasitic capacitance of the output node, and the power tube is fully conducted only in the second start-up stage to avoid current overshoot at the moment of turn-on.

Description

Technical Field

[0001] The present application relates to the field of display driving technology, and particularly relates to a starting control circuit for a power tube, a row driving circuit, and an LED display device. Background Art

[0002] An LED display device generally includes an LED light source array and a display driving chip. The LED light source array includes a plurality of LED lamp beads arranged in a row-column staggered manner, and the display driving chip is divided into a row driving chip and a column driving chip. For the row driving chip, it is connected to the same end of the LED lamp beads in the same row to achieve common anode driving or common cathode driving. The row driving chip is responsible for providing driving current for all the LED lamp beads on this row when the row is turned on. Therefore, it is required that the size of the MOS transistor in the output stage of the row driving chip is relatively large to ensure sufficient driving current for the LED lamp beads.

[0003] Figure 1 The schematic diagram of the driving circuit for a large-sized power transistor in the prior art is shown as Figure 1 As shown, the output-stage MOS transistor M0 of the row driving chip is a large-sized NMOS transistor, which is connected to the cathodes of the LED lamp beads (D1, D2... Dm) in the same row. When the MOS transistor M0 is turned on, a conduction path is formed and current flows through the LED lamp beads. The input signal IN of the row driving chip needs to pass through a driver chain composed of a series of inverters to gradually increase the driving ability of the inverters, so as to drive the large MOS transistor M0 in the output stage. At the moment when the output-stage MOS transistor M0 is turned on, the parasitic capacitance Cs of the circuit output node will discharge through the MOS transistor M0. Since the on-resistance of the MOS transistor M0 is very small, a large transient current will be generated on the power supply / ground, causing voltage fluctuations on the power supply / ground, thereby affecting the working state of the circuit. Summary of the Invention

[0004] In order to solve the above technical problems, the present application provides a starting control circuit for a power tube, a row driving circuit, a display driving chip, an LED display device, and a terminal electronic device.

[0005] According to one aspect of the present invention, there is provided a start-up control circuit for a power transistor, comprising: a first start-up branch that provides a first start-up signal to the control terminal of the power transistor when turned on; a second start-up branch that provides a second start-up signal to the control terminal of the power transistor when turned on; a first start-up control circuit that receives an input signal and controls the first start-up branch to turn on at least in a first start-up stage within the valid period of the input signal, and the power transistor starts to conduct when the driving voltage of the power transistor reaches the turn-on threshold by the first start-up signal; and a second start-up control circuit that receives the input signal and the driving voltage and controls the second start-up branch to turn on in a second start-up stage within the valid period of the input signal, and the power transistor is fully turned on by the second start-up signal, wherein the valid period of the input signal includes the adjacent first start-up stage and the second start-up stage.

[0006] Optionally, the first start-up branch is continuously turned on within the valid period of the input signal, and in the time period other than the first start-up stage in each working cycle, the second start-up control circuit controls the on-off state of the second start-up branch to follow the on-off state of the first start-up branch.

[0007] Optionally, the second start-up control circuit includes: a driving state characterization circuit that receives the driving voltage to output a characterization signal characterizing the voltage state of the driving voltage; a following control circuit that controls the connection state between the control terminal of the first start-up branch and the control terminal of the second start-up branch according to the input signal and the characterization signal, and when a connection path is established between the control terminal of the first start-up branch and the control terminal of the second start-up branch, the on-off state of the second start-up branch follows the on-off state of the first start-up branch.

[0008] Optionally, the level state of the characterization signal jumps when the driving voltage reaches the turn-on threshold of the power transistor and reaches the turn-off threshold of the power transistor.

[0009] Optionally, the following control circuit disconnects the connection path between the control terminal of the first start-up branch and the control terminal of the second start-up branch when the input signal starts to be valid, and starts to enter the first start-up stage; the following control circuit also establishes the connection path between the control terminal of the first start-up branch and the control terminal of the second start-up branch when the characterization signal characterizes that the driving voltage reaches the turn-on threshold of the power transistor, and starts to enter the second start-up stage.

[0010] Optionally, the start-up control circuit of the power transistor further includes: a turn-off branch that is turned on when the input signal is invalid and provides a turn-off signal to the control terminal of the power transistor, and the power transistor is turned off when the turn-off signal makes the driving voltage reach the turn-off threshold.

[0011] Optionally, the first startup control circuit includes a plurality of inverters connected in series, which perform signal enhancement and phase adjustment processing on the input signal to provide an input control signal to the control end of the first startup branch.

[0012] Optionally, the first startup branch includes a first MOS transistor, the second startup branch includes a second MOS transistor, and the turn-off branch includes a third MOS transistor; the drive state characterization circuit includes a current source and a fourth MOS transistor connected in series, and the control end of the fourth MOS transistor receives the drive voltage, and provides the characterization signal from the connection node of the current source and the fourth MOS transistor; the following control circuit includes a NAND gate, a switch unit, and a fifth MOS transistor, the input ends of the NAND gate receive the input signal and the characterization signal, and the output end generates a switch signal, and the switch signal controls the conduction states of the switch unit and the fifth MOS transistor.

[0013] Optionally, the switch unit is connected to the control ends of the first MOS transistor and the second MOS transistor, and the switch unit includes a transmission gate, a switching transistor or a switch; the fifth MOS transistor is connected to the control end of the second MOS transistor, and when the fifth MOS transistor is a PMOS transistor, it receives the switch signal, and when the fifth MOS transistor is an NMOS transistor, it receives the inverted signal of the switch signal.

[0014] Optionally, when the power transistor is an NMOS transistor, the first MOS transistor and the second MOS transistor are PMOS transistors, the third MOS transistor and the fourth MOS transistor are NMOS transistors, and the first startup control circuit includes an odd number of inverters; when the power transistor is a PMOS transistor, the first MOS transistor and the second MOS transistor are NMOS transistors, the third MOS transistor and the fourth MOS transistor are PMOS transistors, and the first startup control circuit includes an even number of inverters.

[0015] According to another aspect of the present invention, a row driving circuit is provided, which is connected to the same end of a row of LED lamp beads. Wherein, the row driving circuit includes: a power transistor, which serves as the output stage of the row driving circuit; and the startup control circuit of the above-mentioned power transistor, and the startup control circuit of the power transistor is used to control the conduction state of the power transistor, so that a stable driving current flows through the row of LED lamp beads when the power transistor is turned on.

[0016] According to another aspect of the present invention, a display driving chip is provided, which includes: a power supply; and a plurality of row driving circuits, each row driving circuit is connected to the same end of the same row of LED lamp beads, wherein, the row driving circuit includes a power transistor as the output stage and the startup control circuit of the above-mentioned power transistor.

[0017] According to another aspect of the present invention, there is provided an LED display device, comprising: an LED array, the LED array comprising a plurality of LED lamp beads arranged in an array; and a plurality of row drive circuits, each of the row drive circuits correspondingly controlling a row of LED lamp beads, and each of the row drive circuits comprising a power tube and a start-up control circuit for the power tube.

[0018] According to another aspect of the present invention, there is provided a terminal electronic device, comprising: a power tube and a start-up control circuit of the power tube.

[0019] The beneficial effects of this application include at least:

[0020] The embodiment of the present application provides a startup control circuit of a power tube, a row drive circuit, a display driver chip, an LED display device and a terminal electronic device, and two startup branches are set at the control end of the power tube of the output stage. In the first startup stage when the input signal is valid, the first startup branch first changes the driving voltage of the power tube, and the driving voltage reaches the turn-on threshold value to put the power tube in a weak turn-on state, and the charge on the parasitic capacitor of the output node is slowly released through the power tube to avoid the formation of a large transient current. Afterwards, in the second startup stage when the input signal is valid, the second startup branch is turned on to make the power tube fully turned on, providing a current path for the LED lamp beads. Through the cooperation of the two startup branches, the charge on the parasitic capacitor is well discharged, and the normal working state of the circuit is not affected. A stable current path can also be provided for the LED lamp beads to ensure the stability of the picture of the LED display device.

[0021] Furthermore, the first startup control circuit enables the first startup branch to remain on during the entire period when the input signal is valid, and the second startup control circuit enables the second startup branch to follow the on state of the first startup branch during the period outside the first startup phase. Specifically, the connection state between the control end of the first startup branch and the control end of the second startup branch can be controlled according to the input signal and the characterization signal of the driving voltage, so that the working state of the second startup branch can be accurately controlled to accurately control the start-up timing of the power tube and stabilize the working state of the circuit.

[0022] It should be noted that the above general description and the following detailed description are merely exemplary and explanatory and do not limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic diagram of a driving circuit for a large-size power tube in the prior art is shown;

[0024] Figure 2 A schematic circuit diagram of a power tube startup control circuit and a part of a row drive circuit according to a first embodiment of the present invention is shown;

[0025] Figure 3 Shows Figure 2 a schematic diagram of waveforms of various signals in the startup control circuit of a power transistor;

[0026] Figure 4 Shows a schematic circuit diagram of the startup control circuit of a power transistor and a partial row driving circuit according to a second embodiment of the present invention;

[0027] Figure 5 Shows a partial structural schematic diagram of an LED display device according to an embodiment of the present invention. Specific embodiments

[0028] For ease of understanding of the present application, the present application will be described more comprehensively below with reference to relevant drawings. Preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in different forms and is not limited to the embodiments described herein.

[0029] Reference to "one embodiment" or "some embodiments" etc. described in this specification means that specific features, structures or characteristics described in connection with the embodiment are included in one or more embodiments of the present application. Thus, statements such as "in one embodiment", "in some embodiments", "in other some embodiments" etc. that appear in different places in this specification do not necessarily all refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in another way. The terms "comprising", "including", "having" and their variants all mean "including but not limited to", unless otherwise specifically emphasized in another way. "A plurality" means two or more than two.

[0030] In addition, the same reference numerals in the figures denote the same or similar structures, and thus their repeated descriptions will be omitted, that is, each part in this specification is described in a way that combines parallelism and progression, and the key point of each part is to illustrate the differences from other parts. For the same or similar parts between each part, reference can be made to each other.

[0031] Figure 2 Shows a schematic circuit diagram of the startup control circuit of a power transistor and a partial row driving circuit according to a first embodiment of the present invention, Figure 3 Shows Figure 2 a schematic diagram of waveforms of various signals in the startup control circuit of a power transistor.

[0032] Similar to Figure 1 the row driving circuit in this embodiment is connected to the same end of a row of LED lamp beads. When the output stage power transistor of the row driving circuit is an NMOS, the cathodes of a row of LED lamp beads are connected together and connected to the drain of the power transistor M0. As Figure 2As shown, the row driving circuit of this embodiment includes a power transistor M0 and a start control circuit 100 for the power transistor (other circuit structures and LED lamp beads are not shown). The power transistor M0 serves as the output stage of the row driving circuit and provides an output signal OUT from the drain. The start control circuit 100 for the power transistor is used to control the conduction state of the power transistor M0 so that a stable driving current flows through a row of LED lamp beads when the power transistor M0 is conducting.

[0033] The start control circuit 100 for the power transistor of this embodiment includes a first start branch 110, a second start branch 120, a first start control circuit 130, and a second start control circuit 140. The output terminal of the first start branch 110 is connected to the control terminal of the power transistor M0. When the first start branch 110 is turned on, it provides a first start signal to the control terminal of the power transistor M0, and this first start signal can cause the driving voltage NGATE of the power transistor M0 to rise slowly. The output terminal of the second start branch 120 is connected to the control terminal of the power transistor M0. When the second start branch 120 is turned on, it provides a second start signal to the control terminal of the power transistor M0, and this second start signal can cause the driving voltage of the power transistor M0 to rise rapidly. The input terminal of the first start control circuit 130 receives an input signal IN, and the output terminal is connected to the control terminal of the first start branch 110, controlling the first start branch 110 to turn on when the input signal IN is valid. In a working cycle, the valid period of the input signal IN includes adjacent first start stage and second start stage. The first start control circuit 130 controls the first start branch 110 to turn on at least in the first start stage, and the first start signal causes the driving voltage NGATE of the power transistor to rise. When the driving voltage NGATE reaches the turn-on threshold value, the power transistor M0 starts to conduct. The turn-on threshold value mentioned here refers to the voltage required for the power transistor M0 to just start to conduct. The second start control circuit 140 receives the input signal IN and the driving voltage NGATE, and controls the second start branch 120 to turn on in the second start stage within the valid period of the input signal IN. The second start signal causes the driving voltage of the power transistor M0 to rise rapidly, and the power transistor M0 is fully conducted. Thus, in the first start stage, the first start branch 110 causes the power transistor M0 to start to conduct and be in a weak turn-on state, and can slowly release the charge on the parasitic capacitor Cs, avoiding the large transient current caused by the discharge of the parasitic capacitor at the moment when the power transistor is turned on. Then in the second start stage, the power transistor is fully turned on and enters the normal working state, enabling the LED lamp beads to form a current path.

[0034] Furthermore, the first startup control circuit 130 can also control the first startup branch 110 to remain turned on during the entire valid period of the input signal. Then, during the time period other than the first startup stage in each working cycle, the second startup control circuit 140 can control the on-state of the second startup branch 120 to follow the on-state of the first startup branch 110. Specifically, the first startup control circuit 130 includes, for example, a plurality of serially connected inverters, which perform signal enhancement and phase adjustment processing on the input signal IN to provide an input control signal X to the control terminal of the first startup branch 110. In this embodiment, the power transistor M0 is an NMOS transistor, and the first startup control circuit 130 includes an odd number of inverters, for example, 3 inverters connected end to end. That is, the input signal IN is output after passing through the inverter O1, the inverter O2, and the inverter O3, and the obtained input control signal X has a phase opposite to that of the input signal IN. Correspondingly, the first startup branch 110 includes, for example, a first MOS transistor P1. Since the power transistor M0 is an NMOS transistor, the first MOS transistor P1 can be a PMOS transistor. The source of the first MOS transistor P1 receives the voltage V1, the drain of the first MOS transistor P1 is connected to the control terminal of the power transistor M0, and the gate of the first MOS transistor P1 is connected to the output terminal of the inverter O3. When the input signal IN is valid, the first MOS transistor P1 conducts during the period when the input control signal X is at a low level. Similarly, the second startup branch 120 includes, for example, a second MOS transistor P2. Since the power transistor M0 is an NMOS transistor, the second MOS transistor P2 is a PMOS transistor. The source of the second MOS transistor P2 receives the voltage V2, the drain of the second MOS transistor P2 is connected to the control terminal of the power transistor M0, and the gate of the second MOS transistor P2 is connected to the output terminal of the second startup control circuit 140 to receive the follow-up control signal Y.

[0035] In one embodiment, the second startup control circuit 140 specifically includes a driving state characterization circuit 141 and a following control circuit 142. The driving state characterization circuit 141 receives the driving voltage NGATE to output a characterization signal CTRL characterizing the voltage state of the driving voltage NGATE. The level state of the characterization signal CTRL jumps when the driving voltage NGATE reaches the turn-on threshold of the power transistor M0 and the turn-off threshold of the power transistor. The following control circuit 142 controls the connection state between the control end of the first startup branch 110 and the control end of the second startup branch 120 according to the input signal IN and the characterization signal CTRL. When a connection path is established between the control end of the first startup branch 110 and the control end of the second startup branch 120, the turn-on state of the second startup branch 120 follows the turn-on state of the first startup branch 110. That is, the following control circuit 142 can control the connection path between the control end of the first MOS transistor P1 and the control end of the second MOS transistor P2. When the connection path is established, the control end of the second MOS transistor P2 is connected to the control end of the first MOS transistor P1, and the following control signal Y changes following the input control signal X. Moreover, the size of the first MOS transistor P1 is smaller than that of the second MOS transistor P2, so that in the first startup stage, the driving voltage NGATE rises slowly, while the power transistor M0 can be fully turned on in the second startup stage.

[0036] When the circuit is operating, the following control circuit 142 disconnects the connection path between the control end of the first startup branch and the control end of the second startup branch when the input signal IN starts to be valid, and starts to enter the first startup stage. That is, within the first startup stage, the control end of the second MOS transistor P2 is disconnected from the control end of the first MOS transistor P1, the following control signal Y is independent of the input control signal X, and the following control signal Y generated by the following control circuit 142 turns off the second MOS transistor P2. Then, the following control circuit 142 also establishes the connection path between the control end of the first startup branch and the control end of the second startup branch when the characterization signal CTRL characterizes that the driving voltage NGATE reaches the turn-on threshold of the power transistor M0, and starts to enter the second startup stage. Therefore, after the driving voltage NGATE reaches the turn-on threshold of the power transistor M0, the level of the characterization signal CTRL flips, the control end of the second MOS transistor P2 is connected to the control end of the first MOS transistor P1, and the following control signal Y follows the level state of the input control signal X. Since the input control signal X maintains a low level during the valid period of the input signal, the following control signal Y also outputs a low level during the second startup stage, turning on the second MOS transistor P2.

[0037] Further, the startup control circuit 100 of the power transistor further includes a turn-off branch 150. The turn-off branch 150 is turned on when the input signal IN is invalid, and provides a turn-off signal to the control terminal of the power transistor M0. When the turn-off signal causes the drive voltage NGATE to reach the turn-off threshold, the power transistor M0 is turned off. The turn-off branch includes a third MOS transistor N1. When the power transistor is an NMOS transistor, the third MOS transistor N1 is an NMOS transistor. The source of the third MOS transistor N1 is grounded, the drain is connected to the drains of the first MOS transistor P1 and the second MOS transistor P2, and the control terminal of the third MOS transistor N1 receives the input control signal X. Therefore, the operating state of the third MOS transistor N1 is opposite to that of the first MOS transistor P1.

[0038] Continue to refer to Figure 2 , the drive state characterization circuit 141 includes a current source A1 and a fourth MOS transistor N2 connected in series. The control terminal of the fourth MOS transistor N2 receives the drive voltage NGATE, and a characterization signal CTRL is provided from the connection node of the current source A1 and the fourth MOS transistor N2. When the power transistor is an NMOS transistor, the fourth MOS transistor N2 is an NMOS transistor. The source of the fourth MOS transistor N2 is grounded, and the drain is connected to the current source A1. The drive state characterization circuit 141 may further include an inverter chain, such as inverters O5 and O6 connected in series. The input terminal of the inverter O5 is connected to the common node of the fourth MOS transistor N2 and the current source A1, and the characterization signal CTRL is provided from the output terminal of the inverter O6. Then, the level state of the characterization signal CTRL is opposite to that of the drive voltage NGATE. The follow-up control circuit 142 includes, for example, a NAND gate U1, a switch unit, and a fifth MOS transistor P3. The two input terminals of the NAND gate U1 respectively receive the input signal IN and the characterization signal CTRL, and a switch signal swn is generated at the output terminal. The switch signal swn is used to control the conduction states of the switch unit and the fifth MOS transistor P3. The switch unit is connected to the control terminals of the first MOS transistor P1 and the second MOS transistor P2. The switch unit includes, for example, a transmission gate, a switch transistor, or a switch. In this embodiment, the switch unit is taken as the transmission gate K1. Then, the output terminal of the NAND gate U1 is further connected to an inverter O4, and the output terminal of the inverter provides an inverted signal swp of the switch signal. The transmission gate K1 is connected between the control terminals of the first MOS transistor P1 and the second MOS transistor P2, and receives the switch signal swn and the inverted signal swp of the switch signal. Then, when the switch unit does not adopt the transmission gate K1, an inverter O4 can be omitted. The fifth MOS transistor P3 is connected to the control terminal of the second MOS transistor P2 and can be an NMOS transistor or a PMOS transistor. As Figure 2When the fifth MOS transistor P3 is a PMOS transistor, its source receives the voltage V3, its gate is connected to the output terminal of the NAND gate U1 to receive the switching signal swn, and its drain is connected to the control terminal of the second MOS transistor P2. When the transmission gate K1 is turned on, the fifth MOS transistor P3 is turned off, and the follow control signal Y is the same as the input control signal X; when the transmission gate K1 is turned off, the fifth MOS transistor P3 is turned on, and the follow control signal Y is at a high level. When the fifth MOS transistor is an NMOS transistor, its control terminal or gate receives the inverted signal swp of the switching signal.

[0039] The working principle of the above circuit is described below in conjunction with Figure 3 as shown in Figure 3 Before the time t1, the input signal IN is in an invalid state, for example, a low level. Then the input control signal X is at a high level, the first MOS transistor P1 is turned off, the third MOS transistor N1 is turned on, and the drive voltage NGATE is at a low level; the characterization signal CTRL is at a high level, so that the switching signal swn output by the NAND gate U1 is at a high level, the transmission gate K1 is opened, and the fifth MOS transistor P3 is turned off; the follow control signal Y follows the input control signal X and is at a high level, and the second MOS transistor P2 is turned off. At the time t1, the input signal IN starts to be valid and enters the first startup stage. Then the input control signal X is at a low level, the first MOS transistor P1 is turned on, the third MOS transistor N1 is turned off, and the drive voltage NGATE starts to rise slowly; before the drive voltage reaches the turn-on threshold, the characterization signal CTRL remains at a high level, so that the switching signal swn output by the NAND gate U1 is at a low level, the transmission gate K1 is turned off, and the fifth MOS transistor P3 is turned on; the follow control signal Y is at a high level, and the second MOS transistor P2 is turned off. The time period from t1 to t2 is the first startup stage. During this time period, the first MOS transistor P1 is turned on and the second MOS transistor P2 is turned off. At the time t2, the drive voltage NGATE reaches the turn-on threshold, the characterization signal CTRL flips to a low level, the switching signal swn output by the NAND gate U1 is at a high level, the transmission gate K1 is opened, and the fifth MOS transistor P3 is turned off; the follow control signal Y follows the input control signal X and is at a low level, the second MOS transistor P2 is turned on, the drive voltage NGATE rises rapidly and then stabilizes, and the power transistor M0 is fully turned on. That is, starting from the time t2, it enters the second startup stage. In this stage, both the first MOS transistor P1 and the second MOS transistor P2 are turned on.

[0040] At time t3, the input signal IN starts to be invalid and the second startup phase ends. Therefore, the time period from t2 to t3 is the second startup phase. At time t3, the input control signal X flips to a high level, the first MOS transistor P1 turns off, and the third MOS transistor N1 turns on; this causes the drive voltage GATE to drop to zero and the power transistor M0 to turn off; afterwards, the level state of the characterization signal CTRL flips, and the switching signal swn output by the NAND gate U1 remains at a high level, the transmission gate K1 turns on, the fifth MOS transistor P3 turns off, and the follow control signal Y follows the input control signal X and flips to a high level. Due to the delay in signal transmission, the follow control signal Y flips to a high level after a period of time after time t3, and the second MOS transistor P2 also turns off accordingly. Then at time t4, the input signal IN starts to be valid again and enters a new working cycle. After time t4, the states of the working cycle from t1 to t4 start to repeat.

[0041] In the above embodiment, the power transistor M0 is an NMOS transistor. In fact, the power transistor M0 can also be a PMOS transistor. At this time, the output terminal of the power transistor M0 is connected to the anodes of a row of LED lamp beads, that is, common anode drive is realized.

[0042] Figure 4 The schematic circuit diagram of the startup control circuit of the power transistor and part of the row drive circuit according to the second embodiment of the present invention is shown.

[0043] As Figure 4 shown, when the output stage MOS transistor of the LED display row drive circuit is a PMOS transistor, it is necessary to control the pull-down speed of the drive voltage PGATE of the control terminal of the power transistor to achieve the segmented turn-on of the PMOS transistor. In this embodiment, the row drive circuit still includes the power transistor M0 and the startup control circuit 100 of the power transistor. The startup control circuit 100 includes a first startup branch 110, a second startup branch 120, a first startup control circuit 130, a second startup control circuit 140, and a turn-off branch 150. Similar to Figure 2 the embodiment, the first startup branch 110 includes the first MOS transistor N1, the second startup branch 120 includes the second MOS transistor N3, and the turn-off branch 150 includes the third MOS transistor P1. That is, both the first MOS transistor N1 and the second MOS transistor N3 are NMOS transistors, while the third MOS transistor P1 is a PMOS transistor. Correspondingly, the first startup control circuit 130 includes an even number of serially connected inverters. For example, it includes the inverter O1 and the inverter O2. Then the input control signal X is in phase with the input signal IN. The second startup control circuit 140 also includes a drive state characterization circuit 141 and a follow control circuit 142. The circuit elements included in the drive state characterization circuit 141 and the follow control circuit 142 are the same as Figure 2The same as the embodiment. The difference is that, in this embodiment, the fourth MOS transistor P4 in the following control circuit 142 is a PMOS transistor, so the characterization signal CTRL is in phase with the driving voltage PGATE. Figure 4 In, the fifth MOS transistor P3 can also be replaced with an NMOS transistor, and its control terminal is controlled by the inverted signal swp of the switching signal.

[0044] This embodiment is the same as Figure 2 The same circuit structure and working principle will not be elaborated here. It can achieve that at least the first MOS transistor N1 is turned on in the first startup stage, and the second MOS transistor N3 is turned on in the second startup stage.

[0045] Of course, the present invention also provides a display driving chip. The display driving chip is used to drive a display panel. The display panel is, for example, an LED panel. The display driving chip may include multiple row driving circuits, and each row driving circuit is connected to the same end of the LED beads in the same row. The display driving chip may also include a power supply and other circuit structures, such as a discharge circuit, a timing controller, etc.

[0046] Figure 5 Shows a partial structural schematic diagram of an LED display device according to an embodiment of the present invention.

[0047] As Figure 5 Shown, this embodiment also provides an LED display device 300. The LED display device 300 includes an LED array 320 and multiple row driving circuits 310. The LED array 320 includes multiple LED beads (D1, D2, Dm, etc.) arranged in an array. Each row driving circuit 310 correspondingly controls a row of LED beads, and each row driving circuit 310 includes a power transistor M0 and the startup control circuit 100 of the power transistor in the above embodiment.

[0048] Furthermore, the present invention can also provide a terminal electronic device. The terminal electronic device may include the power transistor and the startup control circuit of the power transistor in any of the above embodiments. For example, the terminal electronic device may include Figure 5 The described LED display device. The terminal electronic device may be a mobile phone, a tablet computer, a smart watch, etc., but is not limited thereto.

[0049] The start-up control circuit of the power transistor according to the embodiment of the present invention, the line driving circuit, the display driving chip, the LED display device and the terminal electronic device applying the same are provided with two start-up branches at the control end of the power transistor in the output stage. In the first start-up stage when the input signal is valid, the driving voltage of the power transistor is first changed by the first start-up branch. When the driving voltage reaches the turn-on threshold, the power transistor is in a weak turn-on state, and the charge on the parasitic capacitor of the output node is slowly released through the power transistor, avoiding the formation of a large transient current. Then, in the second start-up stage when the input signal is valid, the second start-up branch is turned on to make the power transistor fully conduct, providing a current path for the LED lamp beads. Through the cooperation of the two start-up branches, the charge on the parasitic capacitor is well discharged, without affecting the normal working state of the circuit, and a stable current path can also be provided for the LED lamp beads, ensuring the stability of the picture of the LED display device.

[0050] Finally, it should be noted that: Obviously, the above embodiments are only examples for clearly illustrating the present application, rather than limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or variations can be made based on the above description. It is not necessary and impossible to enumerate all the implementation manners here. And the obvious changes or variations derived therefrom are still within the protection scope of the present application.

Claims

1. A starting control circuit for a power transistor, comprising: A first starting branch that provides a first starting signal to the control terminal of the power transistor when turned on; A second starting branch that provides a second starting signal to the control terminal of the power transistor when turned on; A first starting control circuit that receives an input signal and continuously conducts during the valid period of the input signal to control the first starting branch to turn on. When the driving voltage of the power transistor reaches the turn-on threshold due to the first starting signal, the power transistor starts to conduct. Wherein, the valid period of the input signal includes adjacent first starting stage and second starting stage; and A second starting control circuit that receives the input signal and the driving voltage, and controls the second starting branch to turn on during the second starting stage within the valid period of the input signal. The second starting signal causes the power transistor to be fully turned on. The second starting control circuit includes: A driving state characterization circuit that receives the driving voltage to output a characterization signal characterizing the voltage state of the driving voltage; A following control circuit that controls the connection state between the control terminal of the first starting branch and the control terminal of the second starting branch according to the input signal and the characterization signal. When a connection path is established between the control terminal of the first starting branch and the control terminal of the second starting branch, the turn-on state of the second starting branch follows the turn-on state of the first starting branch.

2. The startup control circuit of the power transistor according to claim 1, wherein, During the time period other than the first starting stage in each working cycle, the second starting control circuit controls the turn-on state of the second starting branch to follow the turn-on state of the first starting branch.

3. The startup control circuit of the power transistor according to claim 1, wherein, The level state of the characterization signal jumps when the driving voltage reaches the turn-on threshold of the power transistor and the turn-off threshold of the power transistor.

4. The start-up control circuit of the power transistor according to claim 1, wherein, The following control circuit disconnects the connection path between the control terminal of the first starting branch and the control terminal of the second starting branch when the input signal starts to be valid, and starts to enter the first starting stage; The following control circuit also establishes a connection path between the control terminal of the first starting branch and the control terminal of the second starting branch when the characterization signal characterizes that the driving voltage reaches the turn-on threshold of the power transistor, and starts to enter the second starting stage.

5. The starting control circuit for a power transistor according to claim 1, further comprising: A turn-off branch that turns on when the input signal is invalid and provides a turn-off signal to the control terminal of the power transistor. When the turn-off signal causes the driving voltage to reach the turn-off threshold, the power transistor turns off.

6. The startup control circuit of the power transistor according to claim 1, wherein, The first starting control circuit includes a plurality of series-connected inverters that perform signal enhancement and phase adjustment processing on the input signal to provide an input control signal to the control terminal of the first starting branch.

7. The startup control circuit of the power transistor according to claim 1, wherein, The first starting branch includes a first MOS transistor, the second starting branch includes a second MOS transistor, and the turn-off branch includes a third MOS transistor; The driving state characterization circuit includes a series-connected current source and a fourth MOS transistor. The control terminal of the fourth MOS transistor receives the driving voltage, and provides the characterization signal from the connection node of the current source and the fourth MOS transistor. The following control circuit includes a NAND gate, a switch unit, and a fifth MOS transistor. The input terminals of the NAND gate receive the input signal and the characterization signal, and the output terminal generates a switch signal, which controls the conduction states of the switch unit and the fifth MOS transistor.

8. The startup control circuit of the power transistor according to claim 7, wherein, The switch unit is connected to the control terminals of the first MOS transistor and the second MOS transistor. The switch unit includes a transmission gate, a switch transistor, or a switch. The fifth MOS transistor is connected to the control terminal of the second MOS transistor. When the fifth MOS transistor is a PMOS transistor, it receives the switch signal. When the fifth MOS transistor is an NMOS transistor, it receives the inverted signal of the switch signal.

9. The startup control circuit of the power transistor according to claim 7, wherein, When the power transistor is an NMOS transistor, the first MOS transistor and the second MOS transistor are PMOS transistors, the third MOS transistor and the fourth MOS transistor are NMOS transistors, and the first startup control circuit includes an odd number of inverters. When the power transistor is a PMOS transistor, the first MOS transistor and the second MOS transistor are NMOS transistors, the third MOS transistor and the fourth MOS transistor are PMOS transistors, and the first startup control circuit includes an even number of inverters.

10. A row driving circuit is connected to the same ends of a row of LED lamp beads, wherein, The row driving circuit includes: A power transistor, serving as the output stage of the row driving circuit; and The startup control circuit of the power transistor according to any one of claims 1-9, which is used to control the conduction state of the power transistor, so that a stable driving current flows through the LED beads in one row when the power transistor is conducting.

11. A display driving chip, comprising: A power supply; And A plurality of row driving circuits, each row driving circuit being connected to the same end of the LED beads in the same row, wherein the row driving circuit includes a power transistor serving as an output stage and the startup control circuit of the power transistor according to any one of claims 1-9.

12. An LED display device, comprising: An LED array, the LED array including a plurality of LED beads arranged in an array; And A plurality of row driving circuits, each row driving circuit correspondingly controlling one row of LED beads, and each row driving circuit includes a power transistor and the startup control circuit of the power transistor according to any one of claims 1-9.

13. A terminal electronic device, comprising: A power transistor and the startup control circuit of the power transistor according to any one of claims 1-9.

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